2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "anv_private.h"
32 #include "util/debug.h"
35 #include "vk_format_info.h"
38 * Exactly one bit must be set in \a aspect.
40 static isl_surf_usage_flags_t
41 choose_isl_surf_usage(VkImageCreateFlags vk_create_flags
,
42 VkImageUsageFlags vk_usage
,
43 VkImageAspectFlags aspect
)
45 isl_surf_usage_flags_t isl_usage
= 0;
47 if (vk_usage
& VK_IMAGE_USAGE_SAMPLED_BIT
)
48 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
50 if (vk_usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)
51 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
53 if (vk_usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
)
54 isl_usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
56 if (vk_create_flags
& VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT
)
57 isl_usage
|= ISL_SURF_USAGE_CUBE_BIT
;
59 /* Even if we're only using it for transfer operations, clears to depth and
60 * stencil images happen as depth and stencil so they need the right ISL
61 * usage bits or else things will fall apart.
64 case VK_IMAGE_ASPECT_DEPTH_BIT
:
65 isl_usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
67 case VK_IMAGE_ASPECT_STENCIL_BIT
:
68 isl_usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
70 case VK_IMAGE_ASPECT_COLOR_BIT
:
71 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
:
72 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR
:
73 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR
:
76 unreachable("bad VkImageAspect");
79 if (vk_usage
& VK_IMAGE_USAGE_TRANSFER_SRC_BIT
) {
80 /* blorp implements transfers by sampling from the source image. */
81 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
84 if (vk_usage
& VK_IMAGE_USAGE_TRANSFER_DST_BIT
&&
85 aspect
== VK_IMAGE_ASPECT_COLOR_BIT
) {
86 /* blorp implements transfers by rendering into the destination image.
87 * Only request this with color images, as we deal with depth/stencil
88 * formats differently. */
89 isl_usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
96 * Exactly one bit must be set in \a aspect.
98 static struct anv_surface
*
99 get_surface(struct anv_image
*image
, VkImageAspectFlags aspect
)
101 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
102 return &image
->planes
[plane
].surface
;
106 add_surface(struct anv_image
*image
, struct anv_surface
*surf
, uint32_t plane
)
108 assert(surf
->isl
.size
> 0); /* isl surface must be initialized */
110 if (image
->disjoint
) {
111 surf
->offset
= align_u32(image
->planes
[plane
].size
, surf
->isl
.alignment
);
112 /* Plane offset is always 0 when it's disjoint. */
114 surf
->offset
= align_u32(image
->size
, surf
->isl
.alignment
);
115 /* Determine plane's offset only once when the first surface is added. */
116 if (image
->planes
[plane
].size
== 0)
117 image
->planes
[plane
].offset
= image
->size
;
120 image
->size
= surf
->offset
+ surf
->isl
.size
;
121 image
->planes
[plane
].size
= (surf
->offset
+ surf
->isl
.size
) - image
->planes
[plane
].offset
;
123 image
->alignment
= MAX2(image
->alignment
, surf
->isl
.alignment
);
124 image
->planes
[plane
].alignment
= MAX2(image
->planes
[plane
].alignment
,
125 surf
->isl
.alignment
);
130 all_formats_ccs_e_compatible(const struct gen_device_info
*devinfo
,
131 const struct VkImageCreateInfo
*vk_info
)
133 enum isl_format format
=
134 anv_get_isl_format(devinfo
, vk_info
->format
,
135 VK_IMAGE_ASPECT_COLOR_BIT
, vk_info
->tiling
);
137 if (!isl_format_supports_ccs_e(devinfo
, format
))
140 if (!(vk_info
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
))
143 const VkImageFormatListCreateInfoKHR
*fmt_list
=
144 vk_find_struct_const(vk_info
->pNext
, IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
146 if (!fmt_list
|| fmt_list
->viewFormatCount
== 0)
149 for (uint32_t i
= 0; i
< fmt_list
->viewFormatCount
; i
++) {
150 enum isl_format view_format
=
151 anv_get_isl_format(devinfo
, fmt_list
->pViewFormats
[i
],
152 VK_IMAGE_ASPECT_COLOR_BIT
, vk_info
->tiling
);
154 if (!isl_formats_are_ccs_e_compatible(devinfo
, format
, view_format
))
162 * For color images that have an auxiliary surface, request allocation for an
163 * additional buffer that mainly stores fast-clear values. Use of this buffer
164 * allows us to access the image's subresources while being aware of their
165 * fast-clear values in non-trivial cases (e.g., outside of a render pass in
166 * which a fast clear has occurred).
168 * For the purpose of discoverability, the algorithm used to manage this buffer
169 * is described here. A clear value in this buffer is updated when a fast clear
170 * is performed on a subresource. One of two synchronization operations is
171 * performed in order for a following memory access to use the fast-clear
173 * a. Copy the value from the buffer to the surface state object used for
174 * reading. This is done implicitly when the value is the clear value
175 * predetermined to be the default in other surface state objects. This
176 * is currently only done explicitly for the operation below.
177 * b. Do (a) and use the surface state object to resolve the subresource.
178 * This is only done during layout transitions for decent performance.
180 * With the above scheme, we can fast-clear whenever the hardware allows except
181 * for two cases in which synchronization becomes impossible or undesirable:
182 * * The subresource is in the GENERAL layout and is cleared to a value
183 * other than the special default value.
185 * Performing a synchronization operation in order to read from the
186 * subresource is undesirable in this case. Firstly, b) is not an option
187 * because a layout transition isn't required between a write and read of
188 * an image in the GENERAL layout. Secondly, it's undesirable to do a)
189 * explicitly because it would require large infrastructural changes. The
190 * Vulkan API supports us in deciding not to optimize this layout by
191 * stating that using this layout may cause suboptimal performance. NOTE:
192 * the auxiliary buffer must always be enabled to support a) implicitly.
195 * * For the given miplevel, only some of the layers are cleared at once.
197 * If the user clears each layer to a different value, then tries to
198 * render to multiple layers at once, we have no ability to perform a
199 * synchronization operation in between. a) is not helpful because the
200 * object can only hold one clear value. b) is not an option because a
201 * layout transition isn't required in this case.
204 add_fast_clear_state_buffer(struct anv_image
*image
,
205 VkImageAspectFlagBits aspect
,
207 const struct anv_device
*device
)
209 assert(image
&& device
);
210 assert(image
->planes
[plane
].aux_surface
.isl
.size
> 0 &&
211 image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT
);
213 /* The offset to the buffer of clear values must be dword-aligned for GPU
214 * memcpy operations. It is located immediately after the auxiliary surface.
217 /* Tiled images are guaranteed to be 4K aligned, so the image alignment
218 * should also be dword-aligned.
220 assert(image
->alignment
% 4 == 0);
222 /* Auxiliary buffers should be a multiple of 4K, so the start of the clear
223 * values buffer should already be dword-aligned.
225 assert((image
->planes
[plane
].offset
+ image
->planes
[plane
].size
) % 4 == 0);
227 /* This buffer should be at the very end of the plane. */
228 if (image
->disjoint
) {
229 assert(image
->planes
[plane
].size
==
230 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
232 assert(image
->size
==
233 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
236 const unsigned entry_size
= anv_fast_clear_state_entry_size(device
);
237 /* There's no padding between entries, so ensure that they're always a
238 * multiple of 32 bits in order to enable GPU memcpy operations.
240 assert(entry_size
% 4 == 0);
242 const unsigned plane_state_size
=
243 entry_size
* anv_image_aux_levels(image
, aspect
);
245 image
->planes
[plane
].fast_clear_state_offset
=
246 image
->planes
[plane
].offset
+ image
->planes
[plane
].size
;
248 image
->planes
[plane
].size
+= plane_state_size
;
249 image
->size
+= plane_state_size
;
253 * Initialize the anv_image::*_surface selected by \a aspect. Then update the
254 * image's memory requirements (that is, the image's size and alignment).
256 * Exactly one bit must be set in \a aspect.
259 make_surface(const struct anv_device
*dev
,
260 struct anv_image
*image
,
261 const struct anv_image_create_info
*anv_info
,
262 VkImageAspectFlags aspect
)
264 const VkImageCreateInfo
*vk_info
= anv_info
->vk_info
;
267 static const enum isl_surf_dim vk_to_isl_surf_dim
[] = {
268 [VK_IMAGE_TYPE_1D
] = ISL_SURF_DIM_1D
,
269 [VK_IMAGE_TYPE_2D
] = ISL_SURF_DIM_2D
,
270 [VK_IMAGE_TYPE_3D
] = ISL_SURF_DIM_3D
,
273 /* Translate the Vulkan tiling to an equivalent ISL tiling, then filter the
274 * result with an optionally provided ISL tiling argument.
276 isl_tiling_flags_t tiling_flags
=
277 (vk_info
->tiling
== VK_IMAGE_TILING_LINEAR
) ?
278 ISL_TILING_LINEAR_BIT
: ISL_TILING_ANY_MASK
;
280 if (anv_info
->isl_tiling_flags
)
281 tiling_flags
&= anv_info
->isl_tiling_flags
;
283 assert(tiling_flags
);
285 image
->extent
= anv_sanitize_image_extent(vk_info
->imageType
,
288 const unsigned plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
289 const struct anv_format_plane plane_format
=
290 anv_get_format_plane(&dev
->info
, image
->vk_format
, aspect
, image
->tiling
);
291 struct anv_surface
*anv_surf
= &image
->planes
[plane
].surface
;
293 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
294 * fall back to linear on Broadwell and earlier because we aren't
295 * guaranteed that we can handle offsets correctly. On Sky Lake, the
296 * horizontal and vertical alignments are sufficiently high that we can
297 * just use RENDER_SURFACE_STATE::X/Y Offset.
299 bool needs_shadow
= false;
300 if (dev
->info
.gen
<= 8 &&
301 (vk_info
->flags
& VK_IMAGE_CREATE_BLOCK_TEXEL_VIEW_COMPATIBLE_BIT_KHR
) &&
302 vk_info
->tiling
== VK_IMAGE_TILING_OPTIMAL
) {
303 assert(isl_format_is_compressed(plane_format
.isl_format
));
304 tiling_flags
= ISL_TILING_LINEAR_BIT
;
308 ok
= isl_surf_init(&dev
->isl_dev
, &anv_surf
->isl
,
309 .dim
= vk_to_isl_surf_dim
[vk_info
->imageType
],
310 .format
= plane_format
.isl_format
,
311 .width
= image
->extent
.width
/ plane_format
.denominator_scales
[0],
312 .height
= image
->extent
.height
/ plane_format
.denominator_scales
[1],
313 .depth
= image
->extent
.depth
,
314 .levels
= vk_info
->mipLevels
,
315 .array_len
= vk_info
->arrayLayers
,
316 .samples
= vk_info
->samples
,
318 .row_pitch
= anv_info
->stride
,
319 .usage
= choose_isl_surf_usage(vk_info
->flags
, image
->usage
, aspect
),
320 .tiling_flags
= tiling_flags
);
322 /* isl_surf_init() will fail only if provided invalid input. Invalid input
323 * is illegal in Vulkan.
327 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_NONE
;
329 add_surface(image
, anv_surf
, plane
);
331 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
332 * create an identical tiled shadow surface for use while texturing so we
333 * don't get garbage performance.
336 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
337 assert(tiling_flags
== ISL_TILING_LINEAR_BIT
);
339 ok
= isl_surf_init(&dev
->isl_dev
, &image
->planes
[plane
].shadow_surface
.isl
,
340 .dim
= vk_to_isl_surf_dim
[vk_info
->imageType
],
341 .format
= plane_format
.isl_format
,
342 .width
= image
->extent
.width
,
343 .height
= image
->extent
.height
,
344 .depth
= image
->extent
.depth
,
345 .levels
= vk_info
->mipLevels
,
346 .array_len
= vk_info
->arrayLayers
,
347 .samples
= vk_info
->samples
,
349 .row_pitch
= anv_info
->stride
,
350 .usage
= choose_isl_surf_usage(image
->usage
, image
->usage
, aspect
),
351 .tiling_flags
= ISL_TILING_ANY_MASK
);
353 /* isl_surf_init() will fail only if provided invalid input. Invalid input
354 * is illegal in Vulkan.
358 add_surface(image
, &image
->planes
[plane
].shadow_surface
, plane
);
361 /* Add a HiZ surface to a depth buffer that will be used for rendering.
363 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
364 /* We don't advertise that depth buffers could be used as storage
367 assert(!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
));
369 /* Allow the user to control HiZ enabling. Disable by default on gen7
370 * because resolves are not currently implemented pre-BDW.
372 if (!(image
->usage
& VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) {
373 /* It will never be used as an attachment, HiZ is pointless. */
374 } else if (dev
->info
.gen
== 7) {
375 anv_perf_warn(dev
->instance
, image
, "Implement gen7 HiZ");
376 } else if (vk_info
->mipLevels
> 1) {
377 anv_perf_warn(dev
->instance
, image
, "Enable multi-LOD HiZ");
378 } else if (vk_info
->arrayLayers
> 1) {
379 anv_perf_warn(dev
->instance
, image
,
380 "Implement multi-arrayLayer HiZ clears and resolves");
381 } else if (dev
->info
.gen
== 8 && vk_info
->samples
> 1) {
382 anv_perf_warn(dev
->instance
, image
, "Enable gen8 multisampled HiZ");
383 } else if (!unlikely(INTEL_DEBUG
& DEBUG_NO_HIZ
)) {
384 assert(image
->planes
[plane
].aux_surface
.isl
.size
== 0);
385 ok
= isl_surf_get_hiz_surf(&dev
->isl_dev
,
386 &image
->planes
[plane
].surface
.isl
,
387 &image
->planes
[plane
].aux_surface
.isl
);
389 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
390 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_HIZ
;
392 } else if ((aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT
) && vk_info
->samples
== 1) {
393 /* TODO: Disallow compression with :
395 * 1) non multiplanar images (We appear to hit a sampler bug with
396 * CCS & R16G16 format. Putting the clear state a page/4096bytes
397 * further fixes the issue).
399 * 2) alias images, because they might be aliases of images
402 * 3) compression disabled by debug
404 const bool allow_compression
=
405 image
->n_planes
== 1 &&
406 (vk_info
->flags
& VK_IMAGE_CREATE_ALIAS_BIT_KHR
) == 0 &&
407 likely((INTEL_DEBUG
& DEBUG_NO_RBC
) == 0);
409 if (allow_compression
) {
410 assert(image
->planes
[plane
].aux_surface
.isl
.size
== 0);
411 ok
= isl_surf_get_ccs_surf(&dev
->isl_dev
,
412 &image
->planes
[plane
].surface
.isl
,
413 &image
->planes
[plane
].aux_surface
.isl
, 0);
416 /* Disable CCS when it is not useful (i.e., when you can't render
417 * to the image with CCS enabled).
419 if (!isl_format_supports_rendering(&dev
->info
,
420 plane_format
.isl_format
)) {
421 /* While it may be technically possible to enable CCS for this
422 * image, we currently don't have things hooked up to get it
425 anv_perf_warn(dev
->instance
, image
,
426 "This image format doesn't support rendering. "
427 "Not allocating an CCS buffer.");
428 image
->planes
[plane
].aux_surface
.isl
.size
= 0;
432 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
433 add_fast_clear_state_buffer(image
, aspect
, plane
, dev
);
435 /* For images created without MUTABLE_FORMAT_BIT set, we know that
436 * they will always be used with the original format. In
437 * particular, they will always be used with a format that
438 * supports color compression. If it's never used as a storage
439 * image, then it will only be used through the sampler or the as
440 * a render target. This means that it's safe to just leave
441 * compression on at all times for these formats.
443 if (!(vk_info
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) &&
444 all_formats_ccs_e_compatible(&dev
->info
, vk_info
)) {
445 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_CCS_E
;
449 } else if ((aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT
) && vk_info
->samples
> 1) {
450 assert(!(vk_info
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
));
451 assert(image
->planes
[plane
].aux_surface
.isl
.size
== 0);
452 ok
= isl_surf_get_mcs_surf(&dev
->isl_dev
,
453 &image
->planes
[plane
].surface
.isl
,
454 &image
->planes
[plane
].aux_surface
.isl
);
456 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
457 add_fast_clear_state_buffer(image
, aspect
, plane
, dev
);
458 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_MCS
;
462 assert((image
->planes
[plane
].offset
+ image
->planes
[plane
].size
) == image
->size
);
464 /* Upper bound of the last surface should be smaller than the plane's
467 assert((MAX2(image
->planes
[plane
].surface
.offset
,
468 image
->planes
[plane
].aux_surface
.offset
) +
469 (image
->planes
[plane
].aux_surface
.isl
.size
> 0 ?
470 image
->planes
[plane
].aux_surface
.isl
.size
:
471 image
->planes
[plane
].surface
.isl
.size
)) <=
472 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
474 if (image
->planes
[plane
].aux_surface
.isl
.size
) {
475 /* assert(image->planes[plane].fast_clear_state_offset == */
476 /* (image->planes[plane].aux_surface.offset + image->planes[plane].aux_surface.isl.size)); */
477 assert(image
->planes
[plane
].fast_clear_state_offset
<
478 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
485 anv_image_create(VkDevice _device
,
486 const struct anv_image_create_info
*create_info
,
487 const VkAllocationCallbacks
* alloc
,
490 ANV_FROM_HANDLE(anv_device
, device
, _device
);
491 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
492 struct anv_image
*image
= NULL
;
495 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
497 anv_assert(pCreateInfo
->mipLevels
> 0);
498 anv_assert(pCreateInfo
->arrayLayers
> 0);
499 anv_assert(pCreateInfo
->samples
> 0);
500 anv_assert(pCreateInfo
->extent
.width
> 0);
501 anv_assert(pCreateInfo
->extent
.height
> 0);
502 anv_assert(pCreateInfo
->extent
.depth
> 0);
504 image
= vk_zalloc2(&device
->alloc
, alloc
, sizeof(*image
), 8,
505 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
507 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
509 image
->type
= pCreateInfo
->imageType
;
510 image
->extent
= pCreateInfo
->extent
;
511 image
->vk_format
= pCreateInfo
->format
;
512 image
->format
= anv_get_format(pCreateInfo
->format
);
513 image
->aspects
= vk_format_aspects(image
->vk_format
);
514 image
->levels
= pCreateInfo
->mipLevels
;
515 image
->array_size
= pCreateInfo
->arrayLayers
;
516 image
->samples
= pCreateInfo
->samples
;
517 image
->usage
= pCreateInfo
->usage
;
518 image
->tiling
= pCreateInfo
->tiling
;
519 image
->disjoint
= pCreateInfo
->flags
& VK_IMAGE_CREATE_DISJOINT_BIT_KHR
;
521 const struct anv_format
*format
= anv_get_format(image
->vk_format
);
522 assert(format
!= NULL
);
524 image
->n_planes
= format
->n_planes
;
527 for_each_bit(b
, image
->aspects
) {
528 r
= make_surface(device
, image
, create_info
, (1 << b
));
533 *pImage
= anv_image_to_handle(image
);
539 vk_free2(&device
->alloc
, alloc
, image
);
545 anv_CreateImage(VkDevice device
,
546 const VkImageCreateInfo
*pCreateInfo
,
547 const VkAllocationCallbacks
*pAllocator
,
550 return anv_image_create(device
,
551 &(struct anv_image_create_info
) {
552 .vk_info
= pCreateInfo
,
559 anv_DestroyImage(VkDevice _device
, VkImage _image
,
560 const VkAllocationCallbacks
*pAllocator
)
562 ANV_FROM_HANDLE(anv_device
, device
, _device
);
563 ANV_FROM_HANDLE(anv_image
, image
, _image
);
568 vk_free2(&device
->alloc
, pAllocator
, image
);
571 static void anv_image_bind_memory_plane(struct anv_device
*device
,
572 struct anv_image
*image
,
574 struct anv_device_memory
*memory
,
575 uint32_t memory_offset
)
578 image
->planes
[plane
].bo
= NULL
;
579 image
->planes
[plane
].bo_offset
= 0;
582 image
->planes
[plane
].bo
= memory
->bo
;
583 image
->planes
[plane
].bo_offset
= memory_offset
;
586 VkResult
anv_BindImageMemory(
589 VkDeviceMemory _memory
,
590 VkDeviceSize memoryOffset
)
592 ANV_FROM_HANDLE(anv_device
, device
, _device
);
593 ANV_FROM_HANDLE(anv_device_memory
, mem
, _memory
);
594 ANV_FROM_HANDLE(anv_image
, image
, _image
);
597 anv_foreach_image_aspect_bit(aspect_bit
, image
, image
->aspects
) {
599 anv_image_aspect_to_plane(image
->aspects
, 1UL << aspect_bit
);
600 anv_image_bind_memory_plane(device
, image
, plane
, mem
, memoryOffset
);
606 VkResult
anv_BindImageMemory2KHR(
608 uint32_t bindInfoCount
,
609 const VkBindImageMemoryInfoKHR
* pBindInfos
)
611 ANV_FROM_HANDLE(anv_device
, device
, _device
);
613 for (uint32_t i
= 0; i
< bindInfoCount
; i
++) {
614 const VkBindImageMemoryInfoKHR
*bind_info
= &pBindInfos
[i
];
615 ANV_FROM_HANDLE(anv_device_memory
, mem
, bind_info
->memory
);
616 ANV_FROM_HANDLE(anv_image
, image
, bind_info
->image
);
617 VkImageAspectFlags aspects
= image
->aspects
;
619 vk_foreach_struct_const(s
, bind_info
->pNext
) {
621 case VK_STRUCTURE_TYPE_BIND_IMAGE_PLANE_MEMORY_INFO_KHR
: {
622 const VkBindImagePlaneMemoryInfoKHR
*plane_info
=
623 (const VkBindImagePlaneMemoryInfoKHR
*) s
;
625 aspects
= plane_info
->planeAspect
;
629 anv_debug_ignored_stype(s
->sType
);
635 anv_foreach_image_aspect_bit(aspect_bit
, image
, aspects
) {
637 anv_image_aspect_to_plane(image
->aspects
, 1UL << aspect_bit
);
638 anv_image_bind_memory_plane(device
, image
, plane
,
639 mem
, bind_info
->memoryOffset
);
647 anv_surface_get_subresource_layout(struct anv_image
*image
,
648 struct anv_surface
*surface
,
649 const VkImageSubresource
*subresource
,
650 VkSubresourceLayout
*layout
)
652 /* If we are on a non-zero mip level or array slice, we need to
653 * calculate a real offset.
655 anv_assert(subresource
->mipLevel
== 0);
656 anv_assert(subresource
->arrayLayer
== 0);
658 layout
->offset
= surface
->offset
;
659 layout
->rowPitch
= surface
->isl
.row_pitch
;
660 layout
->depthPitch
= isl_surf_get_array_pitch(&surface
->isl
);
661 layout
->arrayPitch
= isl_surf_get_array_pitch(&surface
->isl
);
662 layout
->size
= surface
->isl
.size
;
665 void anv_GetImageSubresourceLayout(
668 const VkImageSubresource
* pSubresource
,
669 VkSubresourceLayout
* pLayout
)
671 ANV_FROM_HANDLE(anv_image
, image
, _image
);
673 assert(__builtin_popcount(pSubresource
->aspectMask
) == 1);
675 anv_surface_get_subresource_layout(image
,
677 pSubresource
->aspectMask
),
678 pSubresource
, pLayout
);
682 * This function determines the optimal buffer to use for a given
683 * VkImageLayout and other pieces of information needed to make that
684 * determination. This does not determine the optimal buffer to use
685 * during a resolve operation.
687 * @param devinfo The device information of the Intel GPU.
688 * @param image The image that may contain a collection of buffers.
689 * @param plane The plane of the image to be accessed.
690 * @param layout The current layout of the image aspect(s).
692 * @return The primary buffer that should be used for the given layout.
695 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
696 const struct anv_image
* const image
,
697 const VkImageAspectFlagBits aspect
,
698 const VkImageLayout layout
)
700 /* Validate the inputs. */
702 /* The devinfo is needed as the optimal buffer varies across generations. */
703 assert(devinfo
!= NULL
);
705 /* The layout of a NULL image is not properly defined. */
706 assert(image
!= NULL
);
708 /* The aspect must be exactly one of the image aspects. */
709 assert(_mesa_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
711 /* Determine the optimal buffer. */
713 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
715 /* If there is no auxiliary surface allocated, we must use the one and only
718 if (image
->planes
[plane
].aux_surface
.isl
.size
== 0)
719 return ISL_AUX_USAGE_NONE
;
721 /* All images that use an auxiliary surface are required to be tiled. */
722 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
724 /* Stencil has no aux */
725 assert(aspect
!= VK_IMAGE_ASPECT_STENCIL_BIT
);
727 /* The following switch currently only handles depth stencil aspects.
728 * TODO: Handle the color aspect.
730 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT
)
731 return image
->planes
[plane
].aux_usage
;
735 /* Invalid Layouts */
736 case VK_IMAGE_LAYOUT_RANGE_SIZE
:
737 case VK_IMAGE_LAYOUT_MAX_ENUM
:
738 unreachable("Invalid image layout.");
742 * The pre-initialized layout is equivalent to the undefined layout for
743 * optimally-tiled images. We can only do color compression (CCS or HiZ)
746 case VK_IMAGE_LAYOUT_UNDEFINED
:
747 case VK_IMAGE_LAYOUT_PREINITIALIZED
:
748 return ISL_AUX_USAGE_NONE
;
753 * This buffer could be a depth buffer used in a transfer operation. BLORP
754 * currently doesn't use HiZ for transfer operations so we must use the main
755 * buffer for this layout. TODO: Enable HiZ in BLORP.
757 case VK_IMAGE_LAYOUT_GENERAL
:
758 case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
:
759 case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
:
760 return ISL_AUX_USAGE_NONE
;
763 /* Sampling Layouts */
764 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL
:
765 assert((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT
) == 0);
767 case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
:
768 case VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL_KHR
:
769 assert(aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
);
770 if (anv_can_sample_with_hiz(devinfo
, image
))
771 return ISL_AUX_USAGE_HIZ
;
773 return ISL_AUX_USAGE_NONE
;
775 case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR
:
776 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
778 /* On SKL+, the render buffer can be decompressed by the presentation
779 * engine. Support for this feature has not yet landed in the wider
780 * ecosystem. TODO: Update this code when support lands.
782 * From the BDW PRM, Vol 7, Render Target Resolve:
784 * If the MCS is enabled on a non-multisampled render target, the
785 * render target must be resolved before being used for other
786 * purposes (display, texture, CPU lock) The clear value from
787 * SURFACE_STATE is written into pixels in the render target
788 * indicated as clear in the MCS.
790 * Pre-SKL, the render buffer must be resolved before being used for
791 * presentation. We can infer that the auxiliary buffer is not used.
793 return ISL_AUX_USAGE_NONE
;
796 /* Rendering Layouts */
797 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
:
798 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
799 unreachable("Color images are not yet supported.");
801 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
:
802 case VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL_KHR
:
803 assert(aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
);
804 return ISL_AUX_USAGE_HIZ
;
806 case VK_IMAGE_LAYOUT_SHARED_PRESENT_KHR
:
807 unreachable("VK_KHR_shared_presentable_image is unsupported");
810 /* If the layout isn't recognized in the exhaustive switch above, the
811 * VkImageLayout value is not defined in vulkan.h.
813 unreachable("layout is not a VkImageLayout enumeration member.");
817 static struct anv_state
818 alloc_surface_state(struct anv_device
*device
)
820 return anv_state_pool_alloc(&device
->surface_state_pool
, 64, 64);
823 static enum isl_channel_select
824 remap_swizzle(VkComponentSwizzle swizzle
, VkComponentSwizzle component
,
825 struct isl_swizzle format_swizzle
)
827 if (swizzle
== VK_COMPONENT_SWIZZLE_IDENTITY
)
831 case VK_COMPONENT_SWIZZLE_ZERO
: return ISL_CHANNEL_SELECT_ZERO
;
832 case VK_COMPONENT_SWIZZLE_ONE
: return ISL_CHANNEL_SELECT_ONE
;
833 case VK_COMPONENT_SWIZZLE_R
: return format_swizzle
.r
;
834 case VK_COMPONENT_SWIZZLE_G
: return format_swizzle
.g
;
835 case VK_COMPONENT_SWIZZLE_B
: return format_swizzle
.b
;
836 case VK_COMPONENT_SWIZZLE_A
: return format_swizzle
.a
;
838 unreachable("Invalid swizzle");
843 anv_image_fill_surface_state(struct anv_device
*device
,
844 const struct anv_image
*image
,
845 VkImageAspectFlagBits aspect
,
846 const struct isl_view
*view_in
,
847 isl_surf_usage_flags_t view_usage
,
848 enum isl_aux_usage aux_usage
,
849 const union isl_color_value
*clear_color
,
850 enum anv_image_view_state_flags flags
,
851 struct anv_surface_state
*state_inout
,
852 struct brw_image_param
*image_param_out
)
854 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
856 const struct anv_surface
*surface
= &image
->planes
[plane
].surface
,
857 *aux_surface
= &image
->planes
[plane
].aux_surface
;
859 struct isl_view view
= *view_in
;
860 view
.usage
|= view_usage
;
862 /* For texturing with VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL from a
863 * compressed surface with a shadow surface, we use the shadow instead of
864 * the primary surface. The shadow surface will be tiled, unlike the main
865 * surface, so it should get significantly better performance.
867 if (image
->planes
[plane
].shadow_surface
.isl
.size
> 0 &&
868 isl_format_is_compressed(view
.format
) &&
869 (flags
& ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
)) {
870 assert(isl_format_is_compressed(surface
->isl
.format
));
871 assert(surface
->isl
.tiling
== ISL_TILING_LINEAR
);
872 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
873 surface
= &image
->planes
[plane
].shadow_surface
;
876 if (view_usage
== ISL_SURF_USAGE_RENDER_TARGET_BIT
)
877 view
.swizzle
= anv_swizzle_for_render(view
.swizzle
);
879 /* If this is a HiZ buffer we can sample from with a programmable clear
880 * value (SKL+), define the clear value to the optimal constant.
882 union isl_color_value default_clear_color
= { .u32
= { 0, } };
883 if (device
->info
.gen
>= 9 && aux_usage
== ISL_AUX_USAGE_HIZ
)
884 default_clear_color
.f32
[0] = ANV_HZ_FC_VAL
;
886 clear_color
= &default_clear_color
;
888 const uint64_t address
= image
->planes
[plane
].bo_offset
+ surface
->offset
;
889 const uint64_t aux_address
= aux_usage
== ISL_AUX_USAGE_NONE
?
890 0 : (image
->planes
[plane
].bo_offset
+ aux_surface
->offset
);
892 if (view_usage
== ISL_SURF_USAGE_STORAGE_BIT
&&
893 !(flags
& ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
) &&
894 !isl_has_matching_typed_storage_image_format(&device
->info
,
896 /* In this case, we are a writeable storage buffer which needs to be
897 * lowered to linear. All tiling and offset calculations will be done in
900 assert(aux_usage
== ISL_AUX_USAGE_NONE
);
901 isl_buffer_fill_state(&device
->isl_dev
, state_inout
->state
.map
,
903 .size
= surface
->isl
.size
,
904 .format
= ISL_FORMAT_RAW
,
906 .mocs
= device
->default_mocs
);
907 state_inout
->address
= address
,
908 state_inout
->aux_address
= 0;
910 if (view_usage
== ISL_SURF_USAGE_STORAGE_BIT
&&
911 !(flags
& ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
)) {
912 /* Typed surface reads support a very limited subset of the shader
913 * image formats. Translate it into the closest format the hardware
916 assert(aux_usage
== ISL_AUX_USAGE_NONE
);
917 view
.format
= isl_lower_storage_image_format(&device
->info
,
921 const struct isl_surf
*isl_surf
= &surface
->isl
;
923 struct isl_surf tmp_surf
;
924 uint32_t offset_B
= 0, tile_x_sa
= 0, tile_y_sa
= 0;
925 if (isl_format_is_compressed(surface
->isl
.format
) &&
926 !isl_format_is_compressed(view
.format
)) {
927 /* We're creating an uncompressed view of a compressed surface. This
928 * is allowed but only for a single level/layer.
930 assert(surface
->isl
.samples
== 1);
931 assert(view
.levels
== 1);
932 assert(view
.array_len
== 1);
934 isl_surf_get_image_surf(&device
->isl_dev
, isl_surf
,
936 surface
->isl
.dim
== ISL_SURF_DIM_3D
?
937 0 : view
.base_array_layer
,
938 surface
->isl
.dim
== ISL_SURF_DIM_3D
?
939 view
.base_array_layer
: 0,
941 &offset_B
, &tile_x_sa
, &tile_y_sa
);
943 /* The newly created image represents the one subimage we're
944 * referencing with this view so it only has one array slice and
947 view
.base_array_layer
= 0;
950 /* We're making an uncompressed view here. The image dimensions need
951 * to be scaled down by the block size.
953 const struct isl_format_layout
*fmtl
=
954 isl_format_get_layout(surface
->isl
.format
);
955 tmp_surf
.format
= view
.format
;
956 tmp_surf
.logical_level0_px
.width
=
957 DIV_ROUND_UP(tmp_surf
.logical_level0_px
.width
, fmtl
->bw
);
958 tmp_surf
.logical_level0_px
.height
=
959 DIV_ROUND_UP(tmp_surf
.logical_level0_px
.height
, fmtl
->bh
);
960 tmp_surf
.phys_level0_sa
.width
/= fmtl
->bw
;
961 tmp_surf
.phys_level0_sa
.height
/= fmtl
->bh
;
962 tile_x_sa
/= fmtl
->bw
;
963 tile_y_sa
/= fmtl
->bh
;
965 isl_surf
= &tmp_surf
;
967 if (device
->info
.gen
<= 8) {
968 assert(surface
->isl
.tiling
== ISL_TILING_LINEAR
);
969 assert(tile_x_sa
== 0);
970 assert(tile_y_sa
== 0);
974 isl_surf_fill_state(&device
->isl_dev
, state_inout
->state
.map
,
977 .address
= address
+ offset_B
,
978 .clear_color
= *clear_color
,
979 .aux_surf
= &aux_surface
->isl
,
980 .aux_usage
= aux_usage
,
981 .aux_address
= aux_address
,
982 .mocs
= device
->default_mocs
,
983 .x_offset_sa
= tile_x_sa
,
984 .y_offset_sa
= tile_y_sa
);
985 state_inout
->address
= address
+ offset_B
;
986 if (device
->info
.gen
>= 8) {
987 state_inout
->aux_address
= aux_address
;
989 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
990 * used to store other information. This should be ok, however,
991 * because surface buffer addresses are always 4K page alinged.
993 uint32_t *aux_addr_dw
= state_inout
->state
.map
+
994 device
->isl_dev
.ss
.aux_addr_offset
;
995 assert((aux_address
& 0xfff) == 0);
996 assert(aux_address
== (*aux_addr_dw
& 0xfffff000));
997 state_inout
->aux_address
= *aux_addr_dw
;
1001 anv_state_flush(device
, state_inout
->state
);
1003 if (image_param_out
) {
1004 assert(view_usage
== ISL_SURF_USAGE_STORAGE_BIT
);
1005 isl_surf_fill_image_param(&device
->isl_dev
, image_param_out
,
1006 &surface
->isl
, &view
);
1010 static VkImageAspectFlags
1011 remap_aspect_flags(VkImageAspectFlags view_aspects
)
1013 if (view_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT
) {
1014 if (_mesa_bitcount(view_aspects
) == 1)
1015 return VK_IMAGE_ASPECT_COLOR_BIT
;
1017 VkImageAspectFlags color_aspects
= 0;
1018 for (uint32_t i
= 0; i
< _mesa_bitcount(view_aspects
); i
++)
1019 color_aspects
|= VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
<< i
;
1020 return color_aspects
;
1022 /* No special remapping needed for depth & stencil aspects. */
1023 return view_aspects
;
1027 anv_CreateImageView(VkDevice _device
,
1028 const VkImageViewCreateInfo
*pCreateInfo
,
1029 const VkAllocationCallbacks
*pAllocator
,
1032 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1033 ANV_FROM_HANDLE(anv_image
, image
, pCreateInfo
->image
);
1034 struct anv_image_view
*iview
;
1036 iview
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*iview
), 8,
1037 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1039 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1041 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
1043 assert(range
->layerCount
> 0);
1044 assert(range
->baseMipLevel
< image
->levels
);
1046 const VkImageViewUsageCreateInfoKHR
*usage_info
=
1047 vk_find_struct_const(pCreateInfo
, IMAGE_VIEW_USAGE_CREATE_INFO_KHR
);
1048 VkImageUsageFlags view_usage
= usage_info
? usage_info
->usage
: image
->usage
;
1049 /* View usage should be a subset of image usage */
1050 assert((view_usage
& ~image
->usage
) == 0);
1051 assert(view_usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
1052 VK_IMAGE_USAGE_STORAGE_BIT
|
1053 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
1054 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
|
1055 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
));
1057 switch (image
->type
) {
1059 unreachable("bad VkImageType");
1060 case VK_IMAGE_TYPE_1D
:
1061 case VK_IMAGE_TYPE_2D
:
1062 assert(range
->baseArrayLayer
+ anv_get_layerCount(image
, range
) - 1 <= image
->array_size
);
1064 case VK_IMAGE_TYPE_3D
:
1065 assert(range
->baseArrayLayer
+ anv_get_layerCount(image
, range
) - 1
1066 <= anv_minify(image
->extent
.depth
, range
->baseMipLevel
));
1070 /* First expand aspects to the image's ones (for example
1071 * VK_IMAGE_ASPECT_COLOR_BIT will be converted to
1072 * VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | VK_IMAGE_ASPECT_PLANE_1_BIT_KHR |
1073 * VK_IMAGE_ASPECT_PLANE_2_BIT_KHR for an image of format
1074 * VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM_KHR.
1076 VkImageAspectFlags expanded_aspects
=
1077 anv_image_expand_aspects(image
, range
->aspectMask
);
1079 iview
->image
= image
;
1081 /* Remap the expanded aspects for the image view. For example if only
1082 * VK_IMAGE_ASPECT_PLANE_1_BIT_KHR was given in range->aspectMask, we will
1083 * convert it to VK_IMAGE_ASPECT_COLOR_BIT since from the point of view of
1084 * the image view, it only has a single plane.
1086 iview
->aspect_mask
= remap_aspect_flags(expanded_aspects
);
1087 iview
->n_planes
= anv_image_aspect_get_planes(iview
->aspect_mask
);
1088 iview
->vk_format
= pCreateInfo
->format
;
1090 iview
->extent
= (VkExtent3D
) {
1091 .width
= anv_minify(image
->extent
.width
, range
->baseMipLevel
),
1092 .height
= anv_minify(image
->extent
.height
, range
->baseMipLevel
),
1093 .depth
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
),
1096 /* Now go through the underlying image selected planes (computed in
1097 * expanded_aspects) and map them to planes in the image view.
1099 uint32_t iaspect_bit
, vplane
= 0;
1100 anv_foreach_image_aspect_bit(iaspect_bit
, image
, expanded_aspects
) {
1102 anv_image_aspect_to_plane(expanded_aspects
, 1UL << iaspect_bit
);
1103 VkImageAspectFlags vplane_aspect
=
1104 anv_plane_to_aspect(iview
->aspect_mask
, vplane
);
1105 struct anv_format_plane format
=
1106 anv_get_format_plane(&device
->info
, pCreateInfo
->format
,
1107 vplane_aspect
, image
->tiling
);
1109 iview
->planes
[vplane
].image_plane
= iplane
;
1111 iview
->planes
[vplane
].isl
= (struct isl_view
) {
1112 .format
= format
.isl_format
,
1113 .base_level
= range
->baseMipLevel
,
1114 .levels
= anv_get_levelCount(image
, range
),
1115 .base_array_layer
= range
->baseArrayLayer
,
1116 .array_len
= anv_get_layerCount(image
, range
),
1118 .r
= remap_swizzle(pCreateInfo
->components
.r
,
1119 VK_COMPONENT_SWIZZLE_R
, format
.swizzle
),
1120 .g
= remap_swizzle(pCreateInfo
->components
.g
,
1121 VK_COMPONENT_SWIZZLE_G
, format
.swizzle
),
1122 .b
= remap_swizzle(pCreateInfo
->components
.b
,
1123 VK_COMPONENT_SWIZZLE_B
, format
.swizzle
),
1124 .a
= remap_swizzle(pCreateInfo
->components
.a
,
1125 VK_COMPONENT_SWIZZLE_A
, format
.swizzle
),
1129 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_3D
) {
1130 iview
->planes
[vplane
].isl
.base_array_layer
= 0;
1131 iview
->planes
[vplane
].isl
.array_len
= iview
->extent
.depth
;
1134 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_CUBE
||
1135 pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
) {
1136 iview
->planes
[vplane
].isl
.usage
= ISL_SURF_USAGE_CUBE_BIT
;
1138 iview
->planes
[vplane
].isl
.usage
= 0;
1141 if (view_usage
& VK_IMAGE_USAGE_SAMPLED_BIT
||
1142 (view_usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
&&
1143 !(iview
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
))) {
1144 iview
->planes
[vplane
].optimal_sampler_surface_state
.state
= alloc_surface_state(device
);
1145 iview
->planes
[vplane
].general_sampler_surface_state
.state
= alloc_surface_state(device
);
1147 enum isl_aux_usage general_aux_usage
=
1148 anv_layout_to_aux_usage(&device
->info
, image
, 1UL << iaspect_bit
,
1149 VK_IMAGE_LAYOUT_GENERAL
);
1150 enum isl_aux_usage optimal_aux_usage
=
1151 anv_layout_to_aux_usage(&device
->info
, image
, 1UL << iaspect_bit
,
1152 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
1154 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1155 &iview
->planes
[vplane
].isl
,
1156 ISL_SURF_USAGE_TEXTURE_BIT
,
1157 optimal_aux_usage
, NULL
,
1158 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
,
1159 &iview
->planes
[vplane
].optimal_sampler_surface_state
,
1162 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1163 &iview
->planes
[vplane
].isl
,
1164 ISL_SURF_USAGE_TEXTURE_BIT
,
1165 general_aux_usage
, NULL
,
1167 &iview
->planes
[vplane
].general_sampler_surface_state
,
1171 /* NOTE: This one needs to go last since it may stomp isl_view.format */
1172 if (view_usage
& VK_IMAGE_USAGE_STORAGE_BIT
) {
1173 iview
->planes
[vplane
].storage_surface_state
.state
= alloc_surface_state(device
);
1174 iview
->planes
[vplane
].writeonly_storage_surface_state
.state
= alloc_surface_state(device
);
1176 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1177 &iview
->planes
[vplane
].isl
,
1178 ISL_SURF_USAGE_STORAGE_BIT
,
1179 ISL_AUX_USAGE_NONE
, NULL
,
1181 &iview
->planes
[vplane
].storage_surface_state
,
1182 &iview
->planes
[vplane
].storage_image_param
);
1184 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1185 &iview
->planes
[vplane
].isl
,
1186 ISL_SURF_USAGE_STORAGE_BIT
,
1187 ISL_AUX_USAGE_NONE
, NULL
,
1188 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
,
1189 &iview
->planes
[vplane
].writeonly_storage_surface_state
,
1196 *pView
= anv_image_view_to_handle(iview
);
1202 anv_DestroyImageView(VkDevice _device
, VkImageView _iview
,
1203 const VkAllocationCallbacks
*pAllocator
)
1205 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1206 ANV_FROM_HANDLE(anv_image_view
, iview
, _iview
);
1211 for (uint32_t plane
= 0; plane
< iview
->n_planes
; plane
++) {
1212 if (iview
->planes
[plane
].optimal_sampler_surface_state
.state
.alloc_size
> 0) {
1213 anv_state_pool_free(&device
->surface_state_pool
,
1214 iview
->planes
[plane
].optimal_sampler_surface_state
.state
);
1217 if (iview
->planes
[plane
].general_sampler_surface_state
.state
.alloc_size
> 0) {
1218 anv_state_pool_free(&device
->surface_state_pool
,
1219 iview
->planes
[plane
].general_sampler_surface_state
.state
);
1222 if (iview
->planes
[plane
].storage_surface_state
.state
.alloc_size
> 0) {
1223 anv_state_pool_free(&device
->surface_state_pool
,
1224 iview
->planes
[plane
].storage_surface_state
.state
);
1227 if (iview
->planes
[plane
].writeonly_storage_surface_state
.state
.alloc_size
> 0) {
1228 anv_state_pool_free(&device
->surface_state_pool
,
1229 iview
->planes
[plane
].writeonly_storage_surface_state
.state
);
1233 vk_free2(&device
->alloc
, pAllocator
, iview
);
1238 anv_CreateBufferView(VkDevice _device
,
1239 const VkBufferViewCreateInfo
*pCreateInfo
,
1240 const VkAllocationCallbacks
*pAllocator
,
1241 VkBufferView
*pView
)
1243 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1244 ANV_FROM_HANDLE(anv_buffer
, buffer
, pCreateInfo
->buffer
);
1245 struct anv_buffer_view
*view
;
1247 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1248 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1250 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1252 /* TODO: Handle the format swizzle? */
1254 view
->format
= anv_get_isl_format(&device
->info
, pCreateInfo
->format
,
1255 VK_IMAGE_ASPECT_COLOR_BIT
,
1256 VK_IMAGE_TILING_LINEAR
);
1257 const uint32_t format_bs
= isl_format_get_layout(view
->format
)->bpb
/ 8;
1258 view
->bo
= buffer
->bo
;
1259 view
->offset
= buffer
->offset
+ pCreateInfo
->offset
;
1260 view
->range
= anv_buffer_get_range(buffer
, pCreateInfo
->offset
,
1261 pCreateInfo
->range
);
1262 view
->range
= align_down_npot_u32(view
->range
, format_bs
);
1264 if (buffer
->usage
& VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT
) {
1265 view
->surface_state
= alloc_surface_state(device
);
1267 anv_fill_buffer_surface_state(device
, view
->surface_state
,
1269 view
->offset
, view
->range
, format_bs
);
1271 view
->surface_state
= (struct anv_state
){ 0 };
1274 if (buffer
->usage
& VK_BUFFER_USAGE_STORAGE_TEXEL_BUFFER_BIT
) {
1275 view
->storage_surface_state
= alloc_surface_state(device
);
1276 view
->writeonly_storage_surface_state
= alloc_surface_state(device
);
1278 enum isl_format storage_format
=
1279 isl_has_matching_typed_storage_image_format(&device
->info
,
1281 isl_lower_storage_image_format(&device
->info
, view
->format
) :
1284 anv_fill_buffer_surface_state(device
, view
->storage_surface_state
,
1286 view
->offset
, view
->range
,
1287 (storage_format
== ISL_FORMAT_RAW
? 1 :
1288 isl_format_get_layout(storage_format
)->bpb
/ 8));
1290 /* Write-only accesses should use the original format. */
1291 anv_fill_buffer_surface_state(device
, view
->writeonly_storage_surface_state
,
1293 view
->offset
, view
->range
,
1294 isl_format_get_layout(view
->format
)->bpb
/ 8);
1296 isl_buffer_fill_image_param(&device
->isl_dev
,
1297 &view
->storage_image_param
,
1298 view
->format
, view
->range
);
1300 view
->storage_surface_state
= (struct anv_state
){ 0 };
1301 view
->writeonly_storage_surface_state
= (struct anv_state
){ 0 };
1304 *pView
= anv_buffer_view_to_handle(view
);
1310 anv_DestroyBufferView(VkDevice _device
, VkBufferView bufferView
,
1311 const VkAllocationCallbacks
*pAllocator
)
1313 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1314 ANV_FROM_HANDLE(anv_buffer_view
, view
, bufferView
);
1319 if (view
->surface_state
.alloc_size
> 0)
1320 anv_state_pool_free(&device
->surface_state_pool
,
1321 view
->surface_state
);
1323 if (view
->storage_surface_state
.alloc_size
> 0)
1324 anv_state_pool_free(&device
->surface_state_pool
,
1325 view
->storage_surface_state
);
1327 if (view
->writeonly_storage_surface_state
.alloc_size
> 0)
1328 anv_state_pool_free(&device
->surface_state_pool
,
1329 view
->writeonly_storage_surface_state
);
1331 vk_free2(&device
->alloc
, pAllocator
, view
);
1334 const struct anv_surface
*
1335 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
1336 VkImageAspectFlags aspect_mask
)
1338 VkImageAspectFlags sanitized_mask
;
1340 switch (aspect_mask
) {
1341 case VK_IMAGE_ASPECT_COLOR_BIT
:
1342 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1343 sanitized_mask
= VK_IMAGE_ASPECT_COLOR_BIT
;
1345 case VK_IMAGE_ASPECT_DEPTH_BIT
:
1346 assert(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
);
1347 sanitized_mask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
1349 case VK_IMAGE_ASPECT_STENCIL_BIT
:
1350 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
1351 sanitized_mask
= VK_IMAGE_ASPECT_STENCIL_BIT
;
1353 case VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
:
1354 /* FINISHME: The Vulkan spec (git a511ba2) requires support for
1355 * combined depth stencil formats. Specifically, it states:
1357 * At least one of ename:VK_FORMAT_D24_UNORM_S8_UINT or
1358 * ename:VK_FORMAT_D32_SFLOAT_S8_UINT must be supported.
1360 * Image views with both depth and stencil aspects are only valid for
1361 * render target attachments, in which case
1362 * cmd_buffer_emit_depth_stencil() will pick out both the depth and
1363 * stencil surfaces from the underlying surface.
1365 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1366 sanitized_mask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
1368 assert(image
->aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
1369 sanitized_mask
= VK_IMAGE_ASPECT_STENCIL_BIT
;
1372 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
:
1373 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT
) == 0);
1374 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
;
1376 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR
:
1377 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT
) == 0);
1378 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_1_BIT_KHR
;
1380 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR
:
1381 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT
) == 0);
1382 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_2_BIT_KHR
;
1385 unreachable("image does not have aspect");
1389 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, sanitized_mask
);
1390 return &image
->planes
[plane
].surface
;