anv: Add WSI support for the I915_FORMAT_MOD_Y_TILED_CCS
[mesa.git] / src / intel / vulkan / anv_image.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29 #include <sys/mman.h>
30 #include <drm_fourcc.h>
31
32 #include "anv_private.h"
33 #include "util/debug.h"
34 #include "vk_util.h"
35
36 #include "vk_format_info.h"
37
38 static isl_surf_usage_flags_t
39 choose_isl_surf_usage(VkImageCreateFlags vk_create_flags,
40 VkImageUsageFlags vk_usage,
41 isl_surf_usage_flags_t isl_extra_usage,
42 VkImageAspectFlagBits aspect)
43 {
44 isl_surf_usage_flags_t isl_usage = isl_extra_usage;
45
46 if (vk_usage & VK_IMAGE_USAGE_SAMPLED_BIT)
47 isl_usage |= ISL_SURF_USAGE_TEXTURE_BIT;
48
49 if (vk_usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)
50 isl_usage |= ISL_SURF_USAGE_TEXTURE_BIT;
51
52 if (vk_usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT)
53 isl_usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
54
55 if (vk_create_flags & VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT)
56 isl_usage |= ISL_SURF_USAGE_CUBE_BIT;
57
58 /* Even if we're only using it for transfer operations, clears to depth and
59 * stencil images happen as depth and stencil so they need the right ISL
60 * usage bits or else things will fall apart.
61 */
62 switch (aspect) {
63 case VK_IMAGE_ASPECT_DEPTH_BIT:
64 isl_usage |= ISL_SURF_USAGE_DEPTH_BIT;
65 break;
66 case VK_IMAGE_ASPECT_STENCIL_BIT:
67 isl_usage |= ISL_SURF_USAGE_STENCIL_BIT;
68 break;
69 case VK_IMAGE_ASPECT_COLOR_BIT:
70 case VK_IMAGE_ASPECT_PLANE_0_BIT:
71 case VK_IMAGE_ASPECT_PLANE_1_BIT:
72 case VK_IMAGE_ASPECT_PLANE_2_BIT:
73 break;
74 default:
75 unreachable("bad VkImageAspect");
76 }
77
78 if (vk_usage & VK_IMAGE_USAGE_TRANSFER_SRC_BIT) {
79 /* blorp implements transfers by sampling from the source image. */
80 isl_usage |= ISL_SURF_USAGE_TEXTURE_BIT;
81 }
82
83 if (vk_usage & VK_IMAGE_USAGE_TRANSFER_DST_BIT &&
84 aspect == VK_IMAGE_ASPECT_COLOR_BIT) {
85 /* blorp implements transfers by rendering into the destination image.
86 * Only request this with color images, as we deal with depth/stencil
87 * formats differently. */
88 isl_usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
89 }
90
91 return isl_usage;
92 }
93
94 static isl_tiling_flags_t
95 choose_isl_tiling_flags(const struct anv_image_create_info *anv_info,
96 const struct isl_drm_modifier_info *isl_mod_info,
97 bool legacy_scanout)
98 {
99 const VkImageCreateInfo *base_info = anv_info->vk_info;
100 isl_tiling_flags_t flags = 0;
101
102 switch (base_info->tiling) {
103 default:
104 unreachable("bad VkImageTiling");
105 case VK_IMAGE_TILING_OPTIMAL:
106 flags = ISL_TILING_ANY_MASK;
107 break;
108 case VK_IMAGE_TILING_LINEAR:
109 flags = ISL_TILING_LINEAR_BIT;
110 break;
111 }
112
113 if (anv_info->isl_tiling_flags)
114 flags &= anv_info->isl_tiling_flags;
115
116 if (legacy_scanout)
117 flags &= ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT;
118
119 if (isl_mod_info)
120 flags &= 1 << isl_mod_info->tiling;
121
122 assert(flags);
123
124 return flags;
125 }
126
127 static struct anv_surface *
128 get_surface(struct anv_image *image, VkImageAspectFlagBits aspect)
129 {
130 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
131 return &image->planes[plane].surface;
132 }
133
134 static void
135 add_surface(struct anv_image *image, struct anv_surface *surf, uint32_t plane)
136 {
137 assert(surf->isl.size > 0); /* isl surface must be initialized */
138
139 if (image->disjoint) {
140 surf->offset = align_u32(image->planes[plane].size, surf->isl.alignment);
141 /* Plane offset is always 0 when it's disjoint. */
142 } else {
143 surf->offset = align_u32(image->size, surf->isl.alignment);
144 /* Determine plane's offset only once when the first surface is added. */
145 if (image->planes[plane].size == 0)
146 image->planes[plane].offset = image->size;
147 }
148
149 image->size = surf->offset + surf->isl.size;
150 image->planes[plane].size = (surf->offset + surf->isl.size) - image->planes[plane].offset;
151
152 image->alignment = MAX2(image->alignment, surf->isl.alignment);
153 image->planes[plane].alignment = MAX2(image->planes[plane].alignment,
154 surf->isl.alignment);
155 }
156
157
158 static bool
159 all_formats_ccs_e_compatible(const struct gen_device_info *devinfo,
160 const struct VkImageCreateInfo *vk_info)
161 {
162 enum isl_format format =
163 anv_get_isl_format(devinfo, vk_info->format,
164 VK_IMAGE_ASPECT_COLOR_BIT, vk_info->tiling);
165
166 if (!isl_format_supports_ccs_e(devinfo, format))
167 return false;
168
169 if (!(vk_info->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT))
170 return true;
171
172 const VkImageFormatListCreateInfoKHR *fmt_list =
173 vk_find_struct_const(vk_info->pNext, IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
174
175 if (!fmt_list || fmt_list->viewFormatCount == 0)
176 return false;
177
178 for (uint32_t i = 0; i < fmt_list->viewFormatCount; i++) {
179 enum isl_format view_format =
180 anv_get_isl_format(devinfo, fmt_list->pViewFormats[i],
181 VK_IMAGE_ASPECT_COLOR_BIT, vk_info->tiling);
182
183 if (!isl_formats_are_ccs_e_compatible(devinfo, format, view_format))
184 return false;
185 }
186
187 return true;
188 }
189
190 /**
191 * For color images that have an auxiliary surface, request allocation for an
192 * additional buffer that mainly stores fast-clear values. Use of this buffer
193 * allows us to access the image's subresources while being aware of their
194 * fast-clear values in non-trivial cases (e.g., outside of a render pass in
195 * which a fast clear has occurred).
196 *
197 * In order to avoid having multiple clear colors for a single plane of an
198 * image (hence a single RENDER_SURFACE_STATE), we only allow fast-clears on
199 * the first slice (level 0, layer 0). At the time of our testing (Jan 17,
200 * 2018), there were no known applications which would benefit from fast-
201 * clearing more than just the first slice.
202 *
203 * The fast clear portion of the image is laid out in the following order:
204 *
205 * * 1 or 4 dwords (depending on hardware generation) for the clear color
206 * * 1 dword for the anv_fast_clear_type of the clear color
207 * * On gen9+, 1 dword per level and layer of the image (3D levels count
208 * multiple layers) in level-major order for compression state.
209 *
210 * For the purpose of discoverability, the algorithm used to manage
211 * compression and fast-clears is described here:
212 *
213 * * On a transition from UNDEFINED or PREINITIALIZED to a defined layout,
214 * all of the values in the fast clear portion of the image are initialized
215 * to default values.
216 *
217 * * On fast-clear, the clear value is written into surface state and also
218 * into the buffer and the fast clear type is set appropriately. Both
219 * setting the fast-clear value in the buffer and setting the fast-clear
220 * type happen from the GPU using MI commands.
221 *
222 * * Whenever a render or blorp operation is performed with CCS_E, we call
223 * genX(cmd_buffer_mark_image_written) to set the compression state to
224 * true (which is represented by UINT32_MAX).
225 *
226 * * On pipeline barrier transitions, the worst-case transition is computed
227 * from the image layouts. The command streamer inspects the fast clear
228 * type and compression state dwords and constructs a predicate. The
229 * worst-case resolve is performed with the given predicate and the fast
230 * clear and compression state is set accordingly.
231 *
232 * See anv_layout_to_aux_usage and anv_layout_to_fast_clear_type functions for
233 * details on exactly what is allowed in what layouts.
234 *
235 * On gen7-9, we do not have a concept of indirect clear colors in hardware.
236 * In order to deal with this, we have to do some clear color management.
237 *
238 * * For LOAD_OP_LOAD at the top of a renderpass, we have to copy the clear
239 * value from the buffer into the surface state with MI commands.
240 *
241 * * For any blorp operations, we pass the address to the clear value into
242 * blorp and it knows to copy the clear color.
243 */
244 static void
245 add_aux_state_tracking_buffer(struct anv_image *image,
246 VkImageAspectFlagBits aspect,
247 uint32_t plane,
248 const struct anv_device *device)
249 {
250 assert(image && device);
251 assert(image->planes[plane].aux_surface.isl.size > 0 &&
252 image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
253
254 /* Compressed images must be tiled and therefore everything should be 4K
255 * aligned. The CCS has the same alignment requirements. This is good
256 * because we need at least dword-alignment for MI_LOAD/STORE operations.
257 */
258 assert(image->alignment % 4 == 0);
259 assert((image->planes[plane].offset + image->planes[plane].size) % 4 == 0);
260
261 /* This buffer should be at the very end of the plane. */
262 if (image->disjoint) {
263 assert(image->planes[plane].size ==
264 (image->planes[plane].offset + image->planes[plane].size));
265 } else {
266 assert(image->size ==
267 (image->planes[plane].offset + image->planes[plane].size));
268 }
269
270 const unsigned clear_color_state_size = device->info.gen >= 10 ?
271 device->isl_dev.ss.clear_color_state_size :
272 device->isl_dev.ss.clear_value_size;
273
274 /* Clear color and fast clear type */
275 unsigned state_size = clear_color_state_size + 4;
276
277 /* We only need to track compression on CCS_E surfaces. */
278 if (image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E) {
279 if (image->type == VK_IMAGE_TYPE_3D) {
280 for (uint32_t l = 0; l < image->levels; l++)
281 state_size += anv_minify(image->extent.depth, l) * 4;
282 } else {
283 state_size += image->levels * image->array_size * 4;
284 }
285 }
286
287 image->planes[plane].fast_clear_state_offset =
288 image->planes[plane].offset + image->planes[plane].size;
289
290 image->planes[plane].size += state_size;
291 image->size += state_size;
292 }
293
294 /**
295 * Initialize the anv_image::*_surface selected by \a aspect. Then update the
296 * image's memory requirements (that is, the image's size and alignment).
297 */
298 static VkResult
299 make_surface(const struct anv_device *dev,
300 struct anv_image *image,
301 const struct anv_image_create_info *anv_info,
302 isl_tiling_flags_t tiling_flags,
303 VkImageAspectFlagBits aspect)
304 {
305 const VkImageCreateInfo *vk_info = anv_info->vk_info;
306 bool ok UNUSED;
307
308 static const enum isl_surf_dim vk_to_isl_surf_dim[] = {
309 [VK_IMAGE_TYPE_1D] = ISL_SURF_DIM_1D,
310 [VK_IMAGE_TYPE_2D] = ISL_SURF_DIM_2D,
311 [VK_IMAGE_TYPE_3D] = ISL_SURF_DIM_3D,
312 };
313
314 image->extent = anv_sanitize_image_extent(vk_info->imageType,
315 vk_info->extent);
316
317 const unsigned plane = anv_image_aspect_to_plane(image->aspects, aspect);
318 const struct anv_format_plane plane_format =
319 anv_get_format_plane(&dev->info, image->vk_format, aspect, image->tiling);
320 struct anv_surface *anv_surf = &image->planes[plane].surface;
321
322 const isl_surf_usage_flags_t usage =
323 choose_isl_surf_usage(vk_info->flags, image->usage,
324 anv_info->isl_extra_usage_flags, aspect);
325
326 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
327 * fall back to linear on Broadwell and earlier because we aren't
328 * guaranteed that we can handle offsets correctly. On Sky Lake, the
329 * horizontal and vertical alignments are sufficiently high that we can
330 * just use RENDER_SURFACE_STATE::X/Y Offset.
331 */
332 bool needs_shadow = false;
333 if (dev->info.gen <= 8 &&
334 (vk_info->flags & VK_IMAGE_CREATE_BLOCK_TEXEL_VIEW_COMPATIBLE_BIT) &&
335 vk_info->tiling == VK_IMAGE_TILING_OPTIMAL) {
336 assert(isl_format_is_compressed(plane_format.isl_format));
337 tiling_flags = ISL_TILING_LINEAR_BIT;
338 needs_shadow = true;
339 }
340
341 ok = isl_surf_init(&dev->isl_dev, &anv_surf->isl,
342 .dim = vk_to_isl_surf_dim[vk_info->imageType],
343 .format = plane_format.isl_format,
344 .width = image->extent.width / plane_format.denominator_scales[0],
345 .height = image->extent.height / plane_format.denominator_scales[1],
346 .depth = image->extent.depth,
347 .levels = vk_info->mipLevels,
348 .array_len = vk_info->arrayLayers,
349 .samples = vk_info->samples,
350 .min_alignment = 0,
351 .row_pitch = anv_info->stride,
352 .usage = usage,
353 .tiling_flags = tiling_flags);
354
355 if (!ok)
356 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
357
358 image->planes[plane].aux_usage = ISL_AUX_USAGE_NONE;
359
360 add_surface(image, anv_surf, plane);
361
362 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
363 * create an identical tiled shadow surface for use while texturing so we
364 * don't get garbage performance.
365 */
366 if (needs_shadow) {
367 assert(aspect == VK_IMAGE_ASPECT_COLOR_BIT);
368 assert(tiling_flags == ISL_TILING_LINEAR_BIT);
369
370 ok = isl_surf_init(&dev->isl_dev, &image->planes[plane].shadow_surface.isl,
371 .dim = vk_to_isl_surf_dim[vk_info->imageType],
372 .format = plane_format.isl_format,
373 .width = image->extent.width,
374 .height = image->extent.height,
375 .depth = image->extent.depth,
376 .levels = vk_info->mipLevels,
377 .array_len = vk_info->arrayLayers,
378 .samples = vk_info->samples,
379 .min_alignment = 0,
380 .row_pitch = anv_info->stride,
381 .usage = usage,
382 .tiling_flags = ISL_TILING_ANY_MASK);
383
384 /* isl_surf_init() will fail only if provided invalid input. Invalid input
385 * is illegal in Vulkan.
386 */
387 assert(ok);
388
389 add_surface(image, &image->planes[plane].shadow_surface, plane);
390 }
391
392 /* Add a HiZ surface to a depth buffer that will be used for rendering.
393 */
394 if (aspect == VK_IMAGE_ASPECT_DEPTH_BIT) {
395 /* We don't advertise that depth buffers could be used as storage
396 * images.
397 */
398 assert(!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT));
399
400 /* Allow the user to control HiZ enabling. Disable by default on gen7
401 * because resolves are not currently implemented pre-BDW.
402 */
403 if (!(image->usage & VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) {
404 /* It will never be used as an attachment, HiZ is pointless. */
405 } else if (dev->info.gen == 7) {
406 anv_perf_warn(dev->instance, image, "Implement gen7 HiZ");
407 } else if (vk_info->mipLevels > 1) {
408 anv_perf_warn(dev->instance, image, "Enable multi-LOD HiZ");
409 } else if (vk_info->arrayLayers > 1) {
410 anv_perf_warn(dev->instance, image,
411 "Implement multi-arrayLayer HiZ clears and resolves");
412 } else if (dev->info.gen == 8 && vk_info->samples > 1) {
413 anv_perf_warn(dev->instance, image, "Enable gen8 multisampled HiZ");
414 } else if (!unlikely(INTEL_DEBUG & DEBUG_NO_HIZ)) {
415 assert(image->planes[plane].aux_surface.isl.size == 0);
416 ok = isl_surf_get_hiz_surf(&dev->isl_dev,
417 &image->planes[plane].surface.isl,
418 &image->planes[plane].aux_surface.isl);
419 assert(ok);
420 add_surface(image, &image->planes[plane].aux_surface, plane);
421 image->planes[plane].aux_usage = ISL_AUX_USAGE_HIZ;
422 }
423 } else if ((aspect & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) && vk_info->samples == 1) {
424 /* TODO: Disallow compression with :
425 *
426 * 1) non multiplanar images (We appear to hit a sampler bug with
427 * CCS & R16G16 format. Putting the clear state a page/4096bytes
428 * further fixes the issue).
429 *
430 * 2) alias images, because they might be aliases of images
431 * described in 1)
432 *
433 * 3) compression disabled by debug
434 */
435 const bool allow_compression =
436 image->n_planes == 1 &&
437 (vk_info->flags & VK_IMAGE_CREATE_ALIAS_BIT) == 0 &&
438 likely((INTEL_DEBUG & DEBUG_NO_RBC) == 0);
439
440 if (allow_compression) {
441 assert(image->planes[plane].aux_surface.isl.size == 0);
442 ok = isl_surf_get_ccs_surf(&dev->isl_dev,
443 &image->planes[plane].surface.isl,
444 &image->planes[plane].aux_surface.isl, 0);
445 if (ok) {
446
447 /* Disable CCS when it is not useful (i.e., when you can't render
448 * to the image with CCS enabled).
449 */
450 if (!isl_format_supports_rendering(&dev->info,
451 plane_format.isl_format)) {
452 /* While it may be technically possible to enable CCS for this
453 * image, we currently don't have things hooked up to get it
454 * working.
455 */
456 anv_perf_warn(dev->instance, image,
457 "This image format doesn't support rendering. "
458 "Not allocating an CCS buffer.");
459 image->planes[plane].aux_surface.isl.size = 0;
460 return VK_SUCCESS;
461 }
462
463 add_surface(image, &image->planes[plane].aux_surface, plane);
464 add_aux_state_tracking_buffer(image, aspect, plane, dev);
465
466 /* For images created without MUTABLE_FORMAT_BIT set, we know that
467 * they will always be used with the original format. In
468 * particular, they will always be used with a format that
469 * supports color compression. If it's never used as a storage
470 * image, then it will only be used through the sampler or the as
471 * a render target. This means that it's safe to just leave
472 * compression on at all times for these formats.
473 */
474 if (!(vk_info->usage & VK_IMAGE_USAGE_STORAGE_BIT) &&
475 all_formats_ccs_e_compatible(&dev->info, vk_info)) {
476 image->planes[plane].aux_usage = ISL_AUX_USAGE_CCS_E;
477 }
478 }
479 }
480 } else if ((aspect & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) && vk_info->samples > 1) {
481 assert(!(vk_info->usage & VK_IMAGE_USAGE_STORAGE_BIT));
482 assert(image->planes[plane].aux_surface.isl.size == 0);
483 ok = isl_surf_get_mcs_surf(&dev->isl_dev,
484 &image->planes[plane].surface.isl,
485 &image->planes[plane].aux_surface.isl);
486 if (ok) {
487 add_surface(image, &image->planes[plane].aux_surface, plane);
488 add_aux_state_tracking_buffer(image, aspect, plane, dev);
489 image->planes[plane].aux_usage = ISL_AUX_USAGE_MCS;
490 }
491 }
492
493 assert((image->planes[plane].offset + image->planes[plane].size) == image->size);
494
495 /* Upper bound of the last surface should be smaller than the plane's
496 * size.
497 */
498 assert((MAX2(image->planes[plane].surface.offset,
499 image->planes[plane].aux_surface.offset) +
500 (image->planes[plane].aux_surface.isl.size > 0 ?
501 image->planes[plane].aux_surface.isl.size :
502 image->planes[plane].surface.isl.size)) <=
503 (image->planes[plane].offset + image->planes[plane].size));
504
505 if (image->planes[plane].aux_surface.isl.size) {
506 /* assert(image->planes[plane].fast_clear_state_offset == */
507 /* (image->planes[plane].aux_surface.offset + image->planes[plane].aux_surface.isl.size)); */
508 assert(image->planes[plane].fast_clear_state_offset <
509 (image->planes[plane].offset + image->planes[plane].size));
510 }
511
512 return VK_SUCCESS;
513 }
514
515 static uint32_t
516 score_drm_format_mod(uint64_t modifier)
517 {
518 switch (modifier) {
519 case DRM_FORMAT_MOD_LINEAR: return 1;
520 case I915_FORMAT_MOD_X_TILED: return 2;
521 case I915_FORMAT_MOD_Y_TILED: return 3;
522 case I915_FORMAT_MOD_Y_TILED_CCS: return 4;
523 default: unreachable("bad DRM format modifier");
524 }
525 }
526
527 static const struct isl_drm_modifier_info *
528 choose_drm_format_mod(const struct anv_physical_device *device,
529 uint32_t modifier_count, const uint64_t *modifiers)
530 {
531 uint64_t best_mod = UINT64_MAX;
532 uint32_t best_score = 0;
533
534 for (uint32_t i = 0; i < modifier_count; ++i) {
535 uint32_t score = score_drm_format_mod(modifiers[i]);
536 if (score > best_score) {
537 best_mod = modifiers[i];
538 best_score = score;
539 }
540 }
541
542 if (best_score > 0)
543 return isl_drm_modifier_get_info(best_mod);
544 else
545 return NULL;
546 }
547
548 VkResult
549 anv_image_create(VkDevice _device,
550 const struct anv_image_create_info *create_info,
551 const VkAllocationCallbacks* alloc,
552 VkImage *pImage)
553 {
554 ANV_FROM_HANDLE(anv_device, device, _device);
555 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
556 const struct isl_drm_modifier_info *isl_mod_info = NULL;
557 struct anv_image *image = NULL;
558 VkResult r;
559
560 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
561
562 const struct wsi_image_create_info *wsi_info =
563 vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
564 if (wsi_info && wsi_info->modifier_count > 0) {
565 isl_mod_info = choose_drm_format_mod(&device->instance->physicalDevice,
566 wsi_info->modifier_count,
567 wsi_info->modifiers);
568 assert(isl_mod_info);
569 }
570
571 anv_assert(pCreateInfo->mipLevels > 0);
572 anv_assert(pCreateInfo->arrayLayers > 0);
573 anv_assert(pCreateInfo->samples > 0);
574 anv_assert(pCreateInfo->extent.width > 0);
575 anv_assert(pCreateInfo->extent.height > 0);
576 anv_assert(pCreateInfo->extent.depth > 0);
577
578 image = vk_zalloc2(&device->alloc, alloc, sizeof(*image), 8,
579 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
580 if (!image)
581 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
582
583 image->type = pCreateInfo->imageType;
584 image->extent = pCreateInfo->extent;
585 image->vk_format = pCreateInfo->format;
586 image->format = anv_get_format(pCreateInfo->format);
587 image->aspects = vk_format_aspects(image->vk_format);
588 image->levels = pCreateInfo->mipLevels;
589 image->array_size = pCreateInfo->arrayLayers;
590 image->samples = pCreateInfo->samples;
591 image->usage = pCreateInfo->usage;
592 image->tiling = pCreateInfo->tiling;
593 image->disjoint = pCreateInfo->flags & VK_IMAGE_CREATE_DISJOINT_BIT;
594 image->needs_set_tiling = wsi_info && wsi_info->scanout;
595 image->drm_format_mod = isl_mod_info ? isl_mod_info->modifier :
596 DRM_FORMAT_MOD_INVALID;
597
598 const struct anv_format *format = anv_get_format(image->vk_format);
599 assert(format != NULL);
600
601 const isl_tiling_flags_t isl_tiling_flags =
602 choose_isl_tiling_flags(create_info, isl_mod_info,
603 image->needs_set_tiling);
604
605 image->n_planes = format->n_planes;
606
607 uint32_t b;
608 for_each_bit(b, image->aspects) {
609 r = make_surface(device, image, create_info, isl_tiling_flags,
610 (1 << b));
611 if (r != VK_SUCCESS)
612 goto fail;
613 }
614
615 *pImage = anv_image_to_handle(image);
616
617 return VK_SUCCESS;
618
619 fail:
620 if (image)
621 vk_free2(&device->alloc, alloc, image);
622
623 return r;
624 }
625
626 VkResult
627 anv_CreateImage(VkDevice device,
628 const VkImageCreateInfo *pCreateInfo,
629 const VkAllocationCallbacks *pAllocator,
630 VkImage *pImage)
631 {
632 #ifdef ANDROID
633 const VkNativeBufferANDROID *gralloc_info =
634 vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
635
636 if (gralloc_info)
637 return anv_image_from_gralloc(device, pCreateInfo, gralloc_info,
638 pAllocator, pImage);
639 #endif
640
641 return anv_image_create(device,
642 &(struct anv_image_create_info) {
643 .vk_info = pCreateInfo,
644 },
645 pAllocator,
646 pImage);
647 }
648
649 void
650 anv_DestroyImage(VkDevice _device, VkImage _image,
651 const VkAllocationCallbacks *pAllocator)
652 {
653 ANV_FROM_HANDLE(anv_device, device, _device);
654 ANV_FROM_HANDLE(anv_image, image, _image);
655
656 if (!image)
657 return;
658
659 for (uint32_t p = 0; p < image->n_planes; ++p) {
660 if (image->planes[p].bo_is_owned) {
661 assert(image->planes[p].bo != NULL);
662 anv_bo_cache_release(device, &device->bo_cache, image->planes[p].bo);
663 }
664 }
665
666 vk_free2(&device->alloc, pAllocator, image);
667 }
668
669 static void anv_image_bind_memory_plane(struct anv_device *device,
670 struct anv_image *image,
671 uint32_t plane,
672 struct anv_device_memory *memory,
673 uint32_t memory_offset)
674 {
675 assert(!image->planes[plane].bo_is_owned);
676
677 if (!memory) {
678 image->planes[plane].bo = NULL;
679 image->planes[plane].bo_offset = 0;
680 return;
681 }
682
683 image->planes[plane].bo = memory->bo;
684 image->planes[plane].bo_offset = memory_offset;
685 }
686
687 VkResult anv_BindImageMemory(
688 VkDevice _device,
689 VkImage _image,
690 VkDeviceMemory _memory,
691 VkDeviceSize memoryOffset)
692 {
693 ANV_FROM_HANDLE(anv_device, device, _device);
694 ANV_FROM_HANDLE(anv_device_memory, mem, _memory);
695 ANV_FROM_HANDLE(anv_image, image, _image);
696
697 uint32_t aspect_bit;
698 anv_foreach_image_aspect_bit(aspect_bit, image, image->aspects) {
699 uint32_t plane =
700 anv_image_aspect_to_plane(image->aspects, 1UL << aspect_bit);
701 anv_image_bind_memory_plane(device, image, plane, mem, memoryOffset);
702 }
703
704 return VK_SUCCESS;
705 }
706
707 VkResult anv_BindImageMemory2(
708 VkDevice _device,
709 uint32_t bindInfoCount,
710 const VkBindImageMemoryInfo* pBindInfos)
711 {
712 ANV_FROM_HANDLE(anv_device, device, _device);
713
714 for (uint32_t i = 0; i < bindInfoCount; i++) {
715 const VkBindImageMemoryInfo *bind_info = &pBindInfos[i];
716 ANV_FROM_HANDLE(anv_device_memory, mem, bind_info->memory);
717 ANV_FROM_HANDLE(anv_image, image, bind_info->image);
718 VkImageAspectFlags aspects = image->aspects;
719
720 vk_foreach_struct_const(s, bind_info->pNext) {
721 switch (s->sType) {
722 case VK_STRUCTURE_TYPE_BIND_IMAGE_PLANE_MEMORY_INFO: {
723 const VkBindImagePlaneMemoryInfo *plane_info =
724 (const VkBindImagePlaneMemoryInfo *) s;
725
726 aspects = plane_info->planeAspect;
727 break;
728 }
729 default:
730 anv_debug_ignored_stype(s->sType);
731 break;
732 }
733 }
734
735 uint32_t aspect_bit;
736 anv_foreach_image_aspect_bit(aspect_bit, image, aspects) {
737 uint32_t plane =
738 anv_image_aspect_to_plane(image->aspects, 1UL << aspect_bit);
739 anv_image_bind_memory_plane(device, image, plane,
740 mem, bind_info->memoryOffset);
741 }
742 }
743
744 return VK_SUCCESS;
745 }
746
747 void anv_GetImageSubresourceLayout(
748 VkDevice device,
749 VkImage _image,
750 const VkImageSubresource* subresource,
751 VkSubresourceLayout* layout)
752 {
753 ANV_FROM_HANDLE(anv_image, image, _image);
754
755 const struct anv_surface *surface;
756 if (subresource->aspectMask == VK_IMAGE_ASPECT_PLANE_1_BIT_KHR &&
757 image->drm_format_mod != DRM_FORMAT_MOD_INVALID &&
758 isl_drm_modifier_has_aux(image->drm_format_mod))
759 surface = &image->planes[0].aux_surface;
760 else
761 surface = get_surface(image, subresource->aspectMask);
762
763 assert(__builtin_popcount(subresource->aspectMask) == 1);
764
765 /* If we are on a non-zero mip level or array slice, we need to
766 * calculate a real offset.
767 */
768 anv_assert(subresource->mipLevel == 0);
769 anv_assert(subresource->arrayLayer == 0);
770
771 layout->offset = surface->offset;
772 layout->rowPitch = surface->isl.row_pitch;
773 layout->depthPitch = isl_surf_get_array_pitch(&surface->isl);
774 layout->arrayPitch = isl_surf_get_array_pitch(&surface->isl);
775 layout->size = surface->isl.size;
776 }
777
778 /**
779 * This function determines the optimal buffer to use for a given
780 * VkImageLayout and other pieces of information needed to make that
781 * determination. This does not determine the optimal buffer to use
782 * during a resolve operation.
783 *
784 * @param devinfo The device information of the Intel GPU.
785 * @param image The image that may contain a collection of buffers.
786 * @param aspect The aspect of the image to be accessed.
787 * @param layout The current layout of the image aspect(s).
788 *
789 * @return The primary buffer that should be used for the given layout.
790 */
791 enum isl_aux_usage
792 anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
793 const struct anv_image * const image,
794 const VkImageAspectFlagBits aspect,
795 const VkImageLayout layout)
796 {
797 /* Validate the inputs. */
798
799 /* The devinfo is needed as the optimal buffer varies across generations. */
800 assert(devinfo != NULL);
801
802 /* The layout of a NULL image is not properly defined. */
803 assert(image != NULL);
804
805 /* The aspect must be exactly one of the image aspects. */
806 assert(_mesa_bitcount(aspect) == 1 && (aspect & image->aspects));
807
808 /* Determine the optimal buffer. */
809
810 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
811
812 /* If there is no auxiliary surface allocated, we must use the one and only
813 * main buffer.
814 */
815 if (image->planes[plane].aux_surface.isl.size == 0)
816 return ISL_AUX_USAGE_NONE;
817
818 /* All images that use an auxiliary surface are required to be tiled. */
819 assert(image->tiling == VK_IMAGE_TILING_OPTIMAL);
820
821 /* Stencil has no aux */
822 assert(aspect != VK_IMAGE_ASPECT_STENCIL_BIT);
823
824 switch (layout) {
825
826 /* Invalid Layouts */
827 case VK_IMAGE_LAYOUT_RANGE_SIZE:
828 case VK_IMAGE_LAYOUT_MAX_ENUM:
829 unreachable("Invalid image layout.");
830
831 /* Undefined layouts
832 *
833 * The pre-initialized layout is equivalent to the undefined layout for
834 * optimally-tiled images. We can only do color compression (CCS or HiZ)
835 * on tiled images.
836 */
837 case VK_IMAGE_LAYOUT_UNDEFINED:
838 case VK_IMAGE_LAYOUT_PREINITIALIZED:
839 return ISL_AUX_USAGE_NONE;
840
841
842 /* Transfer Layouts
843 */
844 case VK_IMAGE_LAYOUT_GENERAL:
845 case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL:
846 case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL:
847 if (aspect == VK_IMAGE_ASPECT_DEPTH_BIT) {
848 /* This buffer could be a depth buffer used in a transfer operation.
849 * BLORP currently doesn't use HiZ for transfer operations so we must
850 * use the main buffer for this layout. TODO: Enable HiZ in BLORP.
851 */
852 assert(image->planes[plane].aux_usage == ISL_AUX_USAGE_HIZ);
853 return ISL_AUX_USAGE_NONE;
854 } else {
855 assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
856 return image->planes[plane].aux_usage;
857 }
858
859
860 /* Sampling Layouts */
861 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL:
862 case VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL:
863 assert((image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) == 0);
864 /* Fall-through */
865 case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL:
866 if (aspect == VK_IMAGE_ASPECT_DEPTH_BIT) {
867 if (anv_can_sample_with_hiz(devinfo, image))
868 return ISL_AUX_USAGE_HIZ;
869 else
870 return ISL_AUX_USAGE_NONE;
871 } else {
872 return image->planes[plane].aux_usage;
873 }
874
875
876 case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR: {
877 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
878
879 /* When handing the image off to the presentation engine, we need to
880 * ensure that things are properly resolved. For images with no
881 * modifier, we assume that they follow the old rules and always need
882 * a full resolve because the PE doesn't understand any form of
883 * compression. For images with modifiers, we use the aux usage from
884 * the modifier.
885 */
886 const struct isl_drm_modifier_info *mod_info =
887 isl_drm_modifier_get_info(image->drm_format_mod);
888 return mod_info ? mod_info->aux_usage : ISL_AUX_USAGE_NONE;
889 }
890
891
892 /* Rendering Layouts */
893 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL:
894 assert(aspect & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
895 if (image->planes[plane].aux_usage == ISL_AUX_USAGE_NONE) {
896 assert(image->samples == 1);
897 return ISL_AUX_USAGE_CCS_D;
898 } else {
899 assert(image->planes[plane].aux_usage != ISL_AUX_USAGE_CCS_D);
900 return image->planes[plane].aux_usage;
901 }
902
903 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL:
904 case VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL:
905 assert(aspect == VK_IMAGE_ASPECT_DEPTH_BIT);
906 return ISL_AUX_USAGE_HIZ;
907
908 case VK_IMAGE_LAYOUT_SHARED_PRESENT_KHR:
909 unreachable("VK_KHR_shared_presentable_image is unsupported");
910 }
911
912 /* If the layout isn't recognized in the exhaustive switch above, the
913 * VkImageLayout value is not defined in vulkan.h.
914 */
915 unreachable("layout is not a VkImageLayout enumeration member.");
916 }
917
918 /**
919 * This function returns the level of unresolved fast-clear support of the
920 * given image in the given VkImageLayout.
921 *
922 * @param devinfo The device information of the Intel GPU.
923 * @param image The image that may contain a collection of buffers.
924 * @param aspect The aspect of the image to be accessed.
925 * @param layout The current layout of the image aspect(s).
926 */
927 enum anv_fast_clear_type
928 anv_layout_to_fast_clear_type(const struct gen_device_info * const devinfo,
929 const struct anv_image * const image,
930 const VkImageAspectFlagBits aspect,
931 const VkImageLayout layout)
932 {
933 /* The aspect must be exactly one of the image aspects. */
934 assert(_mesa_bitcount(aspect) == 1 && (aspect & image->aspects));
935
936 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
937
938 /* If there is no auxiliary surface allocated, there are no fast-clears */
939 if (image->planes[plane].aux_surface.isl.size == 0)
940 return ANV_FAST_CLEAR_NONE;
941
942 /* All images that use an auxiliary surface are required to be tiled. */
943 assert(image->tiling == VK_IMAGE_TILING_OPTIMAL);
944
945 /* Stencil has no aux */
946 assert(aspect != VK_IMAGE_ASPECT_STENCIL_BIT);
947
948 if (aspect == VK_IMAGE_ASPECT_DEPTH_BIT) {
949 /* For depth images (with HiZ), the layout supports fast-clears if and
950 * only if it supports HiZ. However, we only support fast-clears to the
951 * default depth value.
952 */
953 enum isl_aux_usage aux_usage =
954 anv_layout_to_aux_usage(devinfo, image, aspect, layout);
955 return aux_usage == ISL_AUX_USAGE_HIZ ?
956 ANV_FAST_CLEAR_DEFAULT_VALUE : ANV_FAST_CLEAR_NONE;
957 }
958
959 assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
960
961 /* We don't support MSAA fast-clears on Ivybridge or Bay Trail because they
962 * lack the MI ALU which we need to determine the predicates.
963 */
964 if (devinfo->gen == 7 && !devinfo->is_haswell && image->samples > 1)
965 return ANV_FAST_CLEAR_NONE;
966
967 switch (layout) {
968 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL:
969 return ANV_FAST_CLEAR_ANY;
970
971 case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR: {
972 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
973 #ifndef NDEBUG
974 /* We do not yet support any modifiers which support clear color so we
975 * just always return NONE. One day, this will change.
976 */
977 const struct isl_drm_modifier_info *mod_info =
978 isl_drm_modifier_get_info(image->drm_format_mod);
979 assert(!mod_info || !mod_info->supports_clear_color);
980 #endif
981 return ANV_FAST_CLEAR_NONE;
982 }
983
984 default:
985 /* If the image has MCS or CCS_E enabled all the time then we can use
986 * fast-clear as long as the clear color is the default value of zero
987 * since this is the default value we program into every surface state
988 * used for texturing.
989 */
990 if (image->planes[plane].aux_usage == ISL_AUX_USAGE_MCS ||
991 image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E)
992 return ANV_FAST_CLEAR_DEFAULT_VALUE;
993 else
994 return ANV_FAST_CLEAR_NONE;
995 }
996 }
997
998
999 static struct anv_state
1000 alloc_surface_state(struct anv_device *device)
1001 {
1002 return anv_state_pool_alloc(&device->surface_state_pool, 64, 64);
1003 }
1004
1005 static enum isl_channel_select
1006 remap_swizzle(VkComponentSwizzle swizzle, VkComponentSwizzle component,
1007 struct isl_swizzle format_swizzle)
1008 {
1009 if (swizzle == VK_COMPONENT_SWIZZLE_IDENTITY)
1010 swizzle = component;
1011
1012 switch (swizzle) {
1013 case VK_COMPONENT_SWIZZLE_ZERO: return ISL_CHANNEL_SELECT_ZERO;
1014 case VK_COMPONENT_SWIZZLE_ONE: return ISL_CHANNEL_SELECT_ONE;
1015 case VK_COMPONENT_SWIZZLE_R: return format_swizzle.r;
1016 case VK_COMPONENT_SWIZZLE_G: return format_swizzle.g;
1017 case VK_COMPONENT_SWIZZLE_B: return format_swizzle.b;
1018 case VK_COMPONENT_SWIZZLE_A: return format_swizzle.a;
1019 default:
1020 unreachable("Invalid swizzle");
1021 }
1022 }
1023
1024 void
1025 anv_image_fill_surface_state(struct anv_device *device,
1026 const struct anv_image *image,
1027 VkImageAspectFlagBits aspect,
1028 const struct isl_view *view_in,
1029 isl_surf_usage_flags_t view_usage,
1030 enum isl_aux_usage aux_usage,
1031 const union isl_color_value *clear_color,
1032 enum anv_image_view_state_flags flags,
1033 struct anv_surface_state *state_inout,
1034 struct brw_image_param *image_param_out)
1035 {
1036 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
1037
1038 const struct anv_surface *surface = &image->planes[plane].surface,
1039 *aux_surface = &image->planes[plane].aux_surface;
1040
1041 struct isl_view view = *view_in;
1042 view.usage |= view_usage;
1043
1044 /* For texturing with VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL from a
1045 * compressed surface with a shadow surface, we use the shadow instead of
1046 * the primary surface. The shadow surface will be tiled, unlike the main
1047 * surface, so it should get significantly better performance.
1048 */
1049 if (image->planes[plane].shadow_surface.isl.size > 0 &&
1050 isl_format_is_compressed(view.format) &&
1051 (flags & ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL)) {
1052 assert(isl_format_is_compressed(surface->isl.format));
1053 assert(surface->isl.tiling == ISL_TILING_LINEAR);
1054 assert(image->planes[plane].shadow_surface.isl.tiling != ISL_TILING_LINEAR);
1055 surface = &image->planes[plane].shadow_surface;
1056 }
1057
1058 if (view_usage == ISL_SURF_USAGE_RENDER_TARGET_BIT)
1059 view.swizzle = anv_swizzle_for_render(view.swizzle);
1060
1061 /* If this is a HiZ buffer we can sample from with a programmable clear
1062 * value (SKL+), define the clear value to the optimal constant.
1063 */
1064 union isl_color_value default_clear_color = { .u32 = { 0, } };
1065 if (device->info.gen >= 9 && aux_usage == ISL_AUX_USAGE_HIZ)
1066 default_clear_color.f32[0] = ANV_HZ_FC_VAL;
1067 if (!clear_color)
1068 clear_color = &default_clear_color;
1069
1070 const uint64_t address = image->planes[plane].bo_offset + surface->offset;
1071 const uint64_t aux_address = aux_usage == ISL_AUX_USAGE_NONE ?
1072 0 : (image->planes[plane].bo_offset + aux_surface->offset);
1073
1074 struct anv_address clear_address = { .bo = NULL };
1075 state_inout->clear_address = 0;
1076
1077 if (device->info.gen >= 10 && aux_usage != ISL_AUX_USAGE_NONE) {
1078 if (aux_usage == ISL_AUX_USAGE_HIZ) {
1079 clear_address = (struct anv_address) { .bo = &device->hiz_clear_bo };
1080 } else {
1081 clear_address = anv_image_get_clear_color_addr(device, image, aspect);
1082 }
1083 }
1084
1085 if (view_usage == ISL_SURF_USAGE_STORAGE_BIT &&
1086 !(flags & ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY) &&
1087 !isl_has_matching_typed_storage_image_format(&device->info,
1088 view.format)) {
1089 /* In this case, we are a writeable storage buffer which needs to be
1090 * lowered to linear. All tiling and offset calculations will be done in
1091 * the shader.
1092 */
1093 assert(aux_usage == ISL_AUX_USAGE_NONE);
1094 isl_buffer_fill_state(&device->isl_dev, state_inout->state.map,
1095 .address = address,
1096 .size = surface->isl.size,
1097 .format = ISL_FORMAT_RAW,
1098 .stride = 1,
1099 .mocs = device->default_mocs);
1100 state_inout->address = address,
1101 state_inout->aux_address = 0;
1102 state_inout->clear_address = 0;
1103 } else {
1104 if (view_usage == ISL_SURF_USAGE_STORAGE_BIT &&
1105 !(flags & ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY)) {
1106 /* Typed surface reads support a very limited subset of the shader
1107 * image formats. Translate it into the closest format the hardware
1108 * supports.
1109 */
1110 assert(aux_usage == ISL_AUX_USAGE_NONE);
1111 view.format = isl_lower_storage_image_format(&device->info,
1112 view.format);
1113 }
1114
1115 const struct isl_surf *isl_surf = &surface->isl;
1116
1117 struct isl_surf tmp_surf;
1118 uint32_t offset_B = 0, tile_x_sa = 0, tile_y_sa = 0;
1119 if (isl_format_is_compressed(surface->isl.format) &&
1120 !isl_format_is_compressed(view.format)) {
1121 /* We're creating an uncompressed view of a compressed surface. This
1122 * is allowed but only for a single level/layer.
1123 */
1124 assert(surface->isl.samples == 1);
1125 assert(view.levels == 1);
1126 assert(view.array_len == 1);
1127
1128 isl_surf_get_image_surf(&device->isl_dev, isl_surf,
1129 view.base_level,
1130 surface->isl.dim == ISL_SURF_DIM_3D ?
1131 0 : view.base_array_layer,
1132 surface->isl.dim == ISL_SURF_DIM_3D ?
1133 view.base_array_layer : 0,
1134 &tmp_surf,
1135 &offset_B, &tile_x_sa, &tile_y_sa);
1136
1137 /* The newly created image represents the one subimage we're
1138 * referencing with this view so it only has one array slice and
1139 * miplevel.
1140 */
1141 view.base_array_layer = 0;
1142 view.base_level = 0;
1143
1144 /* We're making an uncompressed view here. The image dimensions need
1145 * to be scaled down by the block size.
1146 */
1147 const struct isl_format_layout *fmtl =
1148 isl_format_get_layout(surface->isl.format);
1149 tmp_surf.format = view.format;
1150 tmp_surf.logical_level0_px.width =
1151 DIV_ROUND_UP(tmp_surf.logical_level0_px.width, fmtl->bw);
1152 tmp_surf.logical_level0_px.height =
1153 DIV_ROUND_UP(tmp_surf.logical_level0_px.height, fmtl->bh);
1154 tmp_surf.phys_level0_sa.width /= fmtl->bw;
1155 tmp_surf.phys_level0_sa.height /= fmtl->bh;
1156 tile_x_sa /= fmtl->bw;
1157 tile_y_sa /= fmtl->bh;
1158
1159 isl_surf = &tmp_surf;
1160
1161 if (device->info.gen <= 8) {
1162 assert(surface->isl.tiling == ISL_TILING_LINEAR);
1163 assert(tile_x_sa == 0);
1164 assert(tile_y_sa == 0);
1165 }
1166 }
1167
1168 isl_surf_fill_state(&device->isl_dev, state_inout->state.map,
1169 .surf = isl_surf,
1170 .view = &view,
1171 .address = address + offset_B,
1172 .clear_color = *clear_color,
1173 .aux_surf = &aux_surface->isl,
1174 .aux_usage = aux_usage,
1175 .aux_address = aux_address,
1176 .clear_address = clear_address.offset,
1177 .use_clear_address = clear_address.bo != NULL,
1178 .mocs = device->default_mocs,
1179 .x_offset_sa = tile_x_sa,
1180 .y_offset_sa = tile_y_sa);
1181 state_inout->address = address + offset_B;
1182
1183 /* With the exception of gen8, the bottom 12 bits of the MCS base address
1184 * are used to store other information. This should be ok, however,
1185 * because the surface buffer addresses are always 4K page aligned.
1186 */
1187 uint32_t *aux_addr_dw = state_inout->state.map +
1188 device->isl_dev.ss.aux_addr_offset;
1189 assert((aux_address & 0xfff) == 0);
1190 assert(aux_address == (*aux_addr_dw & 0xfffff000));
1191 state_inout->aux_address = *aux_addr_dw;
1192
1193 if (device->info.gen >= 10 && clear_address.bo) {
1194 uint32_t *clear_addr_dw = state_inout->state.map +
1195 device->isl_dev.ss.clear_color_state_offset;
1196 assert((clear_address.offset & 0x3f) == 0);
1197 state_inout->clear_address = *clear_addr_dw;
1198 }
1199 }
1200
1201 anv_state_flush(device, state_inout->state);
1202
1203 if (image_param_out) {
1204 assert(view_usage == ISL_SURF_USAGE_STORAGE_BIT);
1205 isl_surf_fill_image_param(&device->isl_dev, image_param_out,
1206 &surface->isl, &view);
1207 }
1208 }
1209
1210 static VkImageAspectFlags
1211 remap_aspect_flags(VkImageAspectFlags view_aspects)
1212 {
1213 if (view_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
1214 if (_mesa_bitcount(view_aspects) == 1)
1215 return VK_IMAGE_ASPECT_COLOR_BIT;
1216
1217 VkImageAspectFlags color_aspects = 0;
1218 for (uint32_t i = 0; i < _mesa_bitcount(view_aspects); i++)
1219 color_aspects |= VK_IMAGE_ASPECT_PLANE_0_BIT << i;
1220 return color_aspects;
1221 }
1222 /* No special remapping needed for depth & stencil aspects. */
1223 return view_aspects;
1224 }
1225
1226 VkResult
1227 anv_CreateImageView(VkDevice _device,
1228 const VkImageViewCreateInfo *pCreateInfo,
1229 const VkAllocationCallbacks *pAllocator,
1230 VkImageView *pView)
1231 {
1232 ANV_FROM_HANDLE(anv_device, device, _device);
1233 ANV_FROM_HANDLE(anv_image, image, pCreateInfo->image);
1234 struct anv_image_view *iview;
1235
1236 iview = vk_zalloc2(&device->alloc, pAllocator, sizeof(*iview), 8,
1237 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1238 if (iview == NULL)
1239 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1240
1241 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
1242
1243 assert(range->layerCount > 0);
1244 assert(range->baseMipLevel < image->levels);
1245
1246 const VkImageViewUsageCreateInfo *usage_info =
1247 vk_find_struct_const(pCreateInfo, IMAGE_VIEW_USAGE_CREATE_INFO);
1248 VkImageUsageFlags view_usage = usage_info ? usage_info->usage : image->usage;
1249 /* View usage should be a subset of image usage */
1250 assert((view_usage & ~image->usage) == 0);
1251 assert(view_usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
1252 VK_IMAGE_USAGE_STORAGE_BIT |
1253 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
1254 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT |
1255 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT));
1256
1257 switch (image->type) {
1258 default:
1259 unreachable("bad VkImageType");
1260 case VK_IMAGE_TYPE_1D:
1261 case VK_IMAGE_TYPE_2D:
1262 assert(range->baseArrayLayer + anv_get_layerCount(image, range) - 1 <= image->array_size);
1263 break;
1264 case VK_IMAGE_TYPE_3D:
1265 assert(range->baseArrayLayer + anv_get_layerCount(image, range) - 1
1266 <= anv_minify(image->extent.depth, range->baseMipLevel));
1267 break;
1268 }
1269
1270 /* First expand aspects to the image's ones (for example
1271 * VK_IMAGE_ASPECT_COLOR_BIT will be converted to
1272 * VK_IMAGE_ASPECT_PLANE_0_BIT | VK_IMAGE_ASPECT_PLANE_1_BIT |
1273 * VK_IMAGE_ASPECT_PLANE_2_BIT for an image of format
1274 * VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM_KHR.
1275 */
1276 VkImageAspectFlags expanded_aspects =
1277 anv_image_expand_aspects(image, range->aspectMask);
1278
1279 iview->image = image;
1280
1281 /* Remap the expanded aspects for the image view. For example if only
1282 * VK_IMAGE_ASPECT_PLANE_1_BIT was given in range->aspectMask, we will
1283 * convert it to VK_IMAGE_ASPECT_COLOR_BIT since from the point of view of
1284 * the image view, it only has a single plane.
1285 */
1286 iview->aspect_mask = remap_aspect_flags(expanded_aspects);
1287 iview->n_planes = anv_image_aspect_get_planes(iview->aspect_mask);
1288 iview->vk_format = pCreateInfo->format;
1289
1290 iview->extent = (VkExtent3D) {
1291 .width = anv_minify(image->extent.width , range->baseMipLevel),
1292 .height = anv_minify(image->extent.height, range->baseMipLevel),
1293 .depth = anv_minify(image->extent.depth , range->baseMipLevel),
1294 };
1295
1296 /* Now go through the underlying image selected planes (computed in
1297 * expanded_aspects) and map them to planes in the image view.
1298 */
1299 uint32_t iaspect_bit, vplane = 0;
1300 anv_foreach_image_aspect_bit(iaspect_bit, image, expanded_aspects) {
1301 uint32_t iplane =
1302 anv_image_aspect_to_plane(expanded_aspects, 1UL << iaspect_bit);
1303 VkImageAspectFlags vplane_aspect =
1304 anv_plane_to_aspect(iview->aspect_mask, vplane);
1305 struct anv_format_plane format =
1306 anv_get_format_plane(&device->info, pCreateInfo->format,
1307 vplane_aspect, image->tiling);
1308
1309 iview->planes[vplane].image_plane = iplane;
1310
1311 iview->planes[vplane].isl = (struct isl_view) {
1312 .format = format.isl_format,
1313 .base_level = range->baseMipLevel,
1314 .levels = anv_get_levelCount(image, range),
1315 .base_array_layer = range->baseArrayLayer,
1316 .array_len = anv_get_layerCount(image, range),
1317 .swizzle = {
1318 .r = remap_swizzle(pCreateInfo->components.r,
1319 VK_COMPONENT_SWIZZLE_R, format.swizzle),
1320 .g = remap_swizzle(pCreateInfo->components.g,
1321 VK_COMPONENT_SWIZZLE_G, format.swizzle),
1322 .b = remap_swizzle(pCreateInfo->components.b,
1323 VK_COMPONENT_SWIZZLE_B, format.swizzle),
1324 .a = remap_swizzle(pCreateInfo->components.a,
1325 VK_COMPONENT_SWIZZLE_A, format.swizzle),
1326 },
1327 };
1328
1329 if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_3D) {
1330 iview->planes[vplane].isl.base_array_layer = 0;
1331 iview->planes[vplane].isl.array_len = iview->extent.depth;
1332 }
1333
1334 if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_CUBE ||
1335 pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY) {
1336 iview->planes[vplane].isl.usage = ISL_SURF_USAGE_CUBE_BIT;
1337 } else {
1338 iview->planes[vplane].isl.usage = 0;
1339 }
1340
1341 if (view_usage & VK_IMAGE_USAGE_SAMPLED_BIT ||
1342 (view_usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT &&
1343 !(iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT))) {
1344 iview->planes[vplane].optimal_sampler_surface_state.state = alloc_surface_state(device);
1345 iview->planes[vplane].general_sampler_surface_state.state = alloc_surface_state(device);
1346
1347 enum isl_aux_usage general_aux_usage =
1348 anv_layout_to_aux_usage(&device->info, image, 1UL << iaspect_bit,
1349 VK_IMAGE_LAYOUT_GENERAL);
1350 enum isl_aux_usage optimal_aux_usage =
1351 anv_layout_to_aux_usage(&device->info, image, 1UL << iaspect_bit,
1352 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL);
1353
1354 anv_image_fill_surface_state(device, image, 1ULL << iaspect_bit,
1355 &iview->planes[vplane].isl,
1356 ISL_SURF_USAGE_TEXTURE_BIT,
1357 optimal_aux_usage, NULL,
1358 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL,
1359 &iview->planes[vplane].optimal_sampler_surface_state,
1360 NULL);
1361
1362 anv_image_fill_surface_state(device, image, 1ULL << iaspect_bit,
1363 &iview->planes[vplane].isl,
1364 ISL_SURF_USAGE_TEXTURE_BIT,
1365 general_aux_usage, NULL,
1366 0,
1367 &iview->planes[vplane].general_sampler_surface_state,
1368 NULL);
1369 }
1370
1371 /* NOTE: This one needs to go last since it may stomp isl_view.format */
1372 if (view_usage & VK_IMAGE_USAGE_STORAGE_BIT) {
1373 iview->planes[vplane].storage_surface_state.state = alloc_surface_state(device);
1374 iview->planes[vplane].writeonly_storage_surface_state.state = alloc_surface_state(device);
1375
1376 anv_image_fill_surface_state(device, image, 1ULL << iaspect_bit,
1377 &iview->planes[vplane].isl,
1378 ISL_SURF_USAGE_STORAGE_BIT,
1379 ISL_AUX_USAGE_NONE, NULL,
1380 0,
1381 &iview->planes[vplane].storage_surface_state,
1382 &iview->planes[vplane].storage_image_param);
1383
1384 anv_image_fill_surface_state(device, image, 1ULL << iaspect_bit,
1385 &iview->planes[vplane].isl,
1386 ISL_SURF_USAGE_STORAGE_BIT,
1387 ISL_AUX_USAGE_NONE, NULL,
1388 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY,
1389 &iview->planes[vplane].writeonly_storage_surface_state,
1390 NULL);
1391 }
1392
1393 vplane++;
1394 }
1395
1396 *pView = anv_image_view_to_handle(iview);
1397
1398 return VK_SUCCESS;
1399 }
1400
1401 void
1402 anv_DestroyImageView(VkDevice _device, VkImageView _iview,
1403 const VkAllocationCallbacks *pAllocator)
1404 {
1405 ANV_FROM_HANDLE(anv_device, device, _device);
1406 ANV_FROM_HANDLE(anv_image_view, iview, _iview);
1407
1408 if (!iview)
1409 return;
1410
1411 for (uint32_t plane = 0; plane < iview->n_planes; plane++) {
1412 if (iview->planes[plane].optimal_sampler_surface_state.state.alloc_size > 0) {
1413 anv_state_pool_free(&device->surface_state_pool,
1414 iview->planes[plane].optimal_sampler_surface_state.state);
1415 }
1416
1417 if (iview->planes[plane].general_sampler_surface_state.state.alloc_size > 0) {
1418 anv_state_pool_free(&device->surface_state_pool,
1419 iview->planes[plane].general_sampler_surface_state.state);
1420 }
1421
1422 if (iview->planes[plane].storage_surface_state.state.alloc_size > 0) {
1423 anv_state_pool_free(&device->surface_state_pool,
1424 iview->planes[plane].storage_surface_state.state);
1425 }
1426
1427 if (iview->planes[plane].writeonly_storage_surface_state.state.alloc_size > 0) {
1428 anv_state_pool_free(&device->surface_state_pool,
1429 iview->planes[plane].writeonly_storage_surface_state.state);
1430 }
1431 }
1432
1433 vk_free2(&device->alloc, pAllocator, iview);
1434 }
1435
1436
1437 VkResult
1438 anv_CreateBufferView(VkDevice _device,
1439 const VkBufferViewCreateInfo *pCreateInfo,
1440 const VkAllocationCallbacks *pAllocator,
1441 VkBufferView *pView)
1442 {
1443 ANV_FROM_HANDLE(anv_device, device, _device);
1444 ANV_FROM_HANDLE(anv_buffer, buffer, pCreateInfo->buffer);
1445 struct anv_buffer_view *view;
1446
1447 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1448 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1449 if (!view)
1450 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1451
1452 /* TODO: Handle the format swizzle? */
1453
1454 view->format = anv_get_isl_format(&device->info, pCreateInfo->format,
1455 VK_IMAGE_ASPECT_COLOR_BIT,
1456 VK_IMAGE_TILING_LINEAR);
1457 const uint32_t format_bs = isl_format_get_layout(view->format)->bpb / 8;
1458 view->bo = buffer->bo;
1459 view->offset = buffer->offset + pCreateInfo->offset;
1460 view->range = anv_buffer_get_range(buffer, pCreateInfo->offset,
1461 pCreateInfo->range);
1462 view->range = align_down_npot_u32(view->range, format_bs);
1463
1464 if (buffer->usage & VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT) {
1465 view->surface_state = alloc_surface_state(device);
1466
1467 anv_fill_buffer_surface_state(device, view->surface_state,
1468 view->format,
1469 view->offset, view->range, format_bs);
1470 } else {
1471 view->surface_state = (struct anv_state){ 0 };
1472 }
1473
1474 if (buffer->usage & VK_BUFFER_USAGE_STORAGE_TEXEL_BUFFER_BIT) {
1475 view->storage_surface_state = alloc_surface_state(device);
1476 view->writeonly_storage_surface_state = alloc_surface_state(device);
1477
1478 enum isl_format storage_format =
1479 isl_has_matching_typed_storage_image_format(&device->info,
1480 view->format) ?
1481 isl_lower_storage_image_format(&device->info, view->format) :
1482 ISL_FORMAT_RAW;
1483
1484 anv_fill_buffer_surface_state(device, view->storage_surface_state,
1485 storage_format,
1486 view->offset, view->range,
1487 (storage_format == ISL_FORMAT_RAW ? 1 :
1488 isl_format_get_layout(storage_format)->bpb / 8));
1489
1490 /* Write-only accesses should use the original format. */
1491 anv_fill_buffer_surface_state(device, view->writeonly_storage_surface_state,
1492 view->format,
1493 view->offset, view->range,
1494 isl_format_get_layout(view->format)->bpb / 8);
1495
1496 isl_buffer_fill_image_param(&device->isl_dev,
1497 &view->storage_image_param,
1498 view->format, view->range);
1499 } else {
1500 view->storage_surface_state = (struct anv_state){ 0 };
1501 view->writeonly_storage_surface_state = (struct anv_state){ 0 };
1502 }
1503
1504 *pView = anv_buffer_view_to_handle(view);
1505
1506 return VK_SUCCESS;
1507 }
1508
1509 void
1510 anv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1511 const VkAllocationCallbacks *pAllocator)
1512 {
1513 ANV_FROM_HANDLE(anv_device, device, _device);
1514 ANV_FROM_HANDLE(anv_buffer_view, view, bufferView);
1515
1516 if (!view)
1517 return;
1518
1519 if (view->surface_state.alloc_size > 0)
1520 anv_state_pool_free(&device->surface_state_pool,
1521 view->surface_state);
1522
1523 if (view->storage_surface_state.alloc_size > 0)
1524 anv_state_pool_free(&device->surface_state_pool,
1525 view->storage_surface_state);
1526
1527 if (view->writeonly_storage_surface_state.alloc_size > 0)
1528 anv_state_pool_free(&device->surface_state_pool,
1529 view->writeonly_storage_surface_state);
1530
1531 vk_free2(&device->alloc, pAllocator, view);
1532 }
1533
1534 const struct anv_surface *
1535 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
1536 VkImageAspectFlags aspect_mask)
1537 {
1538 VkImageAspectFlags sanitized_mask;
1539
1540 switch (aspect_mask) {
1541 case VK_IMAGE_ASPECT_COLOR_BIT:
1542 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
1543 sanitized_mask = VK_IMAGE_ASPECT_COLOR_BIT;
1544 break;
1545 case VK_IMAGE_ASPECT_DEPTH_BIT:
1546 assert(image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT);
1547 sanitized_mask = VK_IMAGE_ASPECT_DEPTH_BIT;
1548 break;
1549 case VK_IMAGE_ASPECT_STENCIL_BIT:
1550 assert(image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT);
1551 sanitized_mask = VK_IMAGE_ASPECT_STENCIL_BIT;
1552 break;
1553 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
1554 /* FINISHME: The Vulkan spec (git a511ba2) requires support for
1555 * combined depth stencil formats. Specifically, it states:
1556 *
1557 * At least one of ename:VK_FORMAT_D24_UNORM_S8_UINT or
1558 * ename:VK_FORMAT_D32_SFLOAT_S8_UINT must be supported.
1559 *
1560 * Image views with both depth and stencil aspects are only valid for
1561 * render target attachments, in which case
1562 * cmd_buffer_emit_depth_stencil() will pick out both the depth and
1563 * stencil surfaces from the underlying surface.
1564 */
1565 if (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
1566 sanitized_mask = VK_IMAGE_ASPECT_DEPTH_BIT;
1567 } else {
1568 assert(image->aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1569 sanitized_mask = VK_IMAGE_ASPECT_STENCIL_BIT;
1570 }
1571 break;
1572 case VK_IMAGE_ASPECT_PLANE_0_BIT:
1573 assert((image->aspects & ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) == 0);
1574 sanitized_mask = VK_IMAGE_ASPECT_PLANE_0_BIT;
1575 break;
1576 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1577 assert((image->aspects & ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) == 0);
1578 sanitized_mask = VK_IMAGE_ASPECT_PLANE_1_BIT;
1579 break;
1580 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1581 assert((image->aspects & ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) == 0);
1582 sanitized_mask = VK_IMAGE_ASPECT_PLANE_2_BIT;
1583 break;
1584 default:
1585 unreachable("image does not have aspect");
1586 return NULL;
1587 }
1588
1589 uint32_t plane = anv_image_aspect_to_plane(image->aspects, sanitized_mask);
1590 return &image->planes[plane].surface;
1591 }