2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include <drm_fourcc.h>
32 #include "anv_private.h"
33 #include "util/debug.h"
36 #include "vk_format_info.h"
38 static isl_surf_usage_flags_t
39 choose_isl_surf_usage(VkImageCreateFlags vk_create_flags
,
40 VkImageUsageFlags vk_usage
,
41 isl_surf_usage_flags_t isl_extra_usage
,
42 VkImageAspectFlagBits aspect
)
44 isl_surf_usage_flags_t isl_usage
= isl_extra_usage
;
46 if (vk_usage
& VK_IMAGE_USAGE_SAMPLED_BIT
)
47 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
49 if (vk_usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)
50 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
52 if (vk_usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
)
53 isl_usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
55 if (vk_create_flags
& VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT
)
56 isl_usage
|= ISL_SURF_USAGE_CUBE_BIT
;
58 /* Even if we're only using it for transfer operations, clears to depth and
59 * stencil images happen as depth and stencil so they need the right ISL
60 * usage bits or else things will fall apart.
63 case VK_IMAGE_ASPECT_DEPTH_BIT
:
64 isl_usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
66 case VK_IMAGE_ASPECT_STENCIL_BIT
:
67 isl_usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
69 case VK_IMAGE_ASPECT_COLOR_BIT
:
70 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
:
71 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR
:
72 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR
:
75 unreachable("bad VkImageAspect");
78 if (vk_usage
& VK_IMAGE_USAGE_TRANSFER_SRC_BIT
) {
79 /* blorp implements transfers by sampling from the source image. */
80 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
83 if (vk_usage
& VK_IMAGE_USAGE_TRANSFER_DST_BIT
&&
84 aspect
== VK_IMAGE_ASPECT_COLOR_BIT
) {
85 /* blorp implements transfers by rendering into the destination image.
86 * Only request this with color images, as we deal with depth/stencil
87 * formats differently. */
88 isl_usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
94 static isl_tiling_flags_t
95 choose_isl_tiling_flags(const struct anv_image_create_info
*anv_info
,
96 const struct isl_drm_modifier_info
*isl_mod_info
)
98 const VkImageCreateInfo
*base_info
= anv_info
->vk_info
;
99 isl_tiling_flags_t flags
= 0;
101 switch (base_info
->tiling
) {
103 unreachable("bad VkImageTiling");
104 case VK_IMAGE_TILING_OPTIMAL
:
105 flags
= ISL_TILING_ANY_MASK
;
107 case VK_IMAGE_TILING_LINEAR
:
108 flags
= ISL_TILING_LINEAR_BIT
;
112 if (anv_info
->isl_tiling_flags
)
113 flags
&= anv_info
->isl_tiling_flags
;
116 flags
&= 1 << isl_mod_info
->tiling
;
123 static struct anv_surface
*
124 get_surface(struct anv_image
*image
, VkImageAspectFlagBits aspect
)
126 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
127 return &image
->planes
[plane
].surface
;
131 add_surface(struct anv_image
*image
, struct anv_surface
*surf
, uint32_t plane
)
133 assert(surf
->isl
.size
> 0); /* isl surface must be initialized */
135 if (image
->disjoint
) {
136 surf
->offset
= align_u32(image
->planes
[plane
].size
, surf
->isl
.alignment
);
137 /* Plane offset is always 0 when it's disjoint. */
139 surf
->offset
= align_u32(image
->size
, surf
->isl
.alignment
);
140 /* Determine plane's offset only once when the first surface is added. */
141 if (image
->planes
[plane
].size
== 0)
142 image
->planes
[plane
].offset
= image
->size
;
145 image
->size
= surf
->offset
+ surf
->isl
.size
;
146 image
->planes
[plane
].size
= (surf
->offset
+ surf
->isl
.size
) - image
->planes
[plane
].offset
;
148 image
->alignment
= MAX2(image
->alignment
, surf
->isl
.alignment
);
149 image
->planes
[plane
].alignment
= MAX2(image
->planes
[plane
].alignment
,
150 surf
->isl
.alignment
);
155 all_formats_ccs_e_compatible(const struct gen_device_info
*devinfo
,
156 const struct VkImageCreateInfo
*vk_info
)
158 enum isl_format format
=
159 anv_get_isl_format(devinfo
, vk_info
->format
,
160 VK_IMAGE_ASPECT_COLOR_BIT
, vk_info
->tiling
);
162 if (!isl_format_supports_ccs_e(devinfo
, format
))
165 if (!(vk_info
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
))
168 const VkImageFormatListCreateInfoKHR
*fmt_list
=
169 vk_find_struct_const(vk_info
->pNext
, IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
171 if (!fmt_list
|| fmt_list
->viewFormatCount
== 0)
174 for (uint32_t i
= 0; i
< fmt_list
->viewFormatCount
; i
++) {
175 enum isl_format view_format
=
176 anv_get_isl_format(devinfo
, fmt_list
->pViewFormats
[i
],
177 VK_IMAGE_ASPECT_COLOR_BIT
, vk_info
->tiling
);
179 if (!isl_formats_are_ccs_e_compatible(devinfo
, format
, view_format
))
187 * For color images that have an auxiliary surface, request allocation for an
188 * additional buffer that mainly stores fast-clear values. Use of this buffer
189 * allows us to access the image's subresources while being aware of their
190 * fast-clear values in non-trivial cases (e.g., outside of a render pass in
191 * which a fast clear has occurred).
193 * In order to avoid having multiple clear colors for a single plane of an
194 * image (hence a single RENDER_SURFACE_STATE), we only allow fast-clears on
195 * the first slice (level 0, layer 0). At the time of our testing (Jan 17,
196 * 2018), there were no known applications which would benefit from fast-
197 * clearing more than just the first slice.
199 * The fast clear portion of the image is laid out in the following order:
201 * * 1 or 4 dwords (depending on hardware generation) for the clear color
202 * * 1 dword for the anv_fast_clear_type of the clear color
203 * * On gen9+, 1 dword per level and layer of the image (3D levels count
204 * multiple layers) in level-major order for compression state.
206 * For the purpose of discoverability, the algorithm used to manage
207 * compression and fast-clears is described here:
209 * * On a transition from UNDEFINED or PREINITIALIZED to a defined layout,
210 * all of the values in the fast clear portion of the image are initialized
213 * * On fast-clear, the clear value is written into surface state and also
214 * into the buffer and the fast clear type is set appropriately. Both
215 * setting the fast-clear value in the buffer and setting the fast-clear
216 * type happen from the GPU using MI commands.
218 * * Whenever a render or blorp operation is performed with CCS_E, we call
219 * genX(cmd_buffer_mark_image_written) to set the compression state to
220 * true (which is represented by UINT32_MAX).
222 * * On pipeline barrier transitions, the worst-case transition is computed
223 * from the image layouts. The command streamer inspects the fast clear
224 * type and compression state dwords and constructs a predicate. The
225 * worst-case resolve is performed with the given predicate and the fast
226 * clear and compression state is set accordingly.
228 * See anv_layout_to_aux_usage and anv_layout_to_fast_clear_type functions for
229 * details on exactly what is allowed in what layouts.
231 * On gen7-9, we do not have a concept of indirect clear colors in hardware.
232 * In order to deal with this, we have to do some clear color management.
234 * * For LOAD_OP_LOAD at the top of a renderpass, we have to copy the clear
235 * value from the buffer into the surface state with MI commands.
237 * * For any blorp operations, we pass the address to the clear value into
238 * blorp and it knows to copy the clear color.
241 add_aux_state_tracking_buffer(struct anv_image
*image
,
242 VkImageAspectFlagBits aspect
,
244 const struct anv_device
*device
)
246 assert(image
&& device
);
247 assert(image
->planes
[plane
].aux_surface
.isl
.size
> 0 &&
248 image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
250 /* Compressed images must be tiled and therefore everything should be 4K
251 * aligned. The CCS has the same alignment requirements. This is good
252 * because we need at least dword-alignment for MI_LOAD/STORE operations.
254 assert(image
->alignment
% 4 == 0);
255 assert((image
->planes
[plane
].offset
+ image
->planes
[plane
].size
) % 4 == 0);
257 /* This buffer should be at the very end of the plane. */
258 if (image
->disjoint
) {
259 assert(image
->planes
[plane
].size
==
260 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
262 assert(image
->size
==
263 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
266 /* Clear color and fast clear type */
267 unsigned state_size
= device
->isl_dev
.ss
.clear_value_size
+ 4;
269 /* We only need to track compression on CCS_E surfaces. */
270 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
271 if (image
->type
== VK_IMAGE_TYPE_3D
) {
272 for (uint32_t l
= 0; l
< image
->levels
; l
++)
273 state_size
+= anv_minify(image
->extent
.depth
, l
) * 4;
275 state_size
+= image
->levels
* image
->array_size
* 4;
279 image
->planes
[plane
].fast_clear_state_offset
=
280 image
->planes
[plane
].offset
+ image
->planes
[plane
].size
;
282 image
->planes
[plane
].size
+= state_size
;
283 image
->size
+= state_size
;
287 * Initialize the anv_image::*_surface selected by \a aspect. Then update the
288 * image's memory requirements (that is, the image's size and alignment).
291 make_surface(const struct anv_device
*dev
,
292 struct anv_image
*image
,
293 const struct anv_image_create_info
*anv_info
,
294 isl_tiling_flags_t tiling_flags
,
295 VkImageAspectFlagBits aspect
)
297 const VkImageCreateInfo
*vk_info
= anv_info
->vk_info
;
300 static const enum isl_surf_dim vk_to_isl_surf_dim
[] = {
301 [VK_IMAGE_TYPE_1D
] = ISL_SURF_DIM_1D
,
302 [VK_IMAGE_TYPE_2D
] = ISL_SURF_DIM_2D
,
303 [VK_IMAGE_TYPE_3D
] = ISL_SURF_DIM_3D
,
306 image
->extent
= anv_sanitize_image_extent(vk_info
->imageType
,
309 const unsigned plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
310 const struct anv_format_plane plane_format
=
311 anv_get_format_plane(&dev
->info
, image
->vk_format
, aspect
, image
->tiling
);
312 struct anv_surface
*anv_surf
= &image
->planes
[plane
].surface
;
314 const isl_surf_usage_flags_t usage
=
315 choose_isl_surf_usage(vk_info
->flags
, image
->usage
,
316 anv_info
->isl_extra_usage_flags
, aspect
);
318 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
319 * fall back to linear on Broadwell and earlier because we aren't
320 * guaranteed that we can handle offsets correctly. On Sky Lake, the
321 * horizontal and vertical alignments are sufficiently high that we can
322 * just use RENDER_SURFACE_STATE::X/Y Offset.
324 bool needs_shadow
= false;
325 if (dev
->info
.gen
<= 8 &&
326 (vk_info
->flags
& VK_IMAGE_CREATE_BLOCK_TEXEL_VIEW_COMPATIBLE_BIT_KHR
) &&
327 vk_info
->tiling
== VK_IMAGE_TILING_OPTIMAL
) {
328 assert(isl_format_is_compressed(plane_format
.isl_format
));
329 tiling_flags
= ISL_TILING_LINEAR_BIT
;
333 ok
= isl_surf_init(&dev
->isl_dev
, &anv_surf
->isl
,
334 .dim
= vk_to_isl_surf_dim
[vk_info
->imageType
],
335 .format
= plane_format
.isl_format
,
336 .width
= image
->extent
.width
/ plane_format
.denominator_scales
[0],
337 .height
= image
->extent
.height
/ plane_format
.denominator_scales
[1],
338 .depth
= image
->extent
.depth
,
339 .levels
= vk_info
->mipLevels
,
340 .array_len
= vk_info
->arrayLayers
,
341 .samples
= vk_info
->samples
,
343 .row_pitch
= anv_info
->stride
,
345 .tiling_flags
= tiling_flags
);
348 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
350 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_NONE
;
352 add_surface(image
, anv_surf
, plane
);
354 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
355 * create an identical tiled shadow surface for use while texturing so we
356 * don't get garbage performance.
359 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
360 assert(tiling_flags
== ISL_TILING_LINEAR_BIT
);
362 ok
= isl_surf_init(&dev
->isl_dev
, &image
->planes
[plane
].shadow_surface
.isl
,
363 .dim
= vk_to_isl_surf_dim
[vk_info
->imageType
],
364 .format
= plane_format
.isl_format
,
365 .width
= image
->extent
.width
,
366 .height
= image
->extent
.height
,
367 .depth
= image
->extent
.depth
,
368 .levels
= vk_info
->mipLevels
,
369 .array_len
= vk_info
->arrayLayers
,
370 .samples
= vk_info
->samples
,
372 .row_pitch
= anv_info
->stride
,
374 .tiling_flags
= ISL_TILING_ANY_MASK
);
376 /* isl_surf_init() will fail only if provided invalid input. Invalid input
377 * is illegal in Vulkan.
381 add_surface(image
, &image
->planes
[plane
].shadow_surface
, plane
);
384 /* Add a HiZ surface to a depth buffer that will be used for rendering.
386 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
387 /* We don't advertise that depth buffers could be used as storage
390 assert(!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
));
392 /* Allow the user to control HiZ enabling. Disable by default on gen7
393 * because resolves are not currently implemented pre-BDW.
395 if (!(image
->usage
& VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) {
396 /* It will never be used as an attachment, HiZ is pointless. */
397 } else if (dev
->info
.gen
== 7) {
398 anv_perf_warn(dev
->instance
, image
, "Implement gen7 HiZ");
399 } else if (vk_info
->mipLevels
> 1) {
400 anv_perf_warn(dev
->instance
, image
, "Enable multi-LOD HiZ");
401 } else if (vk_info
->arrayLayers
> 1) {
402 anv_perf_warn(dev
->instance
, image
,
403 "Implement multi-arrayLayer HiZ clears and resolves");
404 } else if (dev
->info
.gen
== 8 && vk_info
->samples
> 1) {
405 anv_perf_warn(dev
->instance
, image
, "Enable gen8 multisampled HiZ");
406 } else if (!unlikely(INTEL_DEBUG
& DEBUG_NO_HIZ
)) {
407 assert(image
->planes
[plane
].aux_surface
.isl
.size
== 0);
408 ok
= isl_surf_get_hiz_surf(&dev
->isl_dev
,
409 &image
->planes
[plane
].surface
.isl
,
410 &image
->planes
[plane
].aux_surface
.isl
);
412 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
413 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_HIZ
;
415 } else if ((aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) && vk_info
->samples
== 1) {
416 /* TODO: Disallow compression with :
418 * 1) non multiplanar images (We appear to hit a sampler bug with
419 * CCS & R16G16 format. Putting the clear state a page/4096bytes
420 * further fixes the issue).
422 * 2) alias images, because they might be aliases of images
425 * 3) compression disabled by debug
427 const bool allow_compression
=
428 image
->n_planes
== 1 &&
429 (vk_info
->flags
& VK_IMAGE_CREATE_ALIAS_BIT_KHR
) == 0 &&
430 likely((INTEL_DEBUG
& DEBUG_NO_RBC
) == 0);
432 if (allow_compression
) {
433 assert(image
->planes
[plane
].aux_surface
.isl
.size
== 0);
434 ok
= isl_surf_get_ccs_surf(&dev
->isl_dev
,
435 &image
->planes
[plane
].surface
.isl
,
436 &image
->planes
[plane
].aux_surface
.isl
, 0);
439 /* Disable CCS when it is not useful (i.e., when you can't render
440 * to the image with CCS enabled).
442 if (!isl_format_supports_rendering(&dev
->info
,
443 plane_format
.isl_format
)) {
444 /* While it may be technically possible to enable CCS for this
445 * image, we currently don't have things hooked up to get it
448 anv_perf_warn(dev
->instance
, image
,
449 "This image format doesn't support rendering. "
450 "Not allocating an CCS buffer.");
451 image
->planes
[plane
].aux_surface
.isl
.size
= 0;
455 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
456 add_aux_state_tracking_buffer(image
, aspect
, plane
, dev
);
458 /* For images created without MUTABLE_FORMAT_BIT set, we know that
459 * they will always be used with the original format. In
460 * particular, they will always be used with a format that
461 * supports color compression. If it's never used as a storage
462 * image, then it will only be used through the sampler or the as
463 * a render target. This means that it's safe to just leave
464 * compression on at all times for these formats.
466 if (!(vk_info
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) &&
467 all_formats_ccs_e_compatible(&dev
->info
, vk_info
)) {
468 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_CCS_E
;
472 } else if ((aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) && vk_info
->samples
> 1) {
473 assert(!(vk_info
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
));
474 assert(image
->planes
[plane
].aux_surface
.isl
.size
== 0);
475 ok
= isl_surf_get_mcs_surf(&dev
->isl_dev
,
476 &image
->planes
[plane
].surface
.isl
,
477 &image
->planes
[plane
].aux_surface
.isl
);
479 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
480 add_aux_state_tracking_buffer(image
, aspect
, plane
, dev
);
481 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_MCS
;
485 assert((image
->planes
[plane
].offset
+ image
->planes
[plane
].size
) == image
->size
);
487 /* Upper bound of the last surface should be smaller than the plane's
490 assert((MAX2(image
->planes
[plane
].surface
.offset
,
491 image
->planes
[plane
].aux_surface
.offset
) +
492 (image
->planes
[plane
].aux_surface
.isl
.size
> 0 ?
493 image
->planes
[plane
].aux_surface
.isl
.size
:
494 image
->planes
[plane
].surface
.isl
.size
)) <=
495 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
497 if (image
->planes
[plane
].aux_surface
.isl
.size
) {
498 /* assert(image->planes[plane].fast_clear_state_offset == */
499 /* (image->planes[plane].aux_surface.offset + image->planes[plane].aux_surface.isl.size)); */
500 assert(image
->planes
[plane
].fast_clear_state_offset
<
501 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
507 static const struct isl_drm_modifier_info
*
508 get_legacy_scanout_drm_format_mod(VkImageTiling tiling
)
511 case VK_IMAGE_TILING_OPTIMAL
:
512 return isl_drm_modifier_get_info(I915_FORMAT_MOD_X_TILED
);
513 case VK_IMAGE_TILING_LINEAR
:
514 return isl_drm_modifier_get_info(DRM_FORMAT_MOD_LINEAR
);
516 unreachable("bad VkImageTiling");
521 anv_image_create(VkDevice _device
,
522 const struct anv_image_create_info
*create_info
,
523 const VkAllocationCallbacks
* alloc
,
526 ANV_FROM_HANDLE(anv_device
, device
, _device
);
527 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
528 const struct isl_drm_modifier_info
*isl_mod_info
= NULL
;
529 struct anv_image
*image
= NULL
;
532 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
534 const struct wsi_image_create_info
*wsi_info
=
535 vk_find_struct_const(pCreateInfo
->pNext
, WSI_IMAGE_CREATE_INFO_MESA
);
536 if (wsi_info
&& wsi_info
->scanout
)
537 isl_mod_info
= get_legacy_scanout_drm_format_mod(pCreateInfo
->tiling
);
539 anv_assert(pCreateInfo
->mipLevels
> 0);
540 anv_assert(pCreateInfo
->arrayLayers
> 0);
541 anv_assert(pCreateInfo
->samples
> 0);
542 anv_assert(pCreateInfo
->extent
.width
> 0);
543 anv_assert(pCreateInfo
->extent
.height
> 0);
544 anv_assert(pCreateInfo
->extent
.depth
> 0);
546 image
= vk_zalloc2(&device
->alloc
, alloc
, sizeof(*image
), 8,
547 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
549 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
551 image
->type
= pCreateInfo
->imageType
;
552 image
->extent
= pCreateInfo
->extent
;
553 image
->vk_format
= pCreateInfo
->format
;
554 image
->format
= anv_get_format(pCreateInfo
->format
);
555 image
->aspects
= vk_format_aspects(image
->vk_format
);
556 image
->levels
= pCreateInfo
->mipLevels
;
557 image
->array_size
= pCreateInfo
->arrayLayers
;
558 image
->samples
= pCreateInfo
->samples
;
559 image
->usage
= pCreateInfo
->usage
;
560 image
->tiling
= pCreateInfo
->tiling
;
561 image
->disjoint
= pCreateInfo
->flags
& VK_IMAGE_CREATE_DISJOINT_BIT_KHR
;
562 image
->drm_format_mod
= isl_mod_info
? isl_mod_info
->modifier
:
563 DRM_FORMAT_MOD_INVALID
;
565 const struct anv_format
*format
= anv_get_format(image
->vk_format
);
566 assert(format
!= NULL
);
568 const isl_tiling_flags_t isl_tiling_flags
=
569 choose_isl_tiling_flags(create_info
, isl_mod_info
);
571 image
->n_planes
= format
->n_planes
;
574 for_each_bit(b
, image
->aspects
) {
575 r
= make_surface(device
, image
, create_info
, isl_tiling_flags
,
581 *pImage
= anv_image_to_handle(image
);
587 vk_free2(&device
->alloc
, alloc
, image
);
593 anv_CreateImage(VkDevice device
,
594 const VkImageCreateInfo
*pCreateInfo
,
595 const VkAllocationCallbacks
*pAllocator
,
599 const VkNativeBufferANDROID
*gralloc_info
=
600 vk_find_struct_const(pCreateInfo
->pNext
, NATIVE_BUFFER_ANDROID
);
603 return anv_image_from_gralloc(device
, pCreateInfo
, gralloc_info
,
607 return anv_image_create(device
,
608 &(struct anv_image_create_info
) {
609 .vk_info
= pCreateInfo
,
616 anv_DestroyImage(VkDevice _device
, VkImage _image
,
617 const VkAllocationCallbacks
*pAllocator
)
619 ANV_FROM_HANDLE(anv_device
, device
, _device
);
620 ANV_FROM_HANDLE(anv_image
, image
, _image
);
625 for (uint32_t p
= 0; p
< image
->n_planes
; ++p
) {
626 if (image
->planes
[p
].bo_is_owned
) {
627 assert(image
->planes
[p
].bo
!= NULL
);
628 anv_bo_cache_release(device
, &device
->bo_cache
, image
->planes
[p
].bo
);
632 vk_free2(&device
->alloc
, pAllocator
, image
);
635 static void anv_image_bind_memory_plane(struct anv_device
*device
,
636 struct anv_image
*image
,
638 struct anv_device_memory
*memory
,
639 uint32_t memory_offset
)
641 assert(!image
->planes
[plane
].bo_is_owned
);
644 image
->planes
[plane
].bo
= NULL
;
645 image
->planes
[plane
].bo_offset
= 0;
649 image
->planes
[plane
].bo
= memory
->bo
;
650 image
->planes
[plane
].bo_offset
= memory_offset
;
653 VkResult
anv_BindImageMemory(
656 VkDeviceMemory _memory
,
657 VkDeviceSize memoryOffset
)
659 ANV_FROM_HANDLE(anv_device
, device
, _device
);
660 ANV_FROM_HANDLE(anv_device_memory
, mem
, _memory
);
661 ANV_FROM_HANDLE(anv_image
, image
, _image
);
664 anv_foreach_image_aspect_bit(aspect_bit
, image
, image
->aspects
) {
666 anv_image_aspect_to_plane(image
->aspects
, 1UL << aspect_bit
);
667 anv_image_bind_memory_plane(device
, image
, plane
, mem
, memoryOffset
);
673 VkResult
anv_BindImageMemory2KHR(
675 uint32_t bindInfoCount
,
676 const VkBindImageMemoryInfoKHR
* pBindInfos
)
678 ANV_FROM_HANDLE(anv_device
, device
, _device
);
680 for (uint32_t i
= 0; i
< bindInfoCount
; i
++) {
681 const VkBindImageMemoryInfoKHR
*bind_info
= &pBindInfos
[i
];
682 ANV_FROM_HANDLE(anv_device_memory
, mem
, bind_info
->memory
);
683 ANV_FROM_HANDLE(anv_image
, image
, bind_info
->image
);
684 VkImageAspectFlags aspects
= image
->aspects
;
686 vk_foreach_struct_const(s
, bind_info
->pNext
) {
688 case VK_STRUCTURE_TYPE_BIND_IMAGE_PLANE_MEMORY_INFO_KHR
: {
689 const VkBindImagePlaneMemoryInfoKHR
*plane_info
=
690 (const VkBindImagePlaneMemoryInfoKHR
*) s
;
692 aspects
= plane_info
->planeAspect
;
696 anv_debug_ignored_stype(s
->sType
);
702 anv_foreach_image_aspect_bit(aspect_bit
, image
, aspects
) {
704 anv_image_aspect_to_plane(image
->aspects
, 1UL << aspect_bit
);
705 anv_image_bind_memory_plane(device
, image
, plane
,
706 mem
, bind_info
->memoryOffset
);
713 void anv_GetImageSubresourceLayout(
716 const VkImageSubresource
* subresource
,
717 VkSubresourceLayout
* layout
)
719 ANV_FROM_HANDLE(anv_image
, image
, _image
);
720 const struct anv_surface
*surface
=
721 get_surface(image
, subresource
->aspectMask
);
723 assert(__builtin_popcount(subresource
->aspectMask
) == 1);
725 /* If we are on a non-zero mip level or array slice, we need to
726 * calculate a real offset.
728 anv_assert(subresource
->mipLevel
== 0);
729 anv_assert(subresource
->arrayLayer
== 0);
731 layout
->offset
= surface
->offset
;
732 layout
->rowPitch
= surface
->isl
.row_pitch
;
733 layout
->depthPitch
= isl_surf_get_array_pitch(&surface
->isl
);
734 layout
->arrayPitch
= isl_surf_get_array_pitch(&surface
->isl
);
735 layout
->size
= surface
->isl
.size
;
739 * This function determines the optimal buffer to use for a given
740 * VkImageLayout and other pieces of information needed to make that
741 * determination. This does not determine the optimal buffer to use
742 * during a resolve operation.
744 * @param devinfo The device information of the Intel GPU.
745 * @param image The image that may contain a collection of buffers.
746 * @param aspect The aspect of the image to be accessed.
747 * @param layout The current layout of the image aspect(s).
749 * @return The primary buffer that should be used for the given layout.
752 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
753 const struct anv_image
* const image
,
754 const VkImageAspectFlagBits aspect
,
755 const VkImageLayout layout
)
757 /* Validate the inputs. */
759 /* The devinfo is needed as the optimal buffer varies across generations. */
760 assert(devinfo
!= NULL
);
762 /* The layout of a NULL image is not properly defined. */
763 assert(image
!= NULL
);
765 /* The aspect must be exactly one of the image aspects. */
766 assert(_mesa_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
768 /* Determine the optimal buffer. */
770 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
772 /* If there is no auxiliary surface allocated, we must use the one and only
775 if (image
->planes
[plane
].aux_surface
.isl
.size
== 0)
776 return ISL_AUX_USAGE_NONE
;
778 /* All images that use an auxiliary surface are required to be tiled. */
779 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
781 /* Stencil has no aux */
782 assert(aspect
!= VK_IMAGE_ASPECT_STENCIL_BIT
);
786 /* Invalid Layouts */
787 case VK_IMAGE_LAYOUT_RANGE_SIZE
:
788 case VK_IMAGE_LAYOUT_MAX_ENUM
:
789 unreachable("Invalid image layout.");
793 * The pre-initialized layout is equivalent to the undefined layout for
794 * optimally-tiled images. We can only do color compression (CCS or HiZ)
797 case VK_IMAGE_LAYOUT_UNDEFINED
:
798 case VK_IMAGE_LAYOUT_PREINITIALIZED
:
799 return ISL_AUX_USAGE_NONE
;
804 case VK_IMAGE_LAYOUT_GENERAL
:
805 case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
:
806 case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
:
807 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
808 /* This buffer could be a depth buffer used in a transfer operation.
809 * BLORP currently doesn't use HiZ for transfer operations so we must
810 * use the main buffer for this layout. TODO: Enable HiZ in BLORP.
812 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_HIZ
);
813 return ISL_AUX_USAGE_NONE
;
815 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
816 return image
->planes
[plane
].aux_usage
;
820 /* Sampling Layouts */
821 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL
:
822 case VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL_KHR
:
823 assert((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
825 case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
:
826 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
827 if (anv_can_sample_with_hiz(devinfo
, image
))
828 return ISL_AUX_USAGE_HIZ
;
830 return ISL_AUX_USAGE_NONE
;
832 return image
->planes
[plane
].aux_usage
;
836 case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR
:
837 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
839 /* On SKL+, the render buffer can be decompressed by the presentation
840 * engine. Support for this feature has not yet landed in the wider
841 * ecosystem. TODO: Update this code when support lands.
843 * From the BDW PRM, Vol 7, Render Target Resolve:
845 * If the MCS is enabled on a non-multisampled render target, the
846 * render target must be resolved before being used for other
847 * purposes (display, texture, CPU lock) The clear value from
848 * SURFACE_STATE is written into pixels in the render target
849 * indicated as clear in the MCS.
851 * Pre-SKL, the render buffer must be resolved before being used for
852 * presentation. We can infer that the auxiliary buffer is not used.
854 return ISL_AUX_USAGE_NONE
;
857 /* Rendering Layouts */
858 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
:
859 assert(aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
860 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
) {
861 assert(image
->samples
== 1);
862 return ISL_AUX_USAGE_CCS_D
;
864 assert(image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_D
);
865 return image
->planes
[plane
].aux_usage
;
868 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
:
869 case VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL_KHR
:
870 assert(aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
);
871 return ISL_AUX_USAGE_HIZ
;
873 case VK_IMAGE_LAYOUT_SHARED_PRESENT_KHR
:
874 unreachable("VK_KHR_shared_presentable_image is unsupported");
877 /* If the layout isn't recognized in the exhaustive switch above, the
878 * VkImageLayout value is not defined in vulkan.h.
880 unreachable("layout is not a VkImageLayout enumeration member.");
884 * This function returns the level of unresolved fast-clear support of the
885 * given image in the given VkImageLayout.
887 * @param devinfo The device information of the Intel GPU.
888 * @param image The image that may contain a collection of buffers.
889 * @param aspect The aspect of the image to be accessed.
890 * @param layout The current layout of the image aspect(s).
892 enum anv_fast_clear_type
893 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
894 const struct anv_image
* const image
,
895 const VkImageAspectFlagBits aspect
,
896 const VkImageLayout layout
)
898 /* The aspect must be exactly one of the image aspects. */
899 assert(_mesa_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
901 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
903 /* If there is no auxiliary surface allocated, there are no fast-clears */
904 if (image
->planes
[plane
].aux_surface
.isl
.size
== 0)
905 return ANV_FAST_CLEAR_NONE
;
907 /* All images that use an auxiliary surface are required to be tiled. */
908 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
910 /* Stencil has no aux */
911 assert(aspect
!= VK_IMAGE_ASPECT_STENCIL_BIT
);
913 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
914 /* For depth images (with HiZ), the layout supports fast-clears if and
915 * only if it supports HiZ. However, we only support fast-clears to the
916 * default depth value.
918 enum isl_aux_usage aux_usage
=
919 anv_layout_to_aux_usage(devinfo
, image
, aspect
, layout
);
920 return aux_usage
== ISL_AUX_USAGE_HIZ
?
921 ANV_FAST_CLEAR_DEFAULT_VALUE
: ANV_FAST_CLEAR_NONE
;
924 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
926 /* Multisample fast-clear is not yet supported. */
927 if (image
->samples
> 1)
928 return ANV_FAST_CLEAR_NONE
;
931 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
:
932 return ANV_FAST_CLEAR_ANY
;
934 case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR
:
935 return ANV_FAST_CLEAR_NONE
;
938 /* If the image has CCS_E enabled all the time then we can use
939 * fast-clear as long as the clear color is the default value of zero
940 * since this is the default value we program into every surface state
941 * used for texturing.
943 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
)
944 return ANV_FAST_CLEAR_DEFAULT_VALUE
;
946 return ANV_FAST_CLEAR_NONE
;
951 static struct anv_state
952 alloc_surface_state(struct anv_device
*device
)
954 return anv_state_pool_alloc(&device
->surface_state_pool
, 64, 64);
957 static enum isl_channel_select
958 remap_swizzle(VkComponentSwizzle swizzle
, VkComponentSwizzle component
,
959 struct isl_swizzle format_swizzle
)
961 if (swizzle
== VK_COMPONENT_SWIZZLE_IDENTITY
)
965 case VK_COMPONENT_SWIZZLE_ZERO
: return ISL_CHANNEL_SELECT_ZERO
;
966 case VK_COMPONENT_SWIZZLE_ONE
: return ISL_CHANNEL_SELECT_ONE
;
967 case VK_COMPONENT_SWIZZLE_R
: return format_swizzle
.r
;
968 case VK_COMPONENT_SWIZZLE_G
: return format_swizzle
.g
;
969 case VK_COMPONENT_SWIZZLE_B
: return format_swizzle
.b
;
970 case VK_COMPONENT_SWIZZLE_A
: return format_swizzle
.a
;
972 unreachable("Invalid swizzle");
977 anv_image_fill_surface_state(struct anv_device
*device
,
978 const struct anv_image
*image
,
979 VkImageAspectFlagBits aspect
,
980 const struct isl_view
*view_in
,
981 isl_surf_usage_flags_t view_usage
,
982 enum isl_aux_usage aux_usage
,
983 const union isl_color_value
*clear_color
,
984 enum anv_image_view_state_flags flags
,
985 struct anv_surface_state
*state_inout
,
986 struct brw_image_param
*image_param_out
)
988 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
990 const struct anv_surface
*surface
= &image
->planes
[plane
].surface
,
991 *aux_surface
= &image
->planes
[plane
].aux_surface
;
993 struct isl_view view
= *view_in
;
994 view
.usage
|= view_usage
;
996 /* For texturing with VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL from a
997 * compressed surface with a shadow surface, we use the shadow instead of
998 * the primary surface. The shadow surface will be tiled, unlike the main
999 * surface, so it should get significantly better performance.
1001 if (image
->planes
[plane
].shadow_surface
.isl
.size
> 0 &&
1002 isl_format_is_compressed(view
.format
) &&
1003 (flags
& ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
)) {
1004 assert(isl_format_is_compressed(surface
->isl
.format
));
1005 assert(surface
->isl
.tiling
== ISL_TILING_LINEAR
);
1006 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
1007 surface
= &image
->planes
[plane
].shadow_surface
;
1010 if (view_usage
== ISL_SURF_USAGE_RENDER_TARGET_BIT
)
1011 view
.swizzle
= anv_swizzle_for_render(view
.swizzle
);
1013 /* If this is a HiZ buffer we can sample from with a programmable clear
1014 * value (SKL+), define the clear value to the optimal constant.
1016 union isl_color_value default_clear_color
= { .u32
= { 0, } };
1017 if (device
->info
.gen
>= 9 && aux_usage
== ISL_AUX_USAGE_HIZ
)
1018 default_clear_color
.f32
[0] = ANV_HZ_FC_VAL
;
1020 clear_color
= &default_clear_color
;
1022 const uint64_t address
= image
->planes
[plane
].bo_offset
+ surface
->offset
;
1023 const uint64_t aux_address
= aux_usage
== ISL_AUX_USAGE_NONE
?
1024 0 : (image
->planes
[plane
].bo_offset
+ aux_surface
->offset
);
1026 if (view_usage
== ISL_SURF_USAGE_STORAGE_BIT
&&
1027 !(flags
& ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
) &&
1028 !isl_has_matching_typed_storage_image_format(&device
->info
,
1030 /* In this case, we are a writeable storage buffer which needs to be
1031 * lowered to linear. All tiling and offset calculations will be done in
1034 assert(aux_usage
== ISL_AUX_USAGE_NONE
);
1035 isl_buffer_fill_state(&device
->isl_dev
, state_inout
->state
.map
,
1037 .size
= surface
->isl
.size
,
1038 .format
= ISL_FORMAT_RAW
,
1040 .mocs
= device
->default_mocs
);
1041 state_inout
->address
= address
,
1042 state_inout
->aux_address
= 0;
1044 if (view_usage
== ISL_SURF_USAGE_STORAGE_BIT
&&
1045 !(flags
& ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
)) {
1046 /* Typed surface reads support a very limited subset of the shader
1047 * image formats. Translate it into the closest format the hardware
1050 assert(aux_usage
== ISL_AUX_USAGE_NONE
);
1051 view
.format
= isl_lower_storage_image_format(&device
->info
,
1055 const struct isl_surf
*isl_surf
= &surface
->isl
;
1057 struct isl_surf tmp_surf
;
1058 uint32_t offset_B
= 0, tile_x_sa
= 0, tile_y_sa
= 0;
1059 if (isl_format_is_compressed(surface
->isl
.format
) &&
1060 !isl_format_is_compressed(view
.format
)) {
1061 /* We're creating an uncompressed view of a compressed surface. This
1062 * is allowed but only for a single level/layer.
1064 assert(surface
->isl
.samples
== 1);
1065 assert(view
.levels
== 1);
1066 assert(view
.array_len
== 1);
1068 isl_surf_get_image_surf(&device
->isl_dev
, isl_surf
,
1070 surface
->isl
.dim
== ISL_SURF_DIM_3D
?
1071 0 : view
.base_array_layer
,
1072 surface
->isl
.dim
== ISL_SURF_DIM_3D
?
1073 view
.base_array_layer
: 0,
1075 &offset_B
, &tile_x_sa
, &tile_y_sa
);
1077 /* The newly created image represents the one subimage we're
1078 * referencing with this view so it only has one array slice and
1081 view
.base_array_layer
= 0;
1082 view
.base_level
= 0;
1084 /* We're making an uncompressed view here. The image dimensions need
1085 * to be scaled down by the block size.
1087 const struct isl_format_layout
*fmtl
=
1088 isl_format_get_layout(surface
->isl
.format
);
1089 tmp_surf
.format
= view
.format
;
1090 tmp_surf
.logical_level0_px
.width
=
1091 DIV_ROUND_UP(tmp_surf
.logical_level0_px
.width
, fmtl
->bw
);
1092 tmp_surf
.logical_level0_px
.height
=
1093 DIV_ROUND_UP(tmp_surf
.logical_level0_px
.height
, fmtl
->bh
);
1094 tmp_surf
.phys_level0_sa
.width
/= fmtl
->bw
;
1095 tmp_surf
.phys_level0_sa
.height
/= fmtl
->bh
;
1096 tile_x_sa
/= fmtl
->bw
;
1097 tile_y_sa
/= fmtl
->bh
;
1099 isl_surf
= &tmp_surf
;
1101 if (device
->info
.gen
<= 8) {
1102 assert(surface
->isl
.tiling
== ISL_TILING_LINEAR
);
1103 assert(tile_x_sa
== 0);
1104 assert(tile_y_sa
== 0);
1108 isl_surf_fill_state(&device
->isl_dev
, state_inout
->state
.map
,
1111 .address
= address
+ offset_B
,
1112 .clear_color
= *clear_color
,
1113 .aux_surf
= &aux_surface
->isl
,
1114 .aux_usage
= aux_usage
,
1115 .aux_address
= aux_address
,
1116 .mocs
= device
->default_mocs
,
1117 .x_offset_sa
= tile_x_sa
,
1118 .y_offset_sa
= tile_y_sa
);
1119 state_inout
->address
= address
+ offset_B
;
1120 if (device
->info
.gen
>= 8) {
1121 state_inout
->aux_address
= aux_address
;
1123 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
1124 * used to store other information. This should be ok, however,
1125 * because surface buffer addresses are always 4K page alinged.
1127 uint32_t *aux_addr_dw
= state_inout
->state
.map
+
1128 device
->isl_dev
.ss
.aux_addr_offset
;
1129 assert((aux_address
& 0xfff) == 0);
1130 assert(aux_address
== (*aux_addr_dw
& 0xfffff000));
1131 state_inout
->aux_address
= *aux_addr_dw
;
1135 anv_state_flush(device
, state_inout
->state
);
1137 if (image_param_out
) {
1138 assert(view_usage
== ISL_SURF_USAGE_STORAGE_BIT
);
1139 isl_surf_fill_image_param(&device
->isl_dev
, image_param_out
,
1140 &surface
->isl
, &view
);
1144 static VkImageAspectFlags
1145 remap_aspect_flags(VkImageAspectFlags view_aspects
)
1147 if (view_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1148 if (_mesa_bitcount(view_aspects
) == 1)
1149 return VK_IMAGE_ASPECT_COLOR_BIT
;
1151 VkImageAspectFlags color_aspects
= 0;
1152 for (uint32_t i
= 0; i
< _mesa_bitcount(view_aspects
); i
++)
1153 color_aspects
|= VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
<< i
;
1154 return color_aspects
;
1156 /* No special remapping needed for depth & stencil aspects. */
1157 return view_aspects
;
1161 anv_CreateImageView(VkDevice _device
,
1162 const VkImageViewCreateInfo
*pCreateInfo
,
1163 const VkAllocationCallbacks
*pAllocator
,
1166 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1167 ANV_FROM_HANDLE(anv_image
, image
, pCreateInfo
->image
);
1168 struct anv_image_view
*iview
;
1170 iview
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*iview
), 8,
1171 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1173 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1175 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
1177 assert(range
->layerCount
> 0);
1178 assert(range
->baseMipLevel
< image
->levels
);
1180 const VkImageViewUsageCreateInfoKHR
*usage_info
=
1181 vk_find_struct_const(pCreateInfo
, IMAGE_VIEW_USAGE_CREATE_INFO_KHR
);
1182 VkImageUsageFlags view_usage
= usage_info
? usage_info
->usage
: image
->usage
;
1183 /* View usage should be a subset of image usage */
1184 assert((view_usage
& ~image
->usage
) == 0);
1185 assert(view_usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
1186 VK_IMAGE_USAGE_STORAGE_BIT
|
1187 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
1188 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
|
1189 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
));
1191 switch (image
->type
) {
1193 unreachable("bad VkImageType");
1194 case VK_IMAGE_TYPE_1D
:
1195 case VK_IMAGE_TYPE_2D
:
1196 assert(range
->baseArrayLayer
+ anv_get_layerCount(image
, range
) - 1 <= image
->array_size
);
1198 case VK_IMAGE_TYPE_3D
:
1199 assert(range
->baseArrayLayer
+ anv_get_layerCount(image
, range
) - 1
1200 <= anv_minify(image
->extent
.depth
, range
->baseMipLevel
));
1204 /* First expand aspects to the image's ones (for example
1205 * VK_IMAGE_ASPECT_COLOR_BIT will be converted to
1206 * VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | VK_IMAGE_ASPECT_PLANE_1_BIT_KHR |
1207 * VK_IMAGE_ASPECT_PLANE_2_BIT_KHR for an image of format
1208 * VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM_KHR.
1210 VkImageAspectFlags expanded_aspects
=
1211 anv_image_expand_aspects(image
, range
->aspectMask
);
1213 iview
->image
= image
;
1215 /* Remap the expanded aspects for the image view. For example if only
1216 * VK_IMAGE_ASPECT_PLANE_1_BIT_KHR was given in range->aspectMask, we will
1217 * convert it to VK_IMAGE_ASPECT_COLOR_BIT since from the point of view of
1218 * the image view, it only has a single plane.
1220 iview
->aspect_mask
= remap_aspect_flags(expanded_aspects
);
1221 iview
->n_planes
= anv_image_aspect_get_planes(iview
->aspect_mask
);
1222 iview
->vk_format
= pCreateInfo
->format
;
1224 iview
->extent
= (VkExtent3D
) {
1225 .width
= anv_minify(image
->extent
.width
, range
->baseMipLevel
),
1226 .height
= anv_minify(image
->extent
.height
, range
->baseMipLevel
),
1227 .depth
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
),
1230 /* Now go through the underlying image selected planes (computed in
1231 * expanded_aspects) and map them to planes in the image view.
1233 uint32_t iaspect_bit
, vplane
= 0;
1234 anv_foreach_image_aspect_bit(iaspect_bit
, image
, expanded_aspects
) {
1236 anv_image_aspect_to_plane(expanded_aspects
, 1UL << iaspect_bit
);
1237 VkImageAspectFlags vplane_aspect
=
1238 anv_plane_to_aspect(iview
->aspect_mask
, vplane
);
1239 struct anv_format_plane format
=
1240 anv_get_format_plane(&device
->info
, pCreateInfo
->format
,
1241 vplane_aspect
, image
->tiling
);
1243 iview
->planes
[vplane
].image_plane
= iplane
;
1245 iview
->planes
[vplane
].isl
= (struct isl_view
) {
1246 .format
= format
.isl_format
,
1247 .base_level
= range
->baseMipLevel
,
1248 .levels
= anv_get_levelCount(image
, range
),
1249 .base_array_layer
= range
->baseArrayLayer
,
1250 .array_len
= anv_get_layerCount(image
, range
),
1252 .r
= remap_swizzle(pCreateInfo
->components
.r
,
1253 VK_COMPONENT_SWIZZLE_R
, format
.swizzle
),
1254 .g
= remap_swizzle(pCreateInfo
->components
.g
,
1255 VK_COMPONENT_SWIZZLE_G
, format
.swizzle
),
1256 .b
= remap_swizzle(pCreateInfo
->components
.b
,
1257 VK_COMPONENT_SWIZZLE_B
, format
.swizzle
),
1258 .a
= remap_swizzle(pCreateInfo
->components
.a
,
1259 VK_COMPONENT_SWIZZLE_A
, format
.swizzle
),
1263 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_3D
) {
1264 iview
->planes
[vplane
].isl
.base_array_layer
= 0;
1265 iview
->planes
[vplane
].isl
.array_len
= iview
->extent
.depth
;
1268 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_CUBE
||
1269 pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
) {
1270 iview
->planes
[vplane
].isl
.usage
= ISL_SURF_USAGE_CUBE_BIT
;
1272 iview
->planes
[vplane
].isl
.usage
= 0;
1275 if (view_usage
& VK_IMAGE_USAGE_SAMPLED_BIT
||
1276 (view_usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
&&
1277 !(iview
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
))) {
1278 iview
->planes
[vplane
].optimal_sampler_surface_state
.state
= alloc_surface_state(device
);
1279 iview
->planes
[vplane
].general_sampler_surface_state
.state
= alloc_surface_state(device
);
1281 enum isl_aux_usage general_aux_usage
=
1282 anv_layout_to_aux_usage(&device
->info
, image
, 1UL << iaspect_bit
,
1283 VK_IMAGE_LAYOUT_GENERAL
);
1284 enum isl_aux_usage optimal_aux_usage
=
1285 anv_layout_to_aux_usage(&device
->info
, image
, 1UL << iaspect_bit
,
1286 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
1288 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1289 &iview
->planes
[vplane
].isl
,
1290 ISL_SURF_USAGE_TEXTURE_BIT
,
1291 optimal_aux_usage
, NULL
,
1292 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
,
1293 &iview
->planes
[vplane
].optimal_sampler_surface_state
,
1296 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1297 &iview
->planes
[vplane
].isl
,
1298 ISL_SURF_USAGE_TEXTURE_BIT
,
1299 general_aux_usage
, NULL
,
1301 &iview
->planes
[vplane
].general_sampler_surface_state
,
1305 /* NOTE: This one needs to go last since it may stomp isl_view.format */
1306 if (view_usage
& VK_IMAGE_USAGE_STORAGE_BIT
) {
1307 iview
->planes
[vplane
].storage_surface_state
.state
= alloc_surface_state(device
);
1308 iview
->planes
[vplane
].writeonly_storage_surface_state
.state
= alloc_surface_state(device
);
1310 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1311 &iview
->planes
[vplane
].isl
,
1312 ISL_SURF_USAGE_STORAGE_BIT
,
1313 ISL_AUX_USAGE_NONE
, NULL
,
1315 &iview
->planes
[vplane
].storage_surface_state
,
1316 &iview
->planes
[vplane
].storage_image_param
);
1318 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1319 &iview
->planes
[vplane
].isl
,
1320 ISL_SURF_USAGE_STORAGE_BIT
,
1321 ISL_AUX_USAGE_NONE
, NULL
,
1322 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
,
1323 &iview
->planes
[vplane
].writeonly_storage_surface_state
,
1330 *pView
= anv_image_view_to_handle(iview
);
1336 anv_DestroyImageView(VkDevice _device
, VkImageView _iview
,
1337 const VkAllocationCallbacks
*pAllocator
)
1339 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1340 ANV_FROM_HANDLE(anv_image_view
, iview
, _iview
);
1345 for (uint32_t plane
= 0; plane
< iview
->n_planes
; plane
++) {
1346 if (iview
->planes
[plane
].optimal_sampler_surface_state
.state
.alloc_size
> 0) {
1347 anv_state_pool_free(&device
->surface_state_pool
,
1348 iview
->planes
[plane
].optimal_sampler_surface_state
.state
);
1351 if (iview
->planes
[plane
].general_sampler_surface_state
.state
.alloc_size
> 0) {
1352 anv_state_pool_free(&device
->surface_state_pool
,
1353 iview
->planes
[plane
].general_sampler_surface_state
.state
);
1356 if (iview
->planes
[plane
].storage_surface_state
.state
.alloc_size
> 0) {
1357 anv_state_pool_free(&device
->surface_state_pool
,
1358 iview
->planes
[plane
].storage_surface_state
.state
);
1361 if (iview
->planes
[plane
].writeonly_storage_surface_state
.state
.alloc_size
> 0) {
1362 anv_state_pool_free(&device
->surface_state_pool
,
1363 iview
->planes
[plane
].writeonly_storage_surface_state
.state
);
1367 vk_free2(&device
->alloc
, pAllocator
, iview
);
1372 anv_CreateBufferView(VkDevice _device
,
1373 const VkBufferViewCreateInfo
*pCreateInfo
,
1374 const VkAllocationCallbacks
*pAllocator
,
1375 VkBufferView
*pView
)
1377 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1378 ANV_FROM_HANDLE(anv_buffer
, buffer
, pCreateInfo
->buffer
);
1379 struct anv_buffer_view
*view
;
1381 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1382 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1384 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1386 /* TODO: Handle the format swizzle? */
1388 view
->format
= anv_get_isl_format(&device
->info
, pCreateInfo
->format
,
1389 VK_IMAGE_ASPECT_COLOR_BIT
,
1390 VK_IMAGE_TILING_LINEAR
);
1391 const uint32_t format_bs
= isl_format_get_layout(view
->format
)->bpb
/ 8;
1392 view
->bo
= buffer
->bo
;
1393 view
->offset
= buffer
->offset
+ pCreateInfo
->offset
;
1394 view
->range
= anv_buffer_get_range(buffer
, pCreateInfo
->offset
,
1395 pCreateInfo
->range
);
1396 view
->range
= align_down_npot_u32(view
->range
, format_bs
);
1398 if (buffer
->usage
& VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT
) {
1399 view
->surface_state
= alloc_surface_state(device
);
1401 anv_fill_buffer_surface_state(device
, view
->surface_state
,
1403 view
->offset
, view
->range
, format_bs
);
1405 view
->surface_state
= (struct anv_state
){ 0 };
1408 if (buffer
->usage
& VK_BUFFER_USAGE_STORAGE_TEXEL_BUFFER_BIT
) {
1409 view
->storage_surface_state
= alloc_surface_state(device
);
1410 view
->writeonly_storage_surface_state
= alloc_surface_state(device
);
1412 enum isl_format storage_format
=
1413 isl_has_matching_typed_storage_image_format(&device
->info
,
1415 isl_lower_storage_image_format(&device
->info
, view
->format
) :
1418 anv_fill_buffer_surface_state(device
, view
->storage_surface_state
,
1420 view
->offset
, view
->range
,
1421 (storage_format
== ISL_FORMAT_RAW
? 1 :
1422 isl_format_get_layout(storage_format
)->bpb
/ 8));
1424 /* Write-only accesses should use the original format. */
1425 anv_fill_buffer_surface_state(device
, view
->writeonly_storage_surface_state
,
1427 view
->offset
, view
->range
,
1428 isl_format_get_layout(view
->format
)->bpb
/ 8);
1430 isl_buffer_fill_image_param(&device
->isl_dev
,
1431 &view
->storage_image_param
,
1432 view
->format
, view
->range
);
1434 view
->storage_surface_state
= (struct anv_state
){ 0 };
1435 view
->writeonly_storage_surface_state
= (struct anv_state
){ 0 };
1438 *pView
= anv_buffer_view_to_handle(view
);
1444 anv_DestroyBufferView(VkDevice _device
, VkBufferView bufferView
,
1445 const VkAllocationCallbacks
*pAllocator
)
1447 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1448 ANV_FROM_HANDLE(anv_buffer_view
, view
, bufferView
);
1453 if (view
->surface_state
.alloc_size
> 0)
1454 anv_state_pool_free(&device
->surface_state_pool
,
1455 view
->surface_state
);
1457 if (view
->storage_surface_state
.alloc_size
> 0)
1458 anv_state_pool_free(&device
->surface_state_pool
,
1459 view
->storage_surface_state
);
1461 if (view
->writeonly_storage_surface_state
.alloc_size
> 0)
1462 anv_state_pool_free(&device
->surface_state_pool
,
1463 view
->writeonly_storage_surface_state
);
1465 vk_free2(&device
->alloc
, pAllocator
, view
);
1468 const struct anv_surface
*
1469 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
1470 VkImageAspectFlags aspect_mask
)
1472 VkImageAspectFlags sanitized_mask
;
1474 switch (aspect_mask
) {
1475 case VK_IMAGE_ASPECT_COLOR_BIT
:
1476 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1477 sanitized_mask
= VK_IMAGE_ASPECT_COLOR_BIT
;
1479 case VK_IMAGE_ASPECT_DEPTH_BIT
:
1480 assert(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
);
1481 sanitized_mask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
1483 case VK_IMAGE_ASPECT_STENCIL_BIT
:
1484 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
1485 sanitized_mask
= VK_IMAGE_ASPECT_STENCIL_BIT
;
1487 case VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
:
1488 /* FINISHME: The Vulkan spec (git a511ba2) requires support for
1489 * combined depth stencil formats. Specifically, it states:
1491 * At least one of ename:VK_FORMAT_D24_UNORM_S8_UINT or
1492 * ename:VK_FORMAT_D32_SFLOAT_S8_UINT must be supported.
1494 * Image views with both depth and stencil aspects are only valid for
1495 * render target attachments, in which case
1496 * cmd_buffer_emit_depth_stencil() will pick out both the depth and
1497 * stencil surfaces from the underlying surface.
1499 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1500 sanitized_mask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
1502 assert(image
->aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
1503 sanitized_mask
= VK_IMAGE_ASPECT_STENCIL_BIT
;
1506 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
:
1507 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1508 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
;
1510 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR
:
1511 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1512 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_1_BIT_KHR
;
1514 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR
:
1515 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1516 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_2_BIT_KHR
;
1519 unreachable("image does not have aspect");
1523 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, sanitized_mask
);
1524 return &image
->planes
[plane
].surface
;