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[mesa.git] / src / intel / vulkan / anv_meta_blit2d.c
1 /*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "anv_meta.h"
25 #include "nir/nir_builder.h"
26
27 enum blit2d_src_type {
28 /* We can make a "normal" image view of this source and just texture
29 * from it like you would in any other shader.
30 */
31 BLIT2D_SRC_TYPE_NORMAL,
32
33 /* The source is W-tiled and we need to detile manually in the shader.
34 * This will work on any platform but is needed for all W-tiled sources
35 * prior to Broadwell.
36 */
37 BLIT2D_SRC_TYPE_W_DETILE,
38
39 BLIT2D_NUM_SRC_TYPES,
40 };
41
42 enum blit2d_dst_type {
43 /* We can bind this destination as a "normal" render target and render
44 * to it just like you would anywhere else.
45 */
46 BLIT2D_DST_TYPE_NORMAL,
47
48 /* The destination is W-tiled and we need to do the tiling manually in
49 * the shader. This is required for all W-tiled destinations.
50 *
51 * Sky Lake adds a feature for providing explicit stencil values in the
52 * shader but mesa doesn't support that yet so neither do we.
53 */
54 BLIT2D_DST_TYPE_W_TILE,
55
56 /* The destination has a 3-channel RGB format. Since we can't render to
57 * non-power-of-two textures, we have to bind it as a red texture and
58 * select the correct component for the given red pixel in the shader.
59 */
60 BLIT2D_DST_TYPE_RGB,
61
62 BLIT2D_NUM_DST_TYPES,
63 };
64
65 static VkFormat
66 vk_format_for_size(int bs)
67 {
68 /* The choice of UNORM and UINT formats is very intentional here. Most of
69 * the time, we want to use a UINT format to avoid any rounding error in
70 * the blit. For stencil blits, R8_UINT is required by the hardware.
71 * (It's the only format allowed in conjunction with W-tiling.) Also we
72 * intentionally use the 4-channel formats whenever we can. This is so
73 * that, when we do a RGB <-> RGBX copy, the two formats will line up even
74 * though one of them is 3/4 the size of the other. The choice of UNORM
75 * vs. UINT is also very intentional because Haswell doesn't handle 8 or
76 * 16-bit RGB UINT formats at all so we have to use UNORM there.
77 * Fortunately, the only time we should ever use two different formats in
78 * the table below is for RGB -> RGBA blits and so we will never have any
79 * UNORM/UINT mismatch.
80 */
81 switch (bs) {
82 case 1: return VK_FORMAT_R8_UINT;
83 case 2: return VK_FORMAT_R8G8_UINT;
84 case 3: return VK_FORMAT_R8G8B8_UNORM;
85 case 4: return VK_FORMAT_R8G8B8A8_UNORM;
86 case 6: return VK_FORMAT_R16G16B16_UNORM;
87 case 8: return VK_FORMAT_R16G16B16A16_UNORM;
88 case 12: return VK_FORMAT_R32G32B32_UINT;
89 case 16: return VK_FORMAT_R32G32B32A32_UINT;
90 default:
91 unreachable("Invalid format block size");
92 }
93 }
94
95 static void
96 create_iview(struct anv_cmd_buffer *cmd_buffer,
97 struct anv_meta_blit2d_surf *surf,
98 uint64_t offset,
99 VkImageUsageFlags usage,
100 uint32_t width,
101 uint32_t height,
102 VkImage *img,
103 struct anv_image_view *iview)
104 {
105 const VkImageCreateInfo image_info = {
106 .sType = VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO,
107 .imageType = VK_IMAGE_TYPE_2D,
108 .format = vk_format_for_size(surf->bs),
109 .extent = {
110 .width = width,
111 .height = height,
112 .depth = 1,
113 },
114 .mipLevels = 1,
115 .arrayLayers = 1,
116 .samples = 1,
117 .tiling = surf->tiling == ISL_TILING_LINEAR ?
118 VK_IMAGE_TILING_LINEAR : VK_IMAGE_TILING_OPTIMAL,
119 .usage = usage,
120 };
121
122 /* Create the VkImage that is bound to the surface's memory. */
123 anv_image_create(anv_device_to_handle(cmd_buffer->device),
124 &(struct anv_image_create_info) {
125 .vk_info = &image_info,
126 .isl_tiling_flags = 1 << surf->tiling,
127 .stride = surf->pitch,
128 }, &cmd_buffer->pool->alloc, img);
129
130 /* We could use a vk call to bind memory, but that would require
131 * creating a dummy memory object etc. so there's really no point.
132 */
133 anv_image_from_handle(*img)->bo = surf->bo;
134 anv_image_from_handle(*img)->offset = surf->base_offset + offset;
135
136 anv_image_view_init(iview, cmd_buffer->device,
137 &(VkImageViewCreateInfo) {
138 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
139 .image = *img,
140 .viewType = VK_IMAGE_VIEW_TYPE_2D,
141 .format = image_info.format,
142 .subresourceRange = {
143 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
144 .baseMipLevel = 0,
145 .levelCount = 1,
146 .baseArrayLayer = 0,
147 .layerCount = 1
148 },
149 }, cmd_buffer, usage);
150 }
151
152 struct blit2d_src_temps {
153 VkImage image;
154 struct anv_image_view iview;
155
156 struct anv_buffer buffer;
157 struct anv_buffer_view bview;
158
159 VkDescriptorPool desc_pool;
160 VkDescriptorSet set;
161 };
162
163 static void
164 blit2d_bind_src(struct anv_cmd_buffer *cmd_buffer,
165 struct anv_meta_blit2d_surf *src,
166 enum blit2d_src_type src_type,
167 struct anv_meta_blit2d_rect *rect,
168 struct blit2d_src_temps *tmp)
169 {
170 struct anv_device *device = cmd_buffer->device;
171 VkDevice vk_device = anv_device_to_handle(cmd_buffer->device);
172
173 if (src_type == BLIT2D_SRC_TYPE_NORMAL) {
174 uint32_t offset = 0;
175 isl_tiling_get_intratile_offset_el(&cmd_buffer->device->isl_dev,
176 src->tiling, src->bs, src->pitch,
177 rect->src_x, rect->src_y,
178 &offset, &rect->src_x, &rect->src_y);
179
180 create_iview(cmd_buffer, src, offset, VK_IMAGE_USAGE_SAMPLED_BIT,
181 rect->src_x + rect->width, rect->src_y + rect->height,
182 &tmp->image, &tmp->iview);
183
184 anv_CreateDescriptorPool(vk_device,
185 &(const VkDescriptorPoolCreateInfo) {
186 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_POOL_CREATE_INFO,
187 .pNext = NULL,
188 .flags = 0,
189 .maxSets = 1,
190 .poolSizeCount = 1,
191 .pPoolSizes = (VkDescriptorPoolSize[]) {
192 {
193 .type = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
194 .descriptorCount = 1
195 },
196 }
197 }, &cmd_buffer->pool->alloc, &tmp->desc_pool);
198
199 anv_AllocateDescriptorSets(vk_device,
200 &(VkDescriptorSetAllocateInfo) {
201 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_ALLOCATE_INFO,
202 .descriptorPool = tmp->desc_pool,
203 .descriptorSetCount = 1,
204 .pSetLayouts = &device->meta_state.blit2d.img_ds_layout
205 }, &tmp->set);
206
207 anv_UpdateDescriptorSets(vk_device,
208 1, /* writeCount */
209 (VkWriteDescriptorSet[]) {
210 {
211 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
212 .dstSet = tmp->set,
213 .dstBinding = 0,
214 .dstArrayElement = 0,
215 .descriptorCount = 1,
216 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
217 .pImageInfo = (VkDescriptorImageInfo[]) {
218 {
219 .sampler = NULL,
220 .imageView = anv_image_view_to_handle(&tmp->iview),
221 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
222 },
223 }
224 }
225 }, 0, NULL);
226
227 anv_CmdBindDescriptorSets(anv_cmd_buffer_to_handle(cmd_buffer),
228 VK_PIPELINE_BIND_POINT_GRAPHICS,
229 device->meta_state.blit2d.img_p_layout, 0, 1,
230 &tmp->set, 0, NULL);
231 } else {
232 assert(src_type == BLIT2D_SRC_TYPE_W_DETILE);
233 assert(src->tiling == ISL_TILING_W);
234 assert(src->bs == 1);
235
236 uint32_t tile_offset = 0;
237 isl_tiling_get_intratile_offset_el(&cmd_buffer->device->isl_dev,
238 ISL_TILING_W, 1, src->pitch,
239 rect->src_x, rect->src_y,
240 &tile_offset,
241 &rect->src_x, &rect->src_y);
242
243 tmp->buffer = (struct anv_buffer) {
244 .device = device,
245 .size = align_u32(rect->src_y + rect->height, 64) * src->pitch,
246 .usage = VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT,
247 .bo = src->bo,
248 .offset = src->base_offset + tile_offset,
249 };
250
251 anv_buffer_view_init(&tmp->bview, device,
252 &(VkBufferViewCreateInfo) {
253 .sType = VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO,
254 .buffer = anv_buffer_to_handle(&tmp->buffer),
255 .format = VK_FORMAT_R8_UINT,
256 .offset = 0,
257 .range = VK_WHOLE_SIZE,
258 }, cmd_buffer);
259
260 anv_CreateDescriptorPool(vk_device,
261 &(const VkDescriptorPoolCreateInfo) {
262 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_POOL_CREATE_INFO,
263 .pNext = NULL,
264 .flags = 0,
265 .maxSets = 1,
266 .poolSizeCount = 1,
267 .pPoolSizes = (VkDescriptorPoolSize[]) {
268 {
269 .type = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
270 .descriptorCount = 1
271 },
272 }
273 }, &cmd_buffer->pool->alloc, &tmp->desc_pool);
274
275 anv_AllocateDescriptorSets(vk_device,
276 &(VkDescriptorSetAllocateInfo) {
277 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_ALLOCATE_INFO,
278 .descriptorPool = tmp->desc_pool,
279 .descriptorSetCount = 1,
280 .pSetLayouts = &device->meta_state.blit2d.buf_ds_layout
281 }, &tmp->set);
282
283 anv_UpdateDescriptorSets(vk_device,
284 1, /* writeCount */
285 (VkWriteDescriptorSet[]) {
286 {
287 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
288 .dstSet = tmp->set,
289 .dstBinding = 0,
290 .dstArrayElement = 0,
291 .descriptorCount = 1,
292 .descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
293 .pTexelBufferView = (VkBufferView[]) {
294 anv_buffer_view_to_handle(&tmp->bview),
295 },
296 }
297 }, 0, NULL);
298
299 anv_CmdBindDescriptorSets(anv_cmd_buffer_to_handle(cmd_buffer),
300 VK_PIPELINE_BIND_POINT_GRAPHICS,
301 device->meta_state.blit2d.buf_p_layout, 0, 1,
302 &tmp->set, 0, NULL);
303 }
304 }
305
306 static void
307 blit2d_unbind_src(struct anv_cmd_buffer *cmd_buffer,
308 enum blit2d_src_type src_type,
309 struct blit2d_src_temps *tmp)
310 {
311 anv_DestroyDescriptorPool(anv_device_to_handle(cmd_buffer->device),
312 tmp->desc_pool, &cmd_buffer->pool->alloc);
313 if (src_type == BLIT2D_SRC_TYPE_NORMAL) {
314 anv_DestroyImage(anv_device_to_handle(cmd_buffer->device),
315 tmp->image, &cmd_buffer->pool->alloc);
316 }
317 }
318
319 struct blit2d_dst_temps {
320 VkImage image;
321 struct anv_image_view iview;
322 VkFramebuffer fb;
323 };
324
325 static void
326 blit2d_bind_dst(struct anv_cmd_buffer *cmd_buffer,
327 struct anv_meta_blit2d_surf *dst,
328 uint64_t offset,
329 uint32_t width,
330 uint32_t height,
331 struct blit2d_dst_temps *tmp)
332 {
333 create_iview(cmd_buffer, dst, offset, VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT,
334 width, height, &tmp->image, &tmp->iview);
335
336 anv_CreateFramebuffer(anv_device_to_handle(cmd_buffer->device),
337 &(VkFramebufferCreateInfo) {
338 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
339 .attachmentCount = 1,
340 .pAttachments = (VkImageView[]) {
341 anv_image_view_to_handle(&tmp->iview),
342 },
343 .width = width,
344 .height = height,
345 .layers = 1
346 }, &cmd_buffer->pool->alloc, &tmp->fb);
347
348
349 anv_CmdSetViewport(anv_cmd_buffer_to_handle(cmd_buffer), 0, 1,
350 &(VkViewport) {
351 .x = 0.0f,
352 .y = 0.0f,
353 .width = width,
354 .height = height,
355 .minDepth = 0.0f,
356 .maxDepth = 1.0f,
357 });
358 }
359
360 static void
361 blit2d_unbind_dst(struct anv_cmd_buffer *cmd_buffer,
362 struct blit2d_dst_temps *tmp)
363 {
364 VkDevice vk_device = anv_device_to_handle(cmd_buffer->device);
365 anv_DestroyFramebuffer(vk_device, tmp->fb, &cmd_buffer->pool->alloc);
366 anv_DestroyImage(vk_device, tmp->image, &cmd_buffer->pool->alloc);
367 }
368
369 void
370 anv_meta_end_blit2d(struct anv_cmd_buffer *cmd_buffer,
371 struct anv_meta_saved_state *save)
372 {
373 anv_meta_restore(save, cmd_buffer);
374 }
375
376 void
377 anv_meta_begin_blit2d(struct anv_cmd_buffer *cmd_buffer,
378 struct anv_meta_saved_state *save)
379 {
380 anv_meta_save(save, cmd_buffer,
381 (1 << VK_DYNAMIC_STATE_VIEWPORT));
382 }
383
384 static void
385 bind_pipeline(struct anv_cmd_buffer *cmd_buffer,
386 enum blit2d_src_type src_type,
387 enum blit2d_dst_type dst_type)
388 {
389 VkPipeline pipeline =
390 cmd_buffer->device->meta_state.blit2d.pipelines[src_type][dst_type];
391
392 if (cmd_buffer->state.pipeline != anv_pipeline_from_handle(pipeline)) {
393 anv_CmdBindPipeline(anv_cmd_buffer_to_handle(cmd_buffer),
394 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
395 }
396 }
397
398 static void
399 anv_meta_blit2d_normal_dst(struct anv_cmd_buffer *cmd_buffer,
400 struct anv_meta_blit2d_surf *src,
401 enum blit2d_src_type src_type,
402 struct anv_meta_blit2d_surf *dst,
403 unsigned num_rects,
404 struct anv_meta_blit2d_rect *rects)
405 {
406 struct anv_device *device = cmd_buffer->device;
407
408 for (unsigned r = 0; r < num_rects; ++r) {
409 struct blit2d_src_temps src_temps;
410 blit2d_bind_src(cmd_buffer, src, src_type, &rects[r], &src_temps);
411
412 uint32_t offset = 0;
413 isl_tiling_get_intratile_offset_el(&cmd_buffer->device->isl_dev,
414 dst->tiling, dst->bs, dst->pitch,
415 rects[r].dst_x, rects[r].dst_y,
416 &offset,
417 &rects[r].dst_x, &rects[r].dst_y);
418
419 struct blit2d_dst_temps dst_temps;
420 blit2d_bind_dst(cmd_buffer, dst, offset, rects[r].dst_x + rects[r].width,
421 rects[r].dst_y + rects[r].height, &dst_temps);
422
423 struct blit_vb_data {
424 float pos[2];
425 float tex_coord[3];
426 } *vb_data;
427
428 unsigned vb_size = sizeof(struct anv_vue_header) + 3 * sizeof(*vb_data);
429
430 struct anv_state vb_state =
431 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, vb_size, 16);
432 memset(vb_state.map, 0, sizeof(struct anv_vue_header));
433 vb_data = vb_state.map + sizeof(struct anv_vue_header);
434
435 vb_data[0] = (struct blit_vb_data) {
436 .pos = {
437 rects[r].dst_x + rects[r].width,
438 rects[r].dst_y + rects[r].height,
439 },
440 .tex_coord = {
441 rects[r].src_x + rects[r].width,
442 rects[r].src_y + rects[r].height,
443 src->pitch,
444 },
445 };
446
447 vb_data[1] = (struct blit_vb_data) {
448 .pos = {
449 rects[r].dst_x,
450 rects[r].dst_y + rects[r].height,
451 },
452 .tex_coord = {
453 rects[r].src_x,
454 rects[r].src_y + rects[r].height,
455 src->pitch,
456 },
457 };
458
459 vb_data[2] = (struct blit_vb_data) {
460 .pos = {
461 rects[r].dst_x,
462 rects[r].dst_y,
463 },
464 .tex_coord = {
465 rects[r].src_x,
466 rects[r].src_y,
467 src->pitch,
468 },
469 };
470
471 anv_state_clflush(vb_state);
472
473 struct anv_buffer vertex_buffer = {
474 .device = device,
475 .size = vb_size,
476 .bo = &device->dynamic_state_block_pool.bo,
477 .offset = vb_state.offset,
478 };
479
480 anv_CmdBindVertexBuffers(anv_cmd_buffer_to_handle(cmd_buffer), 0, 2,
481 (VkBuffer[]) {
482 anv_buffer_to_handle(&vertex_buffer),
483 anv_buffer_to_handle(&vertex_buffer)
484 },
485 (VkDeviceSize[]) {
486 0,
487 sizeof(struct anv_vue_header),
488 });
489
490 ANV_CALL(CmdBeginRenderPass)(anv_cmd_buffer_to_handle(cmd_buffer),
491 &(VkRenderPassBeginInfo) {
492 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
493 .renderPass = device->meta_state.blit2d.render_pass,
494 .framebuffer = dst_temps.fb,
495 .renderArea = {
496 .offset = { rects[r].dst_x, rects[r].dst_y, },
497 .extent = { rects[r].width, rects[r].height },
498 },
499 .clearValueCount = 0,
500 .pClearValues = NULL,
501 }, VK_SUBPASS_CONTENTS_INLINE);
502
503 bind_pipeline(cmd_buffer, src_type, BLIT2D_DST_TYPE_NORMAL);
504
505 ANV_CALL(CmdDraw)(anv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
506
507 ANV_CALL(CmdEndRenderPass)(anv_cmd_buffer_to_handle(cmd_buffer));
508
509 /* At the point where we emit the draw call, all data from the
510 * descriptor sets, etc. has been used. We are free to delete it.
511 */
512 blit2d_unbind_src(cmd_buffer, src_type, &src_temps);
513 blit2d_unbind_dst(cmd_buffer, &dst_temps);
514 }
515 }
516
517 static void
518 anv_meta_blit2d_w_tiled_dst(struct anv_cmd_buffer *cmd_buffer,
519 struct anv_meta_blit2d_surf *src,
520 enum blit2d_src_type src_type,
521 struct anv_meta_blit2d_surf *dst,
522 unsigned num_rects,
523 struct anv_meta_blit2d_rect *rects)
524 {
525 struct anv_device *device = cmd_buffer->device;
526
527 for (unsigned r = 0; r < num_rects; ++r) {
528 struct blit2d_src_temps src_temps;
529 blit2d_bind_src(cmd_buffer, src, src_type, &rects[r], &src_temps);
530
531 assert(dst->bs == 1);
532 uint32_t offset;
533 isl_tiling_get_intratile_offset_el(&cmd_buffer->device->isl_dev,
534 ISL_TILING_W, 1, dst->pitch,
535 rects[r].dst_x, rects[r].dst_y,
536 &offset,
537 &rects[r].dst_x, &rects[r].dst_y);
538
539 /* The original coordinates were in terms of an actual W-tiled offset
540 * but we are binding this image as Y-tiled. We need to adjust our
541 * rectangle accordingly.
542 */
543 uint32_t xmin_Y, xmax_Y, ymin_Y, ymax_Y;
544 xmin_Y = (rects[r].dst_x / 8) * 16;
545 xmax_Y = DIV_ROUND_UP(rects[r].dst_x + rects[r].width, 8) * 16;
546 ymin_Y = (rects[r].dst_y / 4) * 2;
547 ymax_Y = DIV_ROUND_UP(rects[r].dst_y + rects[r].height, 4) * 2;
548
549 struct anv_meta_blit2d_surf dst_Y = {
550 .bo = dst->bo,
551 .tiling = ISL_TILING_Y0,
552 .base_offset = dst->base_offset,
553 .bs = 1,
554 .pitch = dst->pitch * 2,
555 };
556
557 struct blit2d_dst_temps dst_temps;
558 blit2d_bind_dst(cmd_buffer, &dst_Y, offset, xmax_Y, ymax_Y, &dst_temps);
559
560 struct blit_vb_header {
561 struct anv_vue_header vue;
562 int32_t tex_offset[2];
563 uint32_t tex_pitch;
564 uint32_t bounds[4];
565 } *vb_header;
566
567 struct blit_vb_data {
568 float pos[2];
569 } *vb_data;
570
571 unsigned vb_size = sizeof(*vb_header) + 3 * sizeof(*vb_data);
572
573 struct anv_state vb_state =
574 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, vb_size, 16);
575 vb_header = vb_state.map;
576
577 *vb_header = (struct blit_vb_header) {
578 .tex_offset = {
579 rects[r].src_x - rects[r].dst_x,
580 rects[r].src_y - rects[r].dst_y,
581 },
582 .tex_pitch = src->pitch,
583 .bounds = {
584 rects[r].dst_x,
585 rects[r].dst_y,
586 rects[r].dst_x + rects[r].width,
587 rects[r].dst_y + rects[r].height,
588 },
589 };
590
591 vb_data = (void *)(vb_header + 1);
592
593 vb_data[0] = (struct blit_vb_data) {
594 .pos = {
595 xmax_Y,
596 ymax_Y,
597 },
598 };
599
600 vb_data[1] = (struct blit_vb_data) {
601 .pos = {
602 xmin_Y,
603 ymax_Y,
604 },
605 };
606
607 vb_data[2] = (struct blit_vb_data) {
608 .pos = {
609 xmin_Y,
610 ymin_Y,
611 },
612 };
613
614 anv_state_clflush(vb_state);
615
616 struct anv_buffer vertex_buffer = {
617 .device = device,
618 .size = vb_size,
619 .bo = &device->dynamic_state_block_pool.bo,
620 .offset = vb_state.offset,
621 };
622
623 anv_CmdBindVertexBuffers(anv_cmd_buffer_to_handle(cmd_buffer), 0, 2,
624 (VkBuffer[]) {
625 anv_buffer_to_handle(&vertex_buffer),
626 anv_buffer_to_handle(&vertex_buffer)
627 },
628 (VkDeviceSize[]) {
629 0,
630 (void *)vb_data - vb_state.map,
631 });
632
633 ANV_CALL(CmdBeginRenderPass)(anv_cmd_buffer_to_handle(cmd_buffer),
634 &(VkRenderPassBeginInfo) {
635 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
636 .renderPass = device->meta_state.blit2d.render_pass,
637 .framebuffer = dst_temps.fb,
638 .renderArea = {
639 .offset = { xmin_Y, ymin_Y, },
640 .extent = { xmax_Y - xmin_Y, ymax_Y - ymin_Y },
641 },
642 .clearValueCount = 0,
643 .pClearValues = NULL,
644 }, VK_SUBPASS_CONTENTS_INLINE);
645
646 bind_pipeline(cmd_buffer, src_type, BLIT2D_DST_TYPE_W_TILE);
647
648 ANV_CALL(CmdDraw)(anv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
649
650 ANV_CALL(CmdEndRenderPass)(anv_cmd_buffer_to_handle(cmd_buffer));
651
652 /* At the point where we emit the draw call, all data from the
653 * descriptor sets, etc. has been used. We are free to delete it.
654 */
655 blit2d_unbind_src(cmd_buffer, src_type, &src_temps);
656 blit2d_unbind_dst(cmd_buffer, &dst_temps);
657 }
658 }
659
660 void
661 anv_meta_blit2d(struct anv_cmd_buffer *cmd_buffer,
662 struct anv_meta_blit2d_surf *src,
663 struct anv_meta_blit2d_surf *dst,
664 unsigned num_rects,
665 struct anv_meta_blit2d_rect *rects)
666 {
667 enum blit2d_src_type src_type;
668 if (src->tiling == ISL_TILING_W && cmd_buffer->device->info.gen < 8) {
669 src_type = BLIT2D_SRC_TYPE_W_DETILE;
670 } else {
671 src_type = BLIT2D_SRC_TYPE_NORMAL;
672 }
673
674 if (dst->tiling == ISL_TILING_W) {
675 anv_meta_blit2d_w_tiled_dst(cmd_buffer, src, src_type, dst,
676 num_rects, rects);
677 return;
678 } else if (dst->bs % 3 == 0) {
679 anv_finishme("Blitting to RGB destinations not yet supported");
680 return;
681 } else {
682 assert(util_is_power_of_two(dst->bs));
683 anv_meta_blit2d_normal_dst(cmd_buffer, src, src_type, dst,
684 num_rects, rects);
685 }
686 }
687
688 static nir_shader *
689 build_nir_vertex_shader(void)
690 {
691 const struct glsl_type *vec4 = glsl_vec4_type();
692 nir_builder b;
693
694 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
695 b.shader->info.name = ralloc_strdup(b.shader, "meta_blit_vs");
696
697 nir_variable *pos_in = nir_variable_create(b.shader, nir_var_shader_in,
698 vec4, "a_pos");
699 pos_in->data.location = VERT_ATTRIB_GENERIC0;
700 nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
701 vec4, "gl_Position");
702 pos_out->data.location = VARYING_SLOT_POS;
703 nir_copy_var(&b, pos_out, pos_in);
704
705 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
706 vec4, "a_tex_pos");
707 tex_pos_in->data.location = VERT_ATTRIB_GENERIC1;
708 nir_variable *tex_pos_out = nir_variable_create(b.shader, nir_var_shader_out,
709 vec4, "v_tex_pos");
710 tex_pos_out->data.location = VARYING_SLOT_VAR0;
711 tex_pos_out->data.interpolation = INTERP_QUALIFIER_SMOOTH;
712 nir_copy_var(&b, tex_pos_out, tex_pos_in);
713
714 nir_variable *other_in = nir_variable_create(b.shader, nir_var_shader_in,
715 vec4, "a_other");
716 other_in->data.location = VERT_ATTRIB_GENERIC2;
717 nir_variable *other_out = nir_variable_create(b.shader, nir_var_shader_out,
718 vec4, "v_other");
719 other_out->data.location = VARYING_SLOT_VAR1;
720 other_out->data.interpolation = INTERP_QUALIFIER_FLAT;
721 nir_copy_var(&b, other_out, other_in);
722
723 return b.shader;
724 }
725
726 typedef nir_ssa_def* (*texel_fetch_build_func)(struct nir_builder *,
727 struct anv_device *,
728 nir_ssa_def *, nir_ssa_def *);
729
730 static nir_ssa_def *
731 nir_copy_bits(struct nir_builder *b, nir_ssa_def *dst, unsigned dst_offset,
732 nir_ssa_def *src, unsigned src_offset, unsigned num_bits)
733 {
734 unsigned src_mask = (~1u >> (32 - num_bits)) << src_offset;
735 nir_ssa_def *masked = nir_iand(b, src, nir_imm_int(b, src_mask));
736
737 nir_ssa_def *shifted;
738 if (dst_offset > src_offset) {
739 shifted = nir_ishl(b, masked, nir_imm_int(b, dst_offset - src_offset));
740 } else if (dst_offset < src_offset) {
741 shifted = nir_ushr(b, masked, nir_imm_int(b, src_offset - dst_offset));
742 } else {
743 assert(dst_offset == src_offset);
744 shifted = masked;
745 }
746
747 return nir_ior(b, dst, shifted);
748 }
749
750 static nir_ssa_def *
751 build_nir_w_tiled_fetch(struct nir_builder *b, struct anv_device *device,
752 nir_ssa_def *tex_pos, nir_ssa_def *tex_pitch)
753 {
754 nir_ssa_def *x = nir_channel(b, tex_pos, 0);
755 nir_ssa_def *y = nir_channel(b, tex_pos, 1);
756
757 /* First, compute the block-aligned offset */
758 nir_ssa_def *x_major = nir_ushr(b, x, nir_imm_int(b, 6));
759 nir_ssa_def *y_major = nir_ushr(b, y, nir_imm_int(b, 6));
760 nir_ssa_def *offset =
761 nir_iadd(b, nir_imul(b, y_major,
762 nir_imul(b, tex_pitch, nir_imm_int(b, 64))),
763 nir_imul(b, x_major, nir_imm_int(b, 4096)));
764
765 /* Compute the bottom 12 bits of the offset */
766 offset = nir_copy_bits(b, offset, 0, x, 0, 1);
767 offset = nir_copy_bits(b, offset, 1, y, 0, 1);
768 offset = nir_copy_bits(b, offset, 2, x, 1, 1);
769 offset = nir_copy_bits(b, offset, 3, y, 1, 1);
770 offset = nir_copy_bits(b, offset, 4, x, 2, 1);
771 offset = nir_copy_bits(b, offset, 5, y, 2, 4);
772 offset = nir_copy_bits(b, offset, 9, x, 3, 3);
773
774 if (device->isl_dev.has_bit6_swizzling) {
775 offset = nir_ixor(b, offset,
776 nir_ushr(b, nir_iand(b, offset, nir_imm_int(b, 0x0200)),
777 nir_imm_int(b, 3)));
778 }
779
780 const struct glsl_type *sampler_type =
781 glsl_sampler_type(GLSL_SAMPLER_DIM_BUF, false, false, GLSL_TYPE_FLOAT);
782 nir_variable *sampler = nir_variable_create(b->shader, nir_var_uniform,
783 sampler_type, "s_tex");
784 sampler->data.descriptor_set = 0;
785 sampler->data.binding = 0;
786
787 nir_tex_instr *tex = nir_tex_instr_create(b->shader, 1);
788 tex->sampler_dim = GLSL_SAMPLER_DIM_BUF;
789 tex->op = nir_texop_txf;
790 tex->src[0].src_type = nir_tex_src_coord;
791 tex->src[0].src = nir_src_for_ssa(offset);
792 tex->dest_type = nir_type_float; /* TODO */
793 tex->is_array = false;
794 tex->coord_components = 1;
795 tex->texture = nir_deref_var_create(tex, sampler);
796 tex->sampler = NULL;
797
798 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
799 nir_builder_instr_insert(b, &tex->instr);
800
801 return &tex->dest.ssa;
802 }
803
804 static nir_ssa_def *
805 build_nir_texel_fetch(struct nir_builder *b, struct anv_device *device,
806 nir_ssa_def *tex_pos, nir_ssa_def *tex_pitch)
807 {
808 const struct glsl_type *sampler_type =
809 glsl_sampler_type(GLSL_SAMPLER_DIM_2D, false, false, GLSL_TYPE_FLOAT);
810 nir_variable *sampler = nir_variable_create(b->shader, nir_var_uniform,
811 sampler_type, "s_tex");
812 sampler->data.descriptor_set = 0;
813 sampler->data.binding = 0;
814
815 nir_tex_instr *tex = nir_tex_instr_create(b->shader, 2);
816 tex->sampler_dim = GLSL_SAMPLER_DIM_2D;
817 tex->op = nir_texop_txf;
818 tex->src[0].src_type = nir_tex_src_coord;
819 tex->src[0].src = nir_src_for_ssa(tex_pos);
820 tex->src[1].src_type = nir_tex_src_lod;
821 tex->src[1].src = nir_src_for_ssa(nir_imm_int(b, 0));
822 tex->dest_type = nir_type_float; /* TODO */
823 tex->is_array = false;
824 tex->coord_components = 2;
825 tex->texture = nir_deref_var_create(tex, sampler);
826 tex->sampler = NULL;
827
828 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
829 nir_builder_instr_insert(b, &tex->instr);
830
831 return &tex->dest.ssa;
832 }
833
834 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info = {
835 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
836 .vertexBindingDescriptionCount = 2,
837 .pVertexBindingDescriptions = (VkVertexInputBindingDescription[]) {
838 {
839 .binding = 0,
840 .stride = 0,
841 .inputRate = VK_VERTEX_INPUT_RATE_INSTANCE
842 },
843 {
844 .binding = 1,
845 .stride = 5 * sizeof(float),
846 .inputRate = VK_VERTEX_INPUT_RATE_VERTEX
847 },
848 },
849 .vertexAttributeDescriptionCount = 3,
850 .pVertexAttributeDescriptions = (VkVertexInputAttributeDescription[]) {
851 {
852 /* VUE Header */
853 .location = 0,
854 .binding = 0,
855 .format = VK_FORMAT_R32G32B32A32_UINT,
856 .offset = 0
857 },
858 {
859 /* Position */
860 .location = 1,
861 .binding = 1,
862 .format = VK_FORMAT_R32G32_SFLOAT,
863 .offset = 0
864 },
865 {
866 /* Texture Coordinate */
867 .location = 2,
868 .binding = 1,
869 .format = VK_FORMAT_R32G32B32_SFLOAT,
870 .offset = 8
871 },
872 },
873 };
874
875 static nir_shader *
876 build_nir_copy_fragment_shader(struct anv_device *device,
877 texel_fetch_build_func txf_func)
878 {
879 const struct glsl_type *vec4 = glsl_vec4_type();
880 const struct glsl_type *vec3 = glsl_vector_type(GLSL_TYPE_FLOAT, 3);
881 nir_builder b;
882
883 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
884 b.shader->info.name = ralloc_strdup(b.shader, "meta_blit2d_fs");
885
886 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
887 vec3, "v_tex_pos");
888 tex_pos_in->data.location = VARYING_SLOT_VAR0;
889
890 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
891 vec4, "f_color");
892 color_out->data.location = FRAG_RESULT_DATA0;
893
894 nir_ssa_def *pos_int = nir_f2i(&b, nir_load_var(&b, tex_pos_in));
895 unsigned swiz[4] = { 0, 1 };
896 nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
897 nir_ssa_def *tex_pitch = nir_channel(&b, pos_int, 2);
898
899 nir_ssa_def *color = txf_func(&b, device, tex_pos, tex_pitch);
900 nir_store_var(&b, color_out, color, 0xf);
901
902 return b.shader;
903 }
904
905 static const VkPipelineVertexInputStateCreateInfo w_tiled_vi_create_info = {
906 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
907 .vertexBindingDescriptionCount = 2,
908 .pVertexBindingDescriptions = (VkVertexInputBindingDescription[]) {
909 {
910 .binding = 0,
911 .stride = 0,
912 .inputRate = VK_VERTEX_INPUT_RATE_INSTANCE
913 },
914 {
915 .binding = 1,
916 .stride = 2 * sizeof(float),
917 .inputRate = VK_VERTEX_INPUT_RATE_VERTEX
918 },
919 },
920 .vertexAttributeDescriptionCount = 4,
921 .pVertexAttributeDescriptions = (VkVertexInputAttributeDescription[]) {
922 {
923 /* VUE Header */
924 .location = 0,
925 .binding = 0,
926 .format = VK_FORMAT_R32G32B32A32_UINT,
927 .offset = 0
928 },
929 {
930 /* Position */
931 .location = 1,
932 .binding = 1,
933 .format = VK_FORMAT_R32G32_SFLOAT,
934 .offset = 0
935 },
936 {
937 /* Texture Offset */
938 .location = 2,
939 .binding = 0,
940 .format = VK_FORMAT_R32G32B32_UINT,
941 .offset = 16
942 },
943 {
944 /* Destination bounds */
945 .location = 3,
946 .binding = 0,
947 .format = VK_FORMAT_R32G32B32A32_UINT,
948 .offset = 28
949 },
950 },
951 };
952
953 static nir_shader *
954 build_nir_w_tiled_fragment_shader(struct anv_device *device,
955 texel_fetch_build_func txf_func)
956 {
957 const struct glsl_type *vec4 = glsl_vec4_type();
958 const struct glsl_type *ivec3 = glsl_vector_type(GLSL_TYPE_INT, 3);
959 const struct glsl_type *uvec4 = glsl_vector_type(GLSL_TYPE_UINT, 4);
960 nir_builder b;
961
962 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
963 b.shader->info.name = ralloc_strdup(b.shader, "meta_blit2d_fs");
964
965 /* We need gl_FragCoord so we know our Y-tiled position */
966 nir_variable *frag_coord_in = nir_variable_create(b.shader,
967 nir_var_shader_in,
968 vec4, "gl_FragCoord");
969 frag_coord_in->data.location = VARYING_SLOT_POS;
970 frag_coord_in->data.origin_upper_left = true;
971
972 /* In location 0 we have an ivec3 that has the offset from dest to
973 * source in the first two components and the stride in the third.
974 */
975 nir_variable *tex_off_in = nir_variable_create(b.shader, nir_var_shader_in,
976 ivec3, "v_tex_off");
977 tex_off_in->data.location = VARYING_SLOT_VAR0;
978 tex_off_in->data.interpolation = INTERP_QUALIFIER_FLAT;
979
980 /* In location 1 we have a uvec4 that gives us the bounds of the
981 * destination. We need to discard if we get outside this boundary.
982 */
983 nir_variable *bounds_in = nir_variable_create(b.shader, nir_var_shader_in,
984 uvec4, "v_bounds");
985 bounds_in->data.location = VARYING_SLOT_VAR1;
986 bounds_in->data.interpolation = INTERP_QUALIFIER_FLAT;
987
988 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
989 vec4, "f_color");
990 color_out->data.location = FRAG_RESULT_DATA0;
991
992 nir_ssa_def *frag_coord_int = nir_f2i(&b, nir_load_var(&b, frag_coord_in));
993 nir_ssa_def *x_Y = nir_channel(&b, frag_coord_int, 0);
994 nir_ssa_def *y_Y = nir_channel(&b, frag_coord_int, 1);
995
996 /* Compute the W-tiled position from the Y-tiled position */
997 nir_ssa_def *x_W = nir_iand(&b, x_Y, nir_imm_int(&b, 0xffffff80));
998 x_W = nir_ushr(&b, x_W, nir_imm_int(&b, 1));
999 x_W = nir_copy_bits(&b, x_W, 0, x_Y, 0, 1);
1000 x_W = nir_copy_bits(&b, x_W, 1, x_Y, 2, 1);
1001 x_W = nir_copy_bits(&b, x_W, 2, y_Y, 0, 1);
1002 x_W = nir_copy_bits(&b, x_W, 3, x_Y, 4, 3);
1003
1004 nir_ssa_def *y_W = nir_iand(&b, y_Y, nir_imm_int(&b, 0xffffffe0));
1005 y_W = nir_ishl(&b, y_W, nir_imm_int(&b, 1));
1006 y_W = nir_copy_bits(&b, y_W, 0, x_Y, 1, 1);
1007 y_W = nir_copy_bits(&b, y_W, 1, x_Y, 3, 1);
1008 y_W = nir_copy_bits(&b, y_W, 2, y_Y, 1, 4);
1009
1010 /* Figure out if we are out-of-bounds and discard */
1011 nir_ssa_def *bounds = nir_load_var(&b, bounds_in);
1012 nir_ssa_def *oob =
1013 nir_ior(&b, nir_ult(&b, x_W, nir_channel(&b, bounds, 0)),
1014 nir_ior(&b, nir_ult(&b, y_W, nir_channel(&b, bounds, 1)),
1015 nir_ior(&b, nir_uge(&b, x_W, nir_channel(&b, bounds, 2)),
1016 nir_uge(&b, y_W, nir_channel(&b, bounds, 3)))));
1017
1018 nir_intrinsic_instr *discard =
1019 nir_intrinsic_instr_create(b.shader, nir_intrinsic_discard_if);
1020 discard->src[0] = nir_src_for_ssa(oob);
1021 nir_builder_instr_insert(&b, &discard->instr);
1022
1023 unsigned swiz[4] = { 0, 1, 0, 0 };
1024 nir_ssa_def *tex_off =
1025 nir_swizzle(&b, nir_load_var(&b, tex_off_in), swiz, 2, false);
1026 nir_ssa_def *tex_pos = nir_iadd(&b, nir_vec2(&b, x_W, y_W), tex_off);
1027 nir_ssa_def *tex_pitch = nir_channel(&b, nir_load_var(&b, tex_off_in), 2);
1028
1029 nir_ssa_def *color = txf_func(&b, device, tex_pos, tex_pitch);
1030 nir_store_var(&b, color_out, color, 0xf);
1031
1032 return b.shader;
1033 }
1034
1035 void
1036 anv_device_finish_meta_blit2d_state(struct anv_device *device)
1037 {
1038 if (device->meta_state.blit2d.render_pass) {
1039 anv_DestroyRenderPass(anv_device_to_handle(device),
1040 device->meta_state.blit2d.render_pass,
1041 &device->meta_state.alloc);
1042 }
1043
1044 if (device->meta_state.blit2d.img_p_layout) {
1045 anv_DestroyPipelineLayout(anv_device_to_handle(device),
1046 device->meta_state.blit2d.img_p_layout,
1047 &device->meta_state.alloc);
1048 }
1049
1050 if (device->meta_state.blit2d.img_ds_layout) {
1051 anv_DestroyDescriptorSetLayout(anv_device_to_handle(device),
1052 device->meta_state.blit2d.img_ds_layout,
1053 &device->meta_state.alloc);
1054 }
1055
1056 if (device->meta_state.blit2d.buf_p_layout) {
1057 anv_DestroyPipelineLayout(anv_device_to_handle(device),
1058 device->meta_state.blit2d.buf_p_layout,
1059 &device->meta_state.alloc);
1060 }
1061
1062 if (device->meta_state.blit2d.buf_ds_layout) {
1063 anv_DestroyDescriptorSetLayout(anv_device_to_handle(device),
1064 device->meta_state.blit2d.buf_ds_layout,
1065 &device->meta_state.alloc);
1066 }
1067
1068 for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
1069 for (unsigned dst = 0; dst < BLIT2D_NUM_DST_TYPES; dst++) {
1070 if (device->meta_state.blit2d.pipelines[src][dst]) {
1071 anv_DestroyPipeline(anv_device_to_handle(device),
1072 device->meta_state.blit2d.pipelines[src][dst],
1073 &device->meta_state.alloc);
1074 }
1075 }
1076 }
1077 }
1078
1079 static VkResult
1080 blit2d_init_pipeline(struct anv_device *device,
1081 enum blit2d_src_type src_type,
1082 enum blit2d_dst_type dst_type)
1083 {
1084 VkResult result;
1085
1086 texel_fetch_build_func src_func;
1087 switch (src_type) {
1088 case BLIT2D_SRC_TYPE_NORMAL:
1089 src_func = build_nir_texel_fetch;
1090 break;
1091 case BLIT2D_SRC_TYPE_W_DETILE:
1092 src_func = build_nir_w_tiled_fetch;
1093 break;
1094 default:
1095 unreachable("Invalid blit2d source type");
1096 }
1097
1098 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
1099 struct anv_shader_module fs = { .nir = NULL };
1100 switch (dst_type) {
1101 case BLIT2D_DST_TYPE_NORMAL:
1102 fs.nir = build_nir_copy_fragment_shader(device, src_func);
1103 vi_create_info = &normal_vi_create_info;
1104 break;
1105 case BLIT2D_DST_TYPE_W_TILE:
1106 fs.nir = build_nir_w_tiled_fragment_shader(device, src_func);
1107 vi_create_info = &w_tiled_vi_create_info;
1108 break;
1109 case BLIT2D_DST_TYPE_RGB:
1110 /* Not yet supported */
1111 default:
1112 return VK_SUCCESS;
1113 }
1114
1115 /* We don't use a vertex shader for blitting, but instead build and pass
1116 * the VUEs directly to the rasterization backend. However, we do need
1117 * to provide GLSL source for the vertex shader so that the compiler
1118 * does not dead-code our inputs.
1119 */
1120 struct anv_shader_module vs = {
1121 .nir = build_nir_vertex_shader(),
1122 };
1123
1124 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
1125 {
1126 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1127 .stage = VK_SHADER_STAGE_VERTEX_BIT,
1128 .module = anv_shader_module_to_handle(&vs),
1129 .pName = "main",
1130 .pSpecializationInfo = NULL
1131 }, {
1132 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1133 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
1134 .module = anv_shader_module_to_handle(&fs),
1135 .pName = "main",
1136 .pSpecializationInfo = NULL
1137 },
1138 };
1139
1140 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
1141 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
1142 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
1143 .pStages = pipeline_shader_stages,
1144 .pVertexInputState = vi_create_info,
1145 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
1146 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
1147 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
1148 .primitiveRestartEnable = false,
1149 },
1150 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
1151 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
1152 .viewportCount = 1,
1153 .scissorCount = 1,
1154 },
1155 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
1156 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
1157 .rasterizerDiscardEnable = false,
1158 .polygonMode = VK_POLYGON_MODE_FILL,
1159 .cullMode = VK_CULL_MODE_NONE,
1160 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
1161 },
1162 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
1163 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
1164 .rasterizationSamples = 1,
1165 .sampleShadingEnable = false,
1166 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
1167 },
1168 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
1169 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
1170 .attachmentCount = 1,
1171 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
1172 { .colorWriteMask =
1173 VK_COLOR_COMPONENT_A_BIT |
1174 VK_COLOR_COMPONENT_R_BIT |
1175 VK_COLOR_COMPONENT_G_BIT |
1176 VK_COLOR_COMPONENT_B_BIT },
1177 }
1178 },
1179 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
1180 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
1181 .dynamicStateCount = 9,
1182 .pDynamicStates = (VkDynamicState[]) {
1183 VK_DYNAMIC_STATE_VIEWPORT,
1184 VK_DYNAMIC_STATE_SCISSOR,
1185 VK_DYNAMIC_STATE_LINE_WIDTH,
1186 VK_DYNAMIC_STATE_DEPTH_BIAS,
1187 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
1188 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
1189 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
1190 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
1191 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
1192 },
1193 },
1194 .flags = 0,
1195 .layout = device->meta_state.blit2d.img_p_layout,
1196 .renderPass = device->meta_state.blit2d.render_pass,
1197 .subpass = 0,
1198 };
1199
1200 const struct anv_graphics_pipeline_create_info anv_pipeline_info = {
1201 .color_attachment_count = -1,
1202 .use_repclear = false,
1203 .disable_viewport = true,
1204 .disable_scissor = true,
1205 .disable_vs = true,
1206 .use_rectlist = true
1207 };
1208
1209 result = anv_graphics_pipeline_create(anv_device_to_handle(device),
1210 VK_NULL_HANDLE,
1211 &vk_pipeline_info, &anv_pipeline_info,
1212 &device->meta_state.alloc,
1213 &device->meta_state.blit2d.pipelines[src_type][dst_type]);
1214
1215 ralloc_free(vs.nir);
1216 ralloc_free(fs.nir);
1217
1218 return result;
1219 }
1220
1221 VkResult
1222 anv_device_init_meta_blit2d_state(struct anv_device *device)
1223 {
1224 VkResult result;
1225
1226 zero(device->meta_state.blit2d);
1227
1228 result = anv_CreateRenderPass(anv_device_to_handle(device),
1229 &(VkRenderPassCreateInfo) {
1230 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1231 .attachmentCount = 1,
1232 .pAttachments = &(VkAttachmentDescription) {
1233 .format = VK_FORMAT_UNDEFINED, /* Our shaders don't care */
1234 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1235 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1236 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
1237 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
1238 },
1239 .subpassCount = 1,
1240 .pSubpasses = &(VkSubpassDescription) {
1241 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1242 .inputAttachmentCount = 0,
1243 .colorAttachmentCount = 1,
1244 .pColorAttachments = &(VkAttachmentReference) {
1245 .attachment = 0,
1246 .layout = VK_IMAGE_LAYOUT_GENERAL,
1247 },
1248 .pResolveAttachments = NULL,
1249 .pDepthStencilAttachment = &(VkAttachmentReference) {
1250 .attachment = VK_ATTACHMENT_UNUSED,
1251 .layout = VK_IMAGE_LAYOUT_GENERAL,
1252 },
1253 .preserveAttachmentCount = 1,
1254 .pPreserveAttachments = (uint32_t[]) { 0 },
1255 },
1256 .dependencyCount = 0,
1257 }, &device->meta_state.alloc, &device->meta_state.blit2d.render_pass);
1258 if (result != VK_SUCCESS)
1259 goto fail;
1260
1261 result = anv_CreateDescriptorSetLayout(anv_device_to_handle(device),
1262 &(VkDescriptorSetLayoutCreateInfo) {
1263 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1264 .bindingCount = 1,
1265 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1266 {
1267 .binding = 0,
1268 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
1269 .descriptorCount = 1,
1270 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1271 .pImmutableSamplers = NULL
1272 },
1273 }
1274 }, &device->meta_state.alloc, &device->meta_state.blit2d.img_ds_layout);
1275 if (result != VK_SUCCESS)
1276 goto fail;
1277
1278 result = anv_CreatePipelineLayout(anv_device_to_handle(device),
1279 &(VkPipelineLayoutCreateInfo) {
1280 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1281 .setLayoutCount = 1,
1282 .pSetLayouts = &device->meta_state.blit2d.img_ds_layout,
1283 },
1284 &device->meta_state.alloc, &device->meta_state.blit2d.img_p_layout);
1285 if (result != VK_SUCCESS)
1286 goto fail;
1287
1288 result = anv_CreateDescriptorSetLayout(anv_device_to_handle(device),
1289 &(VkDescriptorSetLayoutCreateInfo) {
1290 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1291 .bindingCount = 1,
1292 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1293 {
1294 .binding = 0,
1295 .descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
1296 .descriptorCount = 1,
1297 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1298 .pImmutableSamplers = NULL
1299 },
1300 }
1301 }, &device->meta_state.alloc, &device->meta_state.blit2d.buf_ds_layout);
1302 if (result != VK_SUCCESS)
1303 goto fail;
1304
1305 result = anv_CreatePipelineLayout(anv_device_to_handle(device),
1306 &(VkPipelineLayoutCreateInfo) {
1307 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1308 .setLayoutCount = 1,
1309 .pSetLayouts = &device->meta_state.blit2d.buf_ds_layout,
1310 },
1311 &device->meta_state.alloc, &device->meta_state.blit2d.buf_p_layout);
1312 if (result != VK_SUCCESS)
1313 goto fail;
1314
1315 for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
1316 for (unsigned dst = 0; dst < BLIT2D_NUM_DST_TYPES; dst++) {
1317 result = blit2d_init_pipeline(device, src, dst);
1318 if (result != VK_SUCCESS)
1319 goto fail;
1320 }
1321 }
1322
1323 return VK_SUCCESS;
1324
1325 fail:
1326 anv_device_finish_meta_blit2d_state(device);
1327 return result;
1328 }