2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "program/prog_parameter.h"
26 #include "nir/nir_builder.h"
28 struct apply_pipeline_layout_state
{
32 struct anv_pipeline_layout
*layout
;
33 bool add_bounds_checks
;
37 uint8_t *surface_offsets
;
38 uint8_t *sampler_offsets
;
39 uint8_t *image_offsets
;
44 add_binding(struct apply_pipeline_layout_state
*state
,
45 uint32_t set
, uint32_t binding
)
47 BITSET_SET(state
->set
[set
].used
, binding
);
51 add_var_binding(struct apply_pipeline_layout_state
*state
, nir_variable
*var
)
53 add_binding(state
, var
->data
.descriptor_set
, var
->data
.binding
);
57 get_used_bindings_block(nir_block
*block
,
58 struct apply_pipeline_layout_state
*state
)
60 nir_foreach_instr_safe(instr
, block
) {
61 switch (instr
->type
) {
62 case nir_instr_type_intrinsic
: {
63 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
64 switch (intrin
->intrinsic
) {
65 case nir_intrinsic_vulkan_resource_index
:
66 add_binding(state
, nir_intrinsic_desc_set(intrin
),
67 nir_intrinsic_binding(intrin
));
70 case nir_intrinsic_image_load
:
71 case nir_intrinsic_image_store
:
72 case nir_intrinsic_image_atomic_add
:
73 case nir_intrinsic_image_atomic_min
:
74 case nir_intrinsic_image_atomic_max
:
75 case nir_intrinsic_image_atomic_and
:
76 case nir_intrinsic_image_atomic_or
:
77 case nir_intrinsic_image_atomic_xor
:
78 case nir_intrinsic_image_atomic_exchange
:
79 case nir_intrinsic_image_atomic_comp_swap
:
80 case nir_intrinsic_image_size
:
81 case nir_intrinsic_image_samples
:
82 add_var_binding(state
, intrin
->variables
[0]->var
);
90 case nir_instr_type_tex
: {
91 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
93 add_var_binding(state
, tex
->texture
->var
);
95 add_var_binding(state
, tex
->sampler
->var
);
105 lower_res_index_intrinsic(nir_intrinsic_instr
*intrin
,
106 struct apply_pipeline_layout_state
*state
)
108 nir_builder
*b
= &state
->builder
;
110 b
->cursor
= nir_before_instr(&intrin
->instr
);
112 uint32_t set
= nir_intrinsic_desc_set(intrin
);
113 uint32_t binding
= nir_intrinsic_binding(intrin
);
115 uint32_t surface_index
= state
->set
[set
].surface_offsets
[binding
];
116 uint32_t array_size
=
117 state
->layout
->set
[set
].layout
->binding
[binding
].array_size
;
119 nir_ssa_def
*block_index
= nir_ssa_for_src(b
, intrin
->src
[0], 1);
121 if (state
->add_bounds_checks
)
122 block_index
= nir_umin(b
, block_index
, nir_imm_int(b
, array_size
- 1));
124 block_index
= nir_iadd(b
, nir_imm_int(b
, surface_index
), block_index
);
126 assert(intrin
->dest
.is_ssa
);
127 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
, nir_src_for_ssa(block_index
));
128 nir_instr_remove(&intrin
->instr
);
132 lower_tex_deref(nir_tex_instr
*tex
, nir_deref_var
*deref
,
133 unsigned *const_index
, unsigned array_size
,
134 nir_tex_src_type src_type
, bool allow_indirect
,
135 struct apply_pipeline_layout_state
*state
)
137 nir_builder
*b
= &state
->builder
;
139 if (deref
->deref
.child
) {
140 assert(deref
->deref
.child
->deref_type
== nir_deref_type_array
);
141 nir_deref_array
*deref_array
= nir_deref_as_array(deref
->deref
.child
);
143 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
144 /* From VK_KHR_sampler_ycbcr_conversion:
146 * If sampler Y’CBCR conversion is enabled, the combined image
147 * sampler must be indexed only by constant integral expressions when
148 * aggregated into arrays in shader code, irrespective of the
149 * shaderSampledImageArrayDynamicIndexing feature.
151 assert(allow_indirect
);
154 nir_iadd(b
, nir_imm_int(b
, deref_array
->base_offset
),
155 nir_ssa_for_src(b
, deref_array
->indirect
, 1));
157 if (state
->add_bounds_checks
)
158 index
= nir_umin(b
, index
, nir_imm_int(b
, array_size
- 1));
160 nir_tex_instr_add_src(tex
, src_type
, nir_src_for_ssa(index
));
162 *const_index
+= MIN2(deref_array
->base_offset
, array_size
- 1);
168 cleanup_tex_deref(nir_tex_instr
*tex
, nir_deref_var
*deref
)
170 if (deref
->deref
.child
== NULL
)
173 nir_deref_array
*deref_array
= nir_deref_as_array(deref
->deref
.child
);
175 if (deref_array
->deref_array_type
!= nir_deref_array_type_indirect
)
178 nir_instr_rewrite_src(&tex
->instr
, &deref_array
->indirect
, NIR_SRC_INIT
);
182 has_tex_src_plane(nir_tex_instr
*tex
)
184 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
185 if (tex
->src
[i
].src_type
== nir_tex_src_plane
)
193 extract_tex_src_plane(nir_tex_instr
*tex
)
197 int plane_src_idx
= -1;
198 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
199 if (tex
->src
[i
].src_type
== nir_tex_src_plane
) {
200 nir_const_value
*const_plane
=
201 nir_src_as_const_value(tex
->src
[i
].src
);
203 /* Our color conversion lowering pass should only ever insert
206 plane
= const_plane
->u32
[0];
211 assert(plane_src_idx
>= 0);
212 nir_tex_instr_remove_src(tex
, plane_src_idx
);
218 lower_tex(nir_tex_instr
*tex
, struct apply_pipeline_layout_state
*state
)
220 /* No one should have come by and lowered it already */
221 assert(tex
->texture
);
223 state
->builder
.cursor
= nir_before_instr(&tex
->instr
);
225 unsigned set
= tex
->texture
->var
->data
.descriptor_set
;
226 unsigned binding
= tex
->texture
->var
->data
.binding
;
227 unsigned array_size
=
228 state
->layout
->set
[set
].layout
->binding
[binding
].array_size
;
229 bool has_plane
= has_tex_src_plane(tex
);
230 unsigned plane
= has_plane
? extract_tex_src_plane(tex
) : 0;
232 tex
->texture_index
= state
->set
[set
].surface_offsets
[binding
];
233 lower_tex_deref(tex
, tex
->texture
, &tex
->texture_index
, array_size
,
234 nir_tex_src_texture_offset
, !has_plane
, state
);
235 tex
->texture_index
+= plane
;
238 unsigned set
= tex
->sampler
->var
->data
.descriptor_set
;
239 unsigned binding
= tex
->sampler
->var
->data
.binding
;
240 unsigned array_size
=
241 state
->layout
->set
[set
].layout
->binding
[binding
].array_size
;
242 tex
->sampler_index
= state
->set
[set
].sampler_offsets
[binding
];
243 lower_tex_deref(tex
, tex
->sampler
, &tex
->sampler_index
, array_size
,
244 nir_tex_src_sampler_offset
, !has_plane
, state
);
245 tex
->sampler_index
+= plane
;
248 /* The backend only ever uses this to mark used surfaces. We don't care
249 * about that little optimization so it just needs to be non-zero.
251 tex
->texture_array_size
= 1;
253 cleanup_tex_deref(tex
, tex
->texture
);
255 cleanup_tex_deref(tex
, tex
->sampler
);
261 apply_pipeline_layout_block(nir_block
*block
,
262 struct apply_pipeline_layout_state
*state
)
264 nir_foreach_instr_safe(instr
, block
) {
265 switch (instr
->type
) {
266 case nir_instr_type_intrinsic
: {
267 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
268 if (intrin
->intrinsic
== nir_intrinsic_vulkan_resource_index
) {
269 lower_res_index_intrinsic(intrin
, state
);
273 case nir_instr_type_tex
:
274 lower_tex(nir_instr_as_tex(instr
), state
);
283 setup_vec4_uniform_value(uint32_t *params
, uint32_t offset
, unsigned n
)
285 for (unsigned i
= 0; i
< n
; ++i
)
286 params
[i
] = ANV_PARAM_PUSH(offset
+ i
* sizeof(uint32_t));
288 for (unsigned i
= n
; i
< 4; ++i
)
289 params
[i
] = BRW_PARAM_BUILTIN_ZERO
;
293 anv_nir_apply_pipeline_layout(struct anv_pipeline
*pipeline
,
295 struct brw_stage_prog_data
*prog_data
,
296 struct anv_pipeline_bind_map
*map
)
298 struct anv_pipeline_layout
*layout
= pipeline
->layout
;
300 struct apply_pipeline_layout_state state
= {
303 .add_bounds_checks
= pipeline
->device
->robust_buffer_access
,
306 void *mem_ctx
= ralloc_context(NULL
);
308 for (unsigned s
= 0; s
< layout
->num_sets
; s
++) {
309 const unsigned count
= layout
->set
[s
].layout
->binding_count
;
310 const unsigned words
= BITSET_WORDS(count
);
311 state
.set
[s
].used
= rzalloc_array(mem_ctx
, BITSET_WORD
, words
);
312 state
.set
[s
].surface_offsets
= rzalloc_array(mem_ctx
, uint8_t, count
);
313 state
.set
[s
].sampler_offsets
= rzalloc_array(mem_ctx
, uint8_t, count
);
314 state
.set
[s
].image_offsets
= rzalloc_array(mem_ctx
, uint8_t, count
);
317 nir_foreach_function(function
, shader
) {
321 nir_foreach_block(block
, function
->impl
)
322 get_used_bindings_block(block
, &state
);
325 for (uint32_t set
= 0; set
< layout
->num_sets
; set
++) {
326 struct anv_descriptor_set_layout
*set_layout
= layout
->set
[set
].layout
;
329 BITSET_FOREACH_SET(b
, _tmp
, state
.set
[set
].used
,
330 set_layout
->binding_count
) {
331 if (set_layout
->binding
[b
].stage
[shader
->stage
].surface_index
>= 0) {
332 map
->surface_count
+=
333 anv_descriptor_set_binding_layout_get_hw_size(&set_layout
->binding
[b
]);
335 if (set_layout
->binding
[b
].stage
[shader
->stage
].sampler_index
>= 0) {
336 map
->sampler_count
+=
337 anv_descriptor_set_binding_layout_get_hw_size(&set_layout
->binding
[b
]);
339 if (set_layout
->binding
[b
].stage
[shader
->stage
].image_index
>= 0)
340 map
->image_count
+= set_layout
->binding
[b
].array_size
;
344 unsigned surface
= 0;
345 unsigned sampler
= 0;
347 for (uint32_t set
= 0; set
< layout
->num_sets
; set
++) {
348 struct anv_descriptor_set_layout
*set_layout
= layout
->set
[set
].layout
;
351 BITSET_FOREACH_SET(b
, _tmp
, state
.set
[set
].used
,
352 set_layout
->binding_count
) {
353 struct anv_descriptor_set_binding_layout
*binding
=
354 &set_layout
->binding
[b
];
356 if (binding
->stage
[shader
->stage
].surface_index
>= 0) {
357 state
.set
[set
].surface_offsets
[b
] = surface
;
358 struct anv_sampler
**samplers
= binding
->immutable_samplers
;
359 for (unsigned i
= 0; i
< binding
->array_size
; i
++) {
360 uint8_t planes
= samplers
? samplers
[i
]->n_planes
: 1;
361 for (uint8_t p
= 0; p
< planes
; p
++) {
362 map
->surface_to_descriptor
[surface
].set
= set
;
363 map
->surface_to_descriptor
[surface
].binding
= b
;
364 map
->surface_to_descriptor
[surface
].index
= i
;
365 map
->surface_to_descriptor
[surface
].plane
= p
;
371 if (binding
->stage
[shader
->stage
].sampler_index
>= 0) {
372 state
.set
[set
].sampler_offsets
[b
] = sampler
;
373 struct anv_sampler
**samplers
= binding
->immutable_samplers
;
374 for (unsigned i
= 0; i
< binding
->array_size
; i
++) {
375 uint8_t planes
= samplers
? samplers
[i
]->n_planes
: 1;
376 for (uint8_t p
= 0; p
< planes
; p
++) {
377 map
->sampler_to_descriptor
[sampler
].set
= set
;
378 map
->sampler_to_descriptor
[sampler
].binding
= b
;
379 map
->sampler_to_descriptor
[sampler
].index
= i
;
380 map
->sampler_to_descriptor
[sampler
].plane
= p
;
386 if (binding
->stage
[shader
->stage
].image_index
>= 0) {
387 state
.set
[set
].image_offsets
[b
] = image
;
388 image
+= binding
->array_size
;
393 nir_foreach_variable(var
, &shader
->uniforms
) {
394 if (!glsl_type_is_image(var
->interface_type
))
397 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(var
->interface_type
);
399 const uint32_t set
= var
->data
.descriptor_set
;
400 const uint32_t binding
= var
->data
.binding
;
401 const uint32_t array_size
=
402 layout
->set
[set
].layout
->binding
[binding
].array_size
;
404 if (!BITSET_TEST(state
.set
[set
].used
, binding
))
407 struct anv_pipeline_binding
*pipe_binding
=
408 &map
->surface_to_descriptor
[state
.set
[set
].surface_offsets
[binding
]];
409 for (unsigned i
= 0; i
< array_size
; i
++) {
410 assert(pipe_binding
[i
].set
== set
);
411 assert(pipe_binding
[i
].binding
== binding
);
412 assert(pipe_binding
[i
].index
== i
);
414 if (dim
== GLSL_SAMPLER_DIM_SUBPASS
||
415 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
)
416 pipe_binding
[i
].input_attachment_index
= var
->data
.index
+ i
;
418 pipe_binding
[i
].write_only
= var
->data
.image
.write_only
;
422 nir_foreach_function(function
, shader
) {
426 nir_builder_init(&state
.builder
, function
->impl
);
427 nir_foreach_block(block
, function
->impl
)
428 apply_pipeline_layout_block(block
, &state
);
429 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
|
430 nir_metadata_dominance
);
433 if (map
->image_count
> 0) {
434 assert(map
->image_count
<= MAX_IMAGES
);
435 nir_foreach_variable(var
, &shader
->uniforms
) {
436 if (glsl_type_is_image(var
->type
) ||
437 (glsl_type_is_array(var
->type
) &&
438 glsl_type_is_image(glsl_get_array_element(var
->type
)))) {
439 /* Images are represented as uniform push constants and the actual
440 * information required for reading/writing to/from the image is
441 * storred in the uniform.
443 unsigned set
= var
->data
.descriptor_set
;
444 unsigned binding
= var
->data
.binding
;
445 unsigned image_index
= state
.set
[set
].image_offsets
[binding
];
447 var
->data
.driver_location
= shader
->num_uniforms
+
448 image_index
* BRW_IMAGE_PARAM_SIZE
* 4;
452 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
,
454 BRW_IMAGE_PARAM_SIZE
);
455 struct anv_push_constants
*null_data
= NULL
;
456 const struct brw_image_param
*image_param
= null_data
->images
;
457 for (uint32_t i
= 0; i
< map
->image_count
; i
++) {
458 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET
,
459 (uintptr_t)&image_param
->surface_idx
, 1);
460 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_OFFSET_OFFSET
,
461 (uintptr_t)image_param
->offset
, 2);
462 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SIZE_OFFSET
,
463 (uintptr_t)image_param
->size
, 3);
464 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_STRIDE_OFFSET
,
465 (uintptr_t)image_param
->stride
, 4);
466 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_TILING_OFFSET
,
467 (uintptr_t)image_param
->tiling
, 3);
468 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SWIZZLING_OFFSET
,
469 (uintptr_t)image_param
->swizzling
, 2);
471 param
+= BRW_IMAGE_PARAM_SIZE
;
474 assert(param
== prog_data
->param
+ prog_data
->nr_params
);
476 shader
->num_uniforms
+= map
->image_count
* BRW_IMAGE_PARAM_SIZE
* 4;
479 ralloc_free(mem_ctx
);