src/intel/vulkan/anv_nir_apply_pipeline_layout.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "anv_nir.h"
  25 #include "program/prog_parameter.h"
  26 #include "nir/nir_builder.h"
  27 #include "compiler/brw_nir.h"
  28
  29 struct apply_pipeline_layout_state {
  30    nir_shader *shader;
  31    nir_builder builder;
  32
  33    struct anv_pipeline_layout *layout;
  34    bool add_bounds_checks;
  35
  36    unsigned first_image_uniform;
  37
  38    bool uses_constants;
  39    uint8_t constants_offset;
  40    struct {
  41       BITSET_WORD *used;
  42       uint8_t *surface_offsets;
  43       uint8_t *sampler_offsets;
  44       uint8_t *image_offsets;
  45    } set[MAX_SETS];
  46 };
  47
  48 static void
  49 add_binding(struct apply_pipeline_layout_state *state,
  50             uint32_t set, uint32_t binding)
  51 {
  52    BITSET_SET(state->set[set].used, binding);
  53 }
  54
  55 static void
  56 add_var_binding(struct apply_pipeline_layout_state *state, nir_variable *var)
  57 {
  58    add_binding(state, var->data.descriptor_set, var->data.binding);
  59 }
  60
  61 static void
  62 add_deref_src_binding(struct apply_pipeline_layout_state *state, nir_src src)
  63 {
  64    nir_deref_instr *deref = nir_src_as_deref(src);
  65    add_var_binding(state, nir_deref_instr_get_variable(deref));
  66 }
  67
  68 static void
  69 add_tex_src_binding(struct apply_pipeline_layout_state *state,
  70                     nir_tex_instr *tex, nir_tex_src_type deref_src_type)
  71 {
  72    int deref_src_idx = nir_tex_instr_src_index(tex, deref_src_type);
  73    if (deref_src_idx < 0)
  74       return;
  75
  76    add_deref_src_binding(state, tex->src[deref_src_idx].src);
  77 }
  78
  79 static void
  80 get_used_bindings_block(nir_block *block,
  81                         struct apply_pipeline_layout_state *state)
  82 {
  83    nir_foreach_instr_safe(instr, block) {
  84       switch (instr->type) {
  85       case nir_instr_type_intrinsic: {
  86          nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
  87          switch (intrin->intrinsic) {
  88          case nir_intrinsic_vulkan_resource_index:
  89             add_binding(state, nir_intrinsic_desc_set(intrin),
  90                         nir_intrinsic_binding(intrin));
  91             break;
  92
  93          case nir_intrinsic_image_deref_load:
  94          case nir_intrinsic_image_deref_store:
  95          case nir_intrinsic_image_deref_atomic_add:
  96          case nir_intrinsic_image_deref_atomic_min:
  97          case nir_intrinsic_image_deref_atomic_max:
  98          case nir_intrinsic_image_deref_atomic_and:
  99          case nir_intrinsic_image_deref_atomic_or:
 100          case nir_intrinsic_image_deref_atomic_xor:
 101          case nir_intrinsic_image_deref_atomic_exchange:
 102          case nir_intrinsic_image_deref_atomic_comp_swap:
 103          case nir_intrinsic_image_deref_size:
 104          case nir_intrinsic_image_deref_samples:
 105          case nir_intrinsic_image_deref_load_param_intel:
 106          case nir_intrinsic_image_deref_load_raw_intel:
 107          case nir_intrinsic_image_deref_store_raw_intel:
 108             add_deref_src_binding(state, intrin->src[0]);
 109             break;
 110
 111          case nir_intrinsic_load_constant:
 112             state->uses_constants = true;
 113             break;
 114
 115          default:
 116             break;
 117          }
 118          break;
 119       }
 120       case nir_instr_type_tex: {
 121          nir_tex_instr *tex = nir_instr_as_tex(instr);
 122          add_tex_src_binding(state, tex, nir_tex_src_texture_deref);
 123          add_tex_src_binding(state, tex, nir_tex_src_sampler_deref);
 124          break;
 125       }
 126       default:
 127          continue;
 128       }
 129    }
 130 }
 131
 132 static void
 133 lower_res_index_intrinsic(nir_intrinsic_instr *intrin,
 134                           struct apply_pipeline_layout_state *state)
 135 {
 136    nir_builder *b = &state->builder;
 137
 138    b->cursor = nir_before_instr(&intrin->instr);
 139
 140    uint32_t set = nir_intrinsic_desc_set(intrin);
 141    uint32_t binding = nir_intrinsic_binding(intrin);
 142
 143    uint32_t surface_index = state->set[set].surface_offsets[binding];
 144    uint32_t array_size =
 145       state->layout->set[set].layout->binding[binding].array_size;
 146
 147    nir_const_value *const_array_index = nir_src_as_const_value(intrin->src[0]);
 148
 149    nir_ssa_def *block_index;
 150    if (const_array_index) {
 151       unsigned array_index = const_array_index->u32[0];
 152       array_index = MIN2(array_index, array_size - 1);
 153       block_index = nir_imm_int(b, surface_index + array_index);
 154    } else {
 155       block_index = nir_ssa_for_src(b, intrin->src[0], 1);
 156
 157       if (state->add_bounds_checks)
 158          block_index = nir_umin(b, block_index, nir_imm_int(b, array_size - 1));
 159
 160       block_index = nir_iadd(b, nir_imm_int(b, surface_index), block_index);
 161    }
 162
 163    assert(intrin->dest.is_ssa);
 164    nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(block_index));
 165    nir_instr_remove(&intrin->instr);
 166 }
 167
 168 static void
 169 lower_res_reindex_intrinsic(nir_intrinsic_instr *intrin,
 170                             struct apply_pipeline_layout_state *state)
 171 {
 172    nir_builder *b = &state->builder;
 173
 174    /* For us, the resource indices are just indices into the binding table and
 175     * array elements are sequential.  A resource_reindex just turns into an
 176     * add of the two indices.
 177     */
 178    assert(intrin->src[0].is_ssa && intrin->src[1].is_ssa);
 179    nir_ssa_def *new_index = nir_iadd(b, intrin->src[0].ssa,
 180                                         intrin->src[1].ssa);
 181
 182    assert(intrin->dest.is_ssa);
 183    nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(new_index));
 184    nir_instr_remove(&intrin->instr);
 185 }
 186
 187 static void
 188 lower_image_intrinsic(nir_intrinsic_instr *intrin,
 189                       struct apply_pipeline_layout_state *state)
 190 {
 191    nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
 192    nir_variable *var = nir_deref_instr_get_variable(deref);
 193
 194    unsigned set = var->data.descriptor_set;
 195    unsigned binding = var->data.binding;
 196    unsigned array_size =
 197       state->layout->set[set].layout->binding[binding].array_size;
 198
 199    nir_builder *b = &state->builder;
 200    b->cursor = nir_before_instr(&intrin->instr);
 201
 202    nir_ssa_def *index = NULL;
 203    if (deref->deref_type != nir_deref_type_var) {
 204       assert(deref->deref_type == nir_deref_type_array);
 205       index = nir_ssa_for_src(b, deref->arr.index, 1);
 206       if (state->add_bounds_checks)
 207          index = nir_umin(b, index, nir_imm_int(b, array_size - 1));
 208    } else {
 209       index = nir_imm_int(b, 0);
 210    }
 211
 212    if (intrin->intrinsic == nir_intrinsic_image_deref_load_param_intel) {
 213       b->cursor = nir_instr_remove(&intrin->instr);
 214
 215       nir_intrinsic_instr *load =
 216          nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_uniform);
 217
 218       nir_intrinsic_set_base(load, state->first_image_uniform +
 219                                    state->set[set].image_offsets[binding] *
 220                                    BRW_IMAGE_PARAM_SIZE * 4);
 221       nir_intrinsic_set_range(load, array_size * BRW_IMAGE_PARAM_SIZE * 4);
 222
 223       const unsigned param = nir_intrinsic_base(intrin);
 224       nir_ssa_def *offset =
 225          nir_imul(b, index, nir_imm_int(b, BRW_IMAGE_PARAM_SIZE * 4));
 226       offset = nir_iadd(b, offset, nir_imm_int(b, param * 16));
 227       load->src[0] = nir_src_for_ssa(offset);
 228
 229       load->num_components = intrin->dest.ssa.num_components;
 230       nir_ssa_dest_init(&load->instr, &load->dest,
 231                         intrin->dest.ssa.num_components,
 232                         intrin->dest.ssa.bit_size, NULL);
 233       nir_builder_instr_insert(b, &load->instr);
 234
 235       nir_ssa_def_rewrite_uses(&intrin->dest.ssa,
 236                                nir_src_for_ssa(&load->dest.ssa));
 237    } else {
 238       unsigned binding_offset = state->set[set].surface_offsets[binding];
 239       index = nir_iadd(b, index, nir_imm_int(b, binding_offset));
 240       brw_nir_rewrite_image_intrinsic(intrin, index);
 241    }
 242 }
 243
 244 static void
 245 lower_load_constant(nir_intrinsic_instr *intrin,
 246                     struct apply_pipeline_layout_state *state)
 247 {
 248    nir_builder *b = &state->builder;
 249
 250    b->cursor = nir_before_instr(&intrin->instr);
 251
 252    nir_ssa_def *index = nir_imm_int(b, state->constants_offset);
 253    nir_ssa_def *offset = nir_iadd(b, nir_ssa_for_src(b, intrin->src[0], 1),
 254                                   nir_imm_int(b, nir_intrinsic_base(intrin)));
 255
 256    nir_intrinsic_instr *load_ubo =
 257       nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_ubo);
 258    load_ubo->num_components = intrin->num_components;
 259    load_ubo->src[0] = nir_src_for_ssa(index);
 260    load_ubo->src[1] = nir_src_for_ssa(offset);
 261    nir_ssa_dest_init(&load_ubo->instr, &load_ubo->dest,
 262                      intrin->dest.ssa.num_components,
 263                      intrin->dest.ssa.bit_size, NULL);
 264    nir_builder_instr_insert(b, &load_ubo->instr);
 265
 266    nir_ssa_def_rewrite_uses(&intrin->dest.ssa,
 267                             nir_src_for_ssa(&load_ubo->dest.ssa));
 268    nir_instr_remove(&intrin->instr);
 269 }
 270
 271 static void
 272 lower_tex_deref(nir_tex_instr *tex, nir_tex_src_type deref_src_type,
 273                 unsigned *base_index,
 274                 struct apply_pipeline_layout_state *state)
 275 {
 276    int deref_src_idx = nir_tex_instr_src_index(tex, deref_src_type);
 277    if (deref_src_idx < 0)
 278       return;
 279
 280    nir_deref_instr *deref = nir_src_as_deref(tex->src[deref_src_idx].src);
 281    nir_variable *var = nir_deref_instr_get_variable(deref);
 282
 283    unsigned set = var->data.descriptor_set;
 284    unsigned binding = var->data.binding;
 285    unsigned array_size =
 286       state->layout->set[set].layout->binding[binding].array_size;
 287
 288    nir_tex_src_type offset_src_type;
 289    if (deref_src_type == nir_tex_src_texture_deref) {
 290       offset_src_type = nir_tex_src_texture_offset;
 291       *base_index = state->set[set].surface_offsets[binding];
 292    } else {
 293       assert(deref_src_type == nir_tex_src_sampler_deref);
 294       offset_src_type = nir_tex_src_sampler_offset;
 295       *base_index = state->set[set].sampler_offsets[binding];
 296    }
 297
 298    nir_ssa_def *index = NULL;
 299    if (deref->deref_type != nir_deref_type_var) {
 300       assert(deref->deref_type == nir_deref_type_array);
 301
 302       nir_const_value *const_index = nir_src_as_const_value(deref->arr.index);
 303       if (const_index) {
 304          *base_index += MIN2(const_index->u32[0], array_size - 1);
 305       } else {
 306          nir_builder *b = &state->builder;
 307
 308          /* From VK_KHR_sampler_ycbcr_conversion:
 309           *
 310           * If sampler Y’CBCR conversion is enabled, the combined image
 311           * sampler must be indexed only by constant integral expressions when
 312           * aggregated into arrays in shader code, irrespective of the
 313           * shaderSampledImageArrayDynamicIndexing feature.
 314           */
 315          assert(nir_tex_instr_src_index(tex, nir_tex_src_plane) == -1);
 316
 317          index = nir_ssa_for_src(b, deref->arr.index, 1);
 318
 319          if (state->add_bounds_checks)
 320             index = nir_umin(b, index, nir_imm_int(b, array_size - 1));
 321       }
 322    }
 323
 324    if (index) {
 325       nir_instr_rewrite_src(&tex->instr, &tex->src[deref_src_idx].src,
 326                             nir_src_for_ssa(index));
 327       tex->src[deref_src_idx].src_type = offset_src_type;
 328    } else {
 329       nir_tex_instr_remove_src(tex, deref_src_idx);
 330    }
 331 }
 332
 333 static uint32_t
 334 tex_instr_get_and_remove_plane_src(nir_tex_instr *tex)
 335 {
 336    int plane_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_plane);
 337    if (plane_src_idx < 0)
 338       return 0;
 339
 340    unsigned plane =
 341       nir_src_as_const_value(tex->src[plane_src_idx].src)->u32[0];
 342
 343    nir_tex_instr_remove_src(tex, plane_src_idx);
 344
 345    return plane;
 346 }
 347
 348 static void
 349 lower_tex(nir_tex_instr *tex, struct apply_pipeline_layout_state *state)
 350 {
 351    state->builder.cursor = nir_before_instr(&tex->instr);
 352
 353    unsigned plane = tex_instr_get_and_remove_plane_src(tex);
 354
 355    lower_tex_deref(tex, nir_tex_src_texture_deref,
 356                    &tex->texture_index, state);
 357    tex->texture_index += plane;
 358
 359    lower_tex_deref(tex, nir_tex_src_sampler_deref,
 360                    &tex->sampler_index, state);
 361    tex->sampler_index += plane;
 362
 363    /* The backend only ever uses this to mark used surfaces.  We don't care
 364     * about that little optimization so it just needs to be non-zero.
 365     */
 366    tex->texture_array_size = 1;
 367 }
 368
 369 static void
 370 apply_pipeline_layout_block(nir_block *block,
 371                             struct apply_pipeline_layout_state *state)
 372 {
 373    nir_foreach_instr_safe(instr, block) {
 374       switch (instr->type) {
 375       case nir_instr_type_intrinsic: {
 376          nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
 377          switch (intrin->intrinsic) {
 378          case nir_intrinsic_vulkan_resource_index:
 379             lower_res_index_intrinsic(intrin, state);
 380             break;
 381          case nir_intrinsic_vulkan_resource_reindex:
 382             lower_res_reindex_intrinsic(intrin, state);
 383             break;
 384          case nir_intrinsic_image_deref_load:
 385          case nir_intrinsic_image_deref_store:
 386          case nir_intrinsic_image_deref_atomic_add:
 387          case nir_intrinsic_image_deref_atomic_min:
 388          case nir_intrinsic_image_deref_atomic_max:
 389          case nir_intrinsic_image_deref_atomic_and:
 390          case nir_intrinsic_image_deref_atomic_or:
 391          case nir_intrinsic_image_deref_atomic_xor:
 392          case nir_intrinsic_image_deref_atomic_exchange:
 393          case nir_intrinsic_image_deref_atomic_comp_swap:
 394          case nir_intrinsic_image_deref_size:
 395          case nir_intrinsic_image_deref_samples:
 396          case nir_intrinsic_image_deref_load_param_intel:
 397          case nir_intrinsic_image_deref_load_raw_intel:
 398          case nir_intrinsic_image_deref_store_raw_intel:
 399             lower_image_intrinsic(intrin, state);
 400             break;
 401          case nir_intrinsic_load_constant:
 402             lower_load_constant(intrin, state);
 403             break;
 404          default:
 405             break;
 406          }
 407          break;
 408       }
 409       case nir_instr_type_tex:
 410          lower_tex(nir_instr_as_tex(instr), state);
 411          break;
 412       default:
 413          continue;
 414       }
 415    }
 416 }
 417
 418 static void
 419 setup_vec4_uniform_value(uint32_t *params, uint32_t offset, unsigned n)
 420 {
 421    for (unsigned i = 0; i < n; ++i)
 422       params[i] = ANV_PARAM_PUSH(offset + i * sizeof(uint32_t));
 423
 424    for (unsigned i = n; i < 4; ++i)
 425       params[i] = BRW_PARAM_BUILTIN_ZERO;
 426 }
 427
 428 void
 429 anv_nir_apply_pipeline_layout(struct anv_pipeline *pipeline,
 430                               struct anv_pipeline_layout *layout,
 431                               nir_shader *shader,
 432                               struct brw_stage_prog_data *prog_data,
 433                               struct anv_pipeline_bind_map *map)
 434 {
 435    gl_shader_stage stage = shader->info.stage;
 436
 437    struct apply_pipeline_layout_state state = {
 438       .shader = shader,
 439       .layout = layout,
 440       .add_bounds_checks = pipeline->device->robust_buffer_access,
 441    };
 442
 443    void *mem_ctx = ralloc_context(NULL);
 444
 445    for (unsigned s = 0; s < layout->num_sets; s++) {
 446       const unsigned count = layout->set[s].layout->binding_count;
 447       const unsigned words = BITSET_WORDS(count);
 448       state.set[s].used = rzalloc_array(mem_ctx, BITSET_WORD, words);
 449       state.set[s].surface_offsets = rzalloc_array(mem_ctx, uint8_t, count);
 450       state.set[s].sampler_offsets = rzalloc_array(mem_ctx, uint8_t, count);
 451       state.set[s].image_offsets = rzalloc_array(mem_ctx, uint8_t, count);
 452    }
 453
 454    nir_foreach_function(function, shader) {
 455       if (!function->impl)
 456          continue;
 457
 458       nir_foreach_block(block, function->impl)
 459          get_used_bindings_block(block, &state);
 460    }
 461
 462    if (state.uses_constants) {
 463       state.constants_offset = map->surface_count;
 464       map->surface_to_descriptor[map->surface_count].set =
 465          ANV_DESCRIPTOR_SET_SHADER_CONSTANTS;
 466       map->surface_count++;
 467    }
 468
 469    for (uint32_t set = 0; set < layout->num_sets; set++) {
 470       struct anv_descriptor_set_layout *set_layout = layout->set[set].layout;
 471
 472       BITSET_WORD b, _tmp;
 473       BITSET_FOREACH_SET(b, _tmp, state.set[set].used,
 474                          set_layout->binding_count) {
 475          struct anv_descriptor_set_binding_layout *binding =
 476             &set_layout->binding[b];
 477
 478          if (binding->stage[stage].surface_index >= 0) {
 479             state.set[set].surface_offsets[b] = map->surface_count;
 480             struct anv_sampler **samplers = binding->immutable_samplers;
 481             for (unsigned i = 0; i < binding->array_size; i++) {
 482                uint8_t planes = samplers ? samplers[i]->n_planes : 1;
 483                for (uint8_t p = 0; p < planes; p++) {
 484                   map->surface_to_descriptor[map->surface_count++] =
 485                      (struct anv_pipeline_binding) {
 486                         .set = set,
 487                         .binding = b,
 488                         .index = i,
 489                         .plane = p,
 490                      };
 491                }
 492             }
 493          }
 494
 495          if (binding->stage[stage].sampler_index >= 0) {
 496             state.set[set].sampler_offsets[b] = map->sampler_count;
 497             struct anv_sampler **samplers = binding->immutable_samplers;
 498             for (unsigned i = 0; i < binding->array_size; i++) {
 499                uint8_t planes = samplers ? samplers[i]->n_planes : 1;
 500                for (uint8_t p = 0; p < planes; p++) {
 501                   map->sampler_to_descriptor[map->sampler_count++] =
 502                      (struct anv_pipeline_binding) {
 503                         .set = set,
 504                         .binding = b,
 505                         .index = i,
 506                         .plane = p,
 507                      };
 508                }
 509             }
 510          }
 511
 512          if (binding->stage[stage].image_index >= 0) {
 513             state.set[set].image_offsets[b] = map->image_count;
 514             map->image_count += binding->array_size;
 515          }
 516       }
 517    }
 518
 519    if (map->image_count > 0) {
 520       assert(map->image_count <= MAX_IMAGES);
 521       assert(shader->num_uniforms == prog_data->nr_params * 4);
 522       state.first_image_uniform = shader->num_uniforms;
 523       uint32_t *param = brw_stage_prog_data_add_params(prog_data,
 524                                                        map->image_count *
 525                                                        BRW_IMAGE_PARAM_SIZE);
 526       struct anv_push_constants *null_data = NULL;
 527       const struct brw_image_param *image_param = null_data->images;
 528       for (uint32_t i = 0; i < map->image_count; i++) {
 529          setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
 530                                   (uintptr_t)image_param->offset, 2);
 531          setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
 532                                   (uintptr_t)image_param->size, 3);
 533          setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
 534                                   (uintptr_t)image_param->stride, 4);
 535          setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
 536                                   (uintptr_t)image_param->tiling, 3);
 537          setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
 538                                   (uintptr_t)image_param->swizzling, 2);
 539
 540          param += BRW_IMAGE_PARAM_SIZE;
 541          image_param ++;
 542       }
 543       assert(param == prog_data->param + prog_data->nr_params);
 544
 545       shader->num_uniforms += map->image_count * BRW_IMAGE_PARAM_SIZE * 4;
 546       assert(shader->num_uniforms == prog_data->nr_params * 4);
 547    }
 548
 549    nir_foreach_variable(var, &shader->uniforms) {
 550       const struct glsl_type *glsl_type = glsl_without_array(var->type);
 551
 552       if (!glsl_type_is_image(glsl_type))
 553          continue;
 554
 555       enum glsl_sampler_dim dim = glsl_get_sampler_dim(glsl_type);
 556
 557       const uint32_t set = var->data.descriptor_set;
 558       const uint32_t binding = var->data.binding;
 559       const uint32_t array_size =
 560          layout->set[set].layout->binding[binding].array_size;
 561
 562       if (!BITSET_TEST(state.set[set].used, binding))
 563          continue;
 564
 565       struct anv_pipeline_binding *pipe_binding =
 566          &map->surface_to_descriptor[state.set[set].surface_offsets[binding]];
 567       for (unsigned i = 0; i < array_size; i++) {
 568          assert(pipe_binding[i].set == set);
 569          assert(pipe_binding[i].binding == binding);
 570          assert(pipe_binding[i].index == i);
 571
 572          if (dim == GLSL_SAMPLER_DIM_SUBPASS ||
 573              dim == GLSL_SAMPLER_DIM_SUBPASS_MS)
 574             pipe_binding[i].input_attachment_index = var->data.index + i;
 575
 576          pipe_binding[i].write_only =
 577             (var->data.image.access & ACCESS_NON_READABLE) != 0;
 578       }
 579    }
 580
 581    nir_foreach_function(function, shader) {
 582       if (!function->impl)
 583          continue;
 584
 585       nir_builder_init(&state.builder, function->impl);
 586       nir_foreach_block(block, function->impl)
 587          apply_pipeline_layout_block(block, &state);
 588       nir_metadata_preserve(function->impl, nir_metadata_block_index |
 589                                             nir_metadata_dominance);
 590    }
 591
 592    ralloc_free(mem_ctx);
 593 }