2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "util/os_time.h"
32 #include "common/gen_l3_config.h"
33 #include "anv_private.h"
34 #include "compiler/brw_nir.h"
36 #include "nir/nir_xfb_info.h"
37 #include "spirv/nir_spirv.h"
40 /* Needed for SWIZZLE macros */
41 #include "program/prog_instruction.h"
45 VkResult
anv_CreateShaderModule(
47 const VkShaderModuleCreateInfo
* pCreateInfo
,
48 const VkAllocationCallbacks
* pAllocator
,
49 VkShaderModule
* pShaderModule
)
51 ANV_FROM_HANDLE(anv_device
, device
, _device
);
52 struct anv_shader_module
*module
;
54 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
55 assert(pCreateInfo
->flags
== 0);
57 module
= vk_alloc2(&device
->alloc
, pAllocator
,
58 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
59 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
61 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
63 module
->size
= pCreateInfo
->codeSize
;
64 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
66 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
68 *pShaderModule
= anv_shader_module_to_handle(module
);
73 void anv_DestroyShaderModule(
75 VkShaderModule _module
,
76 const VkAllocationCallbacks
* pAllocator
)
78 ANV_FROM_HANDLE(anv_device
, device
, _device
);
79 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
84 vk_free2(&device
->alloc
, pAllocator
, module
);
87 #define SPIR_V_MAGIC_NUMBER 0x07230203
89 static const uint64_t stage_to_debug
[] = {
90 [MESA_SHADER_VERTEX
] = DEBUG_VS
,
91 [MESA_SHADER_TESS_CTRL
] = DEBUG_TCS
,
92 [MESA_SHADER_TESS_EVAL
] = DEBUG_TES
,
93 [MESA_SHADER_GEOMETRY
] = DEBUG_GS
,
94 [MESA_SHADER_FRAGMENT
] = DEBUG_WM
,
95 [MESA_SHADER_COMPUTE
] = DEBUG_CS
,
98 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
99 * we can't do that yet because we don't have the ability to copy nir.
102 anv_shader_compile_to_nir(struct anv_device
*device
,
104 const struct anv_shader_module
*module
,
105 const char *entrypoint_name
,
106 gl_shader_stage stage
,
107 const VkSpecializationInfo
*spec_info
)
109 const struct anv_physical_device
*pdevice
=
110 &device
->instance
->physicalDevice
;
111 const struct brw_compiler
*compiler
= pdevice
->compiler
;
112 const nir_shader_compiler_options
*nir_options
=
113 compiler
->glsl_compiler_options
[stage
].NirOptions
;
115 uint32_t *spirv
= (uint32_t *) module
->data
;
116 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
117 assert(module
->size
% 4 == 0);
119 uint32_t num_spec_entries
= 0;
120 struct nir_spirv_specialization
*spec_entries
= NULL
;
121 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
122 num_spec_entries
= spec_info
->mapEntryCount
;
123 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
124 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
125 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
126 const void *data
= spec_info
->pData
+ entry
.offset
;
127 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
129 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
130 if (spec_info
->dataSize
== 8)
131 spec_entries
[i
].data64
= *(const uint64_t *)data
;
133 spec_entries
[i
].data32
= *(const uint32_t *)data
;
137 struct spirv_to_nir_options spirv_options
= {
138 .lower_workgroup_access_to_offsets
= true,
140 .derivative_group
= true,
141 .descriptor_array_dynamic_indexing
= true,
142 .descriptor_array_non_uniform_indexing
= true,
143 .descriptor_indexing
= true,
144 .device_group
= true,
145 .draw_parameters
= true,
146 .float16
= pdevice
->info
.gen
>= 8,
147 .float64
= pdevice
->info
.gen
>= 8,
148 .fragment_shader_sample_interlock
= pdevice
->info
.gen
>= 9,
149 .fragment_shader_pixel_interlock
= pdevice
->info
.gen
>= 9,
150 .geometry_streams
= true,
151 .image_write_without_format
= true,
152 .int8
= pdevice
->info
.gen
>= 8,
153 .int16
= pdevice
->info
.gen
>= 8,
154 .int64
= pdevice
->info
.gen
>= 8,
155 .int64_atomics
= pdevice
->info
.gen
>= 9 && pdevice
->use_softpin
,
158 .physical_storage_buffer_address
= pdevice
->has_a64_buffer_access
,
159 .post_depth_coverage
= pdevice
->info
.gen
>= 9,
160 .runtime_descriptor_array
= true,
161 .shader_viewport_index_layer
= true,
162 .stencil_export
= pdevice
->info
.gen
>= 9,
163 .storage_8bit
= pdevice
->info
.gen
>= 8,
164 .storage_16bit
= pdevice
->info
.gen
>= 8,
165 .subgroup_arithmetic
= true,
166 .subgroup_basic
= true,
167 .subgroup_ballot
= true,
168 .subgroup_quad
= true,
169 .subgroup_shuffle
= true,
170 .subgroup_vote
= true,
171 .tessellation
= true,
172 .transform_feedback
= pdevice
->info
.gen
>= 8,
173 .variable_pointers
= true,
175 .ubo_addr_format
= nir_address_format_32bit_index_offset
,
177 anv_nir_ssbo_addr_format(pdevice
, device
->robust_buffer_access
),
178 .phys_ssbo_addr_format
= nir_address_format_64bit_global
,
179 .push_const_addr_format
= nir_address_format_logical
,
181 /* TODO: Consider changing this to an address format that has the NULL
182 * pointer equals to 0. That might be a better format to play nice
183 * with certain code / code generators.
185 .shared_addr_format
= nir_address_format_32bit_offset
,
190 spirv_to_nir(spirv
, module
->size
/ 4,
191 spec_entries
, num_spec_entries
,
192 stage
, entrypoint_name
, &spirv_options
, nir_options
);
193 assert(nir
->info
.stage
== stage
);
194 nir_validate_shader(nir
, "after spirv_to_nir");
195 ralloc_steal(mem_ctx
, nir
);
199 if (unlikely(INTEL_DEBUG
& stage_to_debug
[stage
])) {
200 fprintf(stderr
, "NIR (from SPIR-V) for %s shader:\n",
201 gl_shader_stage_name(stage
));
202 nir_print_shader(nir
, stderr
);
205 /* We have to lower away local constant initializers right before we
206 * inline functions. That way they get properly initialized at the top
207 * of the function and not at the top of its caller.
209 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_function_temp
);
210 NIR_PASS_V(nir
, nir_lower_returns
);
211 NIR_PASS_V(nir
, nir_inline_functions
);
212 NIR_PASS_V(nir
, nir_opt_deref
);
214 /* Pick off the single entrypoint that we want */
215 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
216 if (!func
->is_entrypoint
)
217 exec_node_remove(&func
->node
);
219 assert(exec_list_length(&nir
->functions
) == 1);
221 /* Now that we've deleted all but the main function, we can go ahead and
222 * lower the rest of the constant initializers. We do this here so that
223 * nir_remove_dead_variables and split_per_member_structs below see the
224 * corresponding stores.
226 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
228 /* Split member structs. We do this before lower_io_to_temporaries so that
229 * it doesn't lower system values to temporaries by accident.
231 NIR_PASS_V(nir
, nir_split_var_copies
);
232 NIR_PASS_V(nir
, nir_split_per_member_structs
);
234 NIR_PASS_V(nir
, nir_remove_dead_variables
,
235 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
237 NIR_PASS_V(nir
, nir_propagate_invariant
);
238 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
239 nir_shader_get_entrypoint(nir
), true, false);
241 NIR_PASS_V(nir
, nir_lower_frexp
);
243 /* Vulkan uses the separate-shader linking model */
244 nir
->info
.separate_shader
= true;
246 brw_preprocess_nir(compiler
, nir
, NULL
);
251 void anv_DestroyPipeline(
253 VkPipeline _pipeline
,
254 const VkAllocationCallbacks
* pAllocator
)
256 ANV_FROM_HANDLE(anv_device
, device
, _device
);
257 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
262 anv_reloc_list_finish(&pipeline
->batch_relocs
,
263 pAllocator
? pAllocator
: &device
->alloc
);
264 if (pipeline
->blend_state
.map
)
265 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
267 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
268 if (pipeline
->shaders
[s
])
269 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
272 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
275 static const uint32_t vk_to_gen_primitive_type
[] = {
276 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
277 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
278 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
279 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
280 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
281 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
282 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
283 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
284 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
285 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
289 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
290 struct brw_sampler_prog_key_data
*key
)
292 /* Almost all multisampled textures are compressed. The only time when we
293 * don't compress a multisampled texture is for 16x MSAA with a surface
294 * width greater than 8k which is a bit of an edge case. Since the sampler
295 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
296 * to tell the compiler to always assume compression.
298 key
->compressed_multisample_layout_mask
= ~0;
300 /* SkyLake added support for 16x MSAA. With this came a new message for
301 * reading from a 16x MSAA surface with compression. The new message was
302 * needed because now the MCS data is 64 bits instead of 32 or lower as is
303 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
304 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
305 * so we can just use it unconditionally. This may not be quite as
306 * efficient but it saves us from recompiling.
308 if (devinfo
->gen
>= 9)
311 /* XXX: Handle texture swizzle on HSW- */
312 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
313 /* Assume color sampler, no swizzling. (Works for BDW+) */
314 key
->swizzles
[i
] = SWIZZLE_XYZW
;
319 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
320 struct brw_vs_prog_key
*key
)
322 memset(key
, 0, sizeof(*key
));
324 populate_sampler_prog_key(devinfo
, &key
->tex
);
326 /* XXX: Handle vertex input work-arounds */
328 /* XXX: Handle sampler_prog_key */
332 populate_tcs_prog_key(const struct gen_device_info
*devinfo
,
333 unsigned input_vertices
,
334 struct brw_tcs_prog_key
*key
)
336 memset(key
, 0, sizeof(*key
));
338 populate_sampler_prog_key(devinfo
, &key
->tex
);
340 key
->input_vertices
= input_vertices
;
344 populate_tes_prog_key(const struct gen_device_info
*devinfo
,
345 struct brw_tes_prog_key
*key
)
347 memset(key
, 0, sizeof(*key
));
349 populate_sampler_prog_key(devinfo
, &key
->tex
);
353 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
354 struct brw_gs_prog_key
*key
)
356 memset(key
, 0, sizeof(*key
));
358 populate_sampler_prog_key(devinfo
, &key
->tex
);
362 populate_wm_prog_key(const struct gen_device_info
*devinfo
,
363 const struct anv_subpass
*subpass
,
364 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
365 struct brw_wm_prog_key
*key
)
367 memset(key
, 0, sizeof(*key
));
369 populate_sampler_prog_key(devinfo
, &key
->tex
);
371 /* We set this to 0 here and set to the actual value before we call
374 key
->input_slots_valid
= 0;
376 /* Vulkan doesn't specify a default */
377 key
->high_quality_derivatives
= false;
379 /* XXX Vulkan doesn't appear to specify */
380 key
->clamp_fragment_color
= false;
382 assert(subpass
->color_count
<= MAX_RTS
);
383 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
384 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
385 key
->color_outputs_valid
|= (1 << i
);
388 key
->nr_color_regions
= util_bitcount(key
->color_outputs_valid
);
390 /* To reduce possible shader recompilations we would need to know if
391 * there is a SampleMask output variable to compute if we should emit
392 * code to workaround the issue that hardware disables alpha to coverage
393 * when there is SampleMask output.
395 key
->alpha_to_coverage
= ms_info
&& ms_info
->alphaToCoverageEnable
;
397 /* Vulkan doesn't support fixed-function alpha test */
398 key
->alpha_test_replicate_alpha
= false;
401 /* We should probably pull this out of the shader, but it's fairly
402 * harmless to compute it and then let dead-code take care of it.
404 if (ms_info
->rasterizationSamples
> 1) {
405 key
->persample_interp
= ms_info
->sampleShadingEnable
&&
406 (ms_info
->minSampleShading
* ms_info
->rasterizationSamples
) > 1;
407 key
->multisample_fbo
= true;
410 key
->frag_coord_adds_sample_pos
= key
->persample_interp
;
415 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
416 struct brw_cs_prog_key
*key
)
418 memset(key
, 0, sizeof(*key
));
420 populate_sampler_prog_key(devinfo
, &key
->tex
);
423 struct anv_pipeline_stage
{
424 gl_shader_stage stage
;
426 const struct anv_shader_module
*module
;
427 const char *entrypoint
;
428 const VkSpecializationInfo
*spec_info
;
430 unsigned char shader_sha1
[20];
432 union brw_any_prog_key key
;
435 gl_shader_stage stage
;
436 unsigned char sha1
[20];
441 struct anv_pipeline_binding surface_to_descriptor
[256];
442 struct anv_pipeline_binding sampler_to_descriptor
[256];
443 struct anv_pipeline_bind_map bind_map
;
445 union brw_any_prog_data prog_data
;
447 VkPipelineCreationFeedbackEXT feedback
;
451 anv_pipeline_hash_shader(const struct anv_shader_module
*module
,
452 const char *entrypoint
,
453 gl_shader_stage stage
,
454 const VkSpecializationInfo
*spec_info
,
455 unsigned char *sha1_out
)
457 struct mesa_sha1 ctx
;
458 _mesa_sha1_init(&ctx
);
460 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
461 _mesa_sha1_update(&ctx
, entrypoint
, strlen(entrypoint
));
462 _mesa_sha1_update(&ctx
, &stage
, sizeof(stage
));
464 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
465 spec_info
->mapEntryCount
*
466 sizeof(*spec_info
->pMapEntries
));
467 _mesa_sha1_update(&ctx
, spec_info
->pData
,
468 spec_info
->dataSize
);
471 _mesa_sha1_final(&ctx
, sha1_out
);
475 anv_pipeline_hash_graphics(struct anv_pipeline
*pipeline
,
476 struct anv_pipeline_layout
*layout
,
477 struct anv_pipeline_stage
*stages
,
478 unsigned char *sha1_out
)
480 struct mesa_sha1 ctx
;
481 _mesa_sha1_init(&ctx
);
483 _mesa_sha1_update(&ctx
, &pipeline
->subpass
->view_mask
,
484 sizeof(pipeline
->subpass
->view_mask
));
487 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
489 const bool rba
= pipeline
->device
->robust_buffer_access
;
490 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
492 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
493 if (stages
[s
].entrypoint
) {
494 _mesa_sha1_update(&ctx
, stages
[s
].shader_sha1
,
495 sizeof(stages
[s
].shader_sha1
));
496 _mesa_sha1_update(&ctx
, &stages
[s
].key
, brw_prog_key_size(s
));
500 _mesa_sha1_final(&ctx
, sha1_out
);
504 anv_pipeline_hash_compute(struct anv_pipeline
*pipeline
,
505 struct anv_pipeline_layout
*layout
,
506 struct anv_pipeline_stage
*stage
,
507 unsigned char *sha1_out
)
509 struct mesa_sha1 ctx
;
510 _mesa_sha1_init(&ctx
);
513 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
515 const bool rba
= pipeline
->device
->robust_buffer_access
;
516 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
518 _mesa_sha1_update(&ctx
, stage
->shader_sha1
,
519 sizeof(stage
->shader_sha1
));
520 _mesa_sha1_update(&ctx
, &stage
->key
.cs
, sizeof(stage
->key
.cs
));
522 _mesa_sha1_final(&ctx
, sha1_out
);
526 anv_pipeline_stage_get_nir(struct anv_pipeline
*pipeline
,
527 struct anv_pipeline_cache
*cache
,
529 struct anv_pipeline_stage
*stage
)
531 const struct brw_compiler
*compiler
=
532 pipeline
->device
->instance
->physicalDevice
.compiler
;
533 const nir_shader_compiler_options
*nir_options
=
534 compiler
->glsl_compiler_options
[stage
->stage
].NirOptions
;
537 nir
= anv_device_search_for_nir(pipeline
->device
, cache
,
542 assert(nir
->info
.stage
== stage
->stage
);
546 nir
= anv_shader_compile_to_nir(pipeline
->device
,
553 anv_device_upload_nir(pipeline
->device
, cache
, nir
, stage
->shader_sha1
);
561 anv_pipeline_lower_nir(struct anv_pipeline
*pipeline
,
563 struct anv_pipeline_stage
*stage
,
564 struct anv_pipeline_layout
*layout
)
566 const struct anv_physical_device
*pdevice
=
567 &pipeline
->device
->instance
->physicalDevice
;
568 const struct brw_compiler
*compiler
= pdevice
->compiler
;
570 struct brw_stage_prog_data
*prog_data
= &stage
->prog_data
.base
;
571 nir_shader
*nir
= stage
->nir
;
573 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
574 NIR_PASS_V(nir
, nir_lower_wpos_center
, pipeline
->sample_shading_enable
);
575 NIR_PASS_V(nir
, anv_nir_lower_input_attachments
);
578 NIR_PASS_V(nir
, anv_nir_lower_ycbcr_textures
, layout
);
580 NIR_PASS_V(nir
, anv_nir_lower_push_constants
);
582 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
583 NIR_PASS_V(nir
, anv_nir_lower_multiview
, pipeline
->subpass
->view_mask
);
585 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
586 prog_data
->total_shared
= nir
->num_shared
;
588 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
590 if (nir
->num_uniforms
> 0) {
591 assert(prog_data
->nr_params
== 0);
593 /* If the shader uses any push constants at all, we'll just give
594 * them the maximum possible number
596 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
597 nir
->num_uniforms
= MAX_PUSH_CONSTANTS_SIZE
;
598 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
599 prog_data
->param
= ralloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
601 /* We now set the param values to be offsets into a
602 * anv_push_constant_data structure. Since the compiler doesn't
603 * actually dereference any of the gl_constant_value pointers in the
604 * params array, it doesn't really matter what we put here.
606 struct anv_push_constants
*null_data
= NULL
;
607 /* Fill out the push constants section of the param array */
608 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++) {
609 prog_data
->param
[i
] = ANV_PARAM_PUSH(
610 (uintptr_t)&null_data
->client_data
[i
* sizeof(float)]);
614 if (nir
->info
.num_ssbos
> 0 || nir
->info
.num_images
> 0)
615 pipeline
->needs_data_cache
= true;
617 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, compiler
->devinfo
);
619 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_global
,
620 nir_address_format_64bit_global
);
622 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
624 anv_nir_apply_pipeline_layout(pdevice
,
625 pipeline
->device
->robust_buffer_access
,
626 layout
, nir
, prog_data
,
629 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ubo
,
630 nir_address_format_32bit_index_offset
);
631 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ssbo
,
632 anv_nir_ssbo_addr_format(pdevice
,
633 pipeline
->device
->robust_buffer_access
));
635 NIR_PASS_V(nir
, nir_opt_constant_folding
);
637 /* We don't support non-uniform UBOs and non-uniform SSBO access is
638 * handled naturally by falling back to A64 messages.
640 NIR_PASS_V(nir
, nir_lower_non_uniform_access
,
641 nir_lower_non_uniform_texture_access
|
642 nir_lower_non_uniform_image_access
);
645 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
646 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
648 assert(nir
->num_uniforms
== prog_data
->nr_params
* 4);
654 anv_pipeline_link_vs(const struct brw_compiler
*compiler
,
655 struct anv_pipeline_stage
*vs_stage
,
656 struct anv_pipeline_stage
*next_stage
)
659 brw_nir_link_shaders(compiler
, vs_stage
->nir
, next_stage
->nir
);
662 static const unsigned *
663 anv_pipeline_compile_vs(const struct brw_compiler
*compiler
,
665 struct anv_device
*device
,
666 struct anv_pipeline_stage
*vs_stage
)
668 brw_compute_vue_map(compiler
->devinfo
,
669 &vs_stage
->prog_data
.vs
.base
.vue_map
,
670 vs_stage
->nir
->info
.outputs_written
,
671 vs_stage
->nir
->info
.separate_shader
);
673 return brw_compile_vs(compiler
, device
, mem_ctx
, &vs_stage
->key
.vs
,
674 &vs_stage
->prog_data
.vs
, vs_stage
->nir
, -1, NULL
);
678 merge_tess_info(struct shader_info
*tes_info
,
679 const struct shader_info
*tcs_info
)
681 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
683 * "PointMode. Controls generation of points rather than triangles
684 * or lines. This functionality defaults to disabled, and is
685 * enabled if either shader stage includes the execution mode.
687 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
688 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
689 * and OutputVertices, it says:
691 * "One mode must be set in at least one of the tessellation
694 * So, the fields can be set in either the TCS or TES, but they must
695 * agree if set in both. Our backend looks at TES, so bitwise-or in
696 * the values from the TCS.
698 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
699 tes_info
->tess
.tcs_vertices_out
== 0 ||
700 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
701 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
703 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
704 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
705 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
706 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
708 assert(tcs_info
->tess
.primitive_mode
== 0 ||
709 tes_info
->tess
.primitive_mode
== 0 ||
710 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
711 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
712 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
713 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
717 anv_pipeline_link_tcs(const struct brw_compiler
*compiler
,
718 struct anv_pipeline_stage
*tcs_stage
,
719 struct anv_pipeline_stage
*tes_stage
)
721 assert(tes_stage
&& tes_stage
->stage
== MESA_SHADER_TESS_EVAL
);
723 brw_nir_link_shaders(compiler
, tcs_stage
->nir
, tes_stage
->nir
);
725 nir_lower_patch_vertices(tes_stage
->nir
,
726 tcs_stage
->nir
->info
.tess
.tcs_vertices_out
,
729 /* Copy TCS info into the TES info */
730 merge_tess_info(&tes_stage
->nir
->info
, &tcs_stage
->nir
->info
);
732 /* Whacking the key after cache lookup is a bit sketchy, but all of
733 * this comes from the SPIR-V, which is part of the hash used for the
734 * pipeline cache. So it should be safe.
736 tcs_stage
->key
.tcs
.tes_primitive_mode
=
737 tes_stage
->nir
->info
.tess
.primitive_mode
;
738 tcs_stage
->key
.tcs
.quads_workaround
=
739 compiler
->devinfo
->gen
< 9 &&
740 tes_stage
->nir
->info
.tess
.primitive_mode
== 7 /* GL_QUADS */ &&
741 tes_stage
->nir
->info
.tess
.spacing
== TESS_SPACING_EQUAL
;
744 static const unsigned *
745 anv_pipeline_compile_tcs(const struct brw_compiler
*compiler
,
747 struct anv_device
*device
,
748 struct anv_pipeline_stage
*tcs_stage
,
749 struct anv_pipeline_stage
*prev_stage
)
751 tcs_stage
->key
.tcs
.outputs_written
=
752 tcs_stage
->nir
->info
.outputs_written
;
753 tcs_stage
->key
.tcs
.patch_outputs_written
=
754 tcs_stage
->nir
->info
.patch_outputs_written
;
756 return brw_compile_tcs(compiler
, device
, mem_ctx
, &tcs_stage
->key
.tcs
,
757 &tcs_stage
->prog_data
.tcs
, tcs_stage
->nir
,
762 anv_pipeline_link_tes(const struct brw_compiler
*compiler
,
763 struct anv_pipeline_stage
*tes_stage
,
764 struct anv_pipeline_stage
*next_stage
)
767 brw_nir_link_shaders(compiler
, tes_stage
->nir
, next_stage
->nir
);
770 static const unsigned *
771 anv_pipeline_compile_tes(const struct brw_compiler
*compiler
,
773 struct anv_device
*device
,
774 struct anv_pipeline_stage
*tes_stage
,
775 struct anv_pipeline_stage
*tcs_stage
)
777 tes_stage
->key
.tes
.inputs_read
=
778 tcs_stage
->nir
->info
.outputs_written
;
779 tes_stage
->key
.tes
.patch_inputs_read
=
780 tcs_stage
->nir
->info
.patch_outputs_written
;
782 return brw_compile_tes(compiler
, device
, mem_ctx
, &tes_stage
->key
.tes
,
783 &tcs_stage
->prog_data
.tcs
.base
.vue_map
,
784 &tes_stage
->prog_data
.tes
, tes_stage
->nir
,
789 anv_pipeline_link_gs(const struct brw_compiler
*compiler
,
790 struct anv_pipeline_stage
*gs_stage
,
791 struct anv_pipeline_stage
*next_stage
)
794 brw_nir_link_shaders(compiler
, gs_stage
->nir
, next_stage
->nir
);
797 static const unsigned *
798 anv_pipeline_compile_gs(const struct brw_compiler
*compiler
,
800 struct anv_device
*device
,
801 struct anv_pipeline_stage
*gs_stage
,
802 struct anv_pipeline_stage
*prev_stage
)
804 brw_compute_vue_map(compiler
->devinfo
,
805 &gs_stage
->prog_data
.gs
.base
.vue_map
,
806 gs_stage
->nir
->info
.outputs_written
,
807 gs_stage
->nir
->info
.separate_shader
);
809 return brw_compile_gs(compiler
, device
, mem_ctx
, &gs_stage
->key
.gs
,
810 &gs_stage
->prog_data
.gs
, gs_stage
->nir
,
815 anv_pipeline_link_fs(const struct brw_compiler
*compiler
,
816 struct anv_pipeline_stage
*stage
)
818 unsigned num_rts
= 0;
819 const int max_rt
= FRAG_RESULT_DATA7
- FRAG_RESULT_DATA0
+ 1;
820 struct anv_pipeline_binding rt_bindings
[max_rt
];
821 nir_function_impl
*impl
= nir_shader_get_entrypoint(stage
->nir
);
822 int rt_to_bindings
[max_rt
];
823 memset(rt_to_bindings
, -1, sizeof(rt_to_bindings
));
824 bool rt_used
[max_rt
];
825 memset(rt_used
, 0, sizeof(rt_used
));
827 /* Flag used render targets */
828 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
829 if (var
->data
.location
< FRAG_RESULT_DATA0
)
832 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
837 const unsigned array_len
=
838 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
839 assert(rt
+ array_len
<= max_rt
);
842 if (!(stage
->key
.wm
.color_outputs_valid
& BITFIELD_RANGE(rt
, array_len
))) {
843 /* If this is the RT at location 0 and we have alpha to coverage
844 * enabled we will have to create a null RT for it, so mark it as
847 if (rt
> 0 || !stage
->key
.wm
.alpha_to_coverage
)
851 for (unsigned i
= 0; i
< array_len
; i
++)
852 rt_used
[rt
+ i
] = true;
855 /* Set new, compacted, location */
856 for (unsigned i
= 0; i
< max_rt
; i
++) {
860 rt_to_bindings
[i
] = num_rts
;
862 if (stage
->key
.wm
.color_outputs_valid
& (1 << i
)) {
863 rt_bindings
[rt_to_bindings
[i
]] = (struct anv_pipeline_binding
) {
864 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
869 /* Setup a null render target */
870 rt_bindings
[rt_to_bindings
[i
]] = (struct anv_pipeline_binding
) {
871 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
880 bool deleted_output
= false;
881 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
882 if (var
->data
.location
< FRAG_RESULT_DATA0
)
885 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
887 if (rt
>= MAX_RTS
|| !rt_used
[rt
]) {
888 /* Unused or out-of-bounds, throw it away, unless it is the first
889 * RT and we have alpha to coverage enabled.
891 deleted_output
= true;
892 var
->data
.mode
= nir_var_function_temp
;
893 exec_node_remove(&var
->node
);
894 exec_list_push_tail(&impl
->locals
, &var
->node
);
898 /* Give it the new location */
899 assert(rt_to_bindings
[rt
] != -1);
900 var
->data
.location
= rt_to_bindings
[rt
] + FRAG_RESULT_DATA0
;
904 nir_fixup_deref_modes(stage
->nir
);
907 /* If we have no render targets, we need a null render target */
908 rt_bindings
[0] = (struct anv_pipeline_binding
) {
909 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
916 /* Now that we've determined the actual number of render targets, adjust
917 * the key accordingly.
919 stage
->key
.wm
.nr_color_regions
= num_rts
;
920 stage
->key
.wm
.color_outputs_valid
= (1 << num_rts
) - 1;
922 assert(num_rts
<= max_rt
);
923 assert(stage
->bind_map
.surface_count
== 0);
924 typed_memcpy(stage
->bind_map
.surface_to_descriptor
,
925 rt_bindings
, num_rts
);
926 stage
->bind_map
.surface_count
+= num_rts
;
929 static const unsigned *
930 anv_pipeline_compile_fs(const struct brw_compiler
*compiler
,
932 struct anv_device
*device
,
933 struct anv_pipeline_stage
*fs_stage
,
934 struct anv_pipeline_stage
*prev_stage
)
936 /* TODO: we could set this to 0 based on the information in nir_shader, but
937 * we need this before we call spirv_to_nir.
940 fs_stage
->key
.wm
.input_slots_valid
=
941 prev_stage
->prog_data
.vue
.vue_map
.slots_valid
;
943 const unsigned *code
=
944 brw_compile_fs(compiler
, device
, mem_ctx
, &fs_stage
->key
.wm
,
945 &fs_stage
->prog_data
.wm
, fs_stage
->nir
,
946 NULL
, -1, -1, -1, true, false, NULL
, NULL
);
948 if (fs_stage
->key
.wm
.nr_color_regions
== 0 &&
949 !fs_stage
->prog_data
.wm
.has_side_effects
&&
950 !fs_stage
->prog_data
.wm
.uses_kill
&&
951 fs_stage
->prog_data
.wm
.computed_depth_mode
== BRW_PSCDEPTH_OFF
&&
952 !fs_stage
->prog_data
.wm
.computed_stencil
) {
953 /* This fragment shader has no outputs and no side effects. Go ahead
954 * and return the code pointer so we don't accidentally think the
955 * compile failed but zero out prog_data which will set program_size to
956 * zero and disable the stage.
958 memset(&fs_stage
->prog_data
, 0, sizeof(fs_stage
->prog_data
));
965 anv_pipeline_compile_graphics(struct anv_pipeline
*pipeline
,
966 struct anv_pipeline_cache
*cache
,
967 const VkGraphicsPipelineCreateInfo
*info
)
969 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
970 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
972 int64_t pipeline_start
= os_time_get_nano();
974 const struct brw_compiler
*compiler
=
975 pipeline
->device
->instance
->physicalDevice
.compiler
;
976 struct anv_pipeline_stage stages
[MESA_SHADER_STAGES
] = {};
978 pipeline
->active_stages
= 0;
981 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
982 const VkPipelineShaderStageCreateInfo
*sinfo
= &info
->pStages
[i
];
983 gl_shader_stage stage
= vk_to_mesa_shader_stage(sinfo
->stage
);
985 pipeline
->active_stages
|= sinfo
->stage
;
987 int64_t stage_start
= os_time_get_nano();
989 stages
[stage
].stage
= stage
;
990 stages
[stage
].module
= anv_shader_module_from_handle(sinfo
->module
);
991 stages
[stage
].entrypoint
= sinfo
->pName
;
992 stages
[stage
].spec_info
= sinfo
->pSpecializationInfo
;
993 anv_pipeline_hash_shader(stages
[stage
].module
,
994 stages
[stage
].entrypoint
,
996 stages
[stage
].spec_info
,
997 stages
[stage
].shader_sha1
);
999 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1001 case MESA_SHADER_VERTEX
:
1002 populate_vs_prog_key(devinfo
, &stages
[stage
].key
.vs
);
1004 case MESA_SHADER_TESS_CTRL
:
1005 populate_tcs_prog_key(devinfo
,
1006 info
->pTessellationState
->patchControlPoints
,
1007 &stages
[stage
].key
.tcs
);
1009 case MESA_SHADER_TESS_EVAL
:
1010 populate_tes_prog_key(devinfo
, &stages
[stage
].key
.tes
);
1012 case MESA_SHADER_GEOMETRY
:
1013 populate_gs_prog_key(devinfo
, &stages
[stage
].key
.gs
);
1015 case MESA_SHADER_FRAGMENT
:
1016 populate_wm_prog_key(devinfo
, pipeline
->subpass
,
1017 info
->pMultisampleState
,
1018 &stages
[stage
].key
.wm
);
1021 unreachable("Invalid graphics shader stage");
1024 stages
[stage
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1025 stages
[stage
].feedback
.flags
|= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
1028 if (pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
)
1029 pipeline
->active_stages
|= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
1031 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1033 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1035 unsigned char sha1
[20];
1036 anv_pipeline_hash_graphics(pipeline
, layout
, stages
, sha1
);
1039 unsigned cache_hits
= 0;
1040 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1041 if (!stages
[s
].entrypoint
)
1044 int64_t stage_start
= os_time_get_nano();
1046 stages
[s
].cache_key
.stage
= s
;
1047 memcpy(stages
[s
].cache_key
.sha1
, sha1
, sizeof(sha1
));
1050 struct anv_shader_bin
*bin
=
1051 anv_device_search_for_kernel(pipeline
->device
, cache
,
1052 &stages
[s
].cache_key
,
1053 sizeof(stages
[s
].cache_key
), &cache_hit
);
1056 pipeline
->shaders
[s
] = bin
;
1061 stages
[s
].feedback
.flags
|=
1062 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1064 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1067 if (found
== __builtin_popcount(pipeline
->active_stages
)) {
1068 if (cache_hits
== found
) {
1069 pipeline_feedback
.flags
|=
1070 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1072 /* We found all our shaders in the cache. We're done. */
1074 } else if (found
> 0) {
1075 /* We found some but not all of our shaders. This shouldn't happen
1076 * most of the time but it can if we have a partially populated
1079 assert(found
< __builtin_popcount(pipeline
->active_stages
));
1081 vk_debug_report(&pipeline
->device
->instance
->debug_report_callbacks
,
1082 VK_DEBUG_REPORT_WARNING_BIT_EXT
|
1083 VK_DEBUG_REPORT_PERFORMANCE_WARNING_BIT_EXT
,
1084 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT
,
1085 (uint64_t)(uintptr_t)cache
,
1087 "Found a partial pipeline in the cache. This is "
1088 "most likely caused by an incomplete pipeline cache "
1089 "import or export");
1091 /* We're going to have to recompile anyway, so just throw away our
1092 * references to the shaders in the cache. We'll get them out of the
1093 * cache again as part of the compilation process.
1095 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1096 stages
[s
].feedback
.flags
= 0;
1097 if (pipeline
->shaders
[s
]) {
1098 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1099 pipeline
->shaders
[s
] = NULL
;
1104 void *pipeline_ctx
= ralloc_context(NULL
);
1106 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1107 if (!stages
[s
].entrypoint
)
1110 int64_t stage_start
= os_time_get_nano();
1112 assert(stages
[s
].stage
== s
);
1113 assert(pipeline
->shaders
[s
] == NULL
);
1115 stages
[s
].bind_map
= (struct anv_pipeline_bind_map
) {
1116 .surface_to_descriptor
= stages
[s
].surface_to_descriptor
,
1117 .sampler_to_descriptor
= stages
[s
].sampler_to_descriptor
1120 stages
[s
].nir
= anv_pipeline_stage_get_nir(pipeline
, cache
,
1123 if (stages
[s
].nir
== NULL
) {
1124 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1128 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1131 /* Walk backwards to link */
1132 struct anv_pipeline_stage
*next_stage
= NULL
;
1133 for (int s
= MESA_SHADER_STAGES
- 1; s
>= 0; s
--) {
1134 if (!stages
[s
].entrypoint
)
1138 case MESA_SHADER_VERTEX
:
1139 anv_pipeline_link_vs(compiler
, &stages
[s
], next_stage
);
1141 case MESA_SHADER_TESS_CTRL
:
1142 anv_pipeline_link_tcs(compiler
, &stages
[s
], next_stage
);
1144 case MESA_SHADER_TESS_EVAL
:
1145 anv_pipeline_link_tes(compiler
, &stages
[s
], next_stage
);
1147 case MESA_SHADER_GEOMETRY
:
1148 anv_pipeline_link_gs(compiler
, &stages
[s
], next_stage
);
1150 case MESA_SHADER_FRAGMENT
:
1151 anv_pipeline_link_fs(compiler
, &stages
[s
]);
1154 unreachable("Invalid graphics shader stage");
1157 next_stage
= &stages
[s
];
1160 struct anv_pipeline_stage
*prev_stage
= NULL
;
1161 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1162 if (!stages
[s
].entrypoint
)
1165 int64_t stage_start
= os_time_get_nano();
1167 void *stage_ctx
= ralloc_context(NULL
);
1169 nir_xfb_info
*xfb_info
= NULL
;
1170 if (s
== MESA_SHADER_VERTEX
||
1171 s
== MESA_SHADER_TESS_EVAL
||
1172 s
== MESA_SHADER_GEOMETRY
)
1173 xfb_info
= nir_gather_xfb_info(stages
[s
].nir
, stage_ctx
);
1175 anv_pipeline_lower_nir(pipeline
, stage_ctx
, &stages
[s
], layout
);
1177 const unsigned *code
;
1179 case MESA_SHADER_VERTEX
:
1180 code
= anv_pipeline_compile_vs(compiler
, stage_ctx
, pipeline
->device
,
1183 case MESA_SHADER_TESS_CTRL
:
1184 code
= anv_pipeline_compile_tcs(compiler
, stage_ctx
, pipeline
->device
,
1185 &stages
[s
], prev_stage
);
1187 case MESA_SHADER_TESS_EVAL
:
1188 code
= anv_pipeline_compile_tes(compiler
, stage_ctx
, pipeline
->device
,
1189 &stages
[s
], prev_stage
);
1191 case MESA_SHADER_GEOMETRY
:
1192 code
= anv_pipeline_compile_gs(compiler
, stage_ctx
, pipeline
->device
,
1193 &stages
[s
], prev_stage
);
1195 case MESA_SHADER_FRAGMENT
:
1196 code
= anv_pipeline_compile_fs(compiler
, stage_ctx
, pipeline
->device
,
1197 &stages
[s
], prev_stage
);
1200 unreachable("Invalid graphics shader stage");
1203 ralloc_free(stage_ctx
);
1204 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1208 struct anv_shader_bin
*bin
=
1209 anv_device_upload_kernel(pipeline
->device
, cache
,
1210 &stages
[s
].cache_key
,
1211 sizeof(stages
[s
].cache_key
),
1212 code
, stages
[s
].prog_data
.base
.program_size
,
1213 stages
[s
].nir
->constant_data
,
1214 stages
[s
].nir
->constant_data_size
,
1215 &stages
[s
].prog_data
.base
,
1216 brw_prog_data_size(s
),
1217 xfb_info
, &stages
[s
].bind_map
);
1219 ralloc_free(stage_ctx
);
1220 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1224 pipeline
->shaders
[s
] = bin
;
1225 ralloc_free(stage_ctx
);
1227 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1229 prev_stage
= &stages
[s
];
1232 ralloc_free(pipeline_ctx
);
1236 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
] &&
1237 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->prog_data
->program_size
== 0) {
1238 /* This can happen if we decided to implicitly disable the fragment
1239 * shader. See anv_pipeline_compile_fs().
1241 anv_shader_bin_unref(pipeline
->device
,
1242 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
1243 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] = NULL
;
1244 pipeline
->active_stages
&= ~VK_SHADER_STAGE_FRAGMENT_BIT
;
1247 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1249 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1250 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1251 if (create_feedback
) {
1252 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1254 assert(info
->stageCount
== create_feedback
->pipelineStageCreationFeedbackCount
);
1255 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1256 gl_shader_stage s
= vk_to_mesa_shader_stage(info
->pStages
[i
].stage
);
1257 create_feedback
->pPipelineStageCreationFeedbacks
[i
] = stages
[s
].feedback
;
1264 ralloc_free(pipeline_ctx
);
1266 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1267 if (pipeline
->shaders
[s
])
1268 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1275 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1276 struct anv_pipeline_cache
*cache
,
1277 const VkComputePipelineCreateInfo
*info
,
1278 const struct anv_shader_module
*module
,
1279 const char *entrypoint
,
1280 const VkSpecializationInfo
*spec_info
)
1282 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1283 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1285 int64_t pipeline_start
= os_time_get_nano();
1287 const struct brw_compiler
*compiler
=
1288 pipeline
->device
->instance
->physicalDevice
.compiler
;
1290 struct anv_pipeline_stage stage
= {
1291 .stage
= MESA_SHADER_COMPUTE
,
1293 .entrypoint
= entrypoint
,
1294 .spec_info
= spec_info
,
1296 .stage
= MESA_SHADER_COMPUTE
,
1299 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1302 anv_pipeline_hash_shader(stage
.module
,
1304 MESA_SHADER_COMPUTE
,
1308 struct anv_shader_bin
*bin
= NULL
;
1310 populate_cs_prog_key(&pipeline
->device
->info
, &stage
.key
.cs
);
1312 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1314 anv_pipeline_hash_compute(pipeline
, layout
, &stage
, stage
.cache_key
.sha1
);
1316 bin
= anv_device_search_for_kernel(pipeline
->device
, cache
, &stage
.cache_key
,
1317 sizeof(stage
.cache_key
), &cache_hit
);
1320 int64_t stage_start
= os_time_get_nano();
1322 stage
.bind_map
= (struct anv_pipeline_bind_map
) {
1323 .surface_to_descriptor
= stage
.surface_to_descriptor
,
1324 .sampler_to_descriptor
= stage
.sampler_to_descriptor
1327 /* Set up a binding for the gl_NumWorkGroups */
1328 stage
.bind_map
.surface_count
= 1;
1329 stage
.bind_map
.surface_to_descriptor
[0] = (struct anv_pipeline_binding
) {
1330 .set
= ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
,
1333 void *mem_ctx
= ralloc_context(NULL
);
1335 stage
.nir
= anv_pipeline_stage_get_nir(pipeline
, cache
, mem_ctx
, &stage
);
1336 if (stage
.nir
== NULL
) {
1337 ralloc_free(mem_ctx
);
1338 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1341 anv_pipeline_lower_nir(pipeline
, mem_ctx
, &stage
, layout
);
1343 NIR_PASS_V(stage
.nir
, anv_nir_add_base_work_group_id
,
1344 &stage
.prog_data
.cs
);
1346 const unsigned *shader_code
=
1347 brw_compile_cs(compiler
, pipeline
->device
, mem_ctx
, &stage
.key
.cs
,
1348 &stage
.prog_data
.cs
, stage
.nir
, -1, NULL
);
1349 if (shader_code
== NULL
) {
1350 ralloc_free(mem_ctx
);
1351 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1354 const unsigned code_size
= stage
.prog_data
.base
.program_size
;
1355 bin
= anv_device_upload_kernel(pipeline
->device
, cache
,
1356 &stage
.cache_key
, sizeof(stage
.cache_key
),
1357 shader_code
, code_size
,
1358 stage
.nir
->constant_data
,
1359 stage
.nir
->constant_data_size
,
1360 &stage
.prog_data
.base
,
1361 sizeof(stage
.prog_data
.cs
),
1362 NULL
, &stage
.bind_map
);
1364 ralloc_free(mem_ctx
);
1365 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1368 ralloc_free(mem_ctx
);
1370 stage
.feedback
.duration
= os_time_get_nano() - stage_start
;
1374 stage
.feedback
.flags
|=
1375 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1376 pipeline_feedback
.flags
|=
1377 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1379 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1381 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1382 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1383 if (create_feedback
) {
1384 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1386 assert(create_feedback
->pipelineStageCreationFeedbackCount
== 1);
1387 create_feedback
->pPipelineStageCreationFeedbacks
[0] = stage
.feedback
;
1390 pipeline
->active_stages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1391 pipeline
->shaders
[MESA_SHADER_COMPUTE
] = bin
;
1397 * Copy pipeline state not marked as dynamic.
1398 * Dynamic state is pipeline state which hasn't been provided at pipeline
1399 * creation time, but is dynamically provided afterwards using various
1400 * vkCmdSet* functions.
1402 * The set of state considered "non_dynamic" is determined by the pieces of
1403 * state that have their corresponding VkDynamicState enums omitted from
1404 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1406 * @param[out] pipeline Destination non_dynamic state.
1407 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1410 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
1411 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1413 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
1414 struct anv_subpass
*subpass
= pipeline
->subpass
;
1416 pipeline
->dynamic_state
= default_dynamic_state
;
1418 if (pCreateInfo
->pDynamicState
) {
1419 /* Remove all of the states that are marked as dynamic */
1420 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1421 for (uint32_t s
= 0; s
< count
; s
++)
1422 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1425 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1427 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1429 * pViewportState is [...] NULL if the pipeline
1430 * has rasterization disabled.
1432 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1433 assert(pCreateInfo
->pViewportState
);
1435 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1436 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
1437 typed_memcpy(dynamic
->viewport
.viewports
,
1438 pCreateInfo
->pViewportState
->pViewports
,
1439 pCreateInfo
->pViewportState
->viewportCount
);
1442 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1443 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
1444 typed_memcpy(dynamic
->scissor
.scissors
,
1445 pCreateInfo
->pViewportState
->pScissors
,
1446 pCreateInfo
->pViewportState
->scissorCount
);
1450 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1451 assert(pCreateInfo
->pRasterizationState
);
1452 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1455 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1456 assert(pCreateInfo
->pRasterizationState
);
1457 dynamic
->depth_bias
.bias
=
1458 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1459 dynamic
->depth_bias
.clamp
=
1460 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1461 dynamic
->depth_bias
.slope
=
1462 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1465 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1467 * pColorBlendState is [...] NULL if the pipeline has rasterization
1468 * disabled or if the subpass of the render pass the pipeline is
1469 * created against does not use any color attachments.
1471 bool uses_color_att
= false;
1472 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1473 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1474 uses_color_att
= true;
1479 if (uses_color_att
&&
1480 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1481 assert(pCreateInfo
->pColorBlendState
);
1483 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
1484 typed_memcpy(dynamic
->blend_constants
,
1485 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1488 /* If there is no depthstencil attachment, then don't read
1489 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1490 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1491 * no need to override the depthstencil defaults in
1492 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1494 * Section 9.2 of the Vulkan 1.0.15 spec says:
1496 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1497 * disabled or if the subpass of the render pass the pipeline is created
1498 * against does not use a depth/stencil attachment.
1500 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1501 subpass
->depth_stencil_attachment
) {
1502 assert(pCreateInfo
->pDepthStencilState
);
1504 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1505 dynamic
->depth_bounds
.min
=
1506 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1507 dynamic
->depth_bounds
.max
=
1508 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1511 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1512 dynamic
->stencil_compare_mask
.front
=
1513 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1514 dynamic
->stencil_compare_mask
.back
=
1515 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1518 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1519 dynamic
->stencil_write_mask
.front
=
1520 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1521 dynamic
->stencil_write_mask
.back
=
1522 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1525 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1526 dynamic
->stencil_reference
.front
=
1527 pCreateInfo
->pDepthStencilState
->front
.reference
;
1528 dynamic
->stencil_reference
.back
=
1529 pCreateInfo
->pDepthStencilState
->back
.reference
;
1533 pipeline
->dynamic_state_mask
= states
;
1537 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1540 struct anv_render_pass
*renderpass
= NULL
;
1541 struct anv_subpass
*subpass
= NULL
;
1543 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1544 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1546 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1548 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1551 assert(info
->subpass
< renderpass
->subpass_count
);
1552 subpass
= &renderpass
->subpasses
[info
->subpass
];
1554 assert(info
->stageCount
>= 1);
1555 assert(info
->pVertexInputState
);
1556 assert(info
->pInputAssemblyState
);
1557 assert(info
->pRasterizationState
);
1558 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1559 assert(info
->pViewportState
);
1560 assert(info
->pMultisampleState
);
1562 if (subpass
&& subpass
->depth_stencil_attachment
)
1563 assert(info
->pDepthStencilState
);
1565 if (subpass
&& subpass
->color_count
> 0) {
1566 bool all_color_unused
= true;
1567 for (int i
= 0; i
< subpass
->color_count
; i
++) {
1568 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
1569 all_color_unused
= false;
1571 /* pColorBlendState is ignored if the pipeline has rasterization
1572 * disabled or if the subpass of the render pass the pipeline is
1573 * created against does not use any color attachments.
1575 assert(info
->pColorBlendState
|| all_color_unused
);
1579 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1580 switch (info
->pStages
[i
].stage
) {
1581 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1582 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1583 assert(info
->pTessellationState
);
1593 * Calculate the desired L3 partitioning based on the current state of the
1594 * pipeline. For now this simply returns the conservative defaults calculated
1595 * by get_default_l3_weights(), but we could probably do better by gathering
1596 * more statistics from the pipeline state (e.g. guess of expected URB usage
1597 * and bound surfaces), or by using feed-back from performance counters.
1600 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1602 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1604 const struct gen_l3_weights w
=
1605 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
1607 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
1608 pipeline
->urb
.total_size
=
1609 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
1613 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1614 struct anv_device
*device
,
1615 struct anv_pipeline_cache
*cache
,
1616 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1617 const VkAllocationCallbacks
*alloc
)
1621 anv_pipeline_validate_create_info(pCreateInfo
);
1624 alloc
= &device
->alloc
;
1626 pipeline
->device
= device
;
1628 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, pCreateInfo
->renderPass
);
1629 assert(pCreateInfo
->subpass
< render_pass
->subpass_count
);
1630 pipeline
->subpass
= &render_pass
->subpasses
[pCreateInfo
->subpass
];
1632 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1633 if (result
!= VK_SUCCESS
)
1636 pipeline
->batch
.alloc
= alloc
;
1637 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1638 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1639 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1640 pipeline
->batch
.status
= VK_SUCCESS
;
1642 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1643 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1644 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1646 /* Previously we enabled depth clipping when !depthClampEnable.
1647 * DepthClipStateCreateInfo now makes depth clipping explicit so if the
1648 * clipping info is available, use its enable value to determine clipping,
1649 * otherwise fallback to the previous !depthClampEnable logic.
1651 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*clip_info
=
1652 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1653 PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
1654 pipeline
->depth_clip_enable
= clip_info
? clip_info
->depthClipEnable
: !pipeline
->depth_clamp_enable
;
1656 pipeline
->sample_shading_enable
= pCreateInfo
->pMultisampleState
&&
1657 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
1659 pipeline
->needs_data_cache
= false;
1661 /* When we free the pipeline, we detect stages based on the NULL status
1662 * of various prog_data pointers. Make them NULL by default.
1664 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1666 result
= anv_pipeline_compile_graphics(pipeline
, cache
, pCreateInfo
);
1667 if (result
!= VK_SUCCESS
) {
1668 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);
1672 assert(pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1674 anv_pipeline_setup_l3_config(pipeline
, false);
1676 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1677 pCreateInfo
->pVertexInputState
;
1679 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1681 pipeline
->vb_used
= 0;
1682 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1683 const VkVertexInputAttributeDescription
*desc
=
1684 &vi_info
->pVertexAttributeDescriptions
[i
];
1686 if (inputs_read
& (1ull << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1687 pipeline
->vb_used
|= 1 << desc
->binding
;
1690 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1691 const VkVertexInputBindingDescription
*desc
=
1692 &vi_info
->pVertexBindingDescriptions
[i
];
1694 pipeline
->vb
[desc
->binding
].stride
= desc
->stride
;
1696 /* Step rate is programmed per vertex element (attribute), not
1697 * binding. Set up a map of which bindings step per instance, for
1698 * reference by vertex element setup. */
1699 switch (desc
->inputRate
) {
1701 case VK_VERTEX_INPUT_RATE_VERTEX
:
1702 pipeline
->vb
[desc
->binding
].instanced
= false;
1704 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1705 pipeline
->vb
[desc
->binding
].instanced
= true;
1709 pipeline
->vb
[desc
->binding
].instance_divisor
= 1;
1712 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*vi_div_state
=
1713 vk_find_struct_const(vi_info
->pNext
,
1714 PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
1716 for (uint32_t i
= 0; i
< vi_div_state
->vertexBindingDivisorCount
; i
++) {
1717 const VkVertexInputBindingDivisorDescriptionEXT
*desc
=
1718 &vi_div_state
->pVertexBindingDivisors
[i
];
1720 pipeline
->vb
[desc
->binding
].instance_divisor
= desc
->divisor
;
1724 /* Our implementation of VK_KHR_multiview uses instancing to draw the
1725 * different views. If the client asks for instancing, we need to multiply
1726 * the instance divisor by the number of views ensure that we repeat the
1727 * client's per-instance data once for each view.
1729 if (pipeline
->subpass
->view_mask
) {
1730 const uint32_t view_count
= anv_subpass_view_count(pipeline
->subpass
);
1731 for (uint32_t vb
= 0; vb
< MAX_VBS
; vb
++) {
1732 if (pipeline
->vb
[vb
].instanced
)
1733 pipeline
->vb
[vb
].instance_divisor
*= view_count
;
1737 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1738 pCreateInfo
->pInputAssemblyState
;
1739 const VkPipelineTessellationStateCreateInfo
*tess_info
=
1740 pCreateInfo
->pTessellationState
;
1741 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1743 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1744 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
1746 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];