2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "util/os_time.h"
32 #include "common/gen_l3_config.h"
33 #include "anv_private.h"
34 #include "compiler/brw_nir.h"
36 #include "nir/nir_xfb_info.h"
37 #include "spirv/nir_spirv.h"
40 /* Needed for SWIZZLE macros */
41 #include "program/prog_instruction.h"
45 VkResult
anv_CreateShaderModule(
47 const VkShaderModuleCreateInfo
* pCreateInfo
,
48 const VkAllocationCallbacks
* pAllocator
,
49 VkShaderModule
* pShaderModule
)
51 ANV_FROM_HANDLE(anv_device
, device
, _device
);
52 struct anv_shader_module
*module
;
54 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
55 assert(pCreateInfo
->flags
== 0);
57 module
= vk_alloc2(&device
->alloc
, pAllocator
,
58 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
59 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
61 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
63 module
->size
= pCreateInfo
->codeSize
;
64 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
66 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
68 *pShaderModule
= anv_shader_module_to_handle(module
);
73 void anv_DestroyShaderModule(
75 VkShaderModule _module
,
76 const VkAllocationCallbacks
* pAllocator
)
78 ANV_FROM_HANDLE(anv_device
, device
, _device
);
79 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
84 vk_free2(&device
->alloc
, pAllocator
, module
);
87 #define SPIR_V_MAGIC_NUMBER 0x07230203
89 static const uint64_t stage_to_debug
[] = {
90 [MESA_SHADER_VERTEX
] = DEBUG_VS
,
91 [MESA_SHADER_TESS_CTRL
] = DEBUG_TCS
,
92 [MESA_SHADER_TESS_EVAL
] = DEBUG_TES
,
93 [MESA_SHADER_GEOMETRY
] = DEBUG_GS
,
94 [MESA_SHADER_FRAGMENT
] = DEBUG_WM
,
95 [MESA_SHADER_COMPUTE
] = DEBUG_CS
,
98 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
99 * we can't do that yet because we don't have the ability to copy nir.
102 anv_shader_compile_to_nir(struct anv_device
*device
,
104 const struct anv_shader_module
*module
,
105 const char *entrypoint_name
,
106 gl_shader_stage stage
,
107 const VkSpecializationInfo
*spec_info
)
109 const struct anv_physical_device
*pdevice
=
110 &device
->instance
->physicalDevice
;
111 const struct brw_compiler
*compiler
= pdevice
->compiler
;
112 const nir_shader_compiler_options
*nir_options
=
113 compiler
->glsl_compiler_options
[stage
].NirOptions
;
115 uint32_t *spirv
= (uint32_t *) module
->data
;
116 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
117 assert(module
->size
% 4 == 0);
119 uint32_t num_spec_entries
= 0;
120 struct nir_spirv_specialization
*spec_entries
= NULL
;
121 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
122 num_spec_entries
= spec_info
->mapEntryCount
;
123 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
124 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
125 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
126 const void *data
= spec_info
->pData
+ entry
.offset
;
127 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
129 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
130 if (spec_info
->dataSize
== 8)
131 spec_entries
[i
].data64
= *(const uint64_t *)data
;
133 spec_entries
[i
].data32
= *(const uint32_t *)data
;
137 struct spirv_to_nir_options spirv_options
= {
138 .lower_workgroup_access_to_offsets
= true,
140 .derivative_group
= true,
141 .device_group
= true,
142 .draw_parameters
= true,
143 .float16
= pdevice
->info
.gen
>= 8,
144 .float64
= pdevice
->info
.gen
>= 8,
145 .geometry_streams
= true,
146 .image_write_without_format
= true,
147 .int8
= pdevice
->info
.gen
>= 8,
148 .int16
= pdevice
->info
.gen
>= 8,
149 .int64
= pdevice
->info
.gen
>= 8,
150 .int64_atomics
= pdevice
->info
.gen
>= 9 && pdevice
->use_softpin
,
153 .physical_storage_buffer_address
= pdevice
->has_a64_buffer_access
,
154 .post_depth_coverage
= pdevice
->info
.gen
>= 9,
155 .shader_viewport_index_layer
= true,
156 .stencil_export
= pdevice
->info
.gen
>= 9,
157 .storage_8bit
= pdevice
->info
.gen
>= 8,
158 .storage_16bit
= pdevice
->info
.gen
>= 8,
159 .subgroup_arithmetic
= true,
160 .subgroup_basic
= true,
161 .subgroup_ballot
= true,
162 .subgroup_quad
= true,
163 .subgroup_shuffle
= true,
164 .subgroup_vote
= true,
165 .tessellation
= true,
166 .transform_feedback
= pdevice
->info
.gen
>= 8,
167 .variable_pointers
= true,
169 .ubo_ptr_type
= glsl_vector_type(GLSL_TYPE_UINT
, 2),
170 .phys_ssbo_ptr_type
= glsl_vector_type(GLSL_TYPE_UINT64
, 1),
171 .push_const_ptr_type
= glsl_uint_type(),
172 .shared_ptr_type
= glsl_uint_type(),
175 if (pdevice
->has_a64_buffer_access
) {
176 if (device
->robust_buffer_access
)
177 spirv_options
.ssbo_ptr_type
= glsl_vector_type(GLSL_TYPE_UINT
, 4);
179 spirv_options
.ssbo_ptr_type
= glsl_vector_type(GLSL_TYPE_UINT64
, 1);
181 spirv_options
.ssbo_ptr_type
= glsl_vector_type(GLSL_TYPE_UINT
, 2);
184 nir_function
*entry_point
=
185 spirv_to_nir(spirv
, module
->size
/ 4,
186 spec_entries
, num_spec_entries
,
187 stage
, entrypoint_name
, &spirv_options
, nir_options
);
188 nir_shader
*nir
= entry_point
->shader
;
189 assert(nir
->info
.stage
== stage
);
190 nir_validate_shader(nir
, "after spirv_to_nir");
191 ralloc_steal(mem_ctx
, nir
);
195 if (unlikely(INTEL_DEBUG
& stage_to_debug
[stage
])) {
196 fprintf(stderr
, "NIR (from SPIR-V) for %s shader:\n",
197 gl_shader_stage_name(stage
));
198 nir_print_shader(nir
, stderr
);
201 /* We have to lower away local constant initializers right before we
202 * inline functions. That way they get properly initialized at the top
203 * of the function and not at the top of its caller.
205 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_function_temp
);
206 NIR_PASS_V(nir
, nir_lower_returns
);
207 NIR_PASS_V(nir
, nir_inline_functions
);
208 NIR_PASS_V(nir
, nir_opt_deref
);
210 /* Pick off the single entrypoint that we want */
211 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
212 if (func
!= entry_point
)
213 exec_node_remove(&func
->node
);
215 assert(exec_list_length(&nir
->functions
) == 1);
217 /* Now that we've deleted all but the main function, we can go ahead and
218 * lower the rest of the constant initializers. We do this here so that
219 * nir_remove_dead_variables and split_per_member_structs below see the
220 * corresponding stores.
222 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
224 /* Split member structs. We do this before lower_io_to_temporaries so that
225 * it doesn't lower system values to temporaries by accident.
227 NIR_PASS_V(nir
, nir_split_var_copies
);
228 NIR_PASS_V(nir
, nir_split_per_member_structs
);
230 NIR_PASS_V(nir
, nir_remove_dead_variables
,
231 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
233 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_global
,
234 nir_address_format_64bit_global
);
236 NIR_PASS_V(nir
, nir_propagate_invariant
);
237 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
238 entry_point
->impl
, true, false);
240 NIR_PASS_V(nir
, nir_lower_frexp
);
242 /* Vulkan uses the separate-shader linking model */
243 nir
->info
.separate_shader
= true;
245 nir
= brw_preprocess_nir(compiler
, nir
, NULL
);
250 void anv_DestroyPipeline(
252 VkPipeline _pipeline
,
253 const VkAllocationCallbacks
* pAllocator
)
255 ANV_FROM_HANDLE(anv_device
, device
, _device
);
256 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
261 anv_reloc_list_finish(&pipeline
->batch_relocs
,
262 pAllocator
? pAllocator
: &device
->alloc
);
263 if (pipeline
->blend_state
.map
)
264 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
266 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
267 if (pipeline
->shaders
[s
])
268 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
271 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
274 static const uint32_t vk_to_gen_primitive_type
[] = {
275 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
276 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
277 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
278 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
279 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
280 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
281 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
282 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
283 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
284 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
288 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
289 struct brw_sampler_prog_key_data
*key
)
291 /* Almost all multisampled textures are compressed. The only time when we
292 * don't compress a multisampled texture is for 16x MSAA with a surface
293 * width greater than 8k which is a bit of an edge case. Since the sampler
294 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
295 * to tell the compiler to always assume compression.
297 key
->compressed_multisample_layout_mask
= ~0;
299 /* SkyLake added support for 16x MSAA. With this came a new message for
300 * reading from a 16x MSAA surface with compression. The new message was
301 * needed because now the MCS data is 64 bits instead of 32 or lower as is
302 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
303 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
304 * so we can just use it unconditionally. This may not be quite as
305 * efficient but it saves us from recompiling.
307 if (devinfo
->gen
>= 9)
310 /* XXX: Handle texture swizzle on HSW- */
311 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
312 /* Assume color sampler, no swizzling. (Works for BDW+) */
313 key
->swizzles
[i
] = SWIZZLE_XYZW
;
318 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
319 struct brw_vs_prog_key
*key
)
321 memset(key
, 0, sizeof(*key
));
323 populate_sampler_prog_key(devinfo
, &key
->tex
);
325 /* XXX: Handle vertex input work-arounds */
327 /* XXX: Handle sampler_prog_key */
331 populate_tcs_prog_key(const struct gen_device_info
*devinfo
,
332 unsigned input_vertices
,
333 struct brw_tcs_prog_key
*key
)
335 memset(key
, 0, sizeof(*key
));
337 populate_sampler_prog_key(devinfo
, &key
->tex
);
339 key
->input_vertices
= input_vertices
;
343 populate_tes_prog_key(const struct gen_device_info
*devinfo
,
344 struct brw_tes_prog_key
*key
)
346 memset(key
, 0, sizeof(*key
));
348 populate_sampler_prog_key(devinfo
, &key
->tex
);
352 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
353 struct brw_gs_prog_key
*key
)
355 memset(key
, 0, sizeof(*key
));
357 populate_sampler_prog_key(devinfo
, &key
->tex
);
361 populate_wm_prog_key(const struct gen_device_info
*devinfo
,
362 const struct anv_subpass
*subpass
,
363 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
364 struct brw_wm_prog_key
*key
)
366 memset(key
, 0, sizeof(*key
));
368 populate_sampler_prog_key(devinfo
, &key
->tex
);
370 /* We set this to 0 here and set to the actual value before we call
373 key
->input_slots_valid
= 0;
375 /* Vulkan doesn't specify a default */
376 key
->high_quality_derivatives
= false;
378 /* XXX Vulkan doesn't appear to specify */
379 key
->clamp_fragment_color
= false;
381 assert(subpass
->color_count
<= MAX_RTS
);
382 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
383 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
384 key
->color_outputs_valid
|= (1 << i
);
387 key
->nr_color_regions
= util_bitcount(key
->color_outputs_valid
);
389 /* To reduce possible shader recompilations we would need to know if
390 * there is a SampleMask output variable to compute if we should emit
391 * code to workaround the issue that hardware disables alpha to coverage
392 * when there is SampleMask output.
394 key
->alpha_to_coverage
= ms_info
&& ms_info
->alphaToCoverageEnable
;
396 /* Vulkan doesn't support fixed-function alpha test */
397 key
->alpha_test_replicate_alpha
= false;
400 /* We should probably pull this out of the shader, but it's fairly
401 * harmless to compute it and then let dead-code take care of it.
403 if (ms_info
->rasterizationSamples
> 1) {
404 key
->persample_interp
=
405 (ms_info
->minSampleShading
* ms_info
->rasterizationSamples
) > 1;
406 key
->multisample_fbo
= true;
409 key
->frag_coord_adds_sample_pos
= ms_info
->sampleShadingEnable
;
414 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
415 struct brw_cs_prog_key
*key
)
417 memset(key
, 0, sizeof(*key
));
419 populate_sampler_prog_key(devinfo
, &key
->tex
);
422 struct anv_pipeline_stage
{
423 gl_shader_stage stage
;
425 const struct anv_shader_module
*module
;
426 const char *entrypoint
;
427 const VkSpecializationInfo
*spec_info
;
429 unsigned char shader_sha1
[20];
431 union brw_any_prog_key key
;
434 gl_shader_stage stage
;
435 unsigned char sha1
[20];
440 struct anv_pipeline_binding surface_to_descriptor
[256];
441 struct anv_pipeline_binding sampler_to_descriptor
[256];
442 struct anv_pipeline_bind_map bind_map
;
444 union brw_any_prog_data prog_data
;
446 VkPipelineCreationFeedbackEXT feedback
;
450 anv_pipeline_hash_shader(const struct anv_shader_module
*module
,
451 const char *entrypoint
,
452 gl_shader_stage stage
,
453 const VkSpecializationInfo
*spec_info
,
454 unsigned char *sha1_out
)
456 struct mesa_sha1 ctx
;
457 _mesa_sha1_init(&ctx
);
459 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
460 _mesa_sha1_update(&ctx
, entrypoint
, strlen(entrypoint
));
461 _mesa_sha1_update(&ctx
, &stage
, sizeof(stage
));
463 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
464 spec_info
->mapEntryCount
*
465 sizeof(*spec_info
->pMapEntries
));
466 _mesa_sha1_update(&ctx
, spec_info
->pData
,
467 spec_info
->dataSize
);
470 _mesa_sha1_final(&ctx
, sha1_out
);
474 anv_pipeline_hash_graphics(struct anv_pipeline
*pipeline
,
475 struct anv_pipeline_layout
*layout
,
476 struct anv_pipeline_stage
*stages
,
477 unsigned char *sha1_out
)
479 struct mesa_sha1 ctx
;
480 _mesa_sha1_init(&ctx
);
482 _mesa_sha1_update(&ctx
, &pipeline
->subpass
->view_mask
,
483 sizeof(pipeline
->subpass
->view_mask
));
486 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
488 const bool rba
= pipeline
->device
->robust_buffer_access
;
489 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
491 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
492 if (stages
[s
].entrypoint
) {
493 _mesa_sha1_update(&ctx
, stages
[s
].shader_sha1
,
494 sizeof(stages
[s
].shader_sha1
));
495 _mesa_sha1_update(&ctx
, &stages
[s
].key
, brw_prog_key_size(s
));
499 _mesa_sha1_final(&ctx
, sha1_out
);
503 anv_pipeline_hash_compute(struct anv_pipeline
*pipeline
,
504 struct anv_pipeline_layout
*layout
,
505 struct anv_pipeline_stage
*stage
,
506 unsigned char *sha1_out
)
508 struct mesa_sha1 ctx
;
509 _mesa_sha1_init(&ctx
);
512 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
514 const bool rba
= pipeline
->device
->robust_buffer_access
;
515 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
517 _mesa_sha1_update(&ctx
, stage
->shader_sha1
,
518 sizeof(stage
->shader_sha1
));
519 _mesa_sha1_update(&ctx
, &stage
->key
.cs
, sizeof(stage
->key
.cs
));
521 _mesa_sha1_final(&ctx
, sha1_out
);
525 anv_pipeline_stage_get_nir(struct anv_pipeline
*pipeline
,
526 struct anv_pipeline_cache
*cache
,
528 struct anv_pipeline_stage
*stage
)
530 const struct brw_compiler
*compiler
=
531 pipeline
->device
->instance
->physicalDevice
.compiler
;
532 const nir_shader_compiler_options
*nir_options
=
533 compiler
->glsl_compiler_options
[stage
->stage
].NirOptions
;
536 nir
= anv_device_search_for_nir(pipeline
->device
, cache
,
541 assert(nir
->info
.stage
== stage
->stage
);
545 nir
= anv_shader_compile_to_nir(pipeline
->device
,
552 anv_device_upload_nir(pipeline
->device
, cache
, nir
, stage
->shader_sha1
);
560 anv_pipeline_lower_nir(struct anv_pipeline
*pipeline
,
562 struct anv_pipeline_stage
*stage
,
563 struct anv_pipeline_layout
*layout
)
565 const struct anv_physical_device
*pdevice
=
566 &pipeline
->device
->instance
->physicalDevice
;
567 const struct brw_compiler
*compiler
= pdevice
->compiler
;
569 struct brw_stage_prog_data
*prog_data
= &stage
->prog_data
.base
;
570 nir_shader
*nir
= stage
->nir
;
572 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
573 NIR_PASS_V(nir
, nir_lower_wpos_center
, pipeline
->sample_shading_enable
);
574 NIR_PASS_V(nir
, anv_nir_lower_input_attachments
);
577 NIR_PASS_V(nir
, anv_nir_lower_ycbcr_textures
, layout
);
579 NIR_PASS_V(nir
, anv_nir_lower_push_constants
);
581 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
582 NIR_PASS_V(nir
, anv_nir_lower_multiview
, pipeline
->subpass
->view_mask
);
584 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
585 prog_data
->total_shared
= nir
->num_shared
;
587 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
589 if (nir
->num_uniforms
> 0) {
590 assert(prog_data
->nr_params
== 0);
592 /* If the shader uses any push constants at all, we'll just give
593 * them the maximum possible number
595 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
596 nir
->num_uniforms
= MAX_PUSH_CONSTANTS_SIZE
;
597 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
598 prog_data
->param
= ralloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
600 /* We now set the param values to be offsets into a
601 * anv_push_constant_data structure. Since the compiler doesn't
602 * actually dereference any of the gl_constant_value pointers in the
603 * params array, it doesn't really matter what we put here.
605 struct anv_push_constants
*null_data
= NULL
;
606 /* Fill out the push constants section of the param array */
607 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++) {
608 prog_data
->param
[i
] = ANV_PARAM_PUSH(
609 (uintptr_t)&null_data
->client_data
[i
* sizeof(float)]);
613 if (nir
->info
.num_ssbos
> 0 || nir
->info
.num_images
> 0)
614 pipeline
->needs_data_cache
= true;
616 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, compiler
->devinfo
);
618 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
620 anv_nir_apply_pipeline_layout(pdevice
,
621 pipeline
->device
->robust_buffer_access
,
622 layout
, nir
, prog_data
,
625 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ubo
,
626 nir_address_format_32bit_index_offset
);
628 nir_address_format ssbo_address_format
;
629 if (pdevice
->has_a64_buffer_access
) {
630 if (pipeline
->device
->robust_buffer_access
)
631 ssbo_address_format
= nir_address_format_64bit_bounded_global
;
633 ssbo_address_format
= nir_address_format_64bit_global
;
635 ssbo_address_format
= nir_address_format_32bit_index_offset
;
637 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ssbo
,
638 ssbo_address_format
);
640 NIR_PASS_V(nir
, nir_opt_constant_folding
);
643 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
644 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
646 assert(nir
->num_uniforms
== prog_data
->nr_params
* 4);
652 anv_pipeline_link_vs(const struct brw_compiler
*compiler
,
653 struct anv_pipeline_stage
*vs_stage
,
654 struct anv_pipeline_stage
*next_stage
)
657 brw_nir_link_shaders(compiler
, &vs_stage
->nir
, &next_stage
->nir
);
660 static const unsigned *
661 anv_pipeline_compile_vs(const struct brw_compiler
*compiler
,
663 struct anv_device
*device
,
664 struct anv_pipeline_stage
*vs_stage
)
666 brw_compute_vue_map(compiler
->devinfo
,
667 &vs_stage
->prog_data
.vs
.base
.vue_map
,
668 vs_stage
->nir
->info
.outputs_written
,
669 vs_stage
->nir
->info
.separate_shader
);
671 return brw_compile_vs(compiler
, device
, mem_ctx
, &vs_stage
->key
.vs
,
672 &vs_stage
->prog_data
.vs
, vs_stage
->nir
, -1, NULL
);
676 merge_tess_info(struct shader_info
*tes_info
,
677 const struct shader_info
*tcs_info
)
679 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
681 * "PointMode. Controls generation of points rather than triangles
682 * or lines. This functionality defaults to disabled, and is
683 * enabled if either shader stage includes the execution mode.
685 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
686 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
687 * and OutputVertices, it says:
689 * "One mode must be set in at least one of the tessellation
692 * So, the fields can be set in either the TCS or TES, but they must
693 * agree if set in both. Our backend looks at TES, so bitwise-or in
694 * the values from the TCS.
696 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
697 tes_info
->tess
.tcs_vertices_out
== 0 ||
698 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
699 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
701 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
702 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
703 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
704 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
706 assert(tcs_info
->tess
.primitive_mode
== 0 ||
707 tes_info
->tess
.primitive_mode
== 0 ||
708 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
709 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
710 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
711 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
715 anv_pipeline_link_tcs(const struct brw_compiler
*compiler
,
716 struct anv_pipeline_stage
*tcs_stage
,
717 struct anv_pipeline_stage
*tes_stage
)
719 assert(tes_stage
&& tes_stage
->stage
== MESA_SHADER_TESS_EVAL
);
721 brw_nir_link_shaders(compiler
, &tcs_stage
->nir
, &tes_stage
->nir
);
723 nir_lower_patch_vertices(tes_stage
->nir
,
724 tcs_stage
->nir
->info
.tess
.tcs_vertices_out
,
727 /* Copy TCS info into the TES info */
728 merge_tess_info(&tes_stage
->nir
->info
, &tcs_stage
->nir
->info
);
730 /* Whacking the key after cache lookup is a bit sketchy, but all of
731 * this comes from the SPIR-V, which is part of the hash used for the
732 * pipeline cache. So it should be safe.
734 tcs_stage
->key
.tcs
.tes_primitive_mode
=
735 tes_stage
->nir
->info
.tess
.primitive_mode
;
736 tcs_stage
->key
.tcs
.quads_workaround
=
737 compiler
->devinfo
->gen
< 9 &&
738 tes_stage
->nir
->info
.tess
.primitive_mode
== 7 /* GL_QUADS */ &&
739 tes_stage
->nir
->info
.tess
.spacing
== TESS_SPACING_EQUAL
;
742 static const unsigned *
743 anv_pipeline_compile_tcs(const struct brw_compiler
*compiler
,
745 struct anv_device
*device
,
746 struct anv_pipeline_stage
*tcs_stage
,
747 struct anv_pipeline_stage
*prev_stage
)
749 tcs_stage
->key
.tcs
.outputs_written
=
750 tcs_stage
->nir
->info
.outputs_written
;
751 tcs_stage
->key
.tcs
.patch_outputs_written
=
752 tcs_stage
->nir
->info
.patch_outputs_written
;
754 return brw_compile_tcs(compiler
, device
, mem_ctx
, &tcs_stage
->key
.tcs
,
755 &tcs_stage
->prog_data
.tcs
, tcs_stage
->nir
,
760 anv_pipeline_link_tes(const struct brw_compiler
*compiler
,
761 struct anv_pipeline_stage
*tes_stage
,
762 struct anv_pipeline_stage
*next_stage
)
765 brw_nir_link_shaders(compiler
, &tes_stage
->nir
, &next_stage
->nir
);
768 static const unsigned *
769 anv_pipeline_compile_tes(const struct brw_compiler
*compiler
,
771 struct anv_device
*device
,
772 struct anv_pipeline_stage
*tes_stage
,
773 struct anv_pipeline_stage
*tcs_stage
)
775 tes_stage
->key
.tes
.inputs_read
=
776 tcs_stage
->nir
->info
.outputs_written
;
777 tes_stage
->key
.tes
.patch_inputs_read
=
778 tcs_stage
->nir
->info
.patch_outputs_written
;
780 return brw_compile_tes(compiler
, device
, mem_ctx
, &tes_stage
->key
.tes
,
781 &tcs_stage
->prog_data
.tcs
.base
.vue_map
,
782 &tes_stage
->prog_data
.tes
, tes_stage
->nir
,
787 anv_pipeline_link_gs(const struct brw_compiler
*compiler
,
788 struct anv_pipeline_stage
*gs_stage
,
789 struct anv_pipeline_stage
*next_stage
)
792 brw_nir_link_shaders(compiler
, &gs_stage
->nir
, &next_stage
->nir
);
795 static const unsigned *
796 anv_pipeline_compile_gs(const struct brw_compiler
*compiler
,
798 struct anv_device
*device
,
799 struct anv_pipeline_stage
*gs_stage
,
800 struct anv_pipeline_stage
*prev_stage
)
802 brw_compute_vue_map(compiler
->devinfo
,
803 &gs_stage
->prog_data
.gs
.base
.vue_map
,
804 gs_stage
->nir
->info
.outputs_written
,
805 gs_stage
->nir
->info
.separate_shader
);
807 return brw_compile_gs(compiler
, device
, mem_ctx
, &gs_stage
->key
.gs
,
808 &gs_stage
->prog_data
.gs
, gs_stage
->nir
,
813 anv_pipeline_link_fs(const struct brw_compiler
*compiler
,
814 struct anv_pipeline_stage
*stage
)
816 unsigned num_rts
= 0;
817 const int max_rt
= FRAG_RESULT_DATA7
- FRAG_RESULT_DATA0
+ 1;
818 struct anv_pipeline_binding rt_bindings
[max_rt
];
819 nir_function_impl
*impl
= nir_shader_get_entrypoint(stage
->nir
);
820 int rt_to_bindings
[max_rt
];
821 memset(rt_to_bindings
, -1, sizeof(rt_to_bindings
));
822 bool rt_used
[max_rt
];
823 memset(rt_used
, 0, sizeof(rt_used
));
825 /* Flag used render targets */
826 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
827 if (var
->data
.location
< FRAG_RESULT_DATA0
)
830 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
831 /* Unused or out-of-bounds */
832 if (rt
>= MAX_RTS
|| !(stage
->key
.wm
.color_outputs_valid
& (1 << rt
)))
835 const unsigned array_len
=
836 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
837 assert(rt
+ array_len
<= max_rt
);
839 for (unsigned i
= 0; i
< array_len
; i
++)
840 rt_used
[rt
+ i
] = true;
843 /* Set new, compacted, location */
844 for (unsigned i
= 0; i
< max_rt
; i
++) {
848 rt_to_bindings
[i
] = num_rts
;
849 rt_bindings
[rt_to_bindings
[i
]] = (struct anv_pipeline_binding
) {
850 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
857 bool deleted_output
= false;
858 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
859 if (var
->data
.location
< FRAG_RESULT_DATA0
)
862 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
864 !(stage
->key
.wm
.color_outputs_valid
& (1 << rt
))) {
865 /* Unused or out-of-bounds, throw it away */
866 deleted_output
= true;
867 var
->data
.mode
= nir_var_function_temp
;
868 exec_node_remove(&var
->node
);
869 exec_list_push_tail(&impl
->locals
, &var
->node
);
873 /* Give it the new location */
874 assert(rt_to_bindings
[rt
] != -1);
875 var
->data
.location
= rt_to_bindings
[rt
] + FRAG_RESULT_DATA0
;
879 nir_fixup_deref_modes(stage
->nir
);
882 /* If we have no render targets, we need a null render target */
883 rt_bindings
[0] = (struct anv_pipeline_binding
) {
884 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
891 /* Now that we've determined the actual number of render targets, adjust
892 * the key accordingly.
894 stage
->key
.wm
.nr_color_regions
= num_rts
;
895 stage
->key
.wm
.color_outputs_valid
= (1 << num_rts
) - 1;
897 assert(num_rts
<= max_rt
);
898 assert(stage
->bind_map
.surface_count
== 0);
899 typed_memcpy(stage
->bind_map
.surface_to_descriptor
,
900 rt_bindings
, num_rts
);
901 stage
->bind_map
.surface_count
+= num_rts
;
904 static const unsigned *
905 anv_pipeline_compile_fs(const struct brw_compiler
*compiler
,
907 struct anv_device
*device
,
908 struct anv_pipeline_stage
*fs_stage
,
909 struct anv_pipeline_stage
*prev_stage
)
911 /* TODO: we could set this to 0 based on the information in nir_shader, but
912 * we need this before we call spirv_to_nir.
915 fs_stage
->key
.wm
.input_slots_valid
=
916 prev_stage
->prog_data
.vue
.vue_map
.slots_valid
;
918 const unsigned *code
=
919 brw_compile_fs(compiler
, device
, mem_ctx
, &fs_stage
->key
.wm
,
920 &fs_stage
->prog_data
.wm
, fs_stage
->nir
,
921 NULL
, -1, -1, -1, true, false, NULL
, NULL
);
923 if (fs_stage
->key
.wm
.nr_color_regions
== 0 &&
924 !fs_stage
->prog_data
.wm
.has_side_effects
&&
925 !fs_stage
->prog_data
.wm
.uses_kill
&&
926 fs_stage
->prog_data
.wm
.computed_depth_mode
== BRW_PSCDEPTH_OFF
&&
927 !fs_stage
->prog_data
.wm
.computed_stencil
) {
928 /* This fragment shader has no outputs and no side effects. Go ahead
929 * and return the code pointer so we don't accidentally think the
930 * compile failed but zero out prog_data which will set program_size to
931 * zero and disable the stage.
933 memset(&fs_stage
->prog_data
, 0, sizeof(fs_stage
->prog_data
));
940 anv_pipeline_compile_graphics(struct anv_pipeline
*pipeline
,
941 struct anv_pipeline_cache
*cache
,
942 const VkGraphicsPipelineCreateInfo
*info
)
944 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
945 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
947 int64_t pipeline_start
= os_time_get_nano();
949 const struct brw_compiler
*compiler
=
950 pipeline
->device
->instance
->physicalDevice
.compiler
;
951 struct anv_pipeline_stage stages
[MESA_SHADER_STAGES
] = {};
953 pipeline
->active_stages
= 0;
956 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
957 const VkPipelineShaderStageCreateInfo
*sinfo
= &info
->pStages
[i
];
958 gl_shader_stage stage
= vk_to_mesa_shader_stage(sinfo
->stage
);
960 pipeline
->active_stages
|= sinfo
->stage
;
962 int64_t stage_start
= os_time_get_nano();
964 stages
[stage
].stage
= stage
;
965 stages
[stage
].module
= anv_shader_module_from_handle(sinfo
->module
);
966 stages
[stage
].entrypoint
= sinfo
->pName
;
967 stages
[stage
].spec_info
= sinfo
->pSpecializationInfo
;
968 anv_pipeline_hash_shader(stages
[stage
].module
,
969 stages
[stage
].entrypoint
,
971 stages
[stage
].spec_info
,
972 stages
[stage
].shader_sha1
);
974 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
976 case MESA_SHADER_VERTEX
:
977 populate_vs_prog_key(devinfo
, &stages
[stage
].key
.vs
);
979 case MESA_SHADER_TESS_CTRL
:
980 populate_tcs_prog_key(devinfo
,
981 info
->pTessellationState
->patchControlPoints
,
982 &stages
[stage
].key
.tcs
);
984 case MESA_SHADER_TESS_EVAL
:
985 populate_tes_prog_key(devinfo
, &stages
[stage
].key
.tes
);
987 case MESA_SHADER_GEOMETRY
:
988 populate_gs_prog_key(devinfo
, &stages
[stage
].key
.gs
);
990 case MESA_SHADER_FRAGMENT
:
991 populate_wm_prog_key(devinfo
, pipeline
->subpass
,
992 info
->pMultisampleState
,
993 &stages
[stage
].key
.wm
);
996 unreachable("Invalid graphics shader stage");
999 stages
[stage
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1000 stages
[stage
].feedback
.flags
|= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
1003 if (pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
)
1004 pipeline
->active_stages
|= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
1006 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1008 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1010 unsigned char sha1
[20];
1011 anv_pipeline_hash_graphics(pipeline
, layout
, stages
, sha1
);
1014 unsigned cache_hits
= 0;
1015 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1016 if (!stages
[s
].entrypoint
)
1019 int64_t stage_start
= os_time_get_nano();
1021 stages
[s
].cache_key
.stage
= s
;
1022 memcpy(stages
[s
].cache_key
.sha1
, sha1
, sizeof(sha1
));
1025 struct anv_shader_bin
*bin
=
1026 anv_device_search_for_kernel(pipeline
->device
, cache
,
1027 &stages
[s
].cache_key
,
1028 sizeof(stages
[s
].cache_key
), &cache_hit
);
1031 pipeline
->shaders
[s
] = bin
;
1036 stages
[s
].feedback
.flags
|=
1037 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1039 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1042 if (found
== __builtin_popcount(pipeline
->active_stages
)) {
1043 if (cache_hits
== found
) {
1044 pipeline_feedback
.flags
|=
1045 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1047 /* We found all our shaders in the cache. We're done. */
1049 } else if (found
> 0) {
1050 /* We found some but not all of our shaders. This shouldn't happen
1051 * most of the time but it can if we have a partially populated
1054 assert(found
< __builtin_popcount(pipeline
->active_stages
));
1056 vk_debug_report(&pipeline
->device
->instance
->debug_report_callbacks
,
1057 VK_DEBUG_REPORT_WARNING_BIT_EXT
|
1058 VK_DEBUG_REPORT_PERFORMANCE_WARNING_BIT_EXT
,
1059 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT
,
1060 (uint64_t)(uintptr_t)cache
,
1062 "Found a partial pipeline in the cache. This is "
1063 "most likely caused by an incomplete pipeline cache "
1064 "import or export");
1066 /* We're going to have to recompile anyway, so just throw away our
1067 * references to the shaders in the cache. We'll get them out of the
1068 * cache again as part of the compilation process.
1070 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1071 stages
[s
].feedback
.flags
= 0;
1072 if (pipeline
->shaders
[s
]) {
1073 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1074 pipeline
->shaders
[s
] = NULL
;
1079 void *pipeline_ctx
= ralloc_context(NULL
);
1081 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1082 if (!stages
[s
].entrypoint
)
1085 int64_t stage_start
= os_time_get_nano();
1087 assert(stages
[s
].stage
== s
);
1088 assert(pipeline
->shaders
[s
] == NULL
);
1090 stages
[s
].bind_map
= (struct anv_pipeline_bind_map
) {
1091 .surface_to_descriptor
= stages
[s
].surface_to_descriptor
,
1092 .sampler_to_descriptor
= stages
[s
].sampler_to_descriptor
1095 stages
[s
].nir
= anv_pipeline_stage_get_nir(pipeline
, cache
,
1098 if (stages
[s
].nir
== NULL
) {
1099 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1103 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1106 /* Walk backwards to link */
1107 struct anv_pipeline_stage
*next_stage
= NULL
;
1108 for (int s
= MESA_SHADER_STAGES
- 1; s
>= 0; s
--) {
1109 if (!stages
[s
].entrypoint
)
1113 case MESA_SHADER_VERTEX
:
1114 anv_pipeline_link_vs(compiler
, &stages
[s
], next_stage
);
1116 case MESA_SHADER_TESS_CTRL
:
1117 anv_pipeline_link_tcs(compiler
, &stages
[s
], next_stage
);
1119 case MESA_SHADER_TESS_EVAL
:
1120 anv_pipeline_link_tes(compiler
, &stages
[s
], next_stage
);
1122 case MESA_SHADER_GEOMETRY
:
1123 anv_pipeline_link_gs(compiler
, &stages
[s
], next_stage
);
1125 case MESA_SHADER_FRAGMENT
:
1126 anv_pipeline_link_fs(compiler
, &stages
[s
]);
1129 unreachable("Invalid graphics shader stage");
1132 next_stage
= &stages
[s
];
1135 struct anv_pipeline_stage
*prev_stage
= NULL
;
1136 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1137 if (!stages
[s
].entrypoint
)
1140 int64_t stage_start
= os_time_get_nano();
1142 void *stage_ctx
= ralloc_context(NULL
);
1144 nir_xfb_info
*xfb_info
= NULL
;
1145 if (s
== MESA_SHADER_VERTEX
||
1146 s
== MESA_SHADER_TESS_EVAL
||
1147 s
== MESA_SHADER_GEOMETRY
)
1148 xfb_info
= nir_gather_xfb_info(stages
[s
].nir
, stage_ctx
);
1150 anv_pipeline_lower_nir(pipeline
, stage_ctx
, &stages
[s
], layout
);
1152 const unsigned *code
;
1154 case MESA_SHADER_VERTEX
:
1155 code
= anv_pipeline_compile_vs(compiler
, stage_ctx
, pipeline
->device
,
1158 case MESA_SHADER_TESS_CTRL
:
1159 code
= anv_pipeline_compile_tcs(compiler
, stage_ctx
, pipeline
->device
,
1160 &stages
[s
], prev_stage
);
1162 case MESA_SHADER_TESS_EVAL
:
1163 code
= anv_pipeline_compile_tes(compiler
, stage_ctx
, pipeline
->device
,
1164 &stages
[s
], prev_stage
);
1166 case MESA_SHADER_GEOMETRY
:
1167 code
= anv_pipeline_compile_gs(compiler
, stage_ctx
, pipeline
->device
,
1168 &stages
[s
], prev_stage
);
1170 case MESA_SHADER_FRAGMENT
:
1171 code
= anv_pipeline_compile_fs(compiler
, stage_ctx
, pipeline
->device
,
1172 &stages
[s
], prev_stage
);
1175 unreachable("Invalid graphics shader stage");
1178 ralloc_free(stage_ctx
);
1179 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1183 struct anv_shader_bin
*bin
=
1184 anv_device_upload_kernel(pipeline
->device
, cache
,
1185 &stages
[s
].cache_key
,
1186 sizeof(stages
[s
].cache_key
),
1187 code
, stages
[s
].prog_data
.base
.program_size
,
1188 stages
[s
].nir
->constant_data
,
1189 stages
[s
].nir
->constant_data_size
,
1190 &stages
[s
].prog_data
.base
,
1191 brw_prog_data_size(s
),
1192 xfb_info
, &stages
[s
].bind_map
);
1194 ralloc_free(stage_ctx
);
1195 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1199 pipeline
->shaders
[s
] = bin
;
1200 ralloc_free(stage_ctx
);
1202 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1204 prev_stage
= &stages
[s
];
1207 ralloc_free(pipeline_ctx
);
1211 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
] &&
1212 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->prog_data
->program_size
== 0) {
1213 /* This can happen if we decided to implicitly disable the fragment
1214 * shader. See anv_pipeline_compile_fs().
1216 anv_shader_bin_unref(pipeline
->device
,
1217 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
1218 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] = NULL
;
1219 pipeline
->active_stages
&= ~VK_SHADER_STAGE_FRAGMENT_BIT
;
1222 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1224 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1225 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1226 if (create_feedback
) {
1227 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1229 assert(info
->stageCount
== create_feedback
->pipelineStageCreationFeedbackCount
);
1230 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1231 gl_shader_stage s
= vk_to_mesa_shader_stage(info
->pStages
[i
].stage
);
1232 create_feedback
->pPipelineStageCreationFeedbacks
[i
] = stages
[s
].feedback
;
1239 ralloc_free(pipeline_ctx
);
1241 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1242 if (pipeline
->shaders
[s
])
1243 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1250 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1251 struct anv_pipeline_cache
*cache
,
1252 const VkComputePipelineCreateInfo
*info
,
1253 const struct anv_shader_module
*module
,
1254 const char *entrypoint
,
1255 const VkSpecializationInfo
*spec_info
)
1257 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1258 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1260 int64_t pipeline_start
= os_time_get_nano();
1262 const struct brw_compiler
*compiler
=
1263 pipeline
->device
->instance
->physicalDevice
.compiler
;
1265 struct anv_pipeline_stage stage
= {
1266 .stage
= MESA_SHADER_COMPUTE
,
1268 .entrypoint
= entrypoint
,
1269 .spec_info
= spec_info
,
1271 .stage
= MESA_SHADER_COMPUTE
,
1274 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1277 anv_pipeline_hash_shader(stage
.module
,
1279 MESA_SHADER_COMPUTE
,
1283 struct anv_shader_bin
*bin
= NULL
;
1285 populate_cs_prog_key(&pipeline
->device
->info
, &stage
.key
.cs
);
1287 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1289 anv_pipeline_hash_compute(pipeline
, layout
, &stage
, stage
.cache_key
.sha1
);
1291 bin
= anv_device_search_for_kernel(pipeline
->device
, cache
, &stage
.cache_key
,
1292 sizeof(stage
.cache_key
), &cache_hit
);
1295 int64_t stage_start
= os_time_get_nano();
1297 stage
.bind_map
= (struct anv_pipeline_bind_map
) {
1298 .surface_to_descriptor
= stage
.surface_to_descriptor
,
1299 .sampler_to_descriptor
= stage
.sampler_to_descriptor
1302 /* Set up a binding for the gl_NumWorkGroups */
1303 stage
.bind_map
.surface_count
= 1;
1304 stage
.bind_map
.surface_to_descriptor
[0] = (struct anv_pipeline_binding
) {
1305 .set
= ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
,
1308 void *mem_ctx
= ralloc_context(NULL
);
1310 stage
.nir
= anv_pipeline_stage_get_nir(pipeline
, cache
, mem_ctx
, &stage
);
1311 if (stage
.nir
== NULL
) {
1312 ralloc_free(mem_ctx
);
1313 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1316 anv_pipeline_lower_nir(pipeline
, mem_ctx
, &stage
, layout
);
1318 NIR_PASS_V(stage
.nir
, anv_nir_add_base_work_group_id
,
1319 &stage
.prog_data
.cs
);
1321 const unsigned *shader_code
=
1322 brw_compile_cs(compiler
, pipeline
->device
, mem_ctx
, &stage
.key
.cs
,
1323 &stage
.prog_data
.cs
, stage
.nir
, -1, NULL
);
1324 if (shader_code
== NULL
) {
1325 ralloc_free(mem_ctx
);
1326 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1329 const unsigned code_size
= stage
.prog_data
.base
.program_size
;
1330 bin
= anv_device_upload_kernel(pipeline
->device
, cache
,
1331 &stage
.cache_key
, sizeof(stage
.cache_key
),
1332 shader_code
, code_size
,
1333 stage
.nir
->constant_data
,
1334 stage
.nir
->constant_data_size
,
1335 &stage
.prog_data
.base
,
1336 sizeof(stage
.prog_data
.cs
),
1337 NULL
, &stage
.bind_map
);
1339 ralloc_free(mem_ctx
);
1340 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1343 ralloc_free(mem_ctx
);
1345 stage
.feedback
.duration
= os_time_get_nano() - stage_start
;
1349 stage
.feedback
.flags
|=
1350 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1351 pipeline_feedback
.flags
|=
1352 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1354 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1356 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1357 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1358 if (create_feedback
) {
1359 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1361 assert(create_feedback
->pipelineStageCreationFeedbackCount
== 1);
1362 create_feedback
->pPipelineStageCreationFeedbacks
[0] = stage
.feedback
;
1365 pipeline
->active_stages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1366 pipeline
->shaders
[MESA_SHADER_COMPUTE
] = bin
;
1372 * Copy pipeline state not marked as dynamic.
1373 * Dynamic state is pipeline state which hasn't been provided at pipeline
1374 * creation time, but is dynamically provided afterwards using various
1375 * vkCmdSet* functions.
1377 * The set of state considered "non_dynamic" is determined by the pieces of
1378 * state that have their corresponding VkDynamicState enums omitted from
1379 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1381 * @param[out] pipeline Destination non_dynamic state.
1382 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1385 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
1386 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1388 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
1389 struct anv_subpass
*subpass
= pipeline
->subpass
;
1391 pipeline
->dynamic_state
= default_dynamic_state
;
1393 if (pCreateInfo
->pDynamicState
) {
1394 /* Remove all of the states that are marked as dynamic */
1395 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1396 for (uint32_t s
= 0; s
< count
; s
++)
1397 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1400 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1402 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1404 * pViewportState is [...] NULL if the pipeline
1405 * has rasterization disabled.
1407 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1408 assert(pCreateInfo
->pViewportState
);
1410 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1411 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
1412 typed_memcpy(dynamic
->viewport
.viewports
,
1413 pCreateInfo
->pViewportState
->pViewports
,
1414 pCreateInfo
->pViewportState
->viewportCount
);
1417 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1418 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
1419 typed_memcpy(dynamic
->scissor
.scissors
,
1420 pCreateInfo
->pViewportState
->pScissors
,
1421 pCreateInfo
->pViewportState
->scissorCount
);
1425 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1426 assert(pCreateInfo
->pRasterizationState
);
1427 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1430 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1431 assert(pCreateInfo
->pRasterizationState
);
1432 dynamic
->depth_bias
.bias
=
1433 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1434 dynamic
->depth_bias
.clamp
=
1435 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1436 dynamic
->depth_bias
.slope
=
1437 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1440 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1442 * pColorBlendState is [...] NULL if the pipeline has rasterization
1443 * disabled or if the subpass of the render pass the pipeline is
1444 * created against does not use any color attachments.
1446 bool uses_color_att
= false;
1447 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1448 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1449 uses_color_att
= true;
1454 if (uses_color_att
&&
1455 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1456 assert(pCreateInfo
->pColorBlendState
);
1458 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
1459 typed_memcpy(dynamic
->blend_constants
,
1460 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1463 /* If there is no depthstencil attachment, then don't read
1464 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1465 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1466 * no need to override the depthstencil defaults in
1467 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1469 * Section 9.2 of the Vulkan 1.0.15 spec says:
1471 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1472 * disabled or if the subpass of the render pass the pipeline is created
1473 * against does not use a depth/stencil attachment.
1475 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1476 subpass
->depth_stencil_attachment
) {
1477 assert(pCreateInfo
->pDepthStencilState
);
1479 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1480 dynamic
->depth_bounds
.min
=
1481 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1482 dynamic
->depth_bounds
.max
=
1483 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1486 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1487 dynamic
->stencil_compare_mask
.front
=
1488 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1489 dynamic
->stencil_compare_mask
.back
=
1490 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1493 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1494 dynamic
->stencil_write_mask
.front
=
1495 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1496 dynamic
->stencil_write_mask
.back
=
1497 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1500 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1501 dynamic
->stencil_reference
.front
=
1502 pCreateInfo
->pDepthStencilState
->front
.reference
;
1503 dynamic
->stencil_reference
.back
=
1504 pCreateInfo
->pDepthStencilState
->back
.reference
;
1508 pipeline
->dynamic_state_mask
= states
;
1512 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1515 struct anv_render_pass
*renderpass
= NULL
;
1516 struct anv_subpass
*subpass
= NULL
;
1518 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1519 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1521 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1523 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1526 assert(info
->subpass
< renderpass
->subpass_count
);
1527 subpass
= &renderpass
->subpasses
[info
->subpass
];
1529 assert(info
->stageCount
>= 1);
1530 assert(info
->pVertexInputState
);
1531 assert(info
->pInputAssemblyState
);
1532 assert(info
->pRasterizationState
);
1533 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1534 assert(info
->pViewportState
);
1535 assert(info
->pMultisampleState
);
1537 if (subpass
&& subpass
->depth_stencil_attachment
)
1538 assert(info
->pDepthStencilState
);
1540 if (subpass
&& subpass
->color_count
> 0) {
1541 bool all_color_unused
= true;
1542 for (int i
= 0; i
< subpass
->color_count
; i
++) {
1543 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
1544 all_color_unused
= false;
1546 /* pColorBlendState is ignored if the pipeline has rasterization
1547 * disabled or if the subpass of the render pass the pipeline is
1548 * created against does not use any color attachments.
1550 assert(info
->pColorBlendState
|| all_color_unused
);
1554 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1555 switch (info
->pStages
[i
].stage
) {
1556 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1557 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1558 assert(info
->pTessellationState
);
1568 * Calculate the desired L3 partitioning based on the current state of the
1569 * pipeline. For now this simply returns the conservative defaults calculated
1570 * by get_default_l3_weights(), but we could probably do better by gathering
1571 * more statistics from the pipeline state (e.g. guess of expected URB usage
1572 * and bound surfaces), or by using feed-back from performance counters.
1575 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1577 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1579 const struct gen_l3_weights w
=
1580 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
1582 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
1583 pipeline
->urb
.total_size
=
1584 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
1588 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1589 struct anv_device
*device
,
1590 struct anv_pipeline_cache
*cache
,
1591 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1592 const VkAllocationCallbacks
*alloc
)
1596 anv_pipeline_validate_create_info(pCreateInfo
);
1599 alloc
= &device
->alloc
;
1601 pipeline
->device
= device
;
1603 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, pCreateInfo
->renderPass
);
1604 assert(pCreateInfo
->subpass
< render_pass
->subpass_count
);
1605 pipeline
->subpass
= &render_pass
->subpasses
[pCreateInfo
->subpass
];
1607 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1608 if (result
!= VK_SUCCESS
)
1611 pipeline
->batch
.alloc
= alloc
;
1612 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1613 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1614 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1615 pipeline
->batch
.status
= VK_SUCCESS
;
1617 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1618 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1619 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1621 /* Previously we enabled depth clipping when !depthClampEnable.
1622 * DepthClipStateCreateInfo now makes depth clipping explicit so if the
1623 * clipping info is available, use its enable value to determine clipping,
1624 * otherwise fallback to the previous !depthClampEnable logic.
1626 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*clip_info
=
1627 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1628 PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
1629 pipeline
->depth_clip_enable
= clip_info
? clip_info
->depthClipEnable
: !pipeline
->depth_clamp_enable
;
1631 pipeline
->sample_shading_enable
= pCreateInfo
->pMultisampleState
&&
1632 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
1634 pipeline
->needs_data_cache
= false;
1636 /* When we free the pipeline, we detect stages based on the NULL status
1637 * of various prog_data pointers. Make them NULL by default.
1639 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1641 result
= anv_pipeline_compile_graphics(pipeline
, cache
, pCreateInfo
);
1642 if (result
!= VK_SUCCESS
) {
1643 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);
1647 assert(pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1649 anv_pipeline_setup_l3_config(pipeline
, false);
1651 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1652 pCreateInfo
->pVertexInputState
;
1654 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1656 pipeline
->vb_used
= 0;
1657 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1658 const VkVertexInputAttributeDescription
*desc
=
1659 &vi_info
->pVertexAttributeDescriptions
[i
];
1661 if (inputs_read
& (1ull << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1662 pipeline
->vb_used
|= 1 << desc
->binding
;
1665 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1666 const VkVertexInputBindingDescription
*desc
=
1667 &vi_info
->pVertexBindingDescriptions
[i
];
1669 pipeline
->vb
[desc
->binding
].stride
= desc
->stride
;
1671 /* Step rate is programmed per vertex element (attribute), not
1672 * binding. Set up a map of which bindings step per instance, for
1673 * reference by vertex element setup. */
1674 switch (desc
->inputRate
) {
1676 case VK_VERTEX_INPUT_RATE_VERTEX
:
1677 pipeline
->vb
[desc
->binding
].instanced
= false;
1679 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1680 pipeline
->vb
[desc
->binding
].instanced
= true;
1684 pipeline
->vb
[desc
->binding
].instance_divisor
= 1;
1687 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*vi_div_state
=
1688 vk_find_struct_const(vi_info
->pNext
,
1689 PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
1691 for (uint32_t i
= 0; i
< vi_div_state
->vertexBindingDivisorCount
; i
++) {
1692 const VkVertexInputBindingDivisorDescriptionEXT
*desc
=
1693 &vi_div_state
->pVertexBindingDivisors
[i
];
1695 pipeline
->vb
[desc
->binding
].instance_divisor
= desc
->divisor
;
1699 /* Our implementation of VK_KHR_multiview uses instancing to draw the
1700 * different views. If the client asks for instancing, we need to multiply
1701 * the instance divisor by the number of views ensure that we repeat the
1702 * client's per-instance data once for each view.
1704 if (pipeline
->subpass
->view_mask
) {
1705 const uint32_t view_count
= anv_subpass_view_count(pipeline
->subpass
);
1706 for (uint32_t vb
= 0; vb
< MAX_VBS
; vb
++) {
1707 if (pipeline
->vb
[vb
].instanced
)
1708 pipeline
->vb
[vb
].instance_divisor
*= view_count
;
1712 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1713 pCreateInfo
->pInputAssemblyState
;
1714 const VkPipelineTessellationStateCreateInfo
*tess_info
=
1715 pCreateInfo
->pTessellationState
;
1716 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1718 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1719 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
1721 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];