2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "anv_private.h"
34 #include "nir/spirv/nir_spirv.h"
36 /* Needed for SWIZZLE macros */
37 #include "program/prog_instruction.h"
41 VkResult
anv_CreateShaderModule(
43 const VkShaderModuleCreateInfo
* pCreateInfo
,
44 const VkAllocationCallbacks
* pAllocator
,
45 VkShaderModule
* pShaderModule
)
47 ANV_FROM_HANDLE(anv_device
, device
, _device
);
48 struct anv_shader_module
*module
;
50 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
51 assert(pCreateInfo
->flags
== 0);
53 module
= anv_alloc2(&device
->alloc
, pAllocator
,
54 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
55 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
57 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
60 module
->size
= pCreateInfo
->codeSize
;
61 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
63 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
65 *pShaderModule
= anv_shader_module_to_handle(module
);
70 void anv_DestroyShaderModule(
72 VkShaderModule _module
,
73 const VkAllocationCallbacks
* pAllocator
)
75 ANV_FROM_HANDLE(anv_device
, device
, _device
);
76 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
78 anv_free2(&device
->alloc
, pAllocator
, module
);
81 #define SPIR_V_MAGIC_NUMBER 0x07230203
83 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
84 * we can't do that yet because we don't have the ability to copy nir.
87 anv_shader_compile_to_nir(struct anv_device
*device
,
88 struct anv_shader_module
*module
,
89 const char *entrypoint_name
,
90 gl_shader_stage stage
,
91 const VkSpecializationInfo
*spec_info
)
93 if (strcmp(entrypoint_name
, "main") != 0) {
94 anv_finishme("Multiple shaders per module not really supported");
97 const struct brw_compiler
*compiler
=
98 device
->instance
->physicalDevice
.compiler
;
99 const nir_shader_compiler_options
*nir_options
=
100 compiler
->glsl_compiler_options
[stage
].NirOptions
;
103 nir_function
*entry_point
;
105 /* Some things such as our meta clear/blit code will give us a NIR
106 * shader directly. In that case, we just ignore the SPIR-V entirely
107 * and just use the NIR shader */
109 nir
->options
= nir_options
;
110 nir_validate_shader(nir
);
112 assert(exec_list_length(&nir
->functions
) == 1);
113 struct exec_node
*node
= exec_list_get_head(&nir
->functions
);
114 entry_point
= exec_node_data(nir_function
, node
, node
);
116 uint32_t *spirv
= (uint32_t *) module
->data
;
117 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
118 assert(module
->size
% 4 == 0);
120 uint32_t num_spec_entries
= 0;
121 struct nir_spirv_specialization
*spec_entries
= NULL
;
122 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
123 num_spec_entries
= spec_info
->mapEntryCount
;
124 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
125 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
126 const uint32_t *data
=
127 spec_info
->pData
+ spec_info
->pMapEntries
[i
].offset
;
128 assert((const void *)(data
+ 1) <=
129 spec_info
->pData
+ spec_info
->dataSize
);
131 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
132 spec_entries
[i
].data
= *data
;
136 entry_point
= spirv_to_nir(spirv
, module
->size
/ 4,
137 spec_entries
, num_spec_entries
,
138 stage
, entrypoint_name
, nir_options
);
139 nir
= entry_point
->shader
;
140 assert(nir
->stage
== stage
);
141 nir_validate_shader(nir
);
145 nir_lower_returns(nir
);
146 nir_validate_shader(nir
);
148 nir_inline_functions(nir
);
149 nir_validate_shader(nir
);
151 /* Pick off the single entrypoint that we want */
152 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
153 if (func
!= entry_point
)
154 exec_node_remove(&func
->node
);
156 assert(exec_list_length(&nir
->functions
) == 1);
157 entry_point
->name
= ralloc_strdup(entry_point
, "main");
159 nir_remove_dead_variables(nir
, nir_var_shader_in
);
160 nir_remove_dead_variables(nir
, nir_var_shader_out
);
161 nir_remove_dead_variables(nir
, nir_var_system_value
);
162 nir_validate_shader(nir
);
164 nir_lower_outputs_to_temporaries(entry_point
->shader
, entry_point
);
166 nir_lower_system_values(nir
);
167 nir_validate_shader(nir
);
170 /* Vulkan uses the separate-shader linking model */
171 nir
->info
.separate_shader
= true;
173 nir
= brw_preprocess_nir(nir
, compiler
->scalar_stage
[stage
]);
175 nir_shader_gather_info(nir
, entry_point
->impl
);
177 uint32_t indirect_mask
= 0;
178 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectInput
)
179 indirect_mask
|= (1 << nir_var_shader_in
);
180 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectTemp
)
181 indirect_mask
|= 1 << nir_var_local
;
183 nir_lower_indirect_derefs(nir
, indirect_mask
);
188 void anv_DestroyPipeline(
190 VkPipeline _pipeline
,
191 const VkAllocationCallbacks
* pAllocator
)
193 ANV_FROM_HANDLE(anv_device
, device
, _device
);
194 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
196 anv_reloc_list_finish(&pipeline
->batch_relocs
,
197 pAllocator
? pAllocator
: &device
->alloc
);
198 if (pipeline
->blend_state
.map
)
199 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
200 anv_free2(&device
->alloc
, pAllocator
, pipeline
);
203 static const uint32_t vk_to_gen_primitive_type
[] = {
204 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
205 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
206 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
207 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
208 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
209 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
210 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
211 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
212 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
213 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
214 /* [VK_PRIMITIVE_TOPOLOGY_PATCH_LIST] = _3DPRIM_PATCHLIST_1 */
218 populate_sampler_prog_key(const struct brw_device_info
*devinfo
,
219 struct brw_sampler_prog_key_data
*key
)
221 /* XXX: Handle texture swizzle on HSW- */
222 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
223 /* Assume color sampler, no swizzling. (Works for BDW+) */
224 key
->swizzles
[i
] = SWIZZLE_XYZW
;
229 populate_vs_prog_key(const struct brw_device_info
*devinfo
,
230 struct brw_vs_prog_key
*key
)
232 memset(key
, 0, sizeof(*key
));
234 populate_sampler_prog_key(devinfo
, &key
->tex
);
236 /* XXX: Handle vertex input work-arounds */
238 /* XXX: Handle sampler_prog_key */
242 populate_gs_prog_key(const struct brw_device_info
*devinfo
,
243 struct brw_gs_prog_key
*key
)
245 memset(key
, 0, sizeof(*key
));
247 populate_sampler_prog_key(devinfo
, &key
->tex
);
251 populate_wm_prog_key(const struct brw_device_info
*devinfo
,
252 const VkGraphicsPipelineCreateInfo
*info
,
253 const struct anv_graphics_pipeline_create_info
*extra
,
254 struct brw_wm_prog_key
*key
)
256 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, info
->renderPass
);
258 memset(key
, 0, sizeof(*key
));
260 populate_sampler_prog_key(devinfo
, &key
->tex
);
262 /* TODO: Fill out key->input_slots_valid */
264 /* Vulkan doesn't specify a default */
265 key
->high_quality_derivatives
= false;
267 /* XXX Vulkan doesn't appear to specify */
268 key
->clamp_fragment_color
= false;
270 /* Vulkan always specifies upper-left coordinates */
271 key
->drawable_height
= 0;
272 key
->render_to_fbo
= false;
274 if (extra
&& extra
->color_attachment_count
>= 0) {
275 key
->nr_color_regions
= extra
->color_attachment_count
;
277 key
->nr_color_regions
=
278 render_pass
->subpasses
[info
->subpass
].color_count
;
281 key
->replicate_alpha
= key
->nr_color_regions
> 1 &&
282 info
->pMultisampleState
&&
283 info
->pMultisampleState
->alphaToCoverageEnable
;
285 if (info
->pMultisampleState
&& info
->pMultisampleState
->rasterizationSamples
> 1) {
286 /* We should probably pull this out of the shader, but it's fairly
287 * harmless to compute it and then let dead-code take care of it.
289 key
->persample_shading
= info
->pMultisampleState
->sampleShadingEnable
;
290 if (key
->persample_shading
)
291 key
->persample_2x
= info
->pMultisampleState
->rasterizationSamples
== 2;
293 key
->compute_pos_offset
= info
->pMultisampleState
->sampleShadingEnable
;
294 key
->compute_sample_id
= info
->pMultisampleState
->sampleShadingEnable
;
299 populate_cs_prog_key(const struct brw_device_info
*devinfo
,
300 struct brw_cs_prog_key
*key
)
302 memset(key
, 0, sizeof(*key
));
304 populate_sampler_prog_key(devinfo
, &key
->tex
);
308 anv_pipeline_compile(struct anv_pipeline
*pipeline
,
309 struct anv_shader_module
*module
,
310 const char *entrypoint
,
311 gl_shader_stage stage
,
312 const VkSpecializationInfo
*spec_info
,
313 struct brw_stage_prog_data
*prog_data
,
314 struct anv_pipeline_bind_map
*map
)
316 const struct brw_compiler
*compiler
=
317 pipeline
->device
->instance
->physicalDevice
.compiler
;
319 nir_shader
*nir
= anv_shader_compile_to_nir(pipeline
->device
,
320 module
, entrypoint
, stage
,
325 anv_nir_lower_push_constants(nir
, compiler
->scalar_stage
[stage
]);
327 /* Figure out the number of parameters */
328 prog_data
->nr_params
= 0;
330 if (nir
->num_uniforms
> 0) {
331 /* If the shader uses any push constants at all, we'll just give
332 * them the maximum possible number
334 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
337 if (pipeline
->layout
&& pipeline
->layout
->stage
[stage
].has_dynamic_offsets
)
338 prog_data
->nr_params
+= MAX_DYNAMIC_BUFFERS
* 2;
340 if (nir
->info
.num_images
> 0)
341 prog_data
->nr_params
+= nir
->info
.num_images
* BRW_IMAGE_PARAM_SIZE
;
343 if (prog_data
->nr_params
> 0) {
344 /* XXX: I think we're leaking this */
345 prog_data
->param
= (const union gl_constant_value
**)
346 malloc(prog_data
->nr_params
* sizeof(union gl_constant_value
*));
348 /* We now set the param values to be offsets into a
349 * anv_push_constant_data structure. Since the compiler doesn't
350 * actually dereference any of the gl_constant_value pointers in the
351 * params array, it doesn't really matter what we put here.
353 struct anv_push_constants
*null_data
= NULL
;
354 if (nir
->num_uniforms
> 0) {
355 /* Fill out the push constants section of the param array */
356 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++)
357 prog_data
->param
[i
] = (const union gl_constant_value
*)
358 &null_data
->client_data
[i
* sizeof(float)];
362 /* Set up dynamic offsets */
363 anv_nir_apply_dynamic_offsets(pipeline
, nir
, prog_data
);
365 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
366 if (pipeline
->layout
)
367 anv_nir_apply_pipeline_layout(pipeline
, nir
, prog_data
, map
);
369 /* All binding table offsets provided by apply_pipeline_layout() are
370 * relative to the start of the bindint table (plus MAX_RTS for VS).
374 case MESA_SHADER_FRAGMENT
:
377 case MESA_SHADER_COMPUTE
:
384 prog_data
->binding_table
.size_bytes
= 0;
385 prog_data
->binding_table
.texture_start
= bias
;
386 prog_data
->binding_table
.ubo_start
= bias
;
387 prog_data
->binding_table
.ssbo_start
= bias
;
388 prog_data
->binding_table
.image_start
= bias
;
390 /* Finish the optimization and compilation process */
391 if (nir
->stage
== MESA_SHADER_COMPUTE
)
392 brw_nir_lower_shared(nir
);
394 /* nir_lower_io will only handle the push constants; we need to set this
395 * to the full number of possible uniforms.
397 nir
->num_uniforms
= prog_data
->nr_params
* 4;
403 anv_pipeline_add_compiled_stage(struct anv_pipeline
*pipeline
,
404 gl_shader_stage stage
,
405 const struct brw_stage_prog_data
*prog_data
,
406 struct anv_pipeline_bind_map
*map
)
408 struct brw_device_info
*devinfo
= &pipeline
->device
->info
;
409 uint32_t max_threads
[] = {
410 [MESA_SHADER_VERTEX
] = devinfo
->max_vs_threads
,
411 [MESA_SHADER_TESS_CTRL
] = devinfo
->max_hs_threads
,
412 [MESA_SHADER_TESS_EVAL
] = devinfo
->max_ds_threads
,
413 [MESA_SHADER_GEOMETRY
] = devinfo
->max_gs_threads
,
414 [MESA_SHADER_FRAGMENT
] = devinfo
->max_wm_threads
,
415 [MESA_SHADER_COMPUTE
] = devinfo
->max_cs_threads
,
418 pipeline
->prog_data
[stage
] = prog_data
;
419 pipeline
->active_stages
|= mesa_to_vk_shader_stage(stage
);
420 pipeline
->scratch_start
[stage
] = pipeline
->total_scratch
;
421 pipeline
->total_scratch
=
422 align_u32(pipeline
->total_scratch
, 1024) +
423 prog_data
->total_scratch
* max_threads
[stage
];
424 pipeline
->bindings
[stage
] = *map
;
428 anv_pipeline_compile_vs(struct anv_pipeline
*pipeline
,
429 struct anv_pipeline_cache
*cache
,
430 const VkGraphicsPipelineCreateInfo
*info
,
431 struct anv_shader_module
*module
,
432 const char *entrypoint
,
433 const VkSpecializationInfo
*spec_info
)
435 const struct brw_compiler
*compiler
=
436 pipeline
->device
->instance
->physicalDevice
.compiler
;
437 const struct brw_stage_prog_data
*stage_prog_data
;
438 struct anv_pipeline_bind_map map
;
439 struct brw_vs_prog_key key
;
440 uint32_t kernel
= NO_KERNEL
;
441 unsigned char sha1
[20];
443 populate_vs_prog_key(&pipeline
->device
->info
, &key
);
445 if (module
->size
> 0) {
446 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
, spec_info
);
447 kernel
= anv_pipeline_cache_search(cache
, sha1
, &stage_prog_data
, &map
);
450 if (kernel
== NO_KERNEL
) {
451 struct brw_vs_prog_data prog_data
= { 0, };
452 struct anv_pipeline_binding surface_to_descriptor
[256];
453 struct anv_pipeline_binding sampler_to_descriptor
[256];
455 map
= (struct anv_pipeline_bind_map
) {
456 .surface_to_descriptor
= surface_to_descriptor
,
457 .sampler_to_descriptor
= sampler_to_descriptor
460 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
461 MESA_SHADER_VERTEX
, spec_info
,
462 &prog_data
.base
.base
, &map
);
464 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
466 void *mem_ctx
= ralloc_context(NULL
);
468 if (module
->nir
== NULL
)
469 ralloc_steal(mem_ctx
, nir
);
471 prog_data
.inputs_read
= nir
->info
.inputs_read
;
473 brw_compute_vue_map(&pipeline
->device
->info
,
474 &prog_data
.base
.vue_map
,
475 nir
->info
.outputs_written
,
476 nir
->info
.separate_shader
);
479 const unsigned *shader_code
=
480 brw_compile_vs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
481 NULL
, false, -1, &code_size
, NULL
);
482 if (shader_code
== NULL
) {
483 ralloc_free(mem_ctx
);
484 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
487 stage_prog_data
= &prog_data
.base
.base
;
488 kernel
= anv_pipeline_cache_upload_kernel(cache
,
489 module
->size
> 0 ? sha1
: NULL
,
490 shader_code
, code_size
,
491 &stage_prog_data
, sizeof(prog_data
),
493 ralloc_free(mem_ctx
);
496 const struct brw_vs_prog_data
*vs_prog_data
=
497 (const struct brw_vs_prog_data
*) stage_prog_data
;
499 if (vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
) {
500 pipeline
->vs_simd8
= kernel
;
501 pipeline
->vs_vec4
= NO_KERNEL
;
503 pipeline
->vs_simd8
= NO_KERNEL
;
504 pipeline
->vs_vec4
= kernel
;
507 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_VERTEX
,
508 stage_prog_data
, &map
);
514 anv_pipeline_compile_gs(struct anv_pipeline
*pipeline
,
515 struct anv_pipeline_cache
*cache
,
516 const VkGraphicsPipelineCreateInfo
*info
,
517 struct anv_shader_module
*module
,
518 const char *entrypoint
,
519 const VkSpecializationInfo
*spec_info
)
521 const struct brw_compiler
*compiler
=
522 pipeline
->device
->instance
->physicalDevice
.compiler
;
523 const struct brw_stage_prog_data
*stage_prog_data
;
524 struct anv_pipeline_bind_map map
;
525 struct brw_gs_prog_key key
;
526 uint32_t kernel
= NO_KERNEL
;
527 unsigned char sha1
[20];
529 populate_gs_prog_key(&pipeline
->device
->info
, &key
);
531 if (module
->size
> 0) {
532 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
, spec_info
);
533 kernel
= anv_pipeline_cache_search(cache
, sha1
, &stage_prog_data
, &map
);
536 if (kernel
== NO_KERNEL
) {
537 struct brw_gs_prog_data prog_data
= { 0, };
538 struct anv_pipeline_binding surface_to_descriptor
[256];
539 struct anv_pipeline_binding sampler_to_descriptor
[256];
541 map
= (struct anv_pipeline_bind_map
) {
542 .surface_to_descriptor
= surface_to_descriptor
,
543 .sampler_to_descriptor
= sampler_to_descriptor
546 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
547 MESA_SHADER_GEOMETRY
, spec_info
,
548 &prog_data
.base
.base
, &map
);
550 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
552 void *mem_ctx
= ralloc_context(NULL
);
554 if (module
->nir
== NULL
)
555 ralloc_steal(mem_ctx
, nir
);
557 brw_compute_vue_map(&pipeline
->device
->info
,
558 &prog_data
.base
.vue_map
,
559 nir
->info
.outputs_written
,
560 nir
->info
.separate_shader
);
563 const unsigned *shader_code
=
564 brw_compile_gs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
565 NULL
, -1, &code_size
, NULL
);
566 if (shader_code
== NULL
) {
567 ralloc_free(mem_ctx
);
568 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
572 stage_prog_data
= &prog_data
.base
.base
;
573 kernel
= anv_pipeline_cache_upload_kernel(cache
,
574 module
->size
> 0 ? sha1
: NULL
,
575 shader_code
, code_size
,
576 &stage_prog_data
, sizeof(prog_data
),
579 ralloc_free(mem_ctx
);
582 pipeline
->gs_kernel
= kernel
;
584 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_GEOMETRY
,
585 stage_prog_data
, &map
);
591 anv_pipeline_compile_fs(struct anv_pipeline
*pipeline
,
592 struct anv_pipeline_cache
*cache
,
593 const VkGraphicsPipelineCreateInfo
*info
,
594 const struct anv_graphics_pipeline_create_info
*extra
,
595 struct anv_shader_module
*module
,
596 const char *entrypoint
,
597 const VkSpecializationInfo
*spec_info
)
599 const struct brw_compiler
*compiler
=
600 pipeline
->device
->instance
->physicalDevice
.compiler
;
601 const struct brw_stage_prog_data
*stage_prog_data
;
602 struct anv_pipeline_bind_map map
;
603 struct brw_wm_prog_key key
;
604 uint32_t kernel
= NO_KERNEL
;
605 unsigned char sha1
[20];
607 populate_wm_prog_key(&pipeline
->device
->info
, info
, extra
, &key
);
609 if (pipeline
->use_repclear
)
610 key
.nr_color_regions
= 1;
612 if (module
->size
> 0) {
613 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
, spec_info
);
614 kernel
= anv_pipeline_cache_search(cache
, sha1
, &stage_prog_data
, &map
);
617 if (kernel
== NO_KERNEL
) {
618 struct brw_wm_prog_data prog_data
= { 0, };
619 struct anv_pipeline_binding surface_to_descriptor
[256];
620 struct anv_pipeline_binding sampler_to_descriptor
[256];
622 map
= (struct anv_pipeline_bind_map
) {
623 .surface_to_descriptor
= surface_to_descriptor
,
624 .sampler_to_descriptor
= sampler_to_descriptor
627 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
628 MESA_SHADER_FRAGMENT
, spec_info
,
629 &prog_data
.base
, &map
);
631 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
633 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
)->impl
;
634 nir_foreach_variable_safe(var
, &nir
->outputs
) {
635 if (var
->data
.location
< FRAG_RESULT_DATA0
)
638 unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
639 if (rt
>= key
.nr_color_regions
) {
640 var
->data
.mode
= nir_var_local
;
641 exec_node_remove(&var
->node
);
642 exec_list_push_tail(&impl
->locals
, &var
->node
);
646 void *mem_ctx
= ralloc_context(NULL
);
648 if (module
->nir
== NULL
)
649 ralloc_steal(mem_ctx
, nir
);
652 const unsigned *shader_code
=
653 brw_compile_fs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
654 NULL
, -1, -1, pipeline
->use_repclear
, &code_size
, NULL
);
655 if (shader_code
== NULL
) {
656 ralloc_free(mem_ctx
);
657 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
660 stage_prog_data
= &prog_data
.base
;
661 kernel
= anv_pipeline_cache_upload_kernel(cache
,
662 module
->size
> 0 ? sha1
: NULL
,
663 shader_code
, code_size
,
664 &stage_prog_data
, sizeof(prog_data
),
667 ralloc_free(mem_ctx
);
670 const struct brw_wm_prog_data
*wm_prog_data
=
671 (const struct brw_wm_prog_data
*) stage_prog_data
;
673 if (wm_prog_data
->no_8
)
674 pipeline
->ps_simd8
= NO_KERNEL
;
676 pipeline
->ps_simd8
= kernel
;
678 if (wm_prog_data
->no_8
|| wm_prog_data
->prog_offset_16
) {
679 pipeline
->ps_simd16
= kernel
+ wm_prog_data
->prog_offset_16
;
681 pipeline
->ps_simd16
= NO_KERNEL
;
684 pipeline
->ps_ksp2
= 0;
685 pipeline
->ps_grf_start2
= 0;
686 if (pipeline
->ps_simd8
!= NO_KERNEL
) {
687 pipeline
->ps_ksp0
= pipeline
->ps_simd8
;
688 pipeline
->ps_grf_start0
= wm_prog_data
->base
.dispatch_grf_start_reg
;
689 if (pipeline
->ps_simd16
!= NO_KERNEL
) {
690 pipeline
->ps_ksp2
= pipeline
->ps_simd16
;
691 pipeline
->ps_grf_start2
= wm_prog_data
->dispatch_grf_start_reg_16
;
693 } else if (pipeline
->ps_simd16
!= NO_KERNEL
) {
694 pipeline
->ps_ksp0
= pipeline
->ps_simd16
;
695 pipeline
->ps_grf_start0
= wm_prog_data
->dispatch_grf_start_reg_16
;
698 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_FRAGMENT
,
699 stage_prog_data
, &map
);
705 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
706 struct anv_pipeline_cache
*cache
,
707 const VkComputePipelineCreateInfo
*info
,
708 struct anv_shader_module
*module
,
709 const char *entrypoint
,
710 const VkSpecializationInfo
*spec_info
)
712 const struct brw_compiler
*compiler
=
713 pipeline
->device
->instance
->physicalDevice
.compiler
;
714 const struct brw_stage_prog_data
*stage_prog_data
;
715 struct anv_pipeline_bind_map map
;
716 struct brw_cs_prog_key key
;
717 uint32_t kernel
= NO_KERNEL
;
718 unsigned char sha1
[20];
720 populate_cs_prog_key(&pipeline
->device
->info
, &key
);
722 if (module
->size
> 0) {
723 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
, spec_info
);
724 kernel
= anv_pipeline_cache_search(cache
, sha1
, &stage_prog_data
, &map
);
727 if (module
->size
== 0 || kernel
== NO_KERNEL
) {
728 struct brw_cs_prog_data prog_data
= { 0, };
729 struct anv_pipeline_binding surface_to_descriptor
[256];
730 struct anv_pipeline_binding sampler_to_descriptor
[256];
732 map
= (struct anv_pipeline_bind_map
) {
733 .surface_to_descriptor
= surface_to_descriptor
,
734 .sampler_to_descriptor
= sampler_to_descriptor
737 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
738 MESA_SHADER_COMPUTE
, spec_info
,
739 &prog_data
.base
, &map
);
741 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
743 prog_data
.base
.total_shared
= nir
->num_shared
;
745 void *mem_ctx
= ralloc_context(NULL
);
747 if (module
->nir
== NULL
)
748 ralloc_steal(mem_ctx
, nir
);
751 const unsigned *shader_code
=
752 brw_compile_cs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
753 -1, &code_size
, NULL
);
754 if (shader_code
== NULL
) {
755 ralloc_free(mem_ctx
);
756 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
759 stage_prog_data
= &prog_data
.base
;
760 kernel
= anv_pipeline_cache_upload_kernel(cache
,
761 module
->size
> 0 ? sha1
: NULL
,
762 shader_code
, code_size
,
763 &stage_prog_data
, sizeof(prog_data
),
766 ralloc_free(mem_ctx
);
769 pipeline
->cs_simd
= kernel
;
771 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_COMPUTE
,
772 stage_prog_data
, &map
);
778 gen7_compute_urb_partition(struct anv_pipeline
*pipeline
)
780 const struct brw_device_info
*devinfo
= &pipeline
->device
->info
;
781 bool vs_present
= pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
;
782 unsigned vs_size
= vs_present
?
783 get_vs_prog_data(pipeline
)->base
.urb_entry_size
: 1;
784 unsigned vs_entry_size_bytes
= vs_size
* 64;
785 bool gs_present
= pipeline
->active_stages
& VK_SHADER_STAGE_GEOMETRY_BIT
;
786 unsigned gs_size
= gs_present
?
787 get_gs_prog_data(pipeline
)->base
.urb_entry_size
: 1;
788 unsigned gs_entry_size_bytes
= gs_size
* 64;
790 /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
792 * VS Number of URB Entries must be divisible by 8 if the VS URB Entry
793 * Allocation Size is less than 9 512-bit URB entries.
795 * Similar text exists for GS.
797 unsigned vs_granularity
= (vs_size
< 9) ? 8 : 1;
798 unsigned gs_granularity
= (gs_size
< 9) ? 8 : 1;
800 /* URB allocations must be done in 8k chunks. */
801 unsigned chunk_size_bytes
= 8192;
803 /* Determine the size of the URB in chunks. */
804 unsigned urb_chunks
= devinfo
->urb
.size
* 1024 / chunk_size_bytes
;
806 /* Reserve space for push constants */
807 unsigned push_constant_kb
;
808 if (pipeline
->device
->info
.gen
>= 8)
809 push_constant_kb
= 32;
810 else if (pipeline
->device
->info
.is_haswell
)
811 push_constant_kb
= pipeline
->device
->info
.gt
== 3 ? 32 : 16;
813 push_constant_kb
= 16;
815 unsigned push_constant_bytes
= push_constant_kb
* 1024;
816 unsigned push_constant_chunks
=
817 push_constant_bytes
/ chunk_size_bytes
;
819 /* Initially, assign each stage the minimum amount of URB space it needs,
820 * and make a note of how much additional space it "wants" (the amount of
821 * additional space it could actually make use of).
824 /* VS has a lower limit on the number of URB entries */
826 ALIGN(devinfo
->urb
.min_vs_entries
* vs_entry_size_bytes
,
827 chunk_size_bytes
) / chunk_size_bytes
;
829 ALIGN(devinfo
->urb
.max_vs_entries
* vs_entry_size_bytes
,
830 chunk_size_bytes
) / chunk_size_bytes
- vs_chunks
;
832 unsigned gs_chunks
= 0;
833 unsigned gs_wants
= 0;
835 /* There are two constraints on the minimum amount of URB space we can
838 * (1) We need room for at least 2 URB entries, since we always operate
839 * the GS in DUAL_OBJECT mode.
841 * (2) We can't allocate less than nr_gs_entries_granularity.
843 gs_chunks
= ALIGN(MAX2(gs_granularity
, 2) * gs_entry_size_bytes
,
844 chunk_size_bytes
) / chunk_size_bytes
;
846 ALIGN(devinfo
->urb
.max_gs_entries
* gs_entry_size_bytes
,
847 chunk_size_bytes
) / chunk_size_bytes
- gs_chunks
;
850 /* There should always be enough URB space to satisfy the minimum
851 * requirements of each stage.
853 unsigned total_needs
= push_constant_chunks
+ vs_chunks
+ gs_chunks
;
854 assert(total_needs
<= urb_chunks
);
856 /* Mete out remaining space (if any) in proportion to "wants". */
857 unsigned total_wants
= vs_wants
+ gs_wants
;
858 unsigned remaining_space
= urb_chunks
- total_needs
;
859 if (remaining_space
> total_wants
)
860 remaining_space
= total_wants
;
861 if (remaining_space
> 0) {
862 unsigned vs_additional
= (unsigned)
863 round(vs_wants
* (((double) remaining_space
) / total_wants
));
864 vs_chunks
+= vs_additional
;
865 remaining_space
-= vs_additional
;
866 gs_chunks
+= remaining_space
;
869 /* Sanity check that we haven't over-allocated. */
870 assert(push_constant_chunks
+ vs_chunks
+ gs_chunks
<= urb_chunks
);
872 /* Finally, compute the number of entries that can fit in the space
873 * allocated to each stage.
875 unsigned nr_vs_entries
= vs_chunks
* chunk_size_bytes
/ vs_entry_size_bytes
;
876 unsigned nr_gs_entries
= gs_chunks
* chunk_size_bytes
/ gs_entry_size_bytes
;
878 /* Since we rounded up when computing *_wants, this may be slightly more
879 * than the maximum allowed amount, so correct for that.
881 nr_vs_entries
= MIN2(nr_vs_entries
, devinfo
->urb
.max_vs_entries
);
882 nr_gs_entries
= MIN2(nr_gs_entries
, devinfo
->urb
.max_gs_entries
);
884 /* Ensure that we program a multiple of the granularity. */
885 nr_vs_entries
= ROUND_DOWN_TO(nr_vs_entries
, vs_granularity
);
886 nr_gs_entries
= ROUND_DOWN_TO(nr_gs_entries
, gs_granularity
);
888 /* Finally, sanity check to make sure we have at least the minimum number
889 * of entries needed for each stage.
891 assert(nr_vs_entries
>= devinfo
->urb
.min_vs_entries
);
893 assert(nr_gs_entries
>= 2);
895 /* Lay out the URB in the following order:
900 pipeline
->urb
.start
[MESA_SHADER_VERTEX
] = push_constant_chunks
;
901 pipeline
->urb
.size
[MESA_SHADER_VERTEX
] = vs_size
;
902 pipeline
->urb
.entries
[MESA_SHADER_VERTEX
] = nr_vs_entries
;
904 pipeline
->urb
.start
[MESA_SHADER_GEOMETRY
] = push_constant_chunks
+ vs_chunks
;
905 pipeline
->urb
.size
[MESA_SHADER_GEOMETRY
] = gs_size
;
906 pipeline
->urb
.entries
[MESA_SHADER_GEOMETRY
] = nr_gs_entries
;
908 pipeline
->urb
.start
[MESA_SHADER_TESS_CTRL
] = push_constant_chunks
;
909 pipeline
->urb
.size
[MESA_SHADER_TESS_CTRL
] = 1;
910 pipeline
->urb
.entries
[MESA_SHADER_TESS_CTRL
] = 0;
912 pipeline
->urb
.start
[MESA_SHADER_TESS_EVAL
] = push_constant_chunks
;
913 pipeline
->urb
.size
[MESA_SHADER_TESS_EVAL
] = 1;
914 pipeline
->urb
.entries
[MESA_SHADER_TESS_EVAL
] = 0;
916 const unsigned stages
=
917 _mesa_bitcount(pipeline
->active_stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
918 unsigned size_per_stage
= stages
? (push_constant_kb
/ stages
) : 0;
919 unsigned used_kb
= 0;
921 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
922 * units of 2KB. Incidentally, these are the same platforms that have
923 * 32KB worth of push constant space.
925 if (push_constant_kb
== 32)
926 size_per_stage
&= ~1u;
928 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
929 pipeline
->urb
.push_size
[i
] =
930 (pipeline
->active_stages
& (1 << i
)) ? size_per_stage
: 0;
931 used_kb
+= pipeline
->urb
.push_size
[i
];
932 assert(used_kb
<= push_constant_kb
);
935 pipeline
->urb
.push_size
[MESA_SHADER_FRAGMENT
] =
936 push_constant_kb
- used_kb
;
940 anv_pipeline_init_dynamic_state(struct anv_pipeline
*pipeline
,
941 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
943 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
944 ANV_FROM_HANDLE(anv_render_pass
, pass
, pCreateInfo
->renderPass
);
945 struct anv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
947 pipeline
->dynamic_state
= default_dynamic_state
;
949 if (pCreateInfo
->pDynamicState
) {
950 /* Remove all of the states that are marked as dynamic */
951 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
952 for (uint32_t s
= 0; s
< count
; s
++)
953 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
956 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
958 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
959 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
960 typed_memcpy(dynamic
->viewport
.viewports
,
961 pCreateInfo
->pViewportState
->pViewports
,
962 pCreateInfo
->pViewportState
->viewportCount
);
965 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
966 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
967 typed_memcpy(dynamic
->scissor
.scissors
,
968 pCreateInfo
->pViewportState
->pScissors
,
969 pCreateInfo
->pViewportState
->scissorCount
);
972 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
973 assert(pCreateInfo
->pRasterizationState
);
974 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
977 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
978 assert(pCreateInfo
->pRasterizationState
);
979 dynamic
->depth_bias
.bias
=
980 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
981 dynamic
->depth_bias
.clamp
=
982 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
983 dynamic
->depth_bias
.slope
=
984 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
987 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
)) {
988 assert(pCreateInfo
->pColorBlendState
);
989 typed_memcpy(dynamic
->blend_constants
,
990 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
993 /* If there is no depthstencil attachment, then don't read
994 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
995 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
996 * no need to override the depthstencil defaults in
997 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
999 * From the Vulkan spec (20 Oct 2015, git-aa308cb):
1001 * pDepthStencilState [...] may only be NULL if renderPass and subpass
1002 * specify a subpass that has no depth/stencil attachment.
1004 if (subpass
->depth_stencil_attachment
!= VK_ATTACHMENT_UNUSED
) {
1005 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1006 assert(pCreateInfo
->pDepthStencilState
);
1007 dynamic
->depth_bounds
.min
=
1008 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1009 dynamic
->depth_bounds
.max
=
1010 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1013 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1014 assert(pCreateInfo
->pDepthStencilState
);
1015 dynamic
->stencil_compare_mask
.front
=
1016 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1017 dynamic
->stencil_compare_mask
.back
=
1018 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1021 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1022 assert(pCreateInfo
->pDepthStencilState
);
1023 dynamic
->stencil_write_mask
.front
=
1024 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1025 dynamic
->stencil_write_mask
.back
=
1026 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1029 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1030 assert(pCreateInfo
->pDepthStencilState
);
1031 dynamic
->stencil_reference
.front
=
1032 pCreateInfo
->pDepthStencilState
->front
.reference
;
1033 dynamic
->stencil_reference
.back
=
1034 pCreateInfo
->pDepthStencilState
->back
.reference
;
1038 pipeline
->dynamic_state_mask
= states
;
1042 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1044 struct anv_render_pass
*renderpass
= NULL
;
1045 struct anv_subpass
*subpass
= NULL
;
1047 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1048 * present, as explained by the Vulkan (20 Oct 2015, git-aa308cb), Section
1049 * 4.2 Graphics Pipeline.
1051 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1053 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1056 if (renderpass
!= &anv_meta_dummy_renderpass
) {
1057 assert(info
->subpass
< renderpass
->subpass_count
);
1058 subpass
= &renderpass
->subpasses
[info
->subpass
];
1061 assert(info
->stageCount
>= 1);
1062 assert(info
->pVertexInputState
);
1063 assert(info
->pInputAssemblyState
);
1064 assert(info
->pViewportState
);
1065 assert(info
->pRasterizationState
);
1067 if (subpass
&& subpass
->depth_stencil_attachment
!= VK_ATTACHMENT_UNUSED
)
1068 assert(info
->pDepthStencilState
);
1070 if (subpass
&& subpass
->color_count
> 0)
1071 assert(info
->pColorBlendState
);
1073 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1074 switch (info
->pStages
[i
].stage
) {
1075 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1076 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1077 assert(info
->pTessellationState
);
1086 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1087 struct anv_device
*device
,
1088 struct anv_pipeline_cache
*cache
,
1089 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1090 const struct anv_graphics_pipeline_create_info
*extra
,
1091 const VkAllocationCallbacks
*alloc
)
1096 anv_pipeline_validate_create_info(pCreateInfo
);
1100 alloc
= &device
->alloc
;
1102 pipeline
->device
= device
;
1103 pipeline
->layout
= anv_pipeline_layout_from_handle(pCreateInfo
->layout
);
1105 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1106 if (result
!= VK_SUCCESS
)
1109 pipeline
->batch
.alloc
= alloc
;
1110 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1111 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1112 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1114 anv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
1116 if (pCreateInfo
->pTessellationState
)
1117 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_TESSELLATION_STATE_CREATE_INFO");
1119 pipeline
->use_repclear
= extra
&& extra
->use_repclear
;
1121 /* When we free the pipeline, we detect stages based on the NULL status
1122 * of various prog_data pointers. Make them NULL by default.
1124 memset(pipeline
->prog_data
, 0, sizeof(pipeline
->prog_data
));
1125 memset(pipeline
->scratch_start
, 0, sizeof(pipeline
->scratch_start
));
1126 memset(pipeline
->bindings
, 0, sizeof(pipeline
->bindings
));
1128 pipeline
->vs_simd8
= NO_KERNEL
;
1129 pipeline
->vs_vec4
= NO_KERNEL
;
1130 pipeline
->gs_kernel
= NO_KERNEL
;
1131 pipeline
->ps_ksp0
= NO_KERNEL
;
1133 pipeline
->active_stages
= 0;
1134 pipeline
->total_scratch
= 0;
1136 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
1137 struct anv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
1138 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
1139 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
1140 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
1141 modules
[stage
] = anv_shader_module_from_handle(pStages
[stage
]->module
);
1144 if (modules
[MESA_SHADER_VERTEX
]) {
1145 anv_pipeline_compile_vs(pipeline
, cache
, pCreateInfo
,
1146 modules
[MESA_SHADER_VERTEX
],
1147 pStages
[MESA_SHADER_VERTEX
]->pName
,
1148 pStages
[MESA_SHADER_VERTEX
]->pSpecializationInfo
);
1151 if (modules
[MESA_SHADER_GEOMETRY
]) {
1152 anv_pipeline_compile_gs(pipeline
, cache
, pCreateInfo
,
1153 modules
[MESA_SHADER_GEOMETRY
],
1154 pStages
[MESA_SHADER_GEOMETRY
]->pName
,
1155 pStages
[MESA_SHADER_GEOMETRY
]->pSpecializationInfo
);
1158 if (modules
[MESA_SHADER_FRAGMENT
]) {
1159 anv_pipeline_compile_fs(pipeline
, cache
, pCreateInfo
, extra
,
1160 modules
[MESA_SHADER_FRAGMENT
],
1161 pStages
[MESA_SHADER_FRAGMENT
]->pName
,
1162 pStages
[MESA_SHADER_FRAGMENT
]->pSpecializationInfo
);
1165 if (!(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
)) {
1166 /* Vertex is only optional if disable_vs is set */
1167 assert(extra
->disable_vs
);
1170 gen7_compute_urb_partition(pipeline
);
1172 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1173 pCreateInfo
->pVertexInputState
;
1175 uint64_t inputs_read
;
1176 if (extra
&& extra
->disable_vs
) {
1177 /* If the VS is disabled, just assume the user knows what they're
1178 * doing and apply the layout blindly. This can only come from
1179 * meta, so this *should* be safe.
1181 inputs_read
= ~0ull;
1183 inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1186 pipeline
->vb_used
= 0;
1187 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1188 const VkVertexInputAttributeDescription
*desc
=
1189 &vi_info
->pVertexAttributeDescriptions
[i
];
1191 if (inputs_read
& (1 << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1192 pipeline
->vb_used
|= 1 << desc
->binding
;
1195 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1196 const VkVertexInputBindingDescription
*desc
=
1197 &vi_info
->pVertexBindingDescriptions
[i
];
1199 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
1201 /* Step rate is programmed per vertex element (attribute), not
1202 * binding. Set up a map of which bindings step per instance, for
1203 * reference by vertex element setup. */
1204 switch (desc
->inputRate
) {
1206 case VK_VERTEX_INPUT_RATE_VERTEX
:
1207 pipeline
->instancing_enable
[desc
->binding
] = false;
1209 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1210 pipeline
->instancing_enable
[desc
->binding
] = true;
1215 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1216 pCreateInfo
->pInputAssemblyState
;
1217 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1218 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];
1220 if (extra
&& extra
->use_rectlist
)
1221 pipeline
->topology
= _3DPRIM_RECTLIST
;
1223 while (anv_block_pool_size(&device
->scratch_block_pool
) <
1224 pipeline
->total_scratch
)
1225 anv_block_pool_alloc(&device
->scratch_block_pool
);
1231 anv_graphics_pipeline_create(
1233 VkPipelineCache _cache
,
1234 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1235 const struct anv_graphics_pipeline_create_info
*extra
,
1236 const VkAllocationCallbacks
*pAllocator
,
1237 VkPipeline
*pPipeline
)
1239 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1240 ANV_FROM_HANDLE(anv_pipeline_cache
, cache
, _cache
);
1243 cache
= &device
->default_pipeline_cache
;
1245 switch (device
->info
.gen
) {
1247 if (device
->info
.is_haswell
)
1248 return gen75_graphics_pipeline_create(_device
, cache
, pCreateInfo
, extra
, pAllocator
, pPipeline
);
1250 return gen7_graphics_pipeline_create(_device
, cache
, pCreateInfo
, extra
, pAllocator
, pPipeline
);
1252 return gen8_graphics_pipeline_create(_device
, cache
, pCreateInfo
, extra
, pAllocator
, pPipeline
);
1254 return gen9_graphics_pipeline_create(_device
, cache
, pCreateInfo
, extra
, pAllocator
, pPipeline
);
1256 unreachable("unsupported gen\n");
1260 VkResult
anv_CreateGraphicsPipelines(
1262 VkPipelineCache pipelineCache
,
1264 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
1265 const VkAllocationCallbacks
* pAllocator
,
1266 VkPipeline
* pPipelines
)
1268 VkResult result
= VK_SUCCESS
;
1271 for (; i
< count
; i
++) {
1272 result
= anv_graphics_pipeline_create(_device
,
1275 NULL
, pAllocator
, &pPipelines
[i
]);
1276 if (result
!= VK_SUCCESS
) {
1277 for (unsigned j
= 0; j
< i
; j
++) {
1278 anv_DestroyPipeline(_device
, pPipelines
[j
], pAllocator
);
1288 static VkResult
anv_compute_pipeline_create(
1290 VkPipelineCache _cache
,
1291 const VkComputePipelineCreateInfo
* pCreateInfo
,
1292 const VkAllocationCallbacks
* pAllocator
,
1293 VkPipeline
* pPipeline
)
1295 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1296 ANV_FROM_HANDLE(anv_pipeline_cache
, cache
, _cache
);
1299 cache
= &device
->default_pipeline_cache
;
1301 switch (device
->info
.gen
) {
1303 if (device
->info
.is_haswell
)
1304 return gen75_compute_pipeline_create(_device
, cache
, pCreateInfo
, pAllocator
, pPipeline
);
1306 return gen7_compute_pipeline_create(_device
, cache
, pCreateInfo
, pAllocator
, pPipeline
);
1308 return gen8_compute_pipeline_create(_device
, cache
, pCreateInfo
, pAllocator
, pPipeline
);
1310 return gen9_compute_pipeline_create(_device
, cache
, pCreateInfo
, pAllocator
, pPipeline
);
1312 unreachable("unsupported gen\n");
1316 VkResult
anv_CreateComputePipelines(
1318 VkPipelineCache pipelineCache
,
1320 const VkComputePipelineCreateInfo
* pCreateInfos
,
1321 const VkAllocationCallbacks
* pAllocator
,
1322 VkPipeline
* pPipelines
)
1324 VkResult result
= VK_SUCCESS
;
1327 for (; i
< count
; i
++) {
1328 result
= anv_compute_pipeline_create(_device
, pipelineCache
,
1330 pAllocator
, &pPipelines
[i
]);
1331 if (result
!= VK_SUCCESS
) {
1332 for (unsigned j
= 0; j
< i
; j
++) {
1333 anv_DestroyPipeline(_device
, pPipelines
[j
], pAllocator
);