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anv/pipeline: Do invariance propagation on SPIR-V shaders
[mesa.git] / src / intel / vulkan / anv_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "util/mesa-sha1.h"
31 #include "anv_private.h"
32 #include "brw_nir.h"
33 #include "anv_nir.h"
34 #include "spirv/nir_spirv.h"
35
36 /* Needed for SWIZZLE macros */
37 #include "program/prog_instruction.h"
38
39 // Shader functions
40
41 VkResult anv_CreateShaderModule(
42 VkDevice _device,
43 const VkShaderModuleCreateInfo* pCreateInfo,
44 const VkAllocationCallbacks* pAllocator,
45 VkShaderModule* pShaderModule)
46 {
47 ANV_FROM_HANDLE(anv_device, device, _device);
48 struct anv_shader_module *module;
49
50 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
51 assert(pCreateInfo->flags == 0);
52
53 module = anv_alloc2(&device->alloc, pAllocator,
54 sizeof(*module) + pCreateInfo->codeSize, 8,
55 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
56 if (module == NULL)
57 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
58
59 module->nir = NULL;
60 module->size = pCreateInfo->codeSize;
61 memcpy(module->data, pCreateInfo->pCode, module->size);
62
63 _mesa_sha1_compute(module->data, module->size, module->sha1);
64
65 *pShaderModule = anv_shader_module_to_handle(module);
66
67 return VK_SUCCESS;
68 }
69
70 void anv_DestroyShaderModule(
71 VkDevice _device,
72 VkShaderModule _module,
73 const VkAllocationCallbacks* pAllocator)
74 {
75 ANV_FROM_HANDLE(anv_device, device, _device);
76 ANV_FROM_HANDLE(anv_shader_module, module, _module);
77
78 anv_free2(&device->alloc, pAllocator, module);
79 }
80
81 #define SPIR_V_MAGIC_NUMBER 0x07230203
82
83 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
84 * we can't do that yet because we don't have the ability to copy nir.
85 */
86 static nir_shader *
87 anv_shader_compile_to_nir(struct anv_device *device,
88 struct anv_shader_module *module,
89 const char *entrypoint_name,
90 gl_shader_stage stage,
91 const VkSpecializationInfo *spec_info)
92 {
93 if (strcmp(entrypoint_name, "main") != 0) {
94 anv_finishme("Multiple shaders per module not really supported");
95 }
96
97 const struct brw_compiler *compiler =
98 device->instance->physicalDevice.compiler;
99 const nir_shader_compiler_options *nir_options =
100 compiler->glsl_compiler_options[stage].NirOptions;
101
102 nir_shader *nir;
103 nir_function *entry_point;
104 if (module->nir) {
105 /* Some things such as our meta clear/blit code will give us a NIR
106 * shader directly. In that case, we just ignore the SPIR-V entirely
107 * and just use the NIR shader */
108 nir = module->nir;
109 nir->options = nir_options;
110 nir_validate_shader(nir);
111
112 assert(exec_list_length(&nir->functions) == 1);
113 struct exec_node *node = exec_list_get_head(&nir->functions);
114 entry_point = exec_node_data(nir_function, node, node);
115 } else {
116 uint32_t *spirv = (uint32_t *) module->data;
117 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
118 assert(module->size % 4 == 0);
119
120 uint32_t num_spec_entries = 0;
121 struct nir_spirv_specialization *spec_entries = NULL;
122 if (spec_info && spec_info->mapEntryCount > 0) {
123 num_spec_entries = spec_info->mapEntryCount;
124 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
125 for (uint32_t i = 0; i < num_spec_entries; i++) {
126 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
127 const void *data = spec_info->pData + entry.offset;
128 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
129
130 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
131 spec_entries[i].data = *(const uint32_t *)data;
132 }
133 }
134
135 entry_point = spirv_to_nir(spirv, module->size / 4,
136 spec_entries, num_spec_entries,
137 stage, entrypoint_name, nir_options);
138 nir = entry_point->shader;
139 assert(nir->stage == stage);
140 nir_validate_shader(nir);
141
142 free(spec_entries);
143
144 if (stage == MESA_SHADER_FRAGMENT) {
145 nir_lower_wpos_center(nir);
146 nir_validate_shader(nir);
147 }
148
149 nir_lower_returns(nir);
150 nir_validate_shader(nir);
151
152 nir_inline_functions(nir);
153 nir_validate_shader(nir);
154
155 /* Pick off the single entrypoint that we want */
156 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
157 if (func != entry_point)
158 exec_node_remove(&func->node);
159 }
160 assert(exec_list_length(&nir->functions) == 1);
161 entry_point->name = ralloc_strdup(entry_point, "main");
162
163 nir_remove_dead_variables(nir, nir_var_shader_in);
164 nir_remove_dead_variables(nir, nir_var_shader_out);
165 nir_remove_dead_variables(nir, nir_var_system_value);
166 nir_validate_shader(nir);
167
168 nir_propagate_invariant(nir);
169 nir_validate_shader(nir);
170
171 nir_lower_io_to_temporaries(entry_point->shader, entry_point, true, false);
172
173 nir_lower_system_values(nir);
174 nir_validate_shader(nir);
175 }
176
177 /* Vulkan uses the separate-shader linking model */
178 nir->info.separate_shader = true;
179
180 nir = brw_preprocess_nir(compiler, nir);
181
182 nir_shader_gather_info(nir, entry_point->impl);
183
184 nir_variable_mode indirect_mask = 0;
185 if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput)
186 indirect_mask |= nir_var_shader_in;
187 if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
188 indirect_mask |= nir_var_local;
189
190 nir_lower_indirect_derefs(nir, indirect_mask);
191
192 return nir;
193 }
194
195 void anv_DestroyPipeline(
196 VkDevice _device,
197 VkPipeline _pipeline,
198 const VkAllocationCallbacks* pAllocator)
199 {
200 ANV_FROM_HANDLE(anv_device, device, _device);
201 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
202
203 anv_reloc_list_finish(&pipeline->batch_relocs,
204 pAllocator ? pAllocator : &device->alloc);
205 if (pipeline->blend_state.map)
206 anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
207 anv_free2(&device->alloc, pAllocator, pipeline);
208 }
209
210 static const uint32_t vk_to_gen_primitive_type[] = {
211 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
212 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
213 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
214 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
215 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
216 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
217 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
218 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
219 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
220 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
221 /* [VK_PRIMITIVE_TOPOLOGY_PATCH_LIST] = _3DPRIM_PATCHLIST_1 */
222 };
223
224 static void
225 populate_sampler_prog_key(const struct brw_device_info *devinfo,
226 struct brw_sampler_prog_key_data *key)
227 {
228 /* XXX: Handle texture swizzle on HSW- */
229 for (int i = 0; i < MAX_SAMPLERS; i++) {
230 /* Assume color sampler, no swizzling. (Works for BDW+) */
231 key->swizzles[i] = SWIZZLE_XYZW;
232 }
233 }
234
235 static void
236 populate_vs_prog_key(const struct brw_device_info *devinfo,
237 struct brw_vs_prog_key *key)
238 {
239 memset(key, 0, sizeof(*key));
240
241 populate_sampler_prog_key(devinfo, &key->tex);
242
243 /* XXX: Handle vertex input work-arounds */
244
245 /* XXX: Handle sampler_prog_key */
246 }
247
248 static void
249 populate_gs_prog_key(const struct brw_device_info *devinfo,
250 struct brw_gs_prog_key *key)
251 {
252 memset(key, 0, sizeof(*key));
253
254 populate_sampler_prog_key(devinfo, &key->tex);
255 }
256
257 static void
258 populate_wm_prog_key(const struct brw_device_info *devinfo,
259 const VkGraphicsPipelineCreateInfo *info,
260 const struct anv_graphics_pipeline_create_info *extra,
261 struct brw_wm_prog_key *key)
262 {
263 ANV_FROM_HANDLE(anv_render_pass, render_pass, info->renderPass);
264
265 memset(key, 0, sizeof(*key));
266
267 populate_sampler_prog_key(devinfo, &key->tex);
268
269 /* TODO: Fill out key->input_slots_valid */
270
271 /* Vulkan doesn't specify a default */
272 key->high_quality_derivatives = false;
273
274 /* XXX Vulkan doesn't appear to specify */
275 key->clamp_fragment_color = false;
276
277 if (extra && extra->color_attachment_count >= 0) {
278 key->nr_color_regions = extra->color_attachment_count;
279 } else {
280 key->nr_color_regions =
281 render_pass->subpasses[info->subpass].color_count;
282 }
283
284 key->replicate_alpha = key->nr_color_regions > 1 &&
285 info->pMultisampleState &&
286 info->pMultisampleState->alphaToCoverageEnable;
287
288 if (info->pMultisampleState && info->pMultisampleState->rasterizationSamples > 1) {
289 /* We should probably pull this out of the shader, but it's fairly
290 * harmless to compute it and then let dead-code take care of it.
291 */
292 key->persample_interp =
293 (info->pMultisampleState->minSampleShading *
294 info->pMultisampleState->rasterizationSamples) > 1;
295 key->multisample_fbo = true;
296 }
297 }
298
299 static void
300 populate_cs_prog_key(const struct brw_device_info *devinfo,
301 struct brw_cs_prog_key *key)
302 {
303 memset(key, 0, sizeof(*key));
304
305 populate_sampler_prog_key(devinfo, &key->tex);
306 }
307
308 static nir_shader *
309 anv_pipeline_compile(struct anv_pipeline *pipeline,
310 struct anv_shader_module *module,
311 const char *entrypoint,
312 gl_shader_stage stage,
313 const VkSpecializationInfo *spec_info,
314 struct brw_stage_prog_data *prog_data,
315 struct anv_pipeline_bind_map *map)
316 {
317 nir_shader *nir = anv_shader_compile_to_nir(pipeline->device,
318 module, entrypoint, stage,
319 spec_info);
320 if (nir == NULL)
321 return NULL;
322
323 anv_nir_lower_push_constants(nir);
324
325 /* Figure out the number of parameters */
326 prog_data->nr_params = 0;
327
328 if (nir->num_uniforms > 0) {
329 /* If the shader uses any push constants at all, we'll just give
330 * them the maximum possible number
331 */
332 prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
333 }
334
335 if (pipeline->layout && pipeline->layout->stage[stage].has_dynamic_offsets)
336 prog_data->nr_params += MAX_DYNAMIC_BUFFERS * 2;
337
338 if (nir->info.num_images > 0) {
339 prog_data->nr_params += nir->info.num_images * BRW_IMAGE_PARAM_SIZE;
340 pipeline->needs_data_cache = true;
341 }
342
343 if (stage == MESA_SHADER_COMPUTE)
344 ((struct brw_cs_prog_data *)prog_data)->thread_local_id_index =
345 prog_data->nr_params++; /* The CS Thread ID uniform */
346
347 if (nir->info.num_ssbos > 0)
348 pipeline->needs_data_cache = true;
349
350 if (prog_data->nr_params > 0) {
351 /* XXX: I think we're leaking this */
352 prog_data->param = (const union gl_constant_value **)
353 malloc(prog_data->nr_params * sizeof(union gl_constant_value *));
354
355 /* We now set the param values to be offsets into a
356 * anv_push_constant_data structure. Since the compiler doesn't
357 * actually dereference any of the gl_constant_value pointers in the
358 * params array, it doesn't really matter what we put here.
359 */
360 struct anv_push_constants *null_data = NULL;
361 if (nir->num_uniforms > 0) {
362 /* Fill out the push constants section of the param array */
363 for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++)
364 prog_data->param[i] = (const union gl_constant_value *)
365 &null_data->client_data[i * sizeof(float)];
366 }
367 }
368
369 /* Set up dynamic offsets */
370 anv_nir_apply_dynamic_offsets(pipeline, nir, prog_data);
371
372 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
373 if (pipeline->layout)
374 anv_nir_apply_pipeline_layout(pipeline, nir, prog_data, map);
375
376 /* nir_lower_io will only handle the push constants; we need to set this
377 * to the full number of possible uniforms.
378 */
379 nir->num_uniforms = prog_data->nr_params * 4;
380
381 return nir;
382 }
383
384 static void
385 anv_fill_binding_table(struct brw_stage_prog_data *prog_data, unsigned bias)
386 {
387 prog_data->binding_table.size_bytes = 0;
388 prog_data->binding_table.texture_start = bias;
389 prog_data->binding_table.ubo_start = bias;
390 prog_data->binding_table.ssbo_start = bias;
391 prog_data->binding_table.image_start = bias;
392 }
393
394 static void
395 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
396 gl_shader_stage stage,
397 const struct brw_stage_prog_data *prog_data,
398 struct anv_pipeline_bind_map *map)
399 {
400 struct brw_device_info *devinfo = &pipeline->device->info;
401 uint32_t max_threads[] = {
402 [MESA_SHADER_VERTEX] = devinfo->max_vs_threads,
403 [MESA_SHADER_TESS_CTRL] = devinfo->max_hs_threads,
404 [MESA_SHADER_TESS_EVAL] = devinfo->max_ds_threads,
405 [MESA_SHADER_GEOMETRY] = devinfo->max_gs_threads,
406 [MESA_SHADER_FRAGMENT] = devinfo->max_wm_threads,
407 [MESA_SHADER_COMPUTE] = devinfo->max_cs_threads,
408 };
409
410 pipeline->prog_data[stage] = prog_data;
411 pipeline->active_stages |= mesa_to_vk_shader_stage(stage);
412 pipeline->scratch_start[stage] = pipeline->total_scratch;
413 pipeline->total_scratch =
414 align_u32(pipeline->total_scratch, 1024) +
415 prog_data->total_scratch * max_threads[stage];
416 pipeline->bindings[stage] = *map;
417 }
418
419 static VkResult
420 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
421 struct anv_pipeline_cache *cache,
422 const VkGraphicsPipelineCreateInfo *info,
423 struct anv_shader_module *module,
424 const char *entrypoint,
425 const VkSpecializationInfo *spec_info)
426 {
427 const struct brw_compiler *compiler =
428 pipeline->device->instance->physicalDevice.compiler;
429 const struct brw_stage_prog_data *stage_prog_data;
430 struct anv_pipeline_bind_map map;
431 struct brw_vs_prog_key key;
432 uint32_t kernel = NO_KERNEL;
433 unsigned char sha1[20];
434
435 populate_vs_prog_key(&pipeline->device->info, &key);
436
437 if (module->size > 0) {
438 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, spec_info);
439 kernel = anv_pipeline_cache_search(cache, sha1, &stage_prog_data, &map);
440 }
441
442 if (kernel == NO_KERNEL) {
443 struct brw_vs_prog_data prog_data = { 0, };
444 struct anv_pipeline_binding surface_to_descriptor[256];
445 struct anv_pipeline_binding sampler_to_descriptor[256];
446
447 map = (struct anv_pipeline_bind_map) {
448 .surface_to_descriptor = surface_to_descriptor,
449 .sampler_to_descriptor = sampler_to_descriptor
450 };
451
452 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
453 MESA_SHADER_VERTEX, spec_info,
454 &prog_data.base.base, &map);
455 if (nir == NULL)
456 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
457
458 anv_fill_binding_table(&prog_data.base.base, 0);
459
460 void *mem_ctx = ralloc_context(NULL);
461
462 if (module->nir == NULL)
463 ralloc_steal(mem_ctx, nir);
464
465 prog_data.inputs_read = nir->info.inputs_read;
466
467 brw_compute_vue_map(&pipeline->device->info,
468 &prog_data.base.vue_map,
469 nir->info.outputs_written,
470 nir->info.separate_shader);
471
472 unsigned code_size;
473 const unsigned *shader_code =
474 brw_compile_vs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
475 NULL, false, -1, &code_size, NULL);
476 if (shader_code == NULL) {
477 ralloc_free(mem_ctx);
478 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
479 }
480
481 stage_prog_data = &prog_data.base.base;
482 kernel = anv_pipeline_cache_upload_kernel(cache,
483 module->size > 0 ? sha1 : NULL,
484 shader_code, code_size,
485 &stage_prog_data, sizeof(prog_data),
486 &map);
487 ralloc_free(mem_ctx);
488 }
489
490 const struct brw_vs_prog_data *vs_prog_data =
491 (const struct brw_vs_prog_data *) stage_prog_data;
492
493 if (vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8) {
494 pipeline->vs_simd8 = kernel;
495 pipeline->vs_vec4 = NO_KERNEL;
496 } else {
497 pipeline->vs_simd8 = NO_KERNEL;
498 pipeline->vs_vec4 = kernel;
499 }
500
501 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX,
502 stage_prog_data, &map);
503
504 return VK_SUCCESS;
505 }
506
507 static VkResult
508 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
509 struct anv_pipeline_cache *cache,
510 const VkGraphicsPipelineCreateInfo *info,
511 struct anv_shader_module *module,
512 const char *entrypoint,
513 const VkSpecializationInfo *spec_info)
514 {
515 const struct brw_compiler *compiler =
516 pipeline->device->instance->physicalDevice.compiler;
517 const struct brw_stage_prog_data *stage_prog_data;
518 struct anv_pipeline_bind_map map;
519 struct brw_gs_prog_key key;
520 uint32_t kernel = NO_KERNEL;
521 unsigned char sha1[20];
522
523 populate_gs_prog_key(&pipeline->device->info, &key);
524
525 if (module->size > 0) {
526 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, spec_info);
527 kernel = anv_pipeline_cache_search(cache, sha1, &stage_prog_data, &map);
528 }
529
530 if (kernel == NO_KERNEL) {
531 struct brw_gs_prog_data prog_data = { 0, };
532 struct anv_pipeline_binding surface_to_descriptor[256];
533 struct anv_pipeline_binding sampler_to_descriptor[256];
534
535 map = (struct anv_pipeline_bind_map) {
536 .surface_to_descriptor = surface_to_descriptor,
537 .sampler_to_descriptor = sampler_to_descriptor
538 };
539
540 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
541 MESA_SHADER_GEOMETRY, spec_info,
542 &prog_data.base.base, &map);
543 if (nir == NULL)
544 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
545
546 anv_fill_binding_table(&prog_data.base.base, 0);
547
548 void *mem_ctx = ralloc_context(NULL);
549
550 if (module->nir == NULL)
551 ralloc_steal(mem_ctx, nir);
552
553 brw_compute_vue_map(&pipeline->device->info,
554 &prog_data.base.vue_map,
555 nir->info.outputs_written,
556 nir->info.separate_shader);
557
558 unsigned code_size;
559 const unsigned *shader_code =
560 brw_compile_gs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
561 NULL, -1, &code_size, NULL);
562 if (shader_code == NULL) {
563 ralloc_free(mem_ctx);
564 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
565 }
566
567 /* TODO: SIMD8 GS */
568 stage_prog_data = &prog_data.base.base;
569 kernel = anv_pipeline_cache_upload_kernel(cache,
570 module->size > 0 ? sha1 : NULL,
571 shader_code, code_size,
572 &stage_prog_data, sizeof(prog_data),
573 &map);
574
575 ralloc_free(mem_ctx);
576 }
577
578 pipeline->gs_kernel = kernel;
579
580 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY,
581 stage_prog_data, &map);
582
583 return VK_SUCCESS;
584 }
585
586 static VkResult
587 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
588 struct anv_pipeline_cache *cache,
589 const VkGraphicsPipelineCreateInfo *info,
590 const struct anv_graphics_pipeline_create_info *extra,
591 struct anv_shader_module *module,
592 const char *entrypoint,
593 const VkSpecializationInfo *spec_info)
594 {
595 const struct brw_compiler *compiler =
596 pipeline->device->instance->physicalDevice.compiler;
597 const struct brw_stage_prog_data *stage_prog_data;
598 struct anv_pipeline_bind_map map;
599 struct brw_wm_prog_key key;
600 unsigned char sha1[20];
601
602 populate_wm_prog_key(&pipeline->device->info, info, extra, &key);
603
604 if (module->size > 0) {
605 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, spec_info);
606 pipeline->ps_ksp0 =
607 anv_pipeline_cache_search(cache, sha1, &stage_prog_data, &map);
608 }
609
610 if (pipeline->ps_ksp0 == NO_KERNEL) {
611 struct brw_wm_prog_data prog_data = { 0, };
612 struct anv_pipeline_binding surface_to_descriptor[256];
613 struct anv_pipeline_binding sampler_to_descriptor[256];
614
615 map = (struct anv_pipeline_bind_map) {
616 .surface_to_descriptor = surface_to_descriptor + 8,
617 .sampler_to_descriptor = sampler_to_descriptor
618 };
619
620 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
621 MESA_SHADER_FRAGMENT, spec_info,
622 &prog_data.base, &map);
623 if (nir == NULL)
624 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
625
626 unsigned num_rts = 0;
627 struct anv_pipeline_binding rt_bindings[8];
628 nir_function_impl *impl = nir_shader_get_entrypoint(nir)->impl;
629 nir_foreach_variable_safe(var, &nir->outputs) {
630 if (var->data.location < FRAG_RESULT_DATA0)
631 continue;
632
633 unsigned rt = var->data.location - FRAG_RESULT_DATA0;
634 if (rt >= key.nr_color_regions) {
635 /* Out-of-bounds, throw it away */
636 var->data.mode = nir_var_local;
637 exec_node_remove(&var->node);
638 exec_list_push_tail(&impl->locals, &var->node);
639 continue;
640 }
641
642 /* Give it a new, compacted, location */
643 var->data.location = FRAG_RESULT_DATA0 + num_rts;
644
645 unsigned array_len =
646 glsl_type_is_array(var->type) ? glsl_get_length(var->type) : 1;
647 assert(num_rts + array_len <= 8);
648
649 for (unsigned i = 0; i < array_len; i++) {
650 rt_bindings[num_rts] = (struct anv_pipeline_binding) {
651 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
652 .binding = 0,
653 .index = rt + i,
654 };
655 }
656
657 num_rts += array_len;
658 }
659
660 if (pipeline->use_repclear) {
661 assert(num_rts == 1);
662 key.nr_color_regions = 1;
663 }
664
665 if (num_rts == 0) {
666 /* If we have no render targets, we need a null render target */
667 rt_bindings[0] = (struct anv_pipeline_binding) {
668 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
669 .binding = 0,
670 .index = UINT8_MAX,
671 };
672 num_rts = 1;
673 }
674
675 assert(num_rts <= 8);
676 map.surface_to_descriptor -= num_rts;
677 map.surface_count += num_rts;
678 assert(map.surface_count <= 256);
679 memcpy(map.surface_to_descriptor, rt_bindings,
680 num_rts * sizeof(*rt_bindings));
681
682 anv_fill_binding_table(&prog_data.base, num_rts);
683
684 void *mem_ctx = ralloc_context(NULL);
685
686 if (module->nir == NULL)
687 ralloc_steal(mem_ctx, nir);
688
689 unsigned code_size;
690 const unsigned *shader_code =
691 brw_compile_fs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
692 NULL, -1, -1, true, pipeline->use_repclear,
693 &code_size, NULL);
694 if (shader_code == NULL) {
695 ralloc_free(mem_ctx);
696 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
697 }
698
699 stage_prog_data = &prog_data.base;
700 pipeline->ps_ksp0 =
701 anv_pipeline_cache_upload_kernel(cache,
702 module->size > 0 ? sha1 : NULL,
703 shader_code, code_size,
704 &stage_prog_data, sizeof(prog_data),
705 &map);
706
707 ralloc_free(mem_ctx);
708 }
709
710 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT,
711 stage_prog_data, &map);
712
713 return VK_SUCCESS;
714 }
715
716 VkResult
717 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
718 struct anv_pipeline_cache *cache,
719 const VkComputePipelineCreateInfo *info,
720 struct anv_shader_module *module,
721 const char *entrypoint,
722 const VkSpecializationInfo *spec_info)
723 {
724 const struct brw_compiler *compiler =
725 pipeline->device->instance->physicalDevice.compiler;
726 const struct brw_stage_prog_data *stage_prog_data;
727 struct anv_pipeline_bind_map map;
728 struct brw_cs_prog_key key;
729 uint32_t kernel = NO_KERNEL;
730 unsigned char sha1[20];
731
732 populate_cs_prog_key(&pipeline->device->info, &key);
733
734 if (module->size > 0) {
735 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, spec_info);
736 kernel = anv_pipeline_cache_search(cache, sha1, &stage_prog_data, &map);
737 }
738
739 if (module->size == 0 || kernel == NO_KERNEL) {
740 struct brw_cs_prog_data prog_data = { 0, };
741 struct anv_pipeline_binding surface_to_descriptor[256];
742 struct anv_pipeline_binding sampler_to_descriptor[256];
743
744 map = (struct anv_pipeline_bind_map) {
745 .surface_to_descriptor = surface_to_descriptor,
746 .sampler_to_descriptor = sampler_to_descriptor
747 };
748
749 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
750 MESA_SHADER_COMPUTE, spec_info,
751 &prog_data.base, &map);
752 if (nir == NULL)
753 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
754
755 anv_fill_binding_table(&prog_data.base, 1);
756
757 void *mem_ctx = ralloc_context(NULL);
758
759 if (module->nir == NULL)
760 ralloc_steal(mem_ctx, nir);
761
762 unsigned code_size;
763 const unsigned *shader_code =
764 brw_compile_cs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
765 -1, &code_size, NULL);
766 if (shader_code == NULL) {
767 ralloc_free(mem_ctx);
768 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
769 }
770
771 stage_prog_data = &prog_data.base;
772 kernel = anv_pipeline_cache_upload_kernel(cache,
773 module->size > 0 ? sha1 : NULL,
774 shader_code, code_size,
775 &stage_prog_data, sizeof(prog_data),
776 &map);
777
778 ralloc_free(mem_ctx);
779 }
780
781 pipeline->cs_simd = kernel;
782
783 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE,
784 stage_prog_data, &map);
785
786 return VK_SUCCESS;
787 }
788
789
790 void
791 anv_setup_pipeline_l3_config(struct anv_pipeline *pipeline)
792 {
793 const struct brw_device_info *devinfo = &pipeline->device->info;
794 switch (devinfo->gen) {
795 case 7:
796 if (devinfo->is_haswell)
797 gen75_setup_pipeline_l3_config(pipeline);
798 else
799 gen7_setup_pipeline_l3_config(pipeline);
800 break;
801 case 8:
802 gen8_setup_pipeline_l3_config(pipeline);
803 break;
804 case 9:
805 gen9_setup_pipeline_l3_config(pipeline);
806 break;
807 default:
808 unreachable("unsupported gen\n");
809 }
810 }
811
812 void
813 anv_compute_urb_partition(struct anv_pipeline *pipeline)
814 {
815 const struct brw_device_info *devinfo = &pipeline->device->info;
816
817 bool vs_present = pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT;
818 unsigned vs_size = vs_present ?
819 get_vs_prog_data(pipeline)->base.urb_entry_size : 1;
820 unsigned vs_entry_size_bytes = vs_size * 64;
821 bool gs_present = pipeline->active_stages & VK_SHADER_STAGE_GEOMETRY_BIT;
822 unsigned gs_size = gs_present ?
823 get_gs_prog_data(pipeline)->base.urb_entry_size : 1;
824 unsigned gs_entry_size_bytes = gs_size * 64;
825
826 /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
827 *
828 * VS Number of URB Entries must be divisible by 8 if the VS URB Entry
829 * Allocation Size is less than 9 512-bit URB entries.
830 *
831 * Similar text exists for GS.
832 */
833 unsigned vs_granularity = (vs_size < 9) ? 8 : 1;
834 unsigned gs_granularity = (gs_size < 9) ? 8 : 1;
835
836 /* URB allocations must be done in 8k chunks. */
837 unsigned chunk_size_bytes = 8192;
838
839 /* Determine the size of the URB in chunks. */
840 unsigned urb_chunks = pipeline->urb.total_size * 1024 / chunk_size_bytes;
841
842 /* Reserve space for push constants */
843 unsigned push_constant_kb;
844 if (pipeline->device->info.gen >= 8)
845 push_constant_kb = 32;
846 else if (pipeline->device->info.is_haswell)
847 push_constant_kb = pipeline->device->info.gt == 3 ? 32 : 16;
848 else
849 push_constant_kb = 16;
850
851 unsigned push_constant_bytes = push_constant_kb * 1024;
852 unsigned push_constant_chunks =
853 push_constant_bytes / chunk_size_bytes;
854
855 /* Initially, assign each stage the minimum amount of URB space it needs,
856 * and make a note of how much additional space it "wants" (the amount of
857 * additional space it could actually make use of).
858 */
859
860 /* VS has a lower limit on the number of URB entries */
861 unsigned vs_chunks =
862 ALIGN(devinfo->urb.min_vs_entries * vs_entry_size_bytes,
863 chunk_size_bytes) / chunk_size_bytes;
864 unsigned vs_wants =
865 ALIGN(devinfo->urb.max_vs_entries * vs_entry_size_bytes,
866 chunk_size_bytes) / chunk_size_bytes - vs_chunks;
867
868 unsigned gs_chunks = 0;
869 unsigned gs_wants = 0;
870 if (gs_present) {
871 /* There are two constraints on the minimum amount of URB space we can
872 * allocate:
873 *
874 * (1) We need room for at least 2 URB entries, since we always operate
875 * the GS in DUAL_OBJECT mode.
876 *
877 * (2) We can't allocate less than nr_gs_entries_granularity.
878 */
879 gs_chunks = ALIGN(MAX2(gs_granularity, 2) * gs_entry_size_bytes,
880 chunk_size_bytes) / chunk_size_bytes;
881 gs_wants =
882 ALIGN(devinfo->urb.max_gs_entries * gs_entry_size_bytes,
883 chunk_size_bytes) / chunk_size_bytes - gs_chunks;
884 }
885
886 /* There should always be enough URB space to satisfy the minimum
887 * requirements of each stage.
888 */
889 unsigned total_needs = push_constant_chunks + vs_chunks + gs_chunks;
890 assert(total_needs <= urb_chunks);
891
892 /* Mete out remaining space (if any) in proportion to "wants". */
893 unsigned total_wants = vs_wants + gs_wants;
894 unsigned remaining_space = urb_chunks - total_needs;
895 if (remaining_space > total_wants)
896 remaining_space = total_wants;
897 if (remaining_space > 0) {
898 unsigned vs_additional = (unsigned)
899 round(vs_wants * (((double) remaining_space) / total_wants));
900 vs_chunks += vs_additional;
901 remaining_space -= vs_additional;
902 gs_chunks += remaining_space;
903 }
904
905 /* Sanity check that we haven't over-allocated. */
906 assert(push_constant_chunks + vs_chunks + gs_chunks <= urb_chunks);
907
908 /* Finally, compute the number of entries that can fit in the space
909 * allocated to each stage.
910 */
911 unsigned nr_vs_entries = vs_chunks * chunk_size_bytes / vs_entry_size_bytes;
912 unsigned nr_gs_entries = gs_chunks * chunk_size_bytes / gs_entry_size_bytes;
913
914 /* Since we rounded up when computing *_wants, this may be slightly more
915 * than the maximum allowed amount, so correct for that.
916 */
917 nr_vs_entries = MIN2(nr_vs_entries, devinfo->urb.max_vs_entries);
918 nr_gs_entries = MIN2(nr_gs_entries, devinfo->urb.max_gs_entries);
919
920 /* Ensure that we program a multiple of the granularity. */
921 nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, vs_granularity);
922 nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, gs_granularity);
923
924 /* Finally, sanity check to make sure we have at least the minimum number
925 * of entries needed for each stage.
926 */
927 assert(nr_vs_entries >= devinfo->urb.min_vs_entries);
928 if (gs_present)
929 assert(nr_gs_entries >= 2);
930
931 /* Lay out the URB in the following order:
932 * - push constants
933 * - VS
934 * - GS
935 */
936 pipeline->urb.start[MESA_SHADER_VERTEX] = push_constant_chunks;
937 pipeline->urb.size[MESA_SHADER_VERTEX] = vs_size;
938 pipeline->urb.entries[MESA_SHADER_VERTEX] = nr_vs_entries;
939
940 pipeline->urb.start[MESA_SHADER_GEOMETRY] = push_constant_chunks + vs_chunks;
941 pipeline->urb.size[MESA_SHADER_GEOMETRY] = gs_size;
942 pipeline->urb.entries[MESA_SHADER_GEOMETRY] = nr_gs_entries;
943
944 pipeline->urb.start[MESA_SHADER_TESS_CTRL] = push_constant_chunks;
945 pipeline->urb.size[MESA_SHADER_TESS_CTRL] = 1;
946 pipeline->urb.entries[MESA_SHADER_TESS_CTRL] = 0;
947
948 pipeline->urb.start[MESA_SHADER_TESS_EVAL] = push_constant_chunks;
949 pipeline->urb.size[MESA_SHADER_TESS_EVAL] = 1;
950 pipeline->urb.entries[MESA_SHADER_TESS_EVAL] = 0;
951 }
952
953 /**
954 * Copy pipeline state not marked as dynamic.
955 * Dynamic state is pipeline state which hasn't been provided at pipeline
956 * creation time, but is dynamically provided afterwards using various
957 * vkCmdSet* functions.
958 *
959 * The set of state considered "non_dynamic" is determined by the pieces of
960 * state that have their corresponding VkDynamicState enums omitted from
961 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
962 *
963 * @param[out] pipeline Destination non_dynamic state.
964 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
965 */
966 static void
967 copy_non_dynamic_state(struct anv_pipeline *pipeline,
968 const VkGraphicsPipelineCreateInfo *pCreateInfo)
969 {
970 anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
971 ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
972 struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
973
974 pipeline->dynamic_state = default_dynamic_state;
975
976 if (pCreateInfo->pDynamicState) {
977 /* Remove all of the states that are marked as dynamic */
978 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
979 for (uint32_t s = 0; s < count; s++)
980 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
981 }
982
983 struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
984
985 /* Section 9.2 of the Vulkan 1.0.15 spec says:
986 *
987 * pViewportState is [...] NULL if the pipeline
988 * has rasterization disabled.
989 */
990 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
991 assert(pCreateInfo->pViewportState);
992
993 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
994 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
995 typed_memcpy(dynamic->viewport.viewports,
996 pCreateInfo->pViewportState->pViewports,
997 pCreateInfo->pViewportState->viewportCount);
998 }
999
1000 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1001 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1002 typed_memcpy(dynamic->scissor.scissors,
1003 pCreateInfo->pViewportState->pScissors,
1004 pCreateInfo->pViewportState->scissorCount);
1005 }
1006 }
1007
1008 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1009 assert(pCreateInfo->pRasterizationState);
1010 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1011 }
1012
1013 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1014 assert(pCreateInfo->pRasterizationState);
1015 dynamic->depth_bias.bias =
1016 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1017 dynamic->depth_bias.clamp =
1018 pCreateInfo->pRasterizationState->depthBiasClamp;
1019 dynamic->depth_bias.slope =
1020 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1021 }
1022
1023 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1024 *
1025 * pColorBlendState is [...] NULL if the pipeline has rasterization
1026 * disabled or if the subpass of the render pass the pipeline is
1027 * created against does not use any color attachments.
1028 */
1029 bool uses_color_att = false;
1030 for (unsigned i = 0; i < subpass->color_count; ++i) {
1031 if (subpass->color_attachments[i] != VK_ATTACHMENT_UNUSED) {
1032 uses_color_att = true;
1033 break;
1034 }
1035 }
1036
1037 if (uses_color_att &&
1038 !pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1039 assert(pCreateInfo->pColorBlendState);
1040
1041 if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
1042 typed_memcpy(dynamic->blend_constants,
1043 pCreateInfo->pColorBlendState->blendConstants, 4);
1044 }
1045
1046 /* If there is no depthstencil attachment, then don't read
1047 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1048 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1049 * no need to override the depthstencil defaults in
1050 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1051 *
1052 * Section 9.2 of the Vulkan 1.0.15 spec says:
1053 *
1054 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1055 * disabled or if the subpass of the render pass the pipeline is created
1056 * against does not use a depth/stencil attachment.
1057 */
1058 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1059 subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
1060 assert(pCreateInfo->pDepthStencilState);
1061
1062 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1063 dynamic->depth_bounds.min =
1064 pCreateInfo->pDepthStencilState->minDepthBounds;
1065 dynamic->depth_bounds.max =
1066 pCreateInfo->pDepthStencilState->maxDepthBounds;
1067 }
1068
1069 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1070 dynamic->stencil_compare_mask.front =
1071 pCreateInfo->pDepthStencilState->front.compareMask;
1072 dynamic->stencil_compare_mask.back =
1073 pCreateInfo->pDepthStencilState->back.compareMask;
1074 }
1075
1076 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1077 dynamic->stencil_write_mask.front =
1078 pCreateInfo->pDepthStencilState->front.writeMask;
1079 dynamic->stencil_write_mask.back =
1080 pCreateInfo->pDepthStencilState->back.writeMask;
1081 }
1082
1083 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1084 dynamic->stencil_reference.front =
1085 pCreateInfo->pDepthStencilState->front.reference;
1086 dynamic->stencil_reference.back =
1087 pCreateInfo->pDepthStencilState->back.reference;
1088 }
1089 }
1090
1091 pipeline->dynamic_state_mask = states;
1092 }
1093
1094 static void
1095 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
1096 {
1097 struct anv_render_pass *renderpass = NULL;
1098 struct anv_subpass *subpass = NULL;
1099
1100 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1101 * present, as explained by the Vulkan (20 Oct 2015, git-aa308cb), Section
1102 * 4.2 Graphics Pipeline.
1103 */
1104 assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
1105
1106 renderpass = anv_render_pass_from_handle(info->renderPass);
1107 assert(renderpass);
1108
1109 if (renderpass != &anv_meta_dummy_renderpass) {
1110 assert(info->subpass < renderpass->subpass_count);
1111 subpass = &renderpass->subpasses[info->subpass];
1112 }
1113
1114 assert(info->stageCount >= 1);
1115 assert(info->pVertexInputState);
1116 assert(info->pInputAssemblyState);
1117 assert(info->pViewportState);
1118 assert(info->pRasterizationState);
1119
1120 if (subpass && subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED)
1121 assert(info->pDepthStencilState);
1122
1123 if (subpass && subpass->color_count > 0)
1124 assert(info->pColorBlendState);
1125
1126 for (uint32_t i = 0; i < info->stageCount; ++i) {
1127 switch (info->pStages[i].stage) {
1128 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
1129 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
1130 assert(info->pTessellationState);
1131 break;
1132 default:
1133 break;
1134 }
1135 }
1136 }
1137
1138 VkResult
1139 anv_pipeline_init(struct anv_pipeline *pipeline,
1140 struct anv_device *device,
1141 struct anv_pipeline_cache *cache,
1142 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1143 const struct anv_graphics_pipeline_create_info *extra,
1144 const VkAllocationCallbacks *alloc)
1145 {
1146 VkResult result;
1147
1148 anv_validate {
1149 anv_pipeline_validate_create_info(pCreateInfo);
1150 }
1151
1152 if (alloc == NULL)
1153 alloc = &device->alloc;
1154
1155 pipeline->device = device;
1156 pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
1157
1158 result = anv_reloc_list_init(&pipeline->batch_relocs, alloc);
1159 if (result != VK_SUCCESS)
1160 return result;
1161
1162 pipeline->batch.alloc = alloc;
1163 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
1164 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
1165 pipeline->batch.relocs = &pipeline->batch_relocs;
1166
1167 copy_non_dynamic_state(pipeline, pCreateInfo);
1168
1169 pipeline->use_repclear = extra && extra->use_repclear;
1170
1171 pipeline->needs_data_cache = false;
1172
1173 /* When we free the pipeline, we detect stages based on the NULL status
1174 * of various prog_data pointers. Make them NULL by default.
1175 */
1176 memset(pipeline->prog_data, 0, sizeof(pipeline->prog_data));
1177 memset(pipeline->scratch_start, 0, sizeof(pipeline->scratch_start));
1178 memset(pipeline->bindings, 0, sizeof(pipeline->bindings));
1179
1180 pipeline->vs_simd8 = NO_KERNEL;
1181 pipeline->vs_vec4 = NO_KERNEL;
1182 pipeline->gs_kernel = NO_KERNEL;
1183 pipeline->ps_ksp0 = NO_KERNEL;
1184
1185 pipeline->active_stages = 0;
1186 pipeline->total_scratch = 0;
1187
1188 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1189 struct anv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1190 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1191 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1192 pStages[stage] = &pCreateInfo->pStages[i];
1193 modules[stage] = anv_shader_module_from_handle(pStages[stage]->module);
1194 }
1195
1196 if (modules[MESA_SHADER_VERTEX]) {
1197 anv_pipeline_compile_vs(pipeline, cache, pCreateInfo,
1198 modules[MESA_SHADER_VERTEX],
1199 pStages[MESA_SHADER_VERTEX]->pName,
1200 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo);
1201 }
1202
1203 if (modules[MESA_SHADER_TESS_CTRL] || modules[MESA_SHADER_TESS_EVAL])
1204 anv_finishme("no tessellation support");
1205
1206 if (modules[MESA_SHADER_GEOMETRY]) {
1207 anv_pipeline_compile_gs(pipeline, cache, pCreateInfo,
1208 modules[MESA_SHADER_GEOMETRY],
1209 pStages[MESA_SHADER_GEOMETRY]->pName,
1210 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo);
1211 }
1212
1213 if (modules[MESA_SHADER_FRAGMENT]) {
1214 anv_pipeline_compile_fs(pipeline, cache, pCreateInfo, extra,
1215 modules[MESA_SHADER_FRAGMENT],
1216 pStages[MESA_SHADER_FRAGMENT]->pName,
1217 pStages[MESA_SHADER_FRAGMENT]->pSpecializationInfo);
1218 }
1219
1220 if (!(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT)) {
1221 /* Vertex is only optional if disable_vs is set */
1222 assert(extra->disable_vs);
1223 }
1224
1225 anv_setup_pipeline_l3_config(pipeline);
1226 anv_compute_urb_partition(pipeline);
1227
1228 const VkPipelineVertexInputStateCreateInfo *vi_info =
1229 pCreateInfo->pVertexInputState;
1230
1231 uint64_t inputs_read;
1232 if (extra && extra->disable_vs) {
1233 /* If the VS is disabled, just assume the user knows what they're
1234 * doing and apply the layout blindly. This can only come from
1235 * meta, so this *should* be safe.
1236 */
1237 inputs_read = ~0ull;
1238 } else {
1239 inputs_read = get_vs_prog_data(pipeline)->inputs_read;
1240 }
1241
1242 pipeline->vb_used = 0;
1243 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1244 const VkVertexInputAttributeDescription *desc =
1245 &vi_info->pVertexAttributeDescriptions[i];
1246
1247 if (inputs_read & (1 << (VERT_ATTRIB_GENERIC0 + desc->location)))
1248 pipeline->vb_used |= 1 << desc->binding;
1249 }
1250
1251 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1252 const VkVertexInputBindingDescription *desc =
1253 &vi_info->pVertexBindingDescriptions[i];
1254
1255 pipeline->binding_stride[desc->binding] = desc->stride;
1256
1257 /* Step rate is programmed per vertex element (attribute), not
1258 * binding. Set up a map of which bindings step per instance, for
1259 * reference by vertex element setup. */
1260 switch (desc->inputRate) {
1261 default:
1262 case VK_VERTEX_INPUT_RATE_VERTEX:
1263 pipeline->instancing_enable[desc->binding] = false;
1264 break;
1265 case VK_VERTEX_INPUT_RATE_INSTANCE:
1266 pipeline->instancing_enable[desc->binding] = true;
1267 break;
1268 }
1269 }
1270
1271 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1272 pCreateInfo->pInputAssemblyState;
1273 pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1274 pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1275
1276 if (extra && extra->use_rectlist)
1277 pipeline->topology = _3DPRIM_RECTLIST;
1278
1279 while (anv_block_pool_size(&device->scratch_block_pool) <
1280 pipeline->total_scratch)
1281 anv_block_pool_alloc(&device->scratch_block_pool);
1282
1283 return VK_SUCCESS;
1284 }
1285
1286 VkResult
1287 anv_graphics_pipeline_create(
1288 VkDevice _device,
1289 VkPipelineCache _cache,
1290 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1291 const struct anv_graphics_pipeline_create_info *extra,
1292 const VkAllocationCallbacks *pAllocator,
1293 VkPipeline *pPipeline)
1294 {
1295 ANV_FROM_HANDLE(anv_device, device, _device);
1296 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
1297
1298 if (cache == NULL)
1299 cache = &device->default_pipeline_cache;
1300
1301 switch (device->info.gen) {
1302 case 7:
1303 if (device->info.is_haswell)
1304 return gen75_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1305 else
1306 return gen7_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1307 case 8:
1308 return gen8_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1309 case 9:
1310 return gen9_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1311 default:
1312 unreachable("unsupported gen\n");
1313 }
1314 }
1315
1316 VkResult anv_CreateGraphicsPipelines(
1317 VkDevice _device,
1318 VkPipelineCache pipelineCache,
1319 uint32_t count,
1320 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1321 const VkAllocationCallbacks* pAllocator,
1322 VkPipeline* pPipelines)
1323 {
1324 VkResult result = VK_SUCCESS;
1325
1326 unsigned i = 0;
1327 for (; i < count; i++) {
1328 result = anv_graphics_pipeline_create(_device,
1329 pipelineCache,
1330 &pCreateInfos[i],
1331 NULL, pAllocator, &pPipelines[i]);
1332 if (result != VK_SUCCESS) {
1333 for (unsigned j = 0; j < i; j++) {
1334 anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1335 }
1336
1337 return result;
1338 }
1339 }
1340
1341 return VK_SUCCESS;
1342 }
1343
1344 static VkResult anv_compute_pipeline_create(
1345 VkDevice _device,
1346 VkPipelineCache _cache,
1347 const VkComputePipelineCreateInfo* pCreateInfo,
1348 const VkAllocationCallbacks* pAllocator,
1349 VkPipeline* pPipeline)
1350 {
1351 ANV_FROM_HANDLE(anv_device, device, _device);
1352 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
1353
1354 if (cache == NULL)
1355 cache = &device->default_pipeline_cache;
1356
1357 switch (device->info.gen) {
1358 case 7:
1359 if (device->info.is_haswell)
1360 return gen75_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1361 else
1362 return gen7_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1363 case 8:
1364 return gen8_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1365 case 9:
1366 return gen9_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1367 default:
1368 unreachable("unsupported gen\n");
1369 }
1370 }
1371
1372 VkResult anv_CreateComputePipelines(
1373 VkDevice _device,
1374 VkPipelineCache pipelineCache,
1375 uint32_t count,
1376 const VkComputePipelineCreateInfo* pCreateInfos,
1377 const VkAllocationCallbacks* pAllocator,
1378 VkPipeline* pPipelines)
1379 {
1380 VkResult result = VK_SUCCESS;
1381
1382 unsigned i = 0;
1383 for (; i < count; i++) {
1384 result = anv_compute_pipeline_create(_device, pipelineCache,
1385 &pCreateInfos[i],
1386 pAllocator, &pPipelines[i]);
1387 if (result != VK_SUCCESS) {
1388 for (unsigned j = 0; j < i; j++) {
1389 anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1390 }
1391
1392 return result;
1393 }
1394 }
1395
1396 return VK_SUCCESS;
1397 }