2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "common/gen_l3_config.h"
32 #include "anv_private.h"
33 #include "compiler/brw_nir.h"
35 #include "spirv/nir_spirv.h"
37 /* Needed for SWIZZLE macros */
38 #include "program/prog_instruction.h"
42 VkResult
anv_CreateShaderModule(
44 const VkShaderModuleCreateInfo
* pCreateInfo
,
45 const VkAllocationCallbacks
* pAllocator
,
46 VkShaderModule
* pShaderModule
)
48 ANV_FROM_HANDLE(anv_device
, device
, _device
);
49 struct anv_shader_module
*module
;
51 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
52 assert(pCreateInfo
->flags
== 0);
54 module
= vk_alloc2(&device
->alloc
, pAllocator
,
55 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
56 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
58 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
60 module
->size
= pCreateInfo
->codeSize
;
61 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
63 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
65 *pShaderModule
= anv_shader_module_to_handle(module
);
70 void anv_DestroyShaderModule(
72 VkShaderModule _module
,
73 const VkAllocationCallbacks
* pAllocator
)
75 ANV_FROM_HANDLE(anv_device
, device
, _device
);
76 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
81 vk_free2(&device
->alloc
, pAllocator
, module
);
84 #define SPIR_V_MAGIC_NUMBER 0x07230203
86 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
87 * we can't do that yet because we don't have the ability to copy nir.
90 anv_shader_compile_to_nir(struct anv_device
*device
,
91 struct anv_shader_module
*module
,
92 const char *entrypoint_name
,
93 gl_shader_stage stage
,
94 const VkSpecializationInfo
*spec_info
)
96 const struct brw_compiler
*compiler
=
97 device
->instance
->physicalDevice
.compiler
;
98 const nir_shader_compiler_options
*nir_options
=
99 compiler
->glsl_compiler_options
[stage
].NirOptions
;
101 uint32_t *spirv
= (uint32_t *) module
->data
;
102 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
103 assert(module
->size
% 4 == 0);
105 uint32_t num_spec_entries
= 0;
106 struct nir_spirv_specialization
*spec_entries
= NULL
;
107 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
108 num_spec_entries
= spec_info
->mapEntryCount
;
109 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
110 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
111 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
112 const void *data
= spec_info
->pData
+ entry
.offset
;
113 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
115 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
116 if (spec_info
->dataSize
== 8)
117 spec_entries
[i
].data64
= *(const uint64_t *)data
;
119 spec_entries
[i
].data32
= *(const uint32_t *)data
;
123 const struct nir_spirv_supported_extensions supported_ext
= {
124 .float64
= device
->instance
->physicalDevice
.info
.gen
>= 8,
125 .int64
= device
->instance
->physicalDevice
.info
.gen
>= 8,
126 .tessellation
= true,
127 .draw_parameters
= true,
128 .image_write_without_format
= true,
131 nir_function
*entry_point
=
132 spirv_to_nir(spirv
, module
->size
/ 4,
133 spec_entries
, num_spec_entries
,
134 stage
, entrypoint_name
, &supported_ext
, nir_options
);
135 nir_shader
*nir
= entry_point
->shader
;
136 assert(nir
->stage
== stage
);
137 nir_validate_shader(nir
);
141 /* We have to lower away local constant initializers right before we
142 * inline functions. That way they get properly initialized at the top
143 * of the function and not at the top of its caller.
145 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_local
);
146 NIR_PASS_V(nir
, nir_lower_returns
);
147 NIR_PASS_V(nir
, nir_inline_functions
);
149 /* Pick off the single entrypoint that we want */
150 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
151 if (func
!= entry_point
)
152 exec_node_remove(&func
->node
);
154 assert(exec_list_length(&nir
->functions
) == 1);
155 entry_point
->name
= ralloc_strdup(entry_point
, "main");
157 NIR_PASS_V(nir
, nir_remove_dead_variables
,
158 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
160 if (stage
== MESA_SHADER_FRAGMENT
)
161 NIR_PASS_V(nir
, nir_lower_wpos_center
);
163 /* Now that we've deleted all but the main function, we can go ahead and
164 * lower the rest of the constant initializers.
166 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
167 NIR_PASS_V(nir
, nir_propagate_invariant
);
168 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
169 entry_point
->impl
, true, false);
170 NIR_PASS_V(nir
, nir_lower_system_values
);
172 /* Vulkan uses the separate-shader linking model */
173 nir
->info
->separate_shader
= true;
175 nir
= brw_preprocess_nir(compiler
, nir
);
177 NIR_PASS_V(nir
, nir_lower_clip_cull_distance_arrays
);
179 if (stage
== MESA_SHADER_FRAGMENT
)
180 NIR_PASS_V(nir
, anv_nir_lower_input_attachments
);
182 nir_shader_gather_info(nir
, entry_point
->impl
);
187 void anv_DestroyPipeline(
189 VkPipeline _pipeline
,
190 const VkAllocationCallbacks
* pAllocator
)
192 ANV_FROM_HANDLE(anv_device
, device
, _device
);
193 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
198 anv_reloc_list_finish(&pipeline
->batch_relocs
,
199 pAllocator
? pAllocator
: &device
->alloc
);
200 if (pipeline
->blend_state
.map
)
201 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
203 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
204 if (pipeline
->shaders
[s
])
205 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
208 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
211 static const uint32_t vk_to_gen_primitive_type
[] = {
212 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
213 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
214 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
215 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
216 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
217 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
218 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
219 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
220 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
221 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
225 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
226 struct brw_sampler_prog_key_data
*key
)
228 /* Almost all multisampled textures are compressed. The only time when we
229 * don't compress a multisampled texture is for 16x MSAA with a surface
230 * width greater than 8k which is a bit of an edge case. Since the sampler
231 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
232 * to tell the compiler to always assume compression.
234 key
->compressed_multisample_layout_mask
= ~0;
236 /* SkyLake added support for 16x MSAA. With this came a new message for
237 * reading from a 16x MSAA surface with compression. The new message was
238 * needed because now the MCS data is 64 bits instead of 32 or lower as is
239 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
240 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
241 * so we can just use it unconditionally. This may not be quite as
242 * efficient but it saves us from recompiling.
244 if (devinfo
->gen
>= 9)
247 /* XXX: Handle texture swizzle on HSW- */
248 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
249 /* Assume color sampler, no swizzling. (Works for BDW+) */
250 key
->swizzles
[i
] = SWIZZLE_XYZW
;
255 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
256 struct brw_vs_prog_key
*key
)
258 memset(key
, 0, sizeof(*key
));
260 populate_sampler_prog_key(devinfo
, &key
->tex
);
262 /* XXX: Handle vertex input work-arounds */
264 /* XXX: Handle sampler_prog_key */
268 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
269 struct brw_gs_prog_key
*key
)
271 memset(key
, 0, sizeof(*key
));
273 populate_sampler_prog_key(devinfo
, &key
->tex
);
277 populate_wm_prog_key(const struct anv_pipeline
*pipeline
,
278 const VkGraphicsPipelineCreateInfo
*info
,
279 struct brw_wm_prog_key
*key
)
281 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
282 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, info
->renderPass
);
284 memset(key
, 0, sizeof(*key
));
286 populate_sampler_prog_key(devinfo
, &key
->tex
);
288 /* TODO: we could set this to 0 based on the information in nir_shader, but
289 * this function is called before spirv_to_nir. */
290 const struct brw_vue_map
*vue_map
=
291 &anv_pipeline_get_last_vue_prog_data(pipeline
)->vue_map
;
292 key
->input_slots_valid
= vue_map
->slots_valid
;
294 /* Vulkan doesn't specify a default */
295 key
->high_quality_derivatives
= false;
297 /* XXX Vulkan doesn't appear to specify */
298 key
->clamp_fragment_color
= false;
300 key
->nr_color_regions
=
301 render_pass
->subpasses
[info
->subpass
].color_count
;
303 key
->replicate_alpha
= key
->nr_color_regions
> 1 &&
304 info
->pMultisampleState
&&
305 info
->pMultisampleState
->alphaToCoverageEnable
;
307 if (info
->pMultisampleState
&& info
->pMultisampleState
->rasterizationSamples
> 1) {
308 /* We should probably pull this out of the shader, but it's fairly
309 * harmless to compute it and then let dead-code take care of it.
311 key
->persample_interp
=
312 (info
->pMultisampleState
->minSampleShading
*
313 info
->pMultisampleState
->rasterizationSamples
) > 1;
314 key
->multisample_fbo
= true;
319 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
320 struct brw_cs_prog_key
*key
)
322 memset(key
, 0, sizeof(*key
));
324 populate_sampler_prog_key(devinfo
, &key
->tex
);
328 anv_pipeline_compile(struct anv_pipeline
*pipeline
,
329 struct anv_shader_module
*module
,
330 const char *entrypoint
,
331 gl_shader_stage stage
,
332 const VkSpecializationInfo
*spec_info
,
333 struct brw_stage_prog_data
*prog_data
,
334 struct anv_pipeline_bind_map
*map
)
336 nir_shader
*nir
= anv_shader_compile_to_nir(pipeline
->device
,
337 module
, entrypoint
, stage
,
342 NIR_PASS_V(nir
, anv_nir_lower_push_constants
);
344 /* Figure out the number of parameters */
345 prog_data
->nr_params
= 0;
347 if (nir
->num_uniforms
> 0) {
348 /* If the shader uses any push constants at all, we'll just give
349 * them the maximum possible number
351 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
352 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
355 if (nir
->info
->num_images
> 0) {
356 prog_data
->nr_params
+= nir
->info
->num_images
* BRW_IMAGE_PARAM_SIZE
;
357 pipeline
->needs_data_cache
= true;
360 if (stage
== MESA_SHADER_COMPUTE
)
361 ((struct brw_cs_prog_data
*)prog_data
)->thread_local_id_index
=
362 prog_data
->nr_params
++; /* The CS Thread ID uniform */
364 if (nir
->info
->num_ssbos
> 0)
365 pipeline
->needs_data_cache
= true;
367 if (prog_data
->nr_params
> 0) {
368 /* XXX: I think we're leaking this */
369 prog_data
->param
= (const union gl_constant_value
**)
370 malloc(prog_data
->nr_params
* sizeof(union gl_constant_value
*));
372 /* We now set the param values to be offsets into a
373 * anv_push_constant_data structure. Since the compiler doesn't
374 * actually dereference any of the gl_constant_value pointers in the
375 * params array, it doesn't really matter what we put here.
377 struct anv_push_constants
*null_data
= NULL
;
378 if (nir
->num_uniforms
> 0) {
379 /* Fill out the push constants section of the param array */
380 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++)
381 prog_data
->param
[i
] = (const union gl_constant_value
*)
382 &null_data
->client_data
[i
* sizeof(float)];
386 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
387 if (pipeline
->layout
)
388 anv_nir_apply_pipeline_layout(pipeline
, nir
, prog_data
, map
);
390 /* nir_lower_io will only handle the push constants; we need to set this
391 * to the full number of possible uniforms.
393 nir
->num_uniforms
= prog_data
->nr_params
* 4;
399 anv_fill_binding_table(struct brw_stage_prog_data
*prog_data
, unsigned bias
)
401 prog_data
->binding_table
.size_bytes
= 0;
402 prog_data
->binding_table
.texture_start
= bias
;
403 prog_data
->binding_table
.gather_texture_start
= bias
;
404 prog_data
->binding_table
.ubo_start
= bias
;
405 prog_data
->binding_table
.ssbo_start
= bias
;
406 prog_data
->binding_table
.image_start
= bias
;
409 static struct anv_shader_bin
*
410 anv_pipeline_upload_kernel(struct anv_pipeline
*pipeline
,
411 struct anv_pipeline_cache
*cache
,
412 const void *key_data
, uint32_t key_size
,
413 const void *kernel_data
, uint32_t kernel_size
,
414 const struct brw_stage_prog_data
*prog_data
,
415 uint32_t prog_data_size
,
416 const struct anv_pipeline_bind_map
*bind_map
)
419 return anv_pipeline_cache_upload_kernel(cache
, key_data
, key_size
,
420 kernel_data
, kernel_size
,
421 prog_data
, prog_data_size
,
424 return anv_shader_bin_create(pipeline
->device
, key_data
, key_size
,
425 kernel_data
, kernel_size
,
426 prog_data
, prog_data_size
,
427 prog_data
->param
, bind_map
);
433 anv_pipeline_add_compiled_stage(struct anv_pipeline
*pipeline
,
434 gl_shader_stage stage
,
435 struct anv_shader_bin
*shader
)
437 pipeline
->shaders
[stage
] = shader
;
438 pipeline
->active_stages
|= mesa_to_vk_shader_stage(stage
);
442 anv_pipeline_compile_vs(struct anv_pipeline
*pipeline
,
443 struct anv_pipeline_cache
*cache
,
444 const VkGraphicsPipelineCreateInfo
*info
,
445 struct anv_shader_module
*module
,
446 const char *entrypoint
,
447 const VkSpecializationInfo
*spec_info
)
449 const struct brw_compiler
*compiler
=
450 pipeline
->device
->instance
->physicalDevice
.compiler
;
451 struct anv_pipeline_bind_map map
;
452 struct brw_vs_prog_key key
;
453 struct anv_shader_bin
*bin
= NULL
;
454 unsigned char sha1
[20];
456 populate_vs_prog_key(&pipeline
->device
->info
, &key
);
459 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
,
460 pipeline
->layout
, spec_info
);
461 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
465 struct brw_vs_prog_data prog_data
= { 0, };
466 struct anv_pipeline_binding surface_to_descriptor
[256];
467 struct anv_pipeline_binding sampler_to_descriptor
[256];
469 map
= (struct anv_pipeline_bind_map
) {
470 .surface_to_descriptor
= surface_to_descriptor
,
471 .sampler_to_descriptor
= sampler_to_descriptor
474 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
475 MESA_SHADER_VERTEX
, spec_info
,
476 &prog_data
.base
.base
, &map
);
478 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
480 anv_fill_binding_table(&prog_data
.base
.base
, 0);
482 void *mem_ctx
= ralloc_context(NULL
);
484 ralloc_steal(mem_ctx
, nir
);
486 prog_data
.inputs_read
= nir
->info
->inputs_read
;
487 prog_data
.double_inputs_read
= nir
->info
->double_inputs_read
;
489 brw_compute_vue_map(&pipeline
->device
->info
,
490 &prog_data
.base
.vue_map
,
491 nir
->info
->outputs_written
,
492 nir
->info
->separate_shader
);
495 const unsigned *shader_code
=
496 brw_compile_vs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
497 NULL
, false, -1, &code_size
, NULL
);
498 if (shader_code
== NULL
) {
499 ralloc_free(mem_ctx
);
500 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
503 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
504 shader_code
, code_size
,
505 &prog_data
.base
.base
, sizeof(prog_data
),
508 ralloc_free(mem_ctx
);
509 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
512 ralloc_free(mem_ctx
);
515 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_VERTEX
, bin
);
521 merge_tess_info(struct shader_info
*tes_info
,
522 const struct shader_info
*tcs_info
)
524 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
526 * "PointMode. Controls generation of points rather than triangles
527 * or lines. This functionality defaults to disabled, and is
528 * enabled if either shader stage includes the execution mode.
530 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
531 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
532 * and OutputVertices, it says:
534 * "One mode must be set in at least one of the tessellation
537 * So, the fields can be set in either the TCS or TES, but they must
538 * agree if set in both. Our backend looks at TES, so bitwise-or in
539 * the values from the TCS.
541 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
542 tes_info
->tess
.tcs_vertices_out
== 0 ||
543 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
544 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
546 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
547 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
548 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
549 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
551 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
552 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
556 anv_pipeline_compile_tcs_tes(struct anv_pipeline
*pipeline
,
557 struct anv_pipeline_cache
*cache
,
558 const VkGraphicsPipelineCreateInfo
*info
,
559 struct anv_shader_module
*tcs_module
,
560 const char *tcs_entrypoint
,
561 const VkSpecializationInfo
*tcs_spec_info
,
562 struct anv_shader_module
*tes_module
,
563 const char *tes_entrypoint
,
564 const VkSpecializationInfo
*tes_spec_info
)
566 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
567 const struct brw_compiler
*compiler
=
568 pipeline
->device
->instance
->physicalDevice
.compiler
;
569 struct anv_pipeline_bind_map tcs_map
;
570 struct anv_pipeline_bind_map tes_map
;
571 struct brw_tcs_prog_key tcs_key
= { 0, };
572 struct brw_tes_prog_key tes_key
= { 0, };
573 struct anv_shader_bin
*tcs_bin
= NULL
;
574 struct anv_shader_bin
*tes_bin
= NULL
;
575 unsigned char tcs_sha1
[40];
576 unsigned char tes_sha1
[40];
578 populate_sampler_prog_key(&pipeline
->device
->info
, &tcs_key
.tex
);
579 populate_sampler_prog_key(&pipeline
->device
->info
, &tes_key
.tex
);
580 tcs_key
.input_vertices
= info
->pTessellationState
->patchControlPoints
;
583 anv_hash_shader(tcs_sha1
, &tcs_key
, sizeof(tcs_key
), tcs_module
,
584 tcs_entrypoint
, pipeline
->layout
, tcs_spec_info
);
585 anv_hash_shader(tes_sha1
, &tes_key
, sizeof(tes_key
), tes_module
,
586 tes_entrypoint
, pipeline
->layout
, tes_spec_info
);
587 memcpy(&tcs_sha1
[20], tes_sha1
, 20);
588 memcpy(&tes_sha1
[20], tcs_sha1
, 20);
589 tcs_bin
= anv_pipeline_cache_search(cache
, tcs_sha1
, sizeof(tcs_sha1
));
590 tes_bin
= anv_pipeline_cache_search(cache
, tes_sha1
, sizeof(tes_sha1
));
593 if (tcs_bin
== NULL
|| tes_bin
== NULL
) {
594 struct brw_tcs_prog_data tcs_prog_data
= { 0, };
595 struct brw_tes_prog_data tes_prog_data
= { 0, };
596 struct anv_pipeline_binding tcs_surface_to_descriptor
[256];
597 struct anv_pipeline_binding tcs_sampler_to_descriptor
[256];
598 struct anv_pipeline_binding tes_surface_to_descriptor
[256];
599 struct anv_pipeline_binding tes_sampler_to_descriptor
[256];
601 tcs_map
= (struct anv_pipeline_bind_map
) {
602 .surface_to_descriptor
= tcs_surface_to_descriptor
,
603 .sampler_to_descriptor
= tcs_sampler_to_descriptor
605 tes_map
= (struct anv_pipeline_bind_map
) {
606 .surface_to_descriptor
= tes_surface_to_descriptor
,
607 .sampler_to_descriptor
= tes_sampler_to_descriptor
610 nir_shader
*tcs_nir
=
611 anv_pipeline_compile(pipeline
, tcs_module
, tcs_entrypoint
,
612 MESA_SHADER_TESS_CTRL
, tcs_spec_info
,
613 &tcs_prog_data
.base
.base
, &tcs_map
);
614 nir_shader
*tes_nir
=
615 anv_pipeline_compile(pipeline
, tes_module
, tes_entrypoint
,
616 MESA_SHADER_TESS_EVAL
, tes_spec_info
,
617 &tes_prog_data
.base
.base
, &tes_map
);
618 if (tcs_nir
== NULL
|| tes_nir
== NULL
)
619 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
621 nir_lower_tes_patch_vertices(tes_nir
,
622 tcs_nir
->info
->tess
.tcs_vertices_out
);
624 /* Copy TCS info into the TES info */
625 merge_tess_info(tes_nir
->info
, tcs_nir
->info
);
627 anv_fill_binding_table(&tcs_prog_data
.base
.base
, 0);
628 anv_fill_binding_table(&tes_prog_data
.base
.base
, 0);
630 void *mem_ctx
= ralloc_context(NULL
);
632 ralloc_steal(mem_ctx
, tcs_nir
);
633 ralloc_steal(mem_ctx
, tes_nir
);
635 /* Whacking the key after cache lookup is a bit sketchy, but all of
636 * this comes from the SPIR-V, which is part of the hash used for the
637 * pipeline cache. So it should be safe.
639 tcs_key
.tes_primitive_mode
= tes_nir
->info
->tess
.primitive_mode
;
640 tcs_key
.outputs_written
= tcs_nir
->info
->outputs_written
;
641 tcs_key
.patch_outputs_written
= tcs_nir
->info
->patch_outputs_written
;
642 tcs_key
.quads_workaround
=
644 tes_nir
->info
->tess
.primitive_mode
== 7 /* GL_QUADS */ &&
645 tes_nir
->info
->tess
.spacing
== TESS_SPACING_EQUAL
;
647 tes_key
.inputs_read
= tcs_key
.outputs_written
;
648 tes_key
.patch_inputs_read
= tcs_key
.patch_outputs_written
;
651 const int shader_time_index
= -1;
652 const unsigned *shader_code
;
655 brw_compile_tcs(compiler
, NULL
, mem_ctx
, &tcs_key
, &tcs_prog_data
,
656 tcs_nir
, shader_time_index
, &code_size
, NULL
);
657 if (shader_code
== NULL
) {
658 ralloc_free(mem_ctx
);
659 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
662 tcs_bin
= anv_pipeline_upload_kernel(pipeline
, cache
,
663 tcs_sha1
, sizeof(tcs_sha1
),
664 shader_code
, code_size
,
665 &tcs_prog_data
.base
.base
,
666 sizeof(tcs_prog_data
),
669 ralloc_free(mem_ctx
);
670 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
674 brw_compile_tes(compiler
, NULL
, mem_ctx
, &tes_key
,
675 &tcs_prog_data
.base
.vue_map
, &tes_prog_data
, tes_nir
,
676 NULL
, shader_time_index
, &code_size
, NULL
);
677 if (shader_code
== NULL
) {
678 ralloc_free(mem_ctx
);
679 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
682 tes_bin
= anv_pipeline_upload_kernel(pipeline
, cache
,
683 tes_sha1
, sizeof(tes_sha1
),
684 shader_code
, code_size
,
685 &tes_prog_data
.base
.base
,
686 sizeof(tes_prog_data
),
689 ralloc_free(mem_ctx
);
690 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
693 ralloc_free(mem_ctx
);
696 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_TESS_CTRL
, tcs_bin
);
697 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_TESS_EVAL
, tes_bin
);
703 anv_pipeline_compile_gs(struct anv_pipeline
*pipeline
,
704 struct anv_pipeline_cache
*cache
,
705 const VkGraphicsPipelineCreateInfo
*info
,
706 struct anv_shader_module
*module
,
707 const char *entrypoint
,
708 const VkSpecializationInfo
*spec_info
)
710 const struct brw_compiler
*compiler
=
711 pipeline
->device
->instance
->physicalDevice
.compiler
;
712 struct anv_pipeline_bind_map map
;
713 struct brw_gs_prog_key key
;
714 struct anv_shader_bin
*bin
= NULL
;
715 unsigned char sha1
[20];
717 populate_gs_prog_key(&pipeline
->device
->info
, &key
);
720 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
,
721 pipeline
->layout
, spec_info
);
722 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
726 struct brw_gs_prog_data prog_data
= { 0, };
727 struct anv_pipeline_binding surface_to_descriptor
[256];
728 struct anv_pipeline_binding sampler_to_descriptor
[256];
730 map
= (struct anv_pipeline_bind_map
) {
731 .surface_to_descriptor
= surface_to_descriptor
,
732 .sampler_to_descriptor
= sampler_to_descriptor
735 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
736 MESA_SHADER_GEOMETRY
, spec_info
,
737 &prog_data
.base
.base
, &map
);
739 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
741 anv_fill_binding_table(&prog_data
.base
.base
, 0);
743 void *mem_ctx
= ralloc_context(NULL
);
745 ralloc_steal(mem_ctx
, nir
);
747 brw_compute_vue_map(&pipeline
->device
->info
,
748 &prog_data
.base
.vue_map
,
749 nir
->info
->outputs_written
,
750 nir
->info
->separate_shader
);
753 const unsigned *shader_code
=
754 brw_compile_gs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
755 NULL
, -1, &code_size
, NULL
);
756 if (shader_code
== NULL
) {
757 ralloc_free(mem_ctx
);
758 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
762 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
763 shader_code
, code_size
,
764 &prog_data
.base
.base
, sizeof(prog_data
),
767 ralloc_free(mem_ctx
);
768 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
771 ralloc_free(mem_ctx
);
774 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_GEOMETRY
, bin
);
780 anv_pipeline_compile_fs(struct anv_pipeline
*pipeline
,
781 struct anv_pipeline_cache
*cache
,
782 const VkGraphicsPipelineCreateInfo
*info
,
783 struct anv_shader_module
*module
,
784 const char *entrypoint
,
785 const VkSpecializationInfo
*spec_info
)
787 const struct brw_compiler
*compiler
=
788 pipeline
->device
->instance
->physicalDevice
.compiler
;
789 struct anv_pipeline_bind_map map
;
790 struct brw_wm_prog_key key
;
791 struct anv_shader_bin
*bin
= NULL
;
792 unsigned char sha1
[20];
794 populate_wm_prog_key(pipeline
, info
, &key
);
797 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
,
798 pipeline
->layout
, spec_info
);
799 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
803 struct brw_wm_prog_data prog_data
= { 0, };
804 struct anv_pipeline_binding surface_to_descriptor
[256];
805 struct anv_pipeline_binding sampler_to_descriptor
[256];
807 map
= (struct anv_pipeline_bind_map
) {
808 .surface_to_descriptor
= surface_to_descriptor
+ 8,
809 .sampler_to_descriptor
= sampler_to_descriptor
812 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
813 MESA_SHADER_FRAGMENT
, spec_info
,
814 &prog_data
.base
, &map
);
816 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
818 unsigned num_rts
= 0;
819 struct anv_pipeline_binding rt_bindings
[8];
820 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
821 nir_foreach_variable_safe(var
, &nir
->outputs
) {
822 if (var
->data
.location
< FRAG_RESULT_DATA0
)
825 unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
826 if (rt
>= key
.nr_color_regions
) {
827 /* Out-of-bounds, throw it away */
828 var
->data
.mode
= nir_var_local
;
829 exec_node_remove(&var
->node
);
830 exec_list_push_tail(&impl
->locals
, &var
->node
);
834 /* Give it a new, compacted, location */
835 var
->data
.location
= FRAG_RESULT_DATA0
+ num_rts
;
838 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
839 assert(num_rts
+ array_len
<= 8);
841 for (unsigned i
= 0; i
< array_len
; i
++) {
842 rt_bindings
[num_rts
+ i
] = (struct anv_pipeline_binding
) {
843 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
849 num_rts
+= array_len
;
853 /* If we have no render targets, we need a null render target */
854 rt_bindings
[0] = (struct anv_pipeline_binding
) {
855 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
862 assert(num_rts
<= 8);
863 map
.surface_to_descriptor
-= num_rts
;
864 map
.surface_count
+= num_rts
;
865 assert(map
.surface_count
<= 256);
866 memcpy(map
.surface_to_descriptor
, rt_bindings
,
867 num_rts
* sizeof(*rt_bindings
));
869 anv_fill_binding_table(&prog_data
.base
, num_rts
);
871 void *mem_ctx
= ralloc_context(NULL
);
873 ralloc_steal(mem_ctx
, nir
);
876 const unsigned *shader_code
=
877 brw_compile_fs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
878 NULL
, -1, -1, true, false, NULL
, &code_size
, NULL
);
879 if (shader_code
== NULL
) {
880 ralloc_free(mem_ctx
);
881 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
884 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
885 shader_code
, code_size
,
886 &prog_data
.base
, sizeof(prog_data
),
889 ralloc_free(mem_ctx
);
890 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
893 ralloc_free(mem_ctx
);
896 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_FRAGMENT
, bin
);
902 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
903 struct anv_pipeline_cache
*cache
,
904 const VkComputePipelineCreateInfo
*info
,
905 struct anv_shader_module
*module
,
906 const char *entrypoint
,
907 const VkSpecializationInfo
*spec_info
)
909 const struct brw_compiler
*compiler
=
910 pipeline
->device
->instance
->physicalDevice
.compiler
;
911 struct anv_pipeline_bind_map map
;
912 struct brw_cs_prog_key key
;
913 struct anv_shader_bin
*bin
= NULL
;
914 unsigned char sha1
[20];
916 populate_cs_prog_key(&pipeline
->device
->info
, &key
);
919 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
,
920 pipeline
->layout
, spec_info
);
921 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
925 struct brw_cs_prog_data prog_data
= { 0, };
926 struct anv_pipeline_binding surface_to_descriptor
[256];
927 struct anv_pipeline_binding sampler_to_descriptor
[256];
929 map
= (struct anv_pipeline_bind_map
) {
930 .surface_to_descriptor
= surface_to_descriptor
,
931 .sampler_to_descriptor
= sampler_to_descriptor
934 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
935 MESA_SHADER_COMPUTE
, spec_info
,
936 &prog_data
.base
, &map
);
938 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
940 anv_fill_binding_table(&prog_data
.base
, 1);
942 void *mem_ctx
= ralloc_context(NULL
);
944 ralloc_steal(mem_ctx
, nir
);
947 const unsigned *shader_code
=
948 brw_compile_cs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
949 -1, &code_size
, NULL
);
950 if (shader_code
== NULL
) {
951 ralloc_free(mem_ctx
);
952 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
955 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
956 shader_code
, code_size
,
957 &prog_data
.base
, sizeof(prog_data
),
960 ralloc_free(mem_ctx
);
961 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
964 ralloc_free(mem_ctx
);
967 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_COMPUTE
, bin
);
973 * Copy pipeline state not marked as dynamic.
974 * Dynamic state is pipeline state which hasn't been provided at pipeline
975 * creation time, but is dynamically provided afterwards using various
976 * vkCmdSet* functions.
978 * The set of state considered "non_dynamic" is determined by the pieces of
979 * state that have their corresponding VkDynamicState enums omitted from
980 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
982 * @param[out] pipeline Destination non_dynamic state.
983 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
986 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
987 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
989 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
990 ANV_FROM_HANDLE(anv_render_pass
, pass
, pCreateInfo
->renderPass
);
991 struct anv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
993 pipeline
->dynamic_state
= default_dynamic_state
;
995 if (pCreateInfo
->pDynamicState
) {
996 /* Remove all of the states that are marked as dynamic */
997 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
998 for (uint32_t s
= 0; s
< count
; s
++)
999 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1002 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1004 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1006 * pViewportState is [...] NULL if the pipeline
1007 * has rasterization disabled.
1009 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1010 assert(pCreateInfo
->pViewportState
);
1012 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1013 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
1014 typed_memcpy(dynamic
->viewport
.viewports
,
1015 pCreateInfo
->pViewportState
->pViewports
,
1016 pCreateInfo
->pViewportState
->viewportCount
);
1019 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1020 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
1021 typed_memcpy(dynamic
->scissor
.scissors
,
1022 pCreateInfo
->pViewportState
->pScissors
,
1023 pCreateInfo
->pViewportState
->scissorCount
);
1027 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1028 assert(pCreateInfo
->pRasterizationState
);
1029 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1032 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1033 assert(pCreateInfo
->pRasterizationState
);
1034 dynamic
->depth_bias
.bias
=
1035 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1036 dynamic
->depth_bias
.clamp
=
1037 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1038 dynamic
->depth_bias
.slope
=
1039 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1042 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1044 * pColorBlendState is [...] NULL if the pipeline has rasterization
1045 * disabled or if the subpass of the render pass the pipeline is
1046 * created against does not use any color attachments.
1048 bool uses_color_att
= false;
1049 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1050 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1051 uses_color_att
= true;
1056 if (uses_color_att
&&
1057 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1058 assert(pCreateInfo
->pColorBlendState
);
1060 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
1061 typed_memcpy(dynamic
->blend_constants
,
1062 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1065 /* If there is no depthstencil attachment, then don't read
1066 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1067 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1068 * no need to override the depthstencil defaults in
1069 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1071 * Section 9.2 of the Vulkan 1.0.15 spec says:
1073 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1074 * disabled or if the subpass of the render pass the pipeline is created
1075 * against does not use a depth/stencil attachment.
1077 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1078 subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1079 assert(pCreateInfo
->pDepthStencilState
);
1081 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1082 dynamic
->depth_bounds
.min
=
1083 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1084 dynamic
->depth_bounds
.max
=
1085 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1088 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1089 dynamic
->stencil_compare_mask
.front
=
1090 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1091 dynamic
->stencil_compare_mask
.back
=
1092 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1095 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1096 dynamic
->stencil_write_mask
.front
=
1097 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1098 dynamic
->stencil_write_mask
.back
=
1099 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1102 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1103 dynamic
->stencil_reference
.front
=
1104 pCreateInfo
->pDepthStencilState
->front
.reference
;
1105 dynamic
->stencil_reference
.back
=
1106 pCreateInfo
->pDepthStencilState
->back
.reference
;
1110 pipeline
->dynamic_state_mask
= states
;
1114 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1117 struct anv_render_pass
*renderpass
= NULL
;
1118 struct anv_subpass
*subpass
= NULL
;
1120 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1121 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1123 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1125 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1128 assert(info
->subpass
< renderpass
->subpass_count
);
1129 subpass
= &renderpass
->subpasses
[info
->subpass
];
1131 assert(info
->stageCount
>= 1);
1132 assert(info
->pVertexInputState
);
1133 assert(info
->pInputAssemblyState
);
1134 assert(info
->pRasterizationState
);
1135 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1136 assert(info
->pViewportState
);
1137 assert(info
->pMultisampleState
);
1139 if (subpass
&& subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
)
1140 assert(info
->pDepthStencilState
);
1142 if (subpass
&& subpass
->color_count
> 0)
1143 assert(info
->pColorBlendState
);
1146 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1147 switch (info
->pStages
[i
].stage
) {
1148 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1149 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1150 assert(info
->pTessellationState
);
1160 * Calculate the desired L3 partitioning based on the current state of the
1161 * pipeline. For now this simply returns the conservative defaults calculated
1162 * by get_default_l3_weights(), but we could probably do better by gathering
1163 * more statistics from the pipeline state (e.g. guess of expected URB usage
1164 * and bound surfaces), or by using feed-back from performance counters.
1167 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1169 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1171 const struct gen_l3_weights w
=
1172 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
1174 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
1175 pipeline
->urb
.total_size
=
1176 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
1180 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1181 struct anv_device
*device
,
1182 struct anv_pipeline_cache
*cache
,
1183 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1184 const VkAllocationCallbacks
*alloc
)
1188 anv_pipeline_validate_create_info(pCreateInfo
);
1191 alloc
= &device
->alloc
;
1193 pipeline
->device
= device
;
1194 pipeline
->layout
= anv_pipeline_layout_from_handle(pCreateInfo
->layout
);
1196 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1197 if (result
!= VK_SUCCESS
)
1200 pipeline
->batch
.alloc
= alloc
;
1201 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1202 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1203 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1205 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1206 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1207 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1209 pipeline
->needs_data_cache
= false;
1211 /* When we free the pipeline, we detect stages based on the NULL status
1212 * of various prog_data pointers. Make them NULL by default.
1214 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1216 pipeline
->active_stages
= 0;
1218 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
1219 struct anv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
1220 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
1221 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
1222 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
1223 modules
[stage
] = anv_shader_module_from_handle(pStages
[stage
]->module
);
1226 if (modules
[MESA_SHADER_VERTEX
]) {
1227 result
= anv_pipeline_compile_vs(pipeline
, cache
, pCreateInfo
,
1228 modules
[MESA_SHADER_VERTEX
],
1229 pStages
[MESA_SHADER_VERTEX
]->pName
,
1230 pStages
[MESA_SHADER_VERTEX
]->pSpecializationInfo
);
1231 if (result
!= VK_SUCCESS
)
1235 if (modules
[MESA_SHADER_TESS_EVAL
]) {
1236 anv_pipeline_compile_tcs_tes(pipeline
, cache
, pCreateInfo
,
1237 modules
[MESA_SHADER_TESS_CTRL
],
1238 pStages
[MESA_SHADER_TESS_CTRL
]->pName
,
1239 pStages
[MESA_SHADER_TESS_CTRL
]->pSpecializationInfo
,
1240 modules
[MESA_SHADER_TESS_EVAL
],
1241 pStages
[MESA_SHADER_TESS_EVAL
]->pName
,
1242 pStages
[MESA_SHADER_TESS_EVAL
]->pSpecializationInfo
);
1245 if (modules
[MESA_SHADER_GEOMETRY
]) {
1246 result
= anv_pipeline_compile_gs(pipeline
, cache
, pCreateInfo
,
1247 modules
[MESA_SHADER_GEOMETRY
],
1248 pStages
[MESA_SHADER_GEOMETRY
]->pName
,
1249 pStages
[MESA_SHADER_GEOMETRY
]->pSpecializationInfo
);
1250 if (result
!= VK_SUCCESS
)
1254 if (modules
[MESA_SHADER_FRAGMENT
]) {
1255 result
= anv_pipeline_compile_fs(pipeline
, cache
, pCreateInfo
,
1256 modules
[MESA_SHADER_FRAGMENT
],
1257 pStages
[MESA_SHADER_FRAGMENT
]->pName
,
1258 pStages
[MESA_SHADER_FRAGMENT
]->pSpecializationInfo
);
1259 if (result
!= VK_SUCCESS
)
1263 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1265 anv_pipeline_setup_l3_config(pipeline
, false);
1267 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1268 pCreateInfo
->pVertexInputState
;
1270 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1272 pipeline
->vb_used
= 0;
1273 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1274 const VkVertexInputAttributeDescription
*desc
=
1275 &vi_info
->pVertexAttributeDescriptions
[i
];
1277 if (inputs_read
& (1 << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1278 pipeline
->vb_used
|= 1 << desc
->binding
;
1281 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1282 const VkVertexInputBindingDescription
*desc
=
1283 &vi_info
->pVertexBindingDescriptions
[i
];
1285 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
1287 /* Step rate is programmed per vertex element (attribute), not
1288 * binding. Set up a map of which bindings step per instance, for
1289 * reference by vertex element setup. */
1290 switch (desc
->inputRate
) {
1292 case VK_VERTEX_INPUT_RATE_VERTEX
:
1293 pipeline
->instancing_enable
[desc
->binding
] = false;
1295 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1296 pipeline
->instancing_enable
[desc
->binding
] = true;
1301 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1302 pCreateInfo
->pInputAssemblyState
;
1303 const VkPipelineTessellationStateCreateInfo
*tess_info
=
1304 pCreateInfo
->pTessellationState
;
1305 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1307 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1308 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
1310 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];
1315 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1316 if (pipeline
->shaders
[s
])
1317 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
1320 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);