2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "util/os_time.h"
32 #include "common/gen_l3_config.h"
33 #include "anv_private.h"
34 #include "compiler/brw_nir.h"
36 #include "nir/nir_xfb_info.h"
37 #include "spirv/nir_spirv.h"
40 /* Needed for SWIZZLE macros */
41 #include "program/prog_instruction.h"
45 VkResult
anv_CreateShaderModule(
47 const VkShaderModuleCreateInfo
* pCreateInfo
,
48 const VkAllocationCallbacks
* pAllocator
,
49 VkShaderModule
* pShaderModule
)
51 ANV_FROM_HANDLE(anv_device
, device
, _device
);
52 struct anv_shader_module
*module
;
54 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
55 assert(pCreateInfo
->flags
== 0);
57 module
= vk_alloc2(&device
->alloc
, pAllocator
,
58 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
59 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
61 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
63 module
->size
= pCreateInfo
->codeSize
;
64 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
66 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
68 *pShaderModule
= anv_shader_module_to_handle(module
);
73 void anv_DestroyShaderModule(
75 VkShaderModule _module
,
76 const VkAllocationCallbacks
* pAllocator
)
78 ANV_FROM_HANDLE(anv_device
, device
, _device
);
79 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
84 vk_free2(&device
->alloc
, pAllocator
, module
);
87 #define SPIR_V_MAGIC_NUMBER 0x07230203
89 static const uint64_t stage_to_debug
[] = {
90 [MESA_SHADER_VERTEX
] = DEBUG_VS
,
91 [MESA_SHADER_TESS_CTRL
] = DEBUG_TCS
,
92 [MESA_SHADER_TESS_EVAL
] = DEBUG_TES
,
93 [MESA_SHADER_GEOMETRY
] = DEBUG_GS
,
94 [MESA_SHADER_FRAGMENT
] = DEBUG_WM
,
95 [MESA_SHADER_COMPUTE
] = DEBUG_CS
,
98 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
99 * we can't do that yet because we don't have the ability to copy nir.
102 anv_shader_compile_to_nir(struct anv_device
*device
,
104 const struct anv_shader_module
*module
,
105 const char *entrypoint_name
,
106 gl_shader_stage stage
,
107 const VkSpecializationInfo
*spec_info
)
109 const struct anv_physical_device
*pdevice
=
110 &device
->instance
->physicalDevice
;
111 const struct brw_compiler
*compiler
= pdevice
->compiler
;
112 const nir_shader_compiler_options
*nir_options
=
113 compiler
->glsl_compiler_options
[stage
].NirOptions
;
115 uint32_t *spirv
= (uint32_t *) module
->data
;
116 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
117 assert(module
->size
% 4 == 0);
119 uint32_t num_spec_entries
= 0;
120 struct nir_spirv_specialization
*spec_entries
= NULL
;
121 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
122 num_spec_entries
= spec_info
->mapEntryCount
;
123 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
124 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
125 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
126 const void *data
= spec_info
->pData
+ entry
.offset
;
127 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
129 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
130 if (spec_info
->dataSize
== 8)
131 spec_entries
[i
].data64
= *(const uint64_t *)data
;
133 spec_entries
[i
].data32
= *(const uint32_t *)data
;
137 nir_address_format ssbo_addr_format
=
138 anv_nir_ssbo_addr_format(pdevice
, device
->robust_buffer_access
);
139 struct spirv_to_nir_options spirv_options
= {
140 .lower_workgroup_access_to_offsets
= true,
142 .derivative_group
= true,
143 .descriptor_array_dynamic_indexing
= true,
144 .device_group
= true,
145 .draw_parameters
= true,
146 .float16
= pdevice
->info
.gen
>= 8,
147 .float64
= pdevice
->info
.gen
>= 8,
148 .geometry_streams
= true,
149 .image_write_without_format
= true,
150 .int8
= pdevice
->info
.gen
>= 8,
151 .int16
= pdevice
->info
.gen
>= 8,
152 .int64
= pdevice
->info
.gen
>= 8,
153 .int64_atomics
= pdevice
->info
.gen
>= 9 && pdevice
->use_softpin
,
156 .physical_storage_buffer_address
= pdevice
->has_a64_buffer_access
,
157 .post_depth_coverage
= pdevice
->info
.gen
>= 9,
158 .runtime_descriptor_array
= true,
159 .shader_viewport_index_layer
= true,
160 .stencil_export
= pdevice
->info
.gen
>= 9,
161 .storage_8bit
= pdevice
->info
.gen
>= 8,
162 .storage_16bit
= pdevice
->info
.gen
>= 8,
163 .subgroup_arithmetic
= true,
164 .subgroup_basic
= true,
165 .subgroup_ballot
= true,
166 .subgroup_quad
= true,
167 .subgroup_shuffle
= true,
168 .subgroup_vote
= true,
169 .tessellation
= true,
170 .transform_feedback
= pdevice
->info
.gen
>= 8,
171 .variable_pointers
= true,
173 .ubo_ptr_type
= glsl_vector_type(GLSL_TYPE_UINT
, 2),
174 .ssbo_ptr_type
= nir_address_format_to_glsl_type(ssbo_addr_format
),
175 .phys_ssbo_ptr_type
= glsl_vector_type(GLSL_TYPE_UINT64
, 1),
176 .push_const_ptr_type
= glsl_uint_type(),
177 .shared_ptr_type
= glsl_uint_type(),
181 nir_function
*entry_point
=
182 spirv_to_nir(spirv
, module
->size
/ 4,
183 spec_entries
, num_spec_entries
,
184 stage
, entrypoint_name
, &spirv_options
, nir_options
);
185 nir_shader
*nir
= entry_point
->shader
;
186 assert(nir
->info
.stage
== stage
);
187 nir_validate_shader(nir
, "after spirv_to_nir");
188 ralloc_steal(mem_ctx
, nir
);
192 if (unlikely(INTEL_DEBUG
& stage_to_debug
[stage
])) {
193 fprintf(stderr
, "NIR (from SPIR-V) for %s shader:\n",
194 gl_shader_stage_name(stage
));
195 nir_print_shader(nir
, stderr
);
198 /* We have to lower away local constant initializers right before we
199 * inline functions. That way they get properly initialized at the top
200 * of the function and not at the top of its caller.
202 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_function_temp
);
203 NIR_PASS_V(nir
, nir_lower_returns
);
204 NIR_PASS_V(nir
, nir_inline_functions
);
205 NIR_PASS_V(nir
, nir_opt_deref
);
207 /* Pick off the single entrypoint that we want */
208 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
209 if (func
!= entry_point
)
210 exec_node_remove(&func
->node
);
212 assert(exec_list_length(&nir
->functions
) == 1);
214 /* Now that we've deleted all but the main function, we can go ahead and
215 * lower the rest of the constant initializers. We do this here so that
216 * nir_remove_dead_variables and split_per_member_structs below see the
217 * corresponding stores.
219 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
221 /* Split member structs. We do this before lower_io_to_temporaries so that
222 * it doesn't lower system values to temporaries by accident.
224 NIR_PASS_V(nir
, nir_split_var_copies
);
225 NIR_PASS_V(nir
, nir_split_per_member_structs
);
227 NIR_PASS_V(nir
, nir_remove_dead_variables
,
228 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
230 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_global
,
231 nir_address_format_64bit_global
);
233 NIR_PASS_V(nir
, nir_propagate_invariant
);
234 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
235 entry_point
->impl
, true, false);
237 NIR_PASS_V(nir
, nir_lower_frexp
);
239 /* Vulkan uses the separate-shader linking model */
240 nir
->info
.separate_shader
= true;
242 nir
= brw_preprocess_nir(compiler
, nir
, NULL
);
247 void anv_DestroyPipeline(
249 VkPipeline _pipeline
,
250 const VkAllocationCallbacks
* pAllocator
)
252 ANV_FROM_HANDLE(anv_device
, device
, _device
);
253 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
258 anv_reloc_list_finish(&pipeline
->batch_relocs
,
259 pAllocator
? pAllocator
: &device
->alloc
);
260 if (pipeline
->blend_state
.map
)
261 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
263 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
264 if (pipeline
->shaders
[s
])
265 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
268 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
271 static const uint32_t vk_to_gen_primitive_type
[] = {
272 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
273 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
274 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
275 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
276 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
277 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
278 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
279 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
280 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
281 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
285 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
286 struct brw_sampler_prog_key_data
*key
)
288 /* Almost all multisampled textures are compressed. The only time when we
289 * don't compress a multisampled texture is for 16x MSAA with a surface
290 * width greater than 8k which is a bit of an edge case. Since the sampler
291 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
292 * to tell the compiler to always assume compression.
294 key
->compressed_multisample_layout_mask
= ~0;
296 /* SkyLake added support for 16x MSAA. With this came a new message for
297 * reading from a 16x MSAA surface with compression. The new message was
298 * needed because now the MCS data is 64 bits instead of 32 or lower as is
299 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
300 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
301 * so we can just use it unconditionally. This may not be quite as
302 * efficient but it saves us from recompiling.
304 if (devinfo
->gen
>= 9)
307 /* XXX: Handle texture swizzle on HSW- */
308 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
309 /* Assume color sampler, no swizzling. (Works for BDW+) */
310 key
->swizzles
[i
] = SWIZZLE_XYZW
;
315 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
316 struct brw_vs_prog_key
*key
)
318 memset(key
, 0, sizeof(*key
));
320 populate_sampler_prog_key(devinfo
, &key
->tex
);
322 /* XXX: Handle vertex input work-arounds */
324 /* XXX: Handle sampler_prog_key */
328 populate_tcs_prog_key(const struct gen_device_info
*devinfo
,
329 unsigned input_vertices
,
330 struct brw_tcs_prog_key
*key
)
332 memset(key
, 0, sizeof(*key
));
334 populate_sampler_prog_key(devinfo
, &key
->tex
);
336 key
->input_vertices
= input_vertices
;
340 populate_tes_prog_key(const struct gen_device_info
*devinfo
,
341 struct brw_tes_prog_key
*key
)
343 memset(key
, 0, sizeof(*key
));
345 populate_sampler_prog_key(devinfo
, &key
->tex
);
349 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
350 struct brw_gs_prog_key
*key
)
352 memset(key
, 0, sizeof(*key
));
354 populate_sampler_prog_key(devinfo
, &key
->tex
);
358 populate_wm_prog_key(const struct gen_device_info
*devinfo
,
359 const struct anv_subpass
*subpass
,
360 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
361 struct brw_wm_prog_key
*key
)
363 memset(key
, 0, sizeof(*key
));
365 populate_sampler_prog_key(devinfo
, &key
->tex
);
367 /* We set this to 0 here and set to the actual value before we call
370 key
->input_slots_valid
= 0;
372 /* Vulkan doesn't specify a default */
373 key
->high_quality_derivatives
= false;
375 /* XXX Vulkan doesn't appear to specify */
376 key
->clamp_fragment_color
= false;
378 assert(subpass
->color_count
<= MAX_RTS
);
379 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
380 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
381 key
->color_outputs_valid
|= (1 << i
);
384 key
->nr_color_regions
= util_bitcount(key
->color_outputs_valid
);
386 /* To reduce possible shader recompilations we would need to know if
387 * there is a SampleMask output variable to compute if we should emit
388 * code to workaround the issue that hardware disables alpha to coverage
389 * when there is SampleMask output.
391 key
->alpha_to_coverage
= ms_info
&& ms_info
->alphaToCoverageEnable
;
393 /* Vulkan doesn't support fixed-function alpha test */
394 key
->alpha_test_replicate_alpha
= false;
397 /* We should probably pull this out of the shader, but it's fairly
398 * harmless to compute it and then let dead-code take care of it.
400 if (ms_info
->rasterizationSamples
> 1) {
401 key
->persample_interp
=
402 (ms_info
->minSampleShading
* ms_info
->rasterizationSamples
) > 1;
403 key
->multisample_fbo
= true;
406 key
->frag_coord_adds_sample_pos
= ms_info
->sampleShadingEnable
;
411 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
412 struct brw_cs_prog_key
*key
)
414 memset(key
, 0, sizeof(*key
));
416 populate_sampler_prog_key(devinfo
, &key
->tex
);
419 struct anv_pipeline_stage
{
420 gl_shader_stage stage
;
422 const struct anv_shader_module
*module
;
423 const char *entrypoint
;
424 const VkSpecializationInfo
*spec_info
;
426 unsigned char shader_sha1
[20];
428 union brw_any_prog_key key
;
431 gl_shader_stage stage
;
432 unsigned char sha1
[20];
437 struct anv_pipeline_binding surface_to_descriptor
[256];
438 struct anv_pipeline_binding sampler_to_descriptor
[256];
439 struct anv_pipeline_bind_map bind_map
;
441 union brw_any_prog_data prog_data
;
443 VkPipelineCreationFeedbackEXT feedback
;
447 anv_pipeline_hash_shader(const struct anv_shader_module
*module
,
448 const char *entrypoint
,
449 gl_shader_stage stage
,
450 const VkSpecializationInfo
*spec_info
,
451 unsigned char *sha1_out
)
453 struct mesa_sha1 ctx
;
454 _mesa_sha1_init(&ctx
);
456 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
457 _mesa_sha1_update(&ctx
, entrypoint
, strlen(entrypoint
));
458 _mesa_sha1_update(&ctx
, &stage
, sizeof(stage
));
460 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
461 spec_info
->mapEntryCount
*
462 sizeof(*spec_info
->pMapEntries
));
463 _mesa_sha1_update(&ctx
, spec_info
->pData
,
464 spec_info
->dataSize
);
467 _mesa_sha1_final(&ctx
, sha1_out
);
471 anv_pipeline_hash_graphics(struct anv_pipeline
*pipeline
,
472 struct anv_pipeline_layout
*layout
,
473 struct anv_pipeline_stage
*stages
,
474 unsigned char *sha1_out
)
476 struct mesa_sha1 ctx
;
477 _mesa_sha1_init(&ctx
);
479 _mesa_sha1_update(&ctx
, &pipeline
->subpass
->view_mask
,
480 sizeof(pipeline
->subpass
->view_mask
));
483 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
485 const bool rba
= pipeline
->device
->robust_buffer_access
;
486 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
488 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
489 if (stages
[s
].entrypoint
) {
490 _mesa_sha1_update(&ctx
, stages
[s
].shader_sha1
,
491 sizeof(stages
[s
].shader_sha1
));
492 _mesa_sha1_update(&ctx
, &stages
[s
].key
, brw_prog_key_size(s
));
496 _mesa_sha1_final(&ctx
, sha1_out
);
500 anv_pipeline_hash_compute(struct anv_pipeline
*pipeline
,
501 struct anv_pipeline_layout
*layout
,
502 struct anv_pipeline_stage
*stage
,
503 unsigned char *sha1_out
)
505 struct mesa_sha1 ctx
;
506 _mesa_sha1_init(&ctx
);
509 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
511 const bool rba
= pipeline
->device
->robust_buffer_access
;
512 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
514 _mesa_sha1_update(&ctx
, stage
->shader_sha1
,
515 sizeof(stage
->shader_sha1
));
516 _mesa_sha1_update(&ctx
, &stage
->key
.cs
, sizeof(stage
->key
.cs
));
518 _mesa_sha1_final(&ctx
, sha1_out
);
522 anv_pipeline_stage_get_nir(struct anv_pipeline
*pipeline
,
523 struct anv_pipeline_cache
*cache
,
525 struct anv_pipeline_stage
*stage
)
527 const struct brw_compiler
*compiler
=
528 pipeline
->device
->instance
->physicalDevice
.compiler
;
529 const nir_shader_compiler_options
*nir_options
=
530 compiler
->glsl_compiler_options
[stage
->stage
].NirOptions
;
533 nir
= anv_device_search_for_nir(pipeline
->device
, cache
,
538 assert(nir
->info
.stage
== stage
->stage
);
542 nir
= anv_shader_compile_to_nir(pipeline
->device
,
549 anv_device_upload_nir(pipeline
->device
, cache
, nir
, stage
->shader_sha1
);
557 anv_pipeline_lower_nir(struct anv_pipeline
*pipeline
,
559 struct anv_pipeline_stage
*stage
,
560 struct anv_pipeline_layout
*layout
)
562 const struct anv_physical_device
*pdevice
=
563 &pipeline
->device
->instance
->physicalDevice
;
564 const struct brw_compiler
*compiler
= pdevice
->compiler
;
566 struct brw_stage_prog_data
*prog_data
= &stage
->prog_data
.base
;
567 nir_shader
*nir
= stage
->nir
;
569 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
570 NIR_PASS_V(nir
, nir_lower_wpos_center
, pipeline
->sample_shading_enable
);
571 NIR_PASS_V(nir
, anv_nir_lower_input_attachments
);
574 NIR_PASS_V(nir
, anv_nir_lower_ycbcr_textures
, layout
);
576 NIR_PASS_V(nir
, anv_nir_lower_push_constants
);
578 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
579 NIR_PASS_V(nir
, anv_nir_lower_multiview
, pipeline
->subpass
->view_mask
);
581 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
582 prog_data
->total_shared
= nir
->num_shared
;
584 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
586 if (nir
->num_uniforms
> 0) {
587 assert(prog_data
->nr_params
== 0);
589 /* If the shader uses any push constants at all, we'll just give
590 * them the maximum possible number
592 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
593 nir
->num_uniforms
= MAX_PUSH_CONSTANTS_SIZE
;
594 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
595 prog_data
->param
= ralloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
597 /* We now set the param values to be offsets into a
598 * anv_push_constant_data structure. Since the compiler doesn't
599 * actually dereference any of the gl_constant_value pointers in the
600 * params array, it doesn't really matter what we put here.
602 struct anv_push_constants
*null_data
= NULL
;
603 /* Fill out the push constants section of the param array */
604 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++) {
605 prog_data
->param
[i
] = ANV_PARAM_PUSH(
606 (uintptr_t)&null_data
->client_data
[i
* sizeof(float)]);
610 if (nir
->info
.num_ssbos
> 0 || nir
->info
.num_images
> 0)
611 pipeline
->needs_data_cache
= true;
613 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, compiler
->devinfo
);
615 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
617 anv_nir_apply_pipeline_layout(pdevice
,
618 pipeline
->device
->robust_buffer_access
,
619 layout
, nir
, prog_data
,
622 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ubo
,
623 nir_address_format_32bit_index_offset
);
624 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ssbo
,
625 anv_nir_ssbo_addr_format(pdevice
,
626 pipeline
->device
->robust_buffer_access
));
628 NIR_PASS_V(nir
, nir_opt_constant_folding
);
630 /* We don't support non-uniform UBOs and non-uniform SSBO access is
631 * handled naturally by falling back to A64 messages.
633 NIR_PASS_V(nir
, nir_lower_non_uniform_access
,
634 nir_lower_non_uniform_texture_access
|
635 nir_lower_non_uniform_image_access
);
638 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
639 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
641 assert(nir
->num_uniforms
== prog_data
->nr_params
* 4);
647 anv_pipeline_link_vs(const struct brw_compiler
*compiler
,
648 struct anv_pipeline_stage
*vs_stage
,
649 struct anv_pipeline_stage
*next_stage
)
652 brw_nir_link_shaders(compiler
, &vs_stage
->nir
, &next_stage
->nir
);
655 static const unsigned *
656 anv_pipeline_compile_vs(const struct brw_compiler
*compiler
,
658 struct anv_device
*device
,
659 struct anv_pipeline_stage
*vs_stage
)
661 brw_compute_vue_map(compiler
->devinfo
,
662 &vs_stage
->prog_data
.vs
.base
.vue_map
,
663 vs_stage
->nir
->info
.outputs_written
,
664 vs_stage
->nir
->info
.separate_shader
);
666 return brw_compile_vs(compiler
, device
, mem_ctx
, &vs_stage
->key
.vs
,
667 &vs_stage
->prog_data
.vs
, vs_stage
->nir
, -1, NULL
);
671 merge_tess_info(struct shader_info
*tes_info
,
672 const struct shader_info
*tcs_info
)
674 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
676 * "PointMode. Controls generation of points rather than triangles
677 * or lines. This functionality defaults to disabled, and is
678 * enabled if either shader stage includes the execution mode.
680 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
681 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
682 * and OutputVertices, it says:
684 * "One mode must be set in at least one of the tessellation
687 * So, the fields can be set in either the TCS or TES, but they must
688 * agree if set in both. Our backend looks at TES, so bitwise-or in
689 * the values from the TCS.
691 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
692 tes_info
->tess
.tcs_vertices_out
== 0 ||
693 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
694 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
696 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
697 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
698 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
699 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
701 assert(tcs_info
->tess
.primitive_mode
== 0 ||
702 tes_info
->tess
.primitive_mode
== 0 ||
703 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
704 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
705 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
706 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
710 anv_pipeline_link_tcs(const struct brw_compiler
*compiler
,
711 struct anv_pipeline_stage
*tcs_stage
,
712 struct anv_pipeline_stage
*tes_stage
)
714 assert(tes_stage
&& tes_stage
->stage
== MESA_SHADER_TESS_EVAL
);
716 brw_nir_link_shaders(compiler
, &tcs_stage
->nir
, &tes_stage
->nir
);
718 nir_lower_patch_vertices(tes_stage
->nir
,
719 tcs_stage
->nir
->info
.tess
.tcs_vertices_out
,
722 /* Copy TCS info into the TES info */
723 merge_tess_info(&tes_stage
->nir
->info
, &tcs_stage
->nir
->info
);
725 /* Whacking the key after cache lookup is a bit sketchy, but all of
726 * this comes from the SPIR-V, which is part of the hash used for the
727 * pipeline cache. So it should be safe.
729 tcs_stage
->key
.tcs
.tes_primitive_mode
=
730 tes_stage
->nir
->info
.tess
.primitive_mode
;
731 tcs_stage
->key
.tcs
.quads_workaround
=
732 compiler
->devinfo
->gen
< 9 &&
733 tes_stage
->nir
->info
.tess
.primitive_mode
== 7 /* GL_QUADS */ &&
734 tes_stage
->nir
->info
.tess
.spacing
== TESS_SPACING_EQUAL
;
737 static const unsigned *
738 anv_pipeline_compile_tcs(const struct brw_compiler
*compiler
,
740 struct anv_device
*device
,
741 struct anv_pipeline_stage
*tcs_stage
,
742 struct anv_pipeline_stage
*prev_stage
)
744 tcs_stage
->key
.tcs
.outputs_written
=
745 tcs_stage
->nir
->info
.outputs_written
;
746 tcs_stage
->key
.tcs
.patch_outputs_written
=
747 tcs_stage
->nir
->info
.patch_outputs_written
;
749 return brw_compile_tcs(compiler
, device
, mem_ctx
, &tcs_stage
->key
.tcs
,
750 &tcs_stage
->prog_data
.tcs
, tcs_stage
->nir
,
755 anv_pipeline_link_tes(const struct brw_compiler
*compiler
,
756 struct anv_pipeline_stage
*tes_stage
,
757 struct anv_pipeline_stage
*next_stage
)
760 brw_nir_link_shaders(compiler
, &tes_stage
->nir
, &next_stage
->nir
);
763 static const unsigned *
764 anv_pipeline_compile_tes(const struct brw_compiler
*compiler
,
766 struct anv_device
*device
,
767 struct anv_pipeline_stage
*tes_stage
,
768 struct anv_pipeline_stage
*tcs_stage
)
770 tes_stage
->key
.tes
.inputs_read
=
771 tcs_stage
->nir
->info
.outputs_written
;
772 tes_stage
->key
.tes
.patch_inputs_read
=
773 tcs_stage
->nir
->info
.patch_outputs_written
;
775 return brw_compile_tes(compiler
, device
, mem_ctx
, &tes_stage
->key
.tes
,
776 &tcs_stage
->prog_data
.tcs
.base
.vue_map
,
777 &tes_stage
->prog_data
.tes
, tes_stage
->nir
,
782 anv_pipeline_link_gs(const struct brw_compiler
*compiler
,
783 struct anv_pipeline_stage
*gs_stage
,
784 struct anv_pipeline_stage
*next_stage
)
787 brw_nir_link_shaders(compiler
, &gs_stage
->nir
, &next_stage
->nir
);
790 static const unsigned *
791 anv_pipeline_compile_gs(const struct brw_compiler
*compiler
,
793 struct anv_device
*device
,
794 struct anv_pipeline_stage
*gs_stage
,
795 struct anv_pipeline_stage
*prev_stage
)
797 brw_compute_vue_map(compiler
->devinfo
,
798 &gs_stage
->prog_data
.gs
.base
.vue_map
,
799 gs_stage
->nir
->info
.outputs_written
,
800 gs_stage
->nir
->info
.separate_shader
);
802 return brw_compile_gs(compiler
, device
, mem_ctx
, &gs_stage
->key
.gs
,
803 &gs_stage
->prog_data
.gs
, gs_stage
->nir
,
808 anv_pipeline_link_fs(const struct brw_compiler
*compiler
,
809 struct anv_pipeline_stage
*stage
)
811 unsigned num_rts
= 0;
812 const int max_rt
= FRAG_RESULT_DATA7
- FRAG_RESULT_DATA0
+ 1;
813 struct anv_pipeline_binding rt_bindings
[max_rt
];
814 nir_function_impl
*impl
= nir_shader_get_entrypoint(stage
->nir
);
815 int rt_to_bindings
[max_rt
];
816 memset(rt_to_bindings
, -1, sizeof(rt_to_bindings
));
817 bool rt_used
[max_rt
];
818 memset(rt_used
, 0, sizeof(rt_used
));
820 /* Flag used render targets */
821 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
822 if (var
->data
.location
< FRAG_RESULT_DATA0
)
825 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
826 /* Unused or out-of-bounds */
827 if (rt
>= MAX_RTS
|| !(stage
->key
.wm
.color_outputs_valid
& (1 << rt
)))
830 const unsigned array_len
=
831 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
832 assert(rt
+ array_len
<= max_rt
);
834 for (unsigned i
= 0; i
< array_len
; i
++)
835 rt_used
[rt
+ i
] = true;
838 /* Set new, compacted, location */
839 for (unsigned i
= 0; i
< max_rt
; i
++) {
843 rt_to_bindings
[i
] = num_rts
;
844 rt_bindings
[rt_to_bindings
[i
]] = (struct anv_pipeline_binding
) {
845 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
852 bool deleted_output
= false;
853 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
854 if (var
->data
.location
< FRAG_RESULT_DATA0
)
857 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
859 !(stage
->key
.wm
.color_outputs_valid
& (1 << rt
))) {
860 /* Unused or out-of-bounds, throw it away */
861 deleted_output
= true;
862 var
->data
.mode
= nir_var_function_temp
;
863 exec_node_remove(&var
->node
);
864 exec_list_push_tail(&impl
->locals
, &var
->node
);
868 /* Give it the new location */
869 assert(rt_to_bindings
[rt
] != -1);
870 var
->data
.location
= rt_to_bindings
[rt
] + FRAG_RESULT_DATA0
;
874 nir_fixup_deref_modes(stage
->nir
);
877 /* If we have no render targets, we need a null render target */
878 rt_bindings
[0] = (struct anv_pipeline_binding
) {
879 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
886 /* Now that we've determined the actual number of render targets, adjust
887 * the key accordingly.
889 stage
->key
.wm
.nr_color_regions
= num_rts
;
890 stage
->key
.wm
.color_outputs_valid
= (1 << num_rts
) - 1;
892 assert(num_rts
<= max_rt
);
893 assert(stage
->bind_map
.surface_count
== 0);
894 typed_memcpy(stage
->bind_map
.surface_to_descriptor
,
895 rt_bindings
, num_rts
);
896 stage
->bind_map
.surface_count
+= num_rts
;
899 static const unsigned *
900 anv_pipeline_compile_fs(const struct brw_compiler
*compiler
,
902 struct anv_device
*device
,
903 struct anv_pipeline_stage
*fs_stage
,
904 struct anv_pipeline_stage
*prev_stage
)
906 /* TODO: we could set this to 0 based on the information in nir_shader, but
907 * we need this before we call spirv_to_nir.
910 fs_stage
->key
.wm
.input_slots_valid
=
911 prev_stage
->prog_data
.vue
.vue_map
.slots_valid
;
913 const unsigned *code
=
914 brw_compile_fs(compiler
, device
, mem_ctx
, &fs_stage
->key
.wm
,
915 &fs_stage
->prog_data
.wm
, fs_stage
->nir
,
916 NULL
, -1, -1, -1, true, false, NULL
, NULL
);
918 if (fs_stage
->key
.wm
.nr_color_regions
== 0 &&
919 !fs_stage
->prog_data
.wm
.has_side_effects
&&
920 !fs_stage
->prog_data
.wm
.uses_kill
&&
921 fs_stage
->prog_data
.wm
.computed_depth_mode
== BRW_PSCDEPTH_OFF
&&
922 !fs_stage
->prog_data
.wm
.computed_stencil
) {
923 /* This fragment shader has no outputs and no side effects. Go ahead
924 * and return the code pointer so we don't accidentally think the
925 * compile failed but zero out prog_data which will set program_size to
926 * zero and disable the stage.
928 memset(&fs_stage
->prog_data
, 0, sizeof(fs_stage
->prog_data
));
935 anv_pipeline_compile_graphics(struct anv_pipeline
*pipeline
,
936 struct anv_pipeline_cache
*cache
,
937 const VkGraphicsPipelineCreateInfo
*info
)
939 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
940 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
942 int64_t pipeline_start
= os_time_get_nano();
944 const struct brw_compiler
*compiler
=
945 pipeline
->device
->instance
->physicalDevice
.compiler
;
946 struct anv_pipeline_stage stages
[MESA_SHADER_STAGES
] = {};
948 pipeline
->active_stages
= 0;
951 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
952 const VkPipelineShaderStageCreateInfo
*sinfo
= &info
->pStages
[i
];
953 gl_shader_stage stage
= vk_to_mesa_shader_stage(sinfo
->stage
);
955 pipeline
->active_stages
|= sinfo
->stage
;
957 int64_t stage_start
= os_time_get_nano();
959 stages
[stage
].stage
= stage
;
960 stages
[stage
].module
= anv_shader_module_from_handle(sinfo
->module
);
961 stages
[stage
].entrypoint
= sinfo
->pName
;
962 stages
[stage
].spec_info
= sinfo
->pSpecializationInfo
;
963 anv_pipeline_hash_shader(stages
[stage
].module
,
964 stages
[stage
].entrypoint
,
966 stages
[stage
].spec_info
,
967 stages
[stage
].shader_sha1
);
969 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
971 case MESA_SHADER_VERTEX
:
972 populate_vs_prog_key(devinfo
, &stages
[stage
].key
.vs
);
974 case MESA_SHADER_TESS_CTRL
:
975 populate_tcs_prog_key(devinfo
,
976 info
->pTessellationState
->patchControlPoints
,
977 &stages
[stage
].key
.tcs
);
979 case MESA_SHADER_TESS_EVAL
:
980 populate_tes_prog_key(devinfo
, &stages
[stage
].key
.tes
);
982 case MESA_SHADER_GEOMETRY
:
983 populate_gs_prog_key(devinfo
, &stages
[stage
].key
.gs
);
985 case MESA_SHADER_FRAGMENT
:
986 populate_wm_prog_key(devinfo
, pipeline
->subpass
,
987 info
->pMultisampleState
,
988 &stages
[stage
].key
.wm
);
991 unreachable("Invalid graphics shader stage");
994 stages
[stage
].feedback
.duration
+= os_time_get_nano() - stage_start
;
995 stages
[stage
].feedback
.flags
|= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
998 if (pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
)
999 pipeline
->active_stages
|= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
1001 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1003 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1005 unsigned char sha1
[20];
1006 anv_pipeline_hash_graphics(pipeline
, layout
, stages
, sha1
);
1009 unsigned cache_hits
= 0;
1010 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1011 if (!stages
[s
].entrypoint
)
1014 int64_t stage_start
= os_time_get_nano();
1016 stages
[s
].cache_key
.stage
= s
;
1017 memcpy(stages
[s
].cache_key
.sha1
, sha1
, sizeof(sha1
));
1020 struct anv_shader_bin
*bin
=
1021 anv_device_search_for_kernel(pipeline
->device
, cache
,
1022 &stages
[s
].cache_key
,
1023 sizeof(stages
[s
].cache_key
), &cache_hit
);
1026 pipeline
->shaders
[s
] = bin
;
1031 stages
[s
].feedback
.flags
|=
1032 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1034 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1037 if (found
== __builtin_popcount(pipeline
->active_stages
)) {
1038 if (cache_hits
== found
) {
1039 pipeline_feedback
.flags
|=
1040 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1042 /* We found all our shaders in the cache. We're done. */
1044 } else if (found
> 0) {
1045 /* We found some but not all of our shaders. This shouldn't happen
1046 * most of the time but it can if we have a partially populated
1049 assert(found
< __builtin_popcount(pipeline
->active_stages
));
1051 vk_debug_report(&pipeline
->device
->instance
->debug_report_callbacks
,
1052 VK_DEBUG_REPORT_WARNING_BIT_EXT
|
1053 VK_DEBUG_REPORT_PERFORMANCE_WARNING_BIT_EXT
,
1054 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT
,
1055 (uint64_t)(uintptr_t)cache
,
1057 "Found a partial pipeline in the cache. This is "
1058 "most likely caused by an incomplete pipeline cache "
1059 "import or export");
1061 /* We're going to have to recompile anyway, so just throw away our
1062 * references to the shaders in the cache. We'll get them out of the
1063 * cache again as part of the compilation process.
1065 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1066 stages
[s
].feedback
.flags
= 0;
1067 if (pipeline
->shaders
[s
]) {
1068 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1069 pipeline
->shaders
[s
] = NULL
;
1074 void *pipeline_ctx
= ralloc_context(NULL
);
1076 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1077 if (!stages
[s
].entrypoint
)
1080 int64_t stage_start
= os_time_get_nano();
1082 assert(stages
[s
].stage
== s
);
1083 assert(pipeline
->shaders
[s
] == NULL
);
1085 stages
[s
].bind_map
= (struct anv_pipeline_bind_map
) {
1086 .surface_to_descriptor
= stages
[s
].surface_to_descriptor
,
1087 .sampler_to_descriptor
= stages
[s
].sampler_to_descriptor
1090 stages
[s
].nir
= anv_pipeline_stage_get_nir(pipeline
, cache
,
1093 if (stages
[s
].nir
== NULL
) {
1094 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1098 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1101 /* Walk backwards to link */
1102 struct anv_pipeline_stage
*next_stage
= NULL
;
1103 for (int s
= MESA_SHADER_STAGES
- 1; s
>= 0; s
--) {
1104 if (!stages
[s
].entrypoint
)
1108 case MESA_SHADER_VERTEX
:
1109 anv_pipeline_link_vs(compiler
, &stages
[s
], next_stage
);
1111 case MESA_SHADER_TESS_CTRL
:
1112 anv_pipeline_link_tcs(compiler
, &stages
[s
], next_stage
);
1114 case MESA_SHADER_TESS_EVAL
:
1115 anv_pipeline_link_tes(compiler
, &stages
[s
], next_stage
);
1117 case MESA_SHADER_GEOMETRY
:
1118 anv_pipeline_link_gs(compiler
, &stages
[s
], next_stage
);
1120 case MESA_SHADER_FRAGMENT
:
1121 anv_pipeline_link_fs(compiler
, &stages
[s
]);
1124 unreachable("Invalid graphics shader stage");
1127 next_stage
= &stages
[s
];
1130 struct anv_pipeline_stage
*prev_stage
= NULL
;
1131 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1132 if (!stages
[s
].entrypoint
)
1135 int64_t stage_start
= os_time_get_nano();
1137 void *stage_ctx
= ralloc_context(NULL
);
1139 nir_xfb_info
*xfb_info
= NULL
;
1140 if (s
== MESA_SHADER_VERTEX
||
1141 s
== MESA_SHADER_TESS_EVAL
||
1142 s
== MESA_SHADER_GEOMETRY
)
1143 xfb_info
= nir_gather_xfb_info(stages
[s
].nir
, stage_ctx
);
1145 anv_pipeline_lower_nir(pipeline
, stage_ctx
, &stages
[s
], layout
);
1147 const unsigned *code
;
1149 case MESA_SHADER_VERTEX
:
1150 code
= anv_pipeline_compile_vs(compiler
, stage_ctx
, pipeline
->device
,
1153 case MESA_SHADER_TESS_CTRL
:
1154 code
= anv_pipeline_compile_tcs(compiler
, stage_ctx
, pipeline
->device
,
1155 &stages
[s
], prev_stage
);
1157 case MESA_SHADER_TESS_EVAL
:
1158 code
= anv_pipeline_compile_tes(compiler
, stage_ctx
, pipeline
->device
,
1159 &stages
[s
], prev_stage
);
1161 case MESA_SHADER_GEOMETRY
:
1162 code
= anv_pipeline_compile_gs(compiler
, stage_ctx
, pipeline
->device
,
1163 &stages
[s
], prev_stage
);
1165 case MESA_SHADER_FRAGMENT
:
1166 code
= anv_pipeline_compile_fs(compiler
, stage_ctx
, pipeline
->device
,
1167 &stages
[s
], prev_stage
);
1170 unreachable("Invalid graphics shader stage");
1173 ralloc_free(stage_ctx
);
1174 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1178 struct anv_shader_bin
*bin
=
1179 anv_device_upload_kernel(pipeline
->device
, cache
,
1180 &stages
[s
].cache_key
,
1181 sizeof(stages
[s
].cache_key
),
1182 code
, stages
[s
].prog_data
.base
.program_size
,
1183 stages
[s
].nir
->constant_data
,
1184 stages
[s
].nir
->constant_data_size
,
1185 &stages
[s
].prog_data
.base
,
1186 brw_prog_data_size(s
),
1187 xfb_info
, &stages
[s
].bind_map
);
1189 ralloc_free(stage_ctx
);
1190 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1194 pipeline
->shaders
[s
] = bin
;
1195 ralloc_free(stage_ctx
);
1197 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1199 prev_stage
= &stages
[s
];
1202 ralloc_free(pipeline_ctx
);
1206 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
] &&
1207 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->prog_data
->program_size
== 0) {
1208 /* This can happen if we decided to implicitly disable the fragment
1209 * shader. See anv_pipeline_compile_fs().
1211 anv_shader_bin_unref(pipeline
->device
,
1212 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
1213 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] = NULL
;
1214 pipeline
->active_stages
&= ~VK_SHADER_STAGE_FRAGMENT_BIT
;
1217 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1219 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1220 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1221 if (create_feedback
) {
1222 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1224 assert(info
->stageCount
== create_feedback
->pipelineStageCreationFeedbackCount
);
1225 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1226 gl_shader_stage s
= vk_to_mesa_shader_stage(info
->pStages
[i
].stage
);
1227 create_feedback
->pPipelineStageCreationFeedbacks
[i
] = stages
[s
].feedback
;
1234 ralloc_free(pipeline_ctx
);
1236 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1237 if (pipeline
->shaders
[s
])
1238 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1245 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1246 struct anv_pipeline_cache
*cache
,
1247 const VkComputePipelineCreateInfo
*info
,
1248 const struct anv_shader_module
*module
,
1249 const char *entrypoint
,
1250 const VkSpecializationInfo
*spec_info
)
1252 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1253 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1255 int64_t pipeline_start
= os_time_get_nano();
1257 const struct brw_compiler
*compiler
=
1258 pipeline
->device
->instance
->physicalDevice
.compiler
;
1260 struct anv_pipeline_stage stage
= {
1261 .stage
= MESA_SHADER_COMPUTE
,
1263 .entrypoint
= entrypoint
,
1264 .spec_info
= spec_info
,
1266 .stage
= MESA_SHADER_COMPUTE
,
1269 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1272 anv_pipeline_hash_shader(stage
.module
,
1274 MESA_SHADER_COMPUTE
,
1278 struct anv_shader_bin
*bin
= NULL
;
1280 populate_cs_prog_key(&pipeline
->device
->info
, &stage
.key
.cs
);
1282 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1284 anv_pipeline_hash_compute(pipeline
, layout
, &stage
, stage
.cache_key
.sha1
);
1286 bin
= anv_device_search_for_kernel(pipeline
->device
, cache
, &stage
.cache_key
,
1287 sizeof(stage
.cache_key
), &cache_hit
);
1290 int64_t stage_start
= os_time_get_nano();
1292 stage
.bind_map
= (struct anv_pipeline_bind_map
) {
1293 .surface_to_descriptor
= stage
.surface_to_descriptor
,
1294 .sampler_to_descriptor
= stage
.sampler_to_descriptor
1297 /* Set up a binding for the gl_NumWorkGroups */
1298 stage
.bind_map
.surface_count
= 1;
1299 stage
.bind_map
.surface_to_descriptor
[0] = (struct anv_pipeline_binding
) {
1300 .set
= ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
,
1303 void *mem_ctx
= ralloc_context(NULL
);
1305 stage
.nir
= anv_pipeline_stage_get_nir(pipeline
, cache
, mem_ctx
, &stage
);
1306 if (stage
.nir
== NULL
) {
1307 ralloc_free(mem_ctx
);
1308 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1311 anv_pipeline_lower_nir(pipeline
, mem_ctx
, &stage
, layout
);
1313 NIR_PASS_V(stage
.nir
, anv_nir_add_base_work_group_id
,
1314 &stage
.prog_data
.cs
);
1316 const unsigned *shader_code
=
1317 brw_compile_cs(compiler
, pipeline
->device
, mem_ctx
, &stage
.key
.cs
,
1318 &stage
.prog_data
.cs
, stage
.nir
, -1, NULL
);
1319 if (shader_code
== NULL
) {
1320 ralloc_free(mem_ctx
);
1321 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1324 const unsigned code_size
= stage
.prog_data
.base
.program_size
;
1325 bin
= anv_device_upload_kernel(pipeline
->device
, cache
,
1326 &stage
.cache_key
, sizeof(stage
.cache_key
),
1327 shader_code
, code_size
,
1328 stage
.nir
->constant_data
,
1329 stage
.nir
->constant_data_size
,
1330 &stage
.prog_data
.base
,
1331 sizeof(stage
.prog_data
.cs
),
1332 NULL
, &stage
.bind_map
);
1334 ralloc_free(mem_ctx
);
1335 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1338 ralloc_free(mem_ctx
);
1340 stage
.feedback
.duration
= os_time_get_nano() - stage_start
;
1344 stage
.feedback
.flags
|=
1345 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1346 pipeline_feedback
.flags
|=
1347 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1349 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1351 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1352 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1353 if (create_feedback
) {
1354 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1356 assert(create_feedback
->pipelineStageCreationFeedbackCount
== 1);
1357 create_feedback
->pPipelineStageCreationFeedbacks
[0] = stage
.feedback
;
1360 pipeline
->active_stages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1361 pipeline
->shaders
[MESA_SHADER_COMPUTE
] = bin
;
1367 * Copy pipeline state not marked as dynamic.
1368 * Dynamic state is pipeline state which hasn't been provided at pipeline
1369 * creation time, but is dynamically provided afterwards using various
1370 * vkCmdSet* functions.
1372 * The set of state considered "non_dynamic" is determined by the pieces of
1373 * state that have their corresponding VkDynamicState enums omitted from
1374 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1376 * @param[out] pipeline Destination non_dynamic state.
1377 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1380 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
1381 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1383 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
1384 struct anv_subpass
*subpass
= pipeline
->subpass
;
1386 pipeline
->dynamic_state
= default_dynamic_state
;
1388 if (pCreateInfo
->pDynamicState
) {
1389 /* Remove all of the states that are marked as dynamic */
1390 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1391 for (uint32_t s
= 0; s
< count
; s
++)
1392 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1395 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1397 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1399 * pViewportState is [...] NULL if the pipeline
1400 * has rasterization disabled.
1402 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1403 assert(pCreateInfo
->pViewportState
);
1405 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1406 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
1407 typed_memcpy(dynamic
->viewport
.viewports
,
1408 pCreateInfo
->pViewportState
->pViewports
,
1409 pCreateInfo
->pViewportState
->viewportCount
);
1412 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1413 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
1414 typed_memcpy(dynamic
->scissor
.scissors
,
1415 pCreateInfo
->pViewportState
->pScissors
,
1416 pCreateInfo
->pViewportState
->scissorCount
);
1420 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1421 assert(pCreateInfo
->pRasterizationState
);
1422 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1425 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1426 assert(pCreateInfo
->pRasterizationState
);
1427 dynamic
->depth_bias
.bias
=
1428 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1429 dynamic
->depth_bias
.clamp
=
1430 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1431 dynamic
->depth_bias
.slope
=
1432 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1435 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1437 * pColorBlendState is [...] NULL if the pipeline has rasterization
1438 * disabled or if the subpass of the render pass the pipeline is
1439 * created against does not use any color attachments.
1441 bool uses_color_att
= false;
1442 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1443 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1444 uses_color_att
= true;
1449 if (uses_color_att
&&
1450 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1451 assert(pCreateInfo
->pColorBlendState
);
1453 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
1454 typed_memcpy(dynamic
->blend_constants
,
1455 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1458 /* If there is no depthstencil attachment, then don't read
1459 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1460 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1461 * no need to override the depthstencil defaults in
1462 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1464 * Section 9.2 of the Vulkan 1.0.15 spec says:
1466 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1467 * disabled or if the subpass of the render pass the pipeline is created
1468 * against does not use a depth/stencil attachment.
1470 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1471 subpass
->depth_stencil_attachment
) {
1472 assert(pCreateInfo
->pDepthStencilState
);
1474 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1475 dynamic
->depth_bounds
.min
=
1476 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1477 dynamic
->depth_bounds
.max
=
1478 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1481 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1482 dynamic
->stencil_compare_mask
.front
=
1483 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1484 dynamic
->stencil_compare_mask
.back
=
1485 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1488 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1489 dynamic
->stencil_write_mask
.front
=
1490 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1491 dynamic
->stencil_write_mask
.back
=
1492 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1495 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1496 dynamic
->stencil_reference
.front
=
1497 pCreateInfo
->pDepthStencilState
->front
.reference
;
1498 dynamic
->stencil_reference
.back
=
1499 pCreateInfo
->pDepthStencilState
->back
.reference
;
1503 pipeline
->dynamic_state_mask
= states
;
1507 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1510 struct anv_render_pass
*renderpass
= NULL
;
1511 struct anv_subpass
*subpass
= NULL
;
1513 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1514 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1516 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1518 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1521 assert(info
->subpass
< renderpass
->subpass_count
);
1522 subpass
= &renderpass
->subpasses
[info
->subpass
];
1524 assert(info
->stageCount
>= 1);
1525 assert(info
->pVertexInputState
);
1526 assert(info
->pInputAssemblyState
);
1527 assert(info
->pRasterizationState
);
1528 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1529 assert(info
->pViewportState
);
1530 assert(info
->pMultisampleState
);
1532 if (subpass
&& subpass
->depth_stencil_attachment
)
1533 assert(info
->pDepthStencilState
);
1535 if (subpass
&& subpass
->color_count
> 0) {
1536 bool all_color_unused
= true;
1537 for (int i
= 0; i
< subpass
->color_count
; i
++) {
1538 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
1539 all_color_unused
= false;
1541 /* pColorBlendState is ignored if the pipeline has rasterization
1542 * disabled or if the subpass of the render pass the pipeline is
1543 * created against does not use any color attachments.
1545 assert(info
->pColorBlendState
|| all_color_unused
);
1549 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1550 switch (info
->pStages
[i
].stage
) {
1551 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1552 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1553 assert(info
->pTessellationState
);
1563 * Calculate the desired L3 partitioning based on the current state of the
1564 * pipeline. For now this simply returns the conservative defaults calculated
1565 * by get_default_l3_weights(), but we could probably do better by gathering
1566 * more statistics from the pipeline state (e.g. guess of expected URB usage
1567 * and bound surfaces), or by using feed-back from performance counters.
1570 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1572 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1574 const struct gen_l3_weights w
=
1575 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
1577 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
1578 pipeline
->urb
.total_size
=
1579 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
1583 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1584 struct anv_device
*device
,
1585 struct anv_pipeline_cache
*cache
,
1586 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1587 const VkAllocationCallbacks
*alloc
)
1591 anv_pipeline_validate_create_info(pCreateInfo
);
1594 alloc
= &device
->alloc
;
1596 pipeline
->device
= device
;
1598 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, pCreateInfo
->renderPass
);
1599 assert(pCreateInfo
->subpass
< render_pass
->subpass_count
);
1600 pipeline
->subpass
= &render_pass
->subpasses
[pCreateInfo
->subpass
];
1602 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1603 if (result
!= VK_SUCCESS
)
1606 pipeline
->batch
.alloc
= alloc
;
1607 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1608 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1609 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1610 pipeline
->batch
.status
= VK_SUCCESS
;
1612 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1613 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1614 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1616 /* Previously we enabled depth clipping when !depthClampEnable.
1617 * DepthClipStateCreateInfo now makes depth clipping explicit so if the
1618 * clipping info is available, use its enable value to determine clipping,
1619 * otherwise fallback to the previous !depthClampEnable logic.
1621 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*clip_info
=
1622 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1623 PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
1624 pipeline
->depth_clip_enable
= clip_info
? clip_info
->depthClipEnable
: !pipeline
->depth_clamp_enable
;
1626 pipeline
->sample_shading_enable
= pCreateInfo
->pMultisampleState
&&
1627 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
1629 pipeline
->needs_data_cache
= false;
1631 /* When we free the pipeline, we detect stages based on the NULL status
1632 * of various prog_data pointers. Make them NULL by default.
1634 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1636 result
= anv_pipeline_compile_graphics(pipeline
, cache
, pCreateInfo
);
1637 if (result
!= VK_SUCCESS
) {
1638 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);
1642 assert(pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1644 anv_pipeline_setup_l3_config(pipeline
, false);
1646 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1647 pCreateInfo
->pVertexInputState
;
1649 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1651 pipeline
->vb_used
= 0;
1652 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1653 const VkVertexInputAttributeDescription
*desc
=
1654 &vi_info
->pVertexAttributeDescriptions
[i
];
1656 if (inputs_read
& (1ull << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1657 pipeline
->vb_used
|= 1 << desc
->binding
;
1660 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1661 const VkVertexInputBindingDescription
*desc
=
1662 &vi_info
->pVertexBindingDescriptions
[i
];
1664 pipeline
->vb
[desc
->binding
].stride
= desc
->stride
;
1666 /* Step rate is programmed per vertex element (attribute), not
1667 * binding. Set up a map of which bindings step per instance, for
1668 * reference by vertex element setup. */
1669 switch (desc
->inputRate
) {
1671 case VK_VERTEX_INPUT_RATE_VERTEX
:
1672 pipeline
->vb
[desc
->binding
].instanced
= false;
1674 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1675 pipeline
->vb
[desc
->binding
].instanced
= true;
1679 pipeline
->vb
[desc
->binding
].instance_divisor
= 1;
1682 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*vi_div_state
=
1683 vk_find_struct_const(vi_info
->pNext
,
1684 PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
1686 for (uint32_t i
= 0; i
< vi_div_state
->vertexBindingDivisorCount
; i
++) {
1687 const VkVertexInputBindingDivisorDescriptionEXT
*desc
=
1688 &vi_div_state
->pVertexBindingDivisors
[i
];
1690 pipeline
->vb
[desc
->binding
].instance_divisor
= desc
->divisor
;
1694 /* Our implementation of VK_KHR_multiview uses instancing to draw the
1695 * different views. If the client asks for instancing, we need to multiply
1696 * the instance divisor by the number of views ensure that we repeat the
1697 * client's per-instance data once for each view.
1699 if (pipeline
->subpass
->view_mask
) {
1700 const uint32_t view_count
= anv_subpass_view_count(pipeline
->subpass
);
1701 for (uint32_t vb
= 0; vb
< MAX_VBS
; vb
++) {
1702 if (pipeline
->vb
[vb
].instanced
)
1703 pipeline
->vb
[vb
].instance_divisor
*= view_count
;
1707 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1708 pCreateInfo
->pInputAssemblyState
;
1709 const VkPipelineTessellationStateCreateInfo
*tess_info
=
1710 pCreateInfo
->pTessellationState
;
1711 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1713 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1714 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
1716 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];