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[mesa.git] / src / intel / vulkan / anv_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "util/mesa-sha1.h"
31 #include "common/gen_l3_config.h"
32 #include "anv_private.h"
33 #include "compiler/brw_nir.h"
34 #include "anv_nir.h"
35 #include "spirv/nir_spirv.h"
36
37 /* Needed for SWIZZLE macros */
38 #include "program/prog_instruction.h"
39
40 // Shader functions
41
42 VkResult anv_CreateShaderModule(
43 VkDevice _device,
44 const VkShaderModuleCreateInfo* pCreateInfo,
45 const VkAllocationCallbacks* pAllocator,
46 VkShaderModule* pShaderModule)
47 {
48 ANV_FROM_HANDLE(anv_device, device, _device);
49 struct anv_shader_module *module;
50
51 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
52 assert(pCreateInfo->flags == 0);
53
54 module = vk_alloc2(&device->alloc, pAllocator,
55 sizeof(*module) + pCreateInfo->codeSize, 8,
56 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
57 if (module == NULL)
58 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
59
60 module->size = pCreateInfo->codeSize;
61 memcpy(module->data, pCreateInfo->pCode, module->size);
62
63 _mesa_sha1_compute(module->data, module->size, module->sha1);
64
65 *pShaderModule = anv_shader_module_to_handle(module);
66
67 return VK_SUCCESS;
68 }
69
70 void anv_DestroyShaderModule(
71 VkDevice _device,
72 VkShaderModule _module,
73 const VkAllocationCallbacks* pAllocator)
74 {
75 ANV_FROM_HANDLE(anv_device, device, _device);
76 ANV_FROM_HANDLE(anv_shader_module, module, _module);
77
78 if (!module)
79 return;
80
81 vk_free2(&device->alloc, pAllocator, module);
82 }
83
84 #define SPIR_V_MAGIC_NUMBER 0x07230203
85
86 static const uint64_t stage_to_debug[] = {
87 [MESA_SHADER_VERTEX] = DEBUG_VS,
88 [MESA_SHADER_TESS_CTRL] = DEBUG_TCS,
89 [MESA_SHADER_TESS_EVAL] = DEBUG_TES,
90 [MESA_SHADER_GEOMETRY] = DEBUG_GS,
91 [MESA_SHADER_FRAGMENT] = DEBUG_WM,
92 [MESA_SHADER_COMPUTE] = DEBUG_CS,
93 };
94
95 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
96 * we can't do that yet because we don't have the ability to copy nir.
97 */
98 static nir_shader *
99 anv_shader_compile_to_nir(struct anv_pipeline *pipeline,
100 void *mem_ctx,
101 struct anv_shader_module *module,
102 const char *entrypoint_name,
103 gl_shader_stage stage,
104 const VkSpecializationInfo *spec_info)
105 {
106 const struct anv_device *device = pipeline->device;
107
108 const struct brw_compiler *compiler =
109 device->instance->physicalDevice.compiler;
110 const nir_shader_compiler_options *nir_options =
111 compiler->glsl_compiler_options[stage].NirOptions;
112
113 uint32_t *spirv = (uint32_t *) module->data;
114 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
115 assert(module->size % 4 == 0);
116
117 uint32_t num_spec_entries = 0;
118 struct nir_spirv_specialization *spec_entries = NULL;
119 if (spec_info && spec_info->mapEntryCount > 0) {
120 num_spec_entries = spec_info->mapEntryCount;
121 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
122 for (uint32_t i = 0; i < num_spec_entries; i++) {
123 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
124 const void *data = spec_info->pData + entry.offset;
125 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
126
127 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
128 if (spec_info->dataSize == 8)
129 spec_entries[i].data64 = *(const uint64_t *)data;
130 else
131 spec_entries[i].data32 = *(const uint32_t *)data;
132 }
133 }
134
135 struct spirv_to_nir_options spirv_options = {
136 .lower_workgroup_access_to_offsets = true,
137 .caps = {
138 .float64 = device->instance->physicalDevice.info.gen >= 8,
139 .int64 = device->instance->physicalDevice.info.gen >= 8,
140 .tessellation = true,
141 .device_group = true,
142 .draw_parameters = true,
143 .image_write_without_format = true,
144 .multiview = true,
145 .variable_pointers = true,
146 .storage_16bit = device->instance->physicalDevice.info.gen >= 8,
147 .int16 = device->instance->physicalDevice.info.gen >= 8,
148 .shader_viewport_index_layer = true,
149 .subgroup_arithmetic = true,
150 .subgroup_basic = true,
151 .subgroup_ballot = true,
152 .subgroup_quad = true,
153 .subgroup_shuffle = true,
154 .subgroup_vote = true,
155 .stencil_export = device->instance->physicalDevice.info.gen >= 9,
156 },
157 };
158
159 nir_function *entry_point =
160 spirv_to_nir(spirv, module->size / 4,
161 spec_entries, num_spec_entries,
162 stage, entrypoint_name, &spirv_options, nir_options);
163 nir_shader *nir = entry_point->shader;
164 assert(nir->info.stage == stage);
165 nir_validate_shader(nir);
166 ralloc_steal(mem_ctx, nir);
167
168 free(spec_entries);
169
170 if (unlikely(INTEL_DEBUG & stage_to_debug[stage])) {
171 fprintf(stderr, "NIR (from SPIR-V) for %s shader:\n",
172 gl_shader_stage_name(stage));
173 nir_print_shader(nir, stderr);
174 }
175
176 /* We have to lower away local constant initializers right before we
177 * inline functions. That way they get properly initialized at the top
178 * of the function and not at the top of its caller.
179 */
180 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
181 NIR_PASS_V(nir, nir_lower_returns);
182 NIR_PASS_V(nir, nir_inline_functions);
183 NIR_PASS_V(nir, nir_copy_prop);
184
185 /* Pick off the single entrypoint that we want */
186 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
187 if (func != entry_point)
188 exec_node_remove(&func->node);
189 }
190 assert(exec_list_length(&nir->functions) == 1);
191 entry_point->name = ralloc_strdup(entry_point, "main");
192
193 /* Now that we've deleted all but the main function, we can go ahead and
194 * lower the rest of the constant initializers. We do this here so that
195 * nir_remove_dead_variables and split_per_member_structs below see the
196 * corresponding stores.
197 */
198 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
199
200 /* Split member structs. We do this before lower_io_to_temporaries so that
201 * it doesn't lower system values to temporaries by accident.
202 */
203 NIR_PASS_V(nir, nir_split_var_copies);
204 NIR_PASS_V(nir, nir_split_per_member_structs);
205
206 NIR_PASS_V(nir, nir_remove_dead_variables,
207 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
208
209 if (stage == MESA_SHADER_FRAGMENT)
210 NIR_PASS_V(nir, nir_lower_wpos_center, pipeline->sample_shading_enable);
211
212 NIR_PASS_V(nir, nir_propagate_invariant);
213 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
214 entry_point->impl, true, false);
215
216 /* Vulkan uses the separate-shader linking model */
217 nir->info.separate_shader = true;
218
219 nir = brw_preprocess_nir(compiler, nir);
220
221 if (stage == MESA_SHADER_FRAGMENT)
222 NIR_PASS_V(nir, anv_nir_lower_input_attachments);
223
224 return nir;
225 }
226
227 void anv_DestroyPipeline(
228 VkDevice _device,
229 VkPipeline _pipeline,
230 const VkAllocationCallbacks* pAllocator)
231 {
232 ANV_FROM_HANDLE(anv_device, device, _device);
233 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
234
235 if (!pipeline)
236 return;
237
238 anv_reloc_list_finish(&pipeline->batch_relocs,
239 pAllocator ? pAllocator : &device->alloc);
240 if (pipeline->blend_state.map)
241 anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
242
243 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
244 if (pipeline->shaders[s])
245 anv_shader_bin_unref(device, pipeline->shaders[s]);
246 }
247
248 vk_free2(&device->alloc, pAllocator, pipeline);
249 }
250
251 static const uint32_t vk_to_gen_primitive_type[] = {
252 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
253 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
254 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
255 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
256 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
257 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
258 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
259 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
260 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
261 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
262 };
263
264 static void
265 populate_sampler_prog_key(const struct gen_device_info *devinfo,
266 struct brw_sampler_prog_key_data *key)
267 {
268 /* Almost all multisampled textures are compressed. The only time when we
269 * don't compress a multisampled texture is for 16x MSAA with a surface
270 * width greater than 8k which is a bit of an edge case. Since the sampler
271 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
272 * to tell the compiler to always assume compression.
273 */
274 key->compressed_multisample_layout_mask = ~0;
275
276 /* SkyLake added support for 16x MSAA. With this came a new message for
277 * reading from a 16x MSAA surface with compression. The new message was
278 * needed because now the MCS data is 64 bits instead of 32 or lower as is
279 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
280 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
281 * so we can just use it unconditionally. This may not be quite as
282 * efficient but it saves us from recompiling.
283 */
284 if (devinfo->gen >= 9)
285 key->msaa_16 = ~0;
286
287 /* XXX: Handle texture swizzle on HSW- */
288 for (int i = 0; i < MAX_SAMPLERS; i++) {
289 /* Assume color sampler, no swizzling. (Works for BDW+) */
290 key->swizzles[i] = SWIZZLE_XYZW;
291 }
292 }
293
294 static void
295 populate_vs_prog_key(const struct gen_device_info *devinfo,
296 struct brw_vs_prog_key *key)
297 {
298 memset(key, 0, sizeof(*key));
299
300 populate_sampler_prog_key(devinfo, &key->tex);
301
302 /* XXX: Handle vertex input work-arounds */
303
304 /* XXX: Handle sampler_prog_key */
305 }
306
307 static void
308 populate_gs_prog_key(const struct gen_device_info *devinfo,
309 struct brw_gs_prog_key *key)
310 {
311 memset(key, 0, sizeof(*key));
312
313 populate_sampler_prog_key(devinfo, &key->tex);
314 }
315
316 static void
317 populate_wm_prog_key(const struct anv_pipeline *pipeline,
318 const VkGraphicsPipelineCreateInfo *info,
319 struct brw_wm_prog_key *key)
320 {
321 const struct gen_device_info *devinfo = &pipeline->device->info;
322
323 memset(key, 0, sizeof(*key));
324
325 populate_sampler_prog_key(devinfo, &key->tex);
326
327 /* TODO: we could set this to 0 based on the information in nir_shader, but
328 * this function is called before spirv_to_nir. */
329 const struct brw_vue_map *vue_map =
330 &anv_pipeline_get_last_vue_prog_data(pipeline)->vue_map;
331 key->input_slots_valid = vue_map->slots_valid;
332
333 /* Vulkan doesn't specify a default */
334 key->high_quality_derivatives = false;
335
336 /* XXX Vulkan doesn't appear to specify */
337 key->clamp_fragment_color = false;
338
339 key->nr_color_regions = pipeline->subpass->color_count;
340
341 key->replicate_alpha = key->nr_color_regions > 1 &&
342 info->pMultisampleState &&
343 info->pMultisampleState->alphaToCoverageEnable;
344
345 if (info->pMultisampleState) {
346 /* We should probably pull this out of the shader, but it's fairly
347 * harmless to compute it and then let dead-code take care of it.
348 */
349 if (info->pMultisampleState->rasterizationSamples > 1) {
350 key->persample_interp =
351 (info->pMultisampleState->minSampleShading *
352 info->pMultisampleState->rasterizationSamples) > 1;
353 key->multisample_fbo = true;
354 }
355
356 key->frag_coord_adds_sample_pos =
357 info->pMultisampleState->sampleShadingEnable;
358 }
359 }
360
361 static void
362 populate_cs_prog_key(const struct gen_device_info *devinfo,
363 struct brw_cs_prog_key *key)
364 {
365 memset(key, 0, sizeof(*key));
366
367 populate_sampler_prog_key(devinfo, &key->tex);
368 }
369
370 static void
371 anv_pipeline_hash_shader(struct anv_pipeline *pipeline,
372 struct anv_pipeline_layout *layout,
373 struct anv_shader_module *module,
374 const char *entrypoint,
375 gl_shader_stage stage,
376 const VkSpecializationInfo *spec_info,
377 const void *key, size_t key_size,
378 unsigned char *sha1_out)
379 {
380 struct mesa_sha1 ctx;
381
382 _mesa_sha1_init(&ctx);
383 if (stage != MESA_SHADER_COMPUTE) {
384 _mesa_sha1_update(&ctx, &pipeline->subpass->view_mask,
385 sizeof(pipeline->subpass->view_mask));
386 }
387 if (layout)
388 _mesa_sha1_update(&ctx, layout->sha1, sizeof(layout->sha1));
389 _mesa_sha1_update(&ctx, module->sha1, sizeof(module->sha1));
390 _mesa_sha1_update(&ctx, entrypoint, strlen(entrypoint));
391 _mesa_sha1_update(&ctx, &stage, sizeof(stage));
392 if (spec_info) {
393 _mesa_sha1_update(&ctx, spec_info->pMapEntries,
394 spec_info->mapEntryCount * sizeof(*spec_info->pMapEntries));
395 _mesa_sha1_update(&ctx, spec_info->pData, spec_info->dataSize);
396 }
397 _mesa_sha1_update(&ctx, key, key_size);
398 _mesa_sha1_final(&ctx, sha1_out);
399 }
400
401 static nir_shader *
402 anv_pipeline_compile(struct anv_pipeline *pipeline,
403 void *mem_ctx,
404 struct anv_pipeline_layout *layout,
405 struct anv_shader_module *module,
406 const char *entrypoint,
407 gl_shader_stage stage,
408 const VkSpecializationInfo *spec_info,
409 struct brw_stage_prog_data *prog_data,
410 struct anv_pipeline_bind_map *map)
411 {
412 const struct brw_compiler *compiler =
413 pipeline->device->instance->physicalDevice.compiler;
414
415 nir_shader *nir = anv_shader_compile_to_nir(pipeline, mem_ctx,
416 module, entrypoint, stage,
417 spec_info);
418 if (nir == NULL)
419 return NULL;
420
421 NIR_PASS_V(nir, anv_nir_lower_ycbcr_textures, layout);
422
423 NIR_PASS_V(nir, anv_nir_lower_push_constants);
424
425 if (stage != MESA_SHADER_COMPUTE)
426 NIR_PASS_V(nir, anv_nir_lower_multiview, pipeline->subpass->view_mask);
427
428 if (stage == MESA_SHADER_COMPUTE)
429 prog_data->total_shared = nir->num_shared;
430
431 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
432
433 if (nir->num_uniforms > 0) {
434 assert(prog_data->nr_params == 0);
435
436 /* If the shader uses any push constants at all, we'll just give
437 * them the maximum possible number
438 */
439 assert(nir->num_uniforms <= MAX_PUSH_CONSTANTS_SIZE);
440 nir->num_uniforms = MAX_PUSH_CONSTANTS_SIZE;
441 prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
442 prog_data->param = ralloc_array(mem_ctx, uint32_t, prog_data->nr_params);
443
444 /* We now set the param values to be offsets into a
445 * anv_push_constant_data structure. Since the compiler doesn't
446 * actually dereference any of the gl_constant_value pointers in the
447 * params array, it doesn't really matter what we put here.
448 */
449 struct anv_push_constants *null_data = NULL;
450 /* Fill out the push constants section of the param array */
451 for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++) {
452 prog_data->param[i] = ANV_PARAM_PUSH(
453 (uintptr_t)&null_data->client_data[i * sizeof(float)]);
454 }
455 }
456
457 if (nir->info.num_ssbos > 0 || nir->info.num_images > 0)
458 pipeline->needs_data_cache = true;
459
460 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
461 if (layout)
462 anv_nir_apply_pipeline_layout(pipeline, layout, nir, prog_data, map);
463
464 if (stage != MESA_SHADER_COMPUTE)
465 brw_nir_analyze_ubo_ranges(compiler, nir, prog_data->ubo_ranges);
466
467 assert(nir->num_uniforms == prog_data->nr_params * 4);
468
469 return nir;
470 }
471
472 static void
473 anv_fill_binding_table(struct brw_stage_prog_data *prog_data, unsigned bias)
474 {
475 prog_data->binding_table.size_bytes = 0;
476 prog_data->binding_table.texture_start = bias;
477 prog_data->binding_table.gather_texture_start = bias;
478 prog_data->binding_table.ubo_start = bias;
479 prog_data->binding_table.ssbo_start = bias;
480 prog_data->binding_table.image_start = bias;
481 }
482
483 static void
484 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
485 gl_shader_stage stage,
486 struct anv_shader_bin *shader)
487 {
488 pipeline->shaders[stage] = shader;
489 }
490
491 static VkResult
492 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
493 struct anv_pipeline_cache *cache,
494 const VkGraphicsPipelineCreateInfo *info,
495 struct anv_shader_module *module,
496 const char *entrypoint,
497 const VkSpecializationInfo *spec_info)
498 {
499 const struct brw_compiler *compiler =
500 pipeline->device->instance->physicalDevice.compiler;
501 struct brw_vs_prog_key key;
502 struct anv_shader_bin *bin = NULL;
503
504 populate_vs_prog_key(&pipeline->device->info, &key);
505
506 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
507
508 unsigned char sha1[20];
509 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
510 MESA_SHADER_VERTEX, spec_info,
511 &key, sizeof(key), sha1);
512 bin = anv_device_search_for_kernel(pipeline->device, cache, sha1, 20);
513
514 if (bin == NULL) {
515 struct brw_vs_prog_data prog_data = {};
516 struct anv_pipeline_binding surface_to_descriptor[256];
517 struct anv_pipeline_binding sampler_to_descriptor[256];
518
519 struct anv_pipeline_bind_map map = {
520 .surface_to_descriptor = surface_to_descriptor,
521 .sampler_to_descriptor = sampler_to_descriptor
522 };
523
524 void *mem_ctx = ralloc_context(NULL);
525
526 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
527 module, entrypoint,
528 MESA_SHADER_VERTEX, spec_info,
529 &prog_data.base.base, &map);
530 if (nir == NULL) {
531 ralloc_free(mem_ctx);
532 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
533 }
534
535 anv_fill_binding_table(&prog_data.base.base, 0);
536
537 brw_compute_vue_map(&pipeline->device->info,
538 &prog_data.base.vue_map,
539 nir->info.outputs_written,
540 nir->info.separate_shader);
541
542 const unsigned *shader_code =
543 brw_compile_vs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
544 -1, NULL);
545 if (shader_code == NULL) {
546 ralloc_free(mem_ctx);
547 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
548 }
549
550 unsigned code_size = prog_data.base.base.program_size;
551 bin = anv_device_upload_kernel(pipeline->device, cache, sha1, 20,
552 shader_code, code_size,
553 nir->constant_data,
554 nir->constant_data_size,
555 &prog_data.base.base, sizeof(prog_data),
556 &map);
557 if (!bin) {
558 ralloc_free(mem_ctx);
559 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
560 }
561
562 ralloc_free(mem_ctx);
563 }
564
565 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX, bin);
566
567 return VK_SUCCESS;
568 }
569
570 static void
571 merge_tess_info(struct shader_info *tes_info,
572 const struct shader_info *tcs_info)
573 {
574 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
575 *
576 * "PointMode. Controls generation of points rather than triangles
577 * or lines. This functionality defaults to disabled, and is
578 * enabled if either shader stage includes the execution mode.
579 *
580 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
581 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
582 * and OutputVertices, it says:
583 *
584 * "One mode must be set in at least one of the tessellation
585 * shader stages."
586 *
587 * So, the fields can be set in either the TCS or TES, but they must
588 * agree if set in both. Our backend looks at TES, so bitwise-or in
589 * the values from the TCS.
590 */
591 assert(tcs_info->tess.tcs_vertices_out == 0 ||
592 tes_info->tess.tcs_vertices_out == 0 ||
593 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
594 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
595
596 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
597 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
598 tcs_info->tess.spacing == tes_info->tess.spacing);
599 tes_info->tess.spacing |= tcs_info->tess.spacing;
600
601 assert(tcs_info->tess.primitive_mode == 0 ||
602 tes_info->tess.primitive_mode == 0 ||
603 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
604 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
605 tes_info->tess.ccw |= tcs_info->tess.ccw;
606 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
607 }
608
609 static VkResult
610 anv_pipeline_compile_tcs_tes(struct anv_pipeline *pipeline,
611 struct anv_pipeline_cache *cache,
612 const VkGraphicsPipelineCreateInfo *info,
613 struct anv_shader_module *tcs_module,
614 const char *tcs_entrypoint,
615 const VkSpecializationInfo *tcs_spec_info,
616 struct anv_shader_module *tes_module,
617 const char *tes_entrypoint,
618 const VkSpecializationInfo *tes_spec_info)
619 {
620 const struct gen_device_info *devinfo = &pipeline->device->info;
621 const struct brw_compiler *compiler =
622 pipeline->device->instance->physicalDevice.compiler;
623 struct brw_tcs_prog_key tcs_key = {};
624 struct brw_tes_prog_key tes_key = {};
625 struct anv_shader_bin *tcs_bin = NULL;
626 struct anv_shader_bin *tes_bin = NULL;
627
628 populate_sampler_prog_key(&pipeline->device->info, &tcs_key.tex);
629 populate_sampler_prog_key(&pipeline->device->info, &tes_key.tex);
630 tcs_key.input_vertices = info->pTessellationState->patchControlPoints;
631
632 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
633
634 unsigned char tcs_sha1[40];
635 unsigned char tes_sha1[40];
636 anv_pipeline_hash_shader(pipeline, layout, tcs_module, tcs_entrypoint,
637 MESA_SHADER_TESS_CTRL, tcs_spec_info,
638 &tcs_key, sizeof(tcs_key), tcs_sha1);
639 anv_pipeline_hash_shader(pipeline, layout, tes_module, tes_entrypoint,
640 MESA_SHADER_TESS_EVAL, tes_spec_info,
641 &tes_key, sizeof(tes_key), tes_sha1);
642 memcpy(&tcs_sha1[20], tes_sha1, 20);
643 memcpy(&tes_sha1[20], tcs_sha1, 20);
644
645 tcs_bin = anv_device_search_for_kernel(pipeline->device, cache,
646 tcs_sha1, sizeof(tcs_sha1));
647 tes_bin = anv_device_search_for_kernel(pipeline->device, cache,
648 tes_sha1, sizeof(tes_sha1));
649
650 if (tcs_bin == NULL || tes_bin == NULL) {
651 struct brw_tcs_prog_data tcs_prog_data = {};
652 struct brw_tes_prog_data tes_prog_data = {};
653 struct anv_pipeline_binding tcs_surface_to_descriptor[256];
654 struct anv_pipeline_binding tcs_sampler_to_descriptor[256];
655 struct anv_pipeline_binding tes_surface_to_descriptor[256];
656 struct anv_pipeline_binding tes_sampler_to_descriptor[256];
657
658 struct anv_pipeline_bind_map tcs_map = {
659 .surface_to_descriptor = tcs_surface_to_descriptor,
660 .sampler_to_descriptor = tcs_sampler_to_descriptor
661 };
662 struct anv_pipeline_bind_map tes_map = {
663 .surface_to_descriptor = tes_surface_to_descriptor,
664 .sampler_to_descriptor = tes_sampler_to_descriptor
665 };
666
667 void *mem_ctx = ralloc_context(NULL);
668
669 nir_shader *tcs_nir =
670 anv_pipeline_compile(pipeline, mem_ctx, layout,
671 tcs_module, tcs_entrypoint,
672 MESA_SHADER_TESS_CTRL, tcs_spec_info,
673 &tcs_prog_data.base.base, &tcs_map);
674 nir_shader *tes_nir =
675 anv_pipeline_compile(pipeline, mem_ctx, layout,
676 tes_module, tes_entrypoint,
677 MESA_SHADER_TESS_EVAL, tes_spec_info,
678 &tes_prog_data.base.base, &tes_map);
679 if (tcs_nir == NULL || tes_nir == NULL) {
680 ralloc_free(mem_ctx);
681 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
682 }
683
684 nir_lower_tes_patch_vertices(tes_nir,
685 tcs_nir->info.tess.tcs_vertices_out);
686
687 /* Copy TCS info into the TES info */
688 merge_tess_info(&tes_nir->info, &tcs_nir->info);
689
690 anv_fill_binding_table(&tcs_prog_data.base.base, 0);
691 anv_fill_binding_table(&tes_prog_data.base.base, 0);
692
693 /* Whacking the key after cache lookup is a bit sketchy, but all of
694 * this comes from the SPIR-V, which is part of the hash used for the
695 * pipeline cache. So it should be safe.
696 */
697 tcs_key.tes_primitive_mode = tes_nir->info.tess.primitive_mode;
698 tcs_key.outputs_written = tcs_nir->info.outputs_written;
699 tcs_key.patch_outputs_written = tcs_nir->info.patch_outputs_written;
700 tcs_key.quads_workaround =
701 devinfo->gen < 9 &&
702 tes_nir->info.tess.primitive_mode == 7 /* GL_QUADS */ &&
703 tes_nir->info.tess.spacing == TESS_SPACING_EQUAL;
704
705 tes_key.inputs_read = tcs_key.outputs_written;
706 tes_key.patch_inputs_read = tcs_key.patch_outputs_written;
707
708 const int shader_time_index = -1;
709 const unsigned *shader_code;
710
711 shader_code =
712 brw_compile_tcs(compiler, NULL, mem_ctx, &tcs_key, &tcs_prog_data,
713 tcs_nir, shader_time_index, NULL);
714 if (shader_code == NULL) {
715 ralloc_free(mem_ctx);
716 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
717 }
718
719 unsigned code_size = tcs_prog_data.base.base.program_size;
720 tcs_bin = anv_device_upload_kernel(pipeline->device, cache,
721 tcs_sha1, sizeof(tcs_sha1),
722 shader_code, code_size,
723 tcs_nir->constant_data,
724 tcs_nir->constant_data_size,
725 &tcs_prog_data.base.base,
726 sizeof(tcs_prog_data),
727 &tcs_map);
728 if (!tcs_bin) {
729 ralloc_free(mem_ctx);
730 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
731 }
732
733 shader_code =
734 brw_compile_tes(compiler, NULL, mem_ctx, &tes_key,
735 &tcs_prog_data.base.vue_map, &tes_prog_data, tes_nir,
736 NULL, shader_time_index, NULL);
737 if (shader_code == NULL) {
738 ralloc_free(mem_ctx);
739 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
740 }
741
742 code_size = tes_prog_data.base.base.program_size;
743 tes_bin = anv_device_upload_kernel(pipeline->device, cache,
744 tes_sha1, sizeof(tes_sha1),
745 shader_code, code_size,
746 tes_nir->constant_data,
747 tes_nir->constant_data_size,
748 &tes_prog_data.base.base,
749 sizeof(tes_prog_data),
750 &tes_map);
751 if (!tes_bin) {
752 ralloc_free(mem_ctx);
753 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
754 }
755
756 ralloc_free(mem_ctx);
757 }
758
759 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_TESS_CTRL, tcs_bin);
760 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_TESS_EVAL, tes_bin);
761
762 return VK_SUCCESS;
763 }
764
765 static VkResult
766 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
767 struct anv_pipeline_cache *cache,
768 const VkGraphicsPipelineCreateInfo *info,
769 struct anv_shader_module *module,
770 const char *entrypoint,
771 const VkSpecializationInfo *spec_info)
772 {
773 const struct brw_compiler *compiler =
774 pipeline->device->instance->physicalDevice.compiler;
775 struct brw_gs_prog_key key;
776 struct anv_shader_bin *bin = NULL;
777
778 populate_gs_prog_key(&pipeline->device->info, &key);
779
780 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
781
782 unsigned char sha1[20];
783 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
784 MESA_SHADER_GEOMETRY, spec_info,
785 &key, sizeof(key), sha1);
786 bin = anv_device_search_for_kernel(pipeline->device, cache, sha1, 20);
787
788 if (bin == NULL) {
789 struct brw_gs_prog_data prog_data = {};
790 struct anv_pipeline_binding surface_to_descriptor[256];
791 struct anv_pipeline_binding sampler_to_descriptor[256];
792
793 struct anv_pipeline_bind_map map = {
794 .surface_to_descriptor = surface_to_descriptor,
795 .sampler_to_descriptor = sampler_to_descriptor
796 };
797
798 void *mem_ctx = ralloc_context(NULL);
799
800 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
801 module, entrypoint,
802 MESA_SHADER_GEOMETRY, spec_info,
803 &prog_data.base.base, &map);
804 if (nir == NULL) {
805 ralloc_free(mem_ctx);
806 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
807 }
808
809 anv_fill_binding_table(&prog_data.base.base, 0);
810
811 brw_compute_vue_map(&pipeline->device->info,
812 &prog_data.base.vue_map,
813 nir->info.outputs_written,
814 nir->info.separate_shader);
815
816 const unsigned *shader_code =
817 brw_compile_gs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
818 NULL, -1, NULL);
819 if (shader_code == NULL) {
820 ralloc_free(mem_ctx);
821 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
822 }
823
824 /* TODO: SIMD8 GS */
825 const unsigned code_size = prog_data.base.base.program_size;
826 bin = anv_device_upload_kernel(pipeline->device, cache, sha1, 20,
827 shader_code, code_size,
828 nir->constant_data,
829 nir->constant_data_size,
830 &prog_data.base.base, sizeof(prog_data),
831 &map);
832 if (!bin) {
833 ralloc_free(mem_ctx);
834 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
835 }
836
837 ralloc_free(mem_ctx);
838 }
839
840 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY, bin);
841
842 return VK_SUCCESS;
843 }
844
845 static VkResult
846 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
847 struct anv_pipeline_cache *cache,
848 const VkGraphicsPipelineCreateInfo *info,
849 struct anv_shader_module *module,
850 const char *entrypoint,
851 const VkSpecializationInfo *spec_info)
852 {
853 const struct brw_compiler *compiler =
854 pipeline->device->instance->physicalDevice.compiler;
855 struct brw_wm_prog_key key;
856 struct anv_shader_bin *bin = NULL;
857
858 populate_wm_prog_key(pipeline, info, &key);
859
860 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
861
862 unsigned char sha1[20];
863 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
864 MESA_SHADER_FRAGMENT, spec_info,
865 &key, sizeof(key), sha1);
866 bin = anv_device_search_for_kernel(pipeline->device, cache, sha1, 20);
867
868 if (bin == NULL) {
869 struct brw_wm_prog_data prog_data = {};
870 struct anv_pipeline_binding surface_to_descriptor[256];
871 struct anv_pipeline_binding sampler_to_descriptor[256];
872
873 struct anv_pipeline_bind_map map = {
874 .surface_to_descriptor = surface_to_descriptor + 8,
875 .sampler_to_descriptor = sampler_to_descriptor
876 };
877
878 void *mem_ctx = ralloc_context(NULL);
879
880 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
881 module, entrypoint,
882 MESA_SHADER_FRAGMENT, spec_info,
883 &prog_data.base, &map);
884 if (nir == NULL) {
885 ralloc_free(mem_ctx);
886 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
887 }
888
889 unsigned num_rts = 0;
890 const int max_rt = FRAG_RESULT_DATA7 - FRAG_RESULT_DATA0 + 1;
891 struct anv_pipeline_binding rt_bindings[max_rt];
892 nir_function_impl *impl = nir_shader_get_entrypoint(nir);
893 int rt_to_bindings[max_rt];
894 memset(rt_to_bindings, -1, sizeof(rt_to_bindings));
895 bool rt_used[max_rt];
896 memset(rt_used, 0, sizeof(rt_used));
897
898 /* Flag used render targets */
899 nir_foreach_variable_safe(var, &nir->outputs) {
900 if (var->data.location < FRAG_RESULT_DATA0)
901 continue;
902
903 const unsigned rt = var->data.location - FRAG_RESULT_DATA0;
904 /* Out-of-bounds */
905 if (rt >= key.nr_color_regions)
906 continue;
907
908 const unsigned array_len =
909 glsl_type_is_array(var->type) ? glsl_get_length(var->type) : 1;
910 assert(rt + array_len <= max_rt);
911
912 for (unsigned i = 0; i < array_len; i++)
913 rt_used[rt + i] = true;
914 }
915
916 /* Set new, compacted, location */
917 for (unsigned i = 0; i < max_rt; i++) {
918 if (!rt_used[i])
919 continue;
920
921 rt_to_bindings[i] = num_rts;
922 rt_bindings[rt_to_bindings[i]] = (struct anv_pipeline_binding) {
923 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
924 .binding = 0,
925 .index = i,
926 };
927 num_rts++;
928 }
929
930 nir_foreach_variable_safe(var, &nir->outputs) {
931 if (var->data.location < FRAG_RESULT_DATA0)
932 continue;
933
934 const unsigned rt = var->data.location - FRAG_RESULT_DATA0;
935 if (rt >= key.nr_color_regions) {
936 /* Out-of-bounds, throw it away */
937 var->data.mode = nir_var_local;
938 exec_node_remove(&var->node);
939 exec_list_push_tail(&impl->locals, &var->node);
940 continue;
941 }
942
943 /* Give it the new location */
944 assert(rt_to_bindings[rt] != -1);
945 var->data.location = rt_to_bindings[rt] + FRAG_RESULT_DATA0;
946 }
947
948 if (num_rts == 0) {
949 /* If we have no render targets, we need a null render target */
950 rt_bindings[0] = (struct anv_pipeline_binding) {
951 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
952 .binding = 0,
953 .index = UINT32_MAX,
954 };
955 num_rts = 1;
956 }
957
958 assert(num_rts <= max_rt);
959 map.surface_to_descriptor -= num_rts;
960 map.surface_count += num_rts;
961 assert(map.surface_count <= 256);
962 memcpy(map.surface_to_descriptor, rt_bindings,
963 num_rts * sizeof(*rt_bindings));
964
965 anv_fill_binding_table(&prog_data.base, num_rts);
966
967 const unsigned *shader_code =
968 brw_compile_fs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
969 NULL, -1, -1, -1, true, false, NULL, NULL);
970 if (shader_code == NULL) {
971 ralloc_free(mem_ctx);
972 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
973 }
974
975 unsigned code_size = prog_data.base.program_size;
976 bin = anv_device_upload_kernel(pipeline->device, cache, sha1, 20,
977 shader_code, code_size,
978 nir->constant_data,
979 nir->constant_data_size,
980 &prog_data.base, sizeof(prog_data),
981 &map);
982 if (!bin) {
983 ralloc_free(mem_ctx);
984 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
985 }
986
987 ralloc_free(mem_ctx);
988 }
989
990 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT, bin);
991
992 return VK_SUCCESS;
993 }
994
995 VkResult
996 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
997 struct anv_pipeline_cache *cache,
998 const VkComputePipelineCreateInfo *info,
999 struct anv_shader_module *module,
1000 const char *entrypoint,
1001 const VkSpecializationInfo *spec_info)
1002 {
1003 const struct brw_compiler *compiler =
1004 pipeline->device->instance->physicalDevice.compiler;
1005 struct brw_cs_prog_key key;
1006 struct anv_shader_bin *bin = NULL;
1007
1008 populate_cs_prog_key(&pipeline->device->info, &key);
1009
1010 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
1011
1012 unsigned char sha1[20];
1013 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
1014 MESA_SHADER_COMPUTE, spec_info,
1015 &key, sizeof(key), sha1);
1016 bin = anv_device_search_for_kernel(pipeline->device, cache, sha1, 20);
1017
1018 if (bin == NULL) {
1019 struct brw_cs_prog_data prog_data = {};
1020 struct anv_pipeline_binding surface_to_descriptor[256];
1021 struct anv_pipeline_binding sampler_to_descriptor[256];
1022
1023 struct anv_pipeline_bind_map map = {
1024 .surface_to_descriptor = surface_to_descriptor,
1025 .sampler_to_descriptor = sampler_to_descriptor
1026 };
1027
1028 void *mem_ctx = ralloc_context(NULL);
1029
1030 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
1031 module, entrypoint,
1032 MESA_SHADER_COMPUTE, spec_info,
1033 &prog_data.base, &map);
1034 if (nir == NULL) {
1035 ralloc_free(mem_ctx);
1036 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1037 }
1038
1039 NIR_PASS_V(nir, anv_nir_add_base_work_group_id, &prog_data);
1040
1041 anv_fill_binding_table(&prog_data.base, 1);
1042
1043 const unsigned *shader_code =
1044 brw_compile_cs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
1045 -1, NULL);
1046 if (shader_code == NULL) {
1047 ralloc_free(mem_ctx);
1048 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1049 }
1050
1051 const unsigned code_size = prog_data.base.program_size;
1052 bin = anv_device_upload_kernel(pipeline->device, cache, sha1, 20,
1053 shader_code, code_size,
1054 nir->constant_data,
1055 nir->constant_data_size,
1056 &prog_data.base, sizeof(prog_data),
1057 &map);
1058 if (!bin) {
1059 ralloc_free(mem_ctx);
1060 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1061 }
1062
1063 ralloc_free(mem_ctx);
1064 }
1065
1066 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE, bin);
1067
1068 return VK_SUCCESS;
1069 }
1070
1071 /**
1072 * Copy pipeline state not marked as dynamic.
1073 * Dynamic state is pipeline state which hasn't been provided at pipeline
1074 * creation time, but is dynamically provided afterwards using various
1075 * vkCmdSet* functions.
1076 *
1077 * The set of state considered "non_dynamic" is determined by the pieces of
1078 * state that have their corresponding VkDynamicState enums omitted from
1079 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1080 *
1081 * @param[out] pipeline Destination non_dynamic state.
1082 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1083 */
1084 static void
1085 copy_non_dynamic_state(struct anv_pipeline *pipeline,
1086 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1087 {
1088 anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
1089 struct anv_subpass *subpass = pipeline->subpass;
1090
1091 pipeline->dynamic_state = default_dynamic_state;
1092
1093 if (pCreateInfo->pDynamicState) {
1094 /* Remove all of the states that are marked as dynamic */
1095 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1096 for (uint32_t s = 0; s < count; s++)
1097 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1098 }
1099
1100 struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
1101
1102 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1103 *
1104 * pViewportState is [...] NULL if the pipeline
1105 * has rasterization disabled.
1106 */
1107 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1108 assert(pCreateInfo->pViewportState);
1109
1110 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1111 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1112 typed_memcpy(dynamic->viewport.viewports,
1113 pCreateInfo->pViewportState->pViewports,
1114 pCreateInfo->pViewportState->viewportCount);
1115 }
1116
1117 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1118 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1119 typed_memcpy(dynamic->scissor.scissors,
1120 pCreateInfo->pViewportState->pScissors,
1121 pCreateInfo->pViewportState->scissorCount);
1122 }
1123 }
1124
1125 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1126 assert(pCreateInfo->pRasterizationState);
1127 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1128 }
1129
1130 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1131 assert(pCreateInfo->pRasterizationState);
1132 dynamic->depth_bias.bias =
1133 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1134 dynamic->depth_bias.clamp =
1135 pCreateInfo->pRasterizationState->depthBiasClamp;
1136 dynamic->depth_bias.slope =
1137 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1138 }
1139
1140 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1141 *
1142 * pColorBlendState is [...] NULL if the pipeline has rasterization
1143 * disabled or if the subpass of the render pass the pipeline is
1144 * created against does not use any color attachments.
1145 */
1146 bool uses_color_att = false;
1147 for (unsigned i = 0; i < subpass->color_count; ++i) {
1148 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1149 uses_color_att = true;
1150 break;
1151 }
1152 }
1153
1154 if (uses_color_att &&
1155 !pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1156 assert(pCreateInfo->pColorBlendState);
1157
1158 if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
1159 typed_memcpy(dynamic->blend_constants,
1160 pCreateInfo->pColorBlendState->blendConstants, 4);
1161 }
1162
1163 /* If there is no depthstencil attachment, then don't read
1164 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1165 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1166 * no need to override the depthstencil defaults in
1167 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1168 *
1169 * Section 9.2 of the Vulkan 1.0.15 spec says:
1170 *
1171 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1172 * disabled or if the subpass of the render pass the pipeline is created
1173 * against does not use a depth/stencil attachment.
1174 */
1175 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1176 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1177 assert(pCreateInfo->pDepthStencilState);
1178
1179 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1180 dynamic->depth_bounds.min =
1181 pCreateInfo->pDepthStencilState->minDepthBounds;
1182 dynamic->depth_bounds.max =
1183 pCreateInfo->pDepthStencilState->maxDepthBounds;
1184 }
1185
1186 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1187 dynamic->stencil_compare_mask.front =
1188 pCreateInfo->pDepthStencilState->front.compareMask;
1189 dynamic->stencil_compare_mask.back =
1190 pCreateInfo->pDepthStencilState->back.compareMask;
1191 }
1192
1193 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1194 dynamic->stencil_write_mask.front =
1195 pCreateInfo->pDepthStencilState->front.writeMask;
1196 dynamic->stencil_write_mask.back =
1197 pCreateInfo->pDepthStencilState->back.writeMask;
1198 }
1199
1200 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1201 dynamic->stencil_reference.front =
1202 pCreateInfo->pDepthStencilState->front.reference;
1203 dynamic->stencil_reference.back =
1204 pCreateInfo->pDepthStencilState->back.reference;
1205 }
1206 }
1207
1208 pipeline->dynamic_state_mask = states;
1209 }
1210
1211 static void
1212 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
1213 {
1214 #ifdef DEBUG
1215 struct anv_render_pass *renderpass = NULL;
1216 struct anv_subpass *subpass = NULL;
1217
1218 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1219 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1220 */
1221 assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
1222
1223 renderpass = anv_render_pass_from_handle(info->renderPass);
1224 assert(renderpass);
1225
1226 assert(info->subpass < renderpass->subpass_count);
1227 subpass = &renderpass->subpasses[info->subpass];
1228
1229 assert(info->stageCount >= 1);
1230 assert(info->pVertexInputState);
1231 assert(info->pInputAssemblyState);
1232 assert(info->pRasterizationState);
1233 if (!info->pRasterizationState->rasterizerDiscardEnable) {
1234 assert(info->pViewportState);
1235 assert(info->pMultisampleState);
1236
1237 if (subpass && subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
1238 assert(info->pDepthStencilState);
1239
1240 if (subpass && subpass->color_count > 0) {
1241 bool all_color_unused = true;
1242 for (int i = 0; i < subpass->color_count; i++) {
1243 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1244 all_color_unused = false;
1245 }
1246 /* pColorBlendState is ignored if the pipeline has rasterization
1247 * disabled or if the subpass of the render pass the pipeline is
1248 * created against does not use any color attachments.
1249 */
1250 assert(info->pColorBlendState || all_color_unused);
1251 }
1252 }
1253
1254 for (uint32_t i = 0; i < info->stageCount; ++i) {
1255 switch (info->pStages[i].stage) {
1256 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
1257 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
1258 assert(info->pTessellationState);
1259 break;
1260 default:
1261 break;
1262 }
1263 }
1264 #endif
1265 }
1266
1267 /**
1268 * Calculate the desired L3 partitioning based on the current state of the
1269 * pipeline. For now this simply returns the conservative defaults calculated
1270 * by get_default_l3_weights(), but we could probably do better by gathering
1271 * more statistics from the pipeline state (e.g. guess of expected URB usage
1272 * and bound surfaces), or by using feed-back from performance counters.
1273 */
1274 void
1275 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm)
1276 {
1277 const struct gen_device_info *devinfo = &pipeline->device->info;
1278
1279 const struct gen_l3_weights w =
1280 gen_get_default_l3_weights(devinfo, pipeline->needs_data_cache, needs_slm);
1281
1282 pipeline->urb.l3_config = gen_get_l3_config(devinfo, w);
1283 pipeline->urb.total_size =
1284 gen_get_l3_config_urb_size(devinfo, pipeline->urb.l3_config);
1285 }
1286
1287 VkResult
1288 anv_pipeline_init(struct anv_pipeline *pipeline,
1289 struct anv_device *device,
1290 struct anv_pipeline_cache *cache,
1291 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1292 const VkAllocationCallbacks *alloc)
1293 {
1294 VkResult result;
1295
1296 anv_pipeline_validate_create_info(pCreateInfo);
1297
1298 if (alloc == NULL)
1299 alloc = &device->alloc;
1300
1301 pipeline->device = device;
1302
1303 ANV_FROM_HANDLE(anv_render_pass, render_pass, pCreateInfo->renderPass);
1304 assert(pCreateInfo->subpass < render_pass->subpass_count);
1305 pipeline->subpass = &render_pass->subpasses[pCreateInfo->subpass];
1306
1307 result = anv_reloc_list_init(&pipeline->batch_relocs, alloc);
1308 if (result != VK_SUCCESS)
1309 return result;
1310
1311 pipeline->batch.alloc = alloc;
1312 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
1313 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
1314 pipeline->batch.relocs = &pipeline->batch_relocs;
1315 pipeline->batch.status = VK_SUCCESS;
1316
1317 copy_non_dynamic_state(pipeline, pCreateInfo);
1318 pipeline->depth_clamp_enable = pCreateInfo->pRasterizationState &&
1319 pCreateInfo->pRasterizationState->depthClampEnable;
1320
1321 pipeline->sample_shading_enable = pCreateInfo->pMultisampleState &&
1322 pCreateInfo->pMultisampleState->sampleShadingEnable;
1323
1324 pipeline->needs_data_cache = false;
1325
1326 /* When we free the pipeline, we detect stages based on the NULL status
1327 * of various prog_data pointers. Make them NULL by default.
1328 */
1329 memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
1330
1331 pipeline->active_stages = 0;
1332
1333 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = {};
1334 struct anv_shader_module *modules[MESA_SHADER_STAGES] = {};
1335 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1336 VkShaderStageFlagBits vk_stage = pCreateInfo->pStages[i].stage;
1337 gl_shader_stage stage = vk_to_mesa_shader_stage(vk_stage);
1338 pStages[stage] = &pCreateInfo->pStages[i];
1339 modules[stage] = anv_shader_module_from_handle(pStages[stage]->module);
1340 pipeline->active_stages |= vk_stage;
1341 }
1342
1343 if (pipeline->active_stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT)
1344 pipeline->active_stages |= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT;
1345
1346 assert(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT);
1347
1348 if (modules[MESA_SHADER_VERTEX]) {
1349 result = anv_pipeline_compile_vs(pipeline, cache, pCreateInfo,
1350 modules[MESA_SHADER_VERTEX],
1351 pStages[MESA_SHADER_VERTEX]->pName,
1352 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo);
1353 if (result != VK_SUCCESS)
1354 goto compile_fail;
1355 }
1356
1357 if (modules[MESA_SHADER_TESS_EVAL]) {
1358 result = anv_pipeline_compile_tcs_tes(pipeline, cache, pCreateInfo,
1359 modules[MESA_SHADER_TESS_CTRL],
1360 pStages[MESA_SHADER_TESS_CTRL]->pName,
1361 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
1362 modules[MESA_SHADER_TESS_EVAL],
1363 pStages[MESA_SHADER_TESS_EVAL]->pName,
1364 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo);
1365 if (result != VK_SUCCESS)
1366 goto compile_fail;
1367 }
1368
1369 if (modules[MESA_SHADER_GEOMETRY]) {
1370 result = anv_pipeline_compile_gs(pipeline, cache, pCreateInfo,
1371 modules[MESA_SHADER_GEOMETRY],
1372 pStages[MESA_SHADER_GEOMETRY]->pName,
1373 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo);
1374 if (result != VK_SUCCESS)
1375 goto compile_fail;
1376 }
1377
1378 if (modules[MESA_SHADER_FRAGMENT]) {
1379 result = anv_pipeline_compile_fs(pipeline, cache, pCreateInfo,
1380 modules[MESA_SHADER_FRAGMENT],
1381 pStages[MESA_SHADER_FRAGMENT]->pName,
1382 pStages[MESA_SHADER_FRAGMENT]->pSpecializationInfo);
1383 if (result != VK_SUCCESS)
1384 goto compile_fail;
1385 }
1386
1387 assert(pipeline->shaders[MESA_SHADER_VERTEX]);
1388
1389 anv_pipeline_setup_l3_config(pipeline, false);
1390
1391 const VkPipelineVertexInputStateCreateInfo *vi_info =
1392 pCreateInfo->pVertexInputState;
1393
1394 const uint64_t inputs_read = get_vs_prog_data(pipeline)->inputs_read;
1395
1396 pipeline->vb_used = 0;
1397 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1398 const VkVertexInputAttributeDescription *desc =
1399 &vi_info->pVertexAttributeDescriptions[i];
1400
1401 if (inputs_read & (1ull << (VERT_ATTRIB_GENERIC0 + desc->location)))
1402 pipeline->vb_used |= 1 << desc->binding;
1403 }
1404
1405 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1406 const VkVertexInputBindingDescription *desc =
1407 &vi_info->pVertexBindingDescriptions[i];
1408
1409 pipeline->binding_stride[desc->binding] = desc->stride;
1410
1411 /* Step rate is programmed per vertex element (attribute), not
1412 * binding. Set up a map of which bindings step per instance, for
1413 * reference by vertex element setup. */
1414 switch (desc->inputRate) {
1415 default:
1416 case VK_VERTEX_INPUT_RATE_VERTEX:
1417 pipeline->instancing_enable[desc->binding] = false;
1418 break;
1419 case VK_VERTEX_INPUT_RATE_INSTANCE:
1420 pipeline->instancing_enable[desc->binding] = true;
1421 break;
1422 }
1423 }
1424
1425 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1426 pCreateInfo->pInputAssemblyState;
1427 const VkPipelineTessellationStateCreateInfo *tess_info =
1428 pCreateInfo->pTessellationState;
1429 pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1430
1431 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
1432 pipeline->topology = _3DPRIM_PATCHLIST(tess_info->patchControlPoints);
1433 else
1434 pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1435
1436 return VK_SUCCESS;
1437
1438 compile_fail:
1439 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
1440 if (pipeline->shaders[s])
1441 anv_shader_bin_unref(device, pipeline->shaders[s]);
1442 }
1443
1444 anv_reloc_list_finish(&pipeline->batch_relocs, alloc);
1445
1446 return result;
1447 }