2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "common/gen_l3_config.h"
32 #include "anv_private.h"
35 #include "spirv/nir_spirv.h"
37 /* Needed for SWIZZLE macros */
38 #include "program/prog_instruction.h"
42 VkResult
anv_CreateShaderModule(
44 const VkShaderModuleCreateInfo
* pCreateInfo
,
45 const VkAllocationCallbacks
* pAllocator
,
46 VkShaderModule
* pShaderModule
)
48 ANV_FROM_HANDLE(anv_device
, device
, _device
);
49 struct anv_shader_module
*module
;
51 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
52 assert(pCreateInfo
->flags
== 0);
54 module
= vk_alloc2(&device
->alloc
, pAllocator
,
55 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
56 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
58 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
60 module
->size
= pCreateInfo
->codeSize
;
61 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
63 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
65 *pShaderModule
= anv_shader_module_to_handle(module
);
70 void anv_DestroyShaderModule(
72 VkShaderModule _module
,
73 const VkAllocationCallbacks
* pAllocator
)
75 ANV_FROM_HANDLE(anv_device
, device
, _device
);
76 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
81 vk_free2(&device
->alloc
, pAllocator
, module
);
84 #define SPIR_V_MAGIC_NUMBER 0x07230203
86 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
87 * we can't do that yet because we don't have the ability to copy nir.
90 anv_shader_compile_to_nir(struct anv_device
*device
,
91 struct anv_shader_module
*module
,
92 const char *entrypoint_name
,
93 gl_shader_stage stage
,
94 const VkSpecializationInfo
*spec_info
)
96 if (strcmp(entrypoint_name
, "main") != 0) {
97 anv_finishme("Multiple shaders per module not really supported");
100 const struct brw_compiler
*compiler
=
101 device
->instance
->physicalDevice
.compiler
;
102 const nir_shader_compiler_options
*nir_options
=
103 compiler
->glsl_compiler_options
[stage
].NirOptions
;
105 uint32_t *spirv
= (uint32_t *) module
->data
;
106 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
107 assert(module
->size
% 4 == 0);
109 uint32_t num_spec_entries
= 0;
110 struct nir_spirv_specialization
*spec_entries
= NULL
;
111 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
112 num_spec_entries
= spec_info
->mapEntryCount
;
113 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
114 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
115 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
116 const void *data
= spec_info
->pData
+ entry
.offset
;
117 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
119 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
120 if (spec_info
->dataSize
== 8)
121 spec_entries
[i
].data64
= *(const uint64_t *)data
;
123 spec_entries
[i
].data32
= *(const uint32_t *)data
;
127 const struct nir_spirv_supported_extensions supported_ext
= {
128 .float64
= device
->instance
->physicalDevice
.info
.gen
>= 8,
131 nir_function
*entry_point
=
132 spirv_to_nir(spirv
, module
->size
/ 4,
133 spec_entries
, num_spec_entries
,
134 stage
, entrypoint_name
, &supported_ext
, nir_options
);
135 nir_shader
*nir
= entry_point
->shader
;
136 assert(nir
->stage
== stage
);
137 nir_validate_shader(nir
);
141 if (stage
== MESA_SHADER_FRAGMENT
)
142 NIR_PASS_V(nir
, nir_lower_wpos_center
);
144 /* We have to lower away local constant initializers right before we
145 * inline functions. That way they get properly initialized at the top
146 * of the function and not at the top of its caller.
148 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_local
);
149 NIR_PASS_V(nir
, nir_lower_returns
);
150 NIR_PASS_V(nir
, nir_inline_functions
);
152 /* Pick off the single entrypoint that we want */
153 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
154 if (func
!= entry_point
)
155 exec_node_remove(&func
->node
);
157 assert(exec_list_length(&nir
->functions
) == 1);
158 entry_point
->name
= ralloc_strdup(entry_point
, "main");
160 NIR_PASS_V(nir
, nir_remove_dead_variables
,
161 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
163 /* Now that we've deleted all but the main function, we can go ahead and
164 * lower the rest of the constant initializers.
166 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
167 NIR_PASS_V(nir
, nir_propagate_invariant
);
168 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
169 entry_point
->impl
, true, false);
170 NIR_PASS_V(nir
, nir_lower_system_values
);
172 /* Vulkan uses the separate-shader linking model */
173 nir
->info
->separate_shader
= true;
175 nir
= brw_preprocess_nir(compiler
, nir
);
177 NIR_PASS_V(nir
, nir_lower_clip_cull_distance_arrays
);
179 if (stage
== MESA_SHADER_FRAGMENT
)
180 NIR_PASS_V(nir
, anv_nir_lower_input_attachments
);
182 nir_shader_gather_info(nir
, entry_point
->impl
);
187 void anv_DestroyPipeline(
189 VkPipeline _pipeline
,
190 const VkAllocationCallbacks
* pAllocator
)
192 ANV_FROM_HANDLE(anv_device
, device
, _device
);
193 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
198 anv_reloc_list_finish(&pipeline
->batch_relocs
,
199 pAllocator
? pAllocator
: &device
->alloc
);
200 if (pipeline
->blend_state
.map
)
201 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
203 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
204 if (pipeline
->shaders
[s
])
205 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
208 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
211 static const uint32_t vk_to_gen_primitive_type
[] = {
212 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
213 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
214 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
215 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
216 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
217 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
218 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
219 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
220 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
221 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
222 /* [VK_PRIMITIVE_TOPOLOGY_PATCH_LIST] = _3DPRIM_PATCHLIST_1 */
226 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
227 struct brw_sampler_prog_key_data
*key
)
229 /* XXX: Handle texture swizzle on HSW- */
230 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
231 /* Assume color sampler, no swizzling. (Works for BDW+) */
232 key
->swizzles
[i
] = SWIZZLE_XYZW
;
237 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
238 struct brw_vs_prog_key
*key
)
240 memset(key
, 0, sizeof(*key
));
242 populate_sampler_prog_key(devinfo
, &key
->tex
);
244 /* XXX: Handle vertex input work-arounds */
246 /* XXX: Handle sampler_prog_key */
250 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
251 struct brw_gs_prog_key
*key
)
253 memset(key
, 0, sizeof(*key
));
255 populate_sampler_prog_key(devinfo
, &key
->tex
);
259 populate_wm_prog_key(const struct gen_device_info
*devinfo
,
260 const VkGraphicsPipelineCreateInfo
*info
,
261 struct brw_wm_prog_key
*key
)
263 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, info
->renderPass
);
265 memset(key
, 0, sizeof(*key
));
267 populate_sampler_prog_key(devinfo
, &key
->tex
);
269 /* TODO: Fill out key->input_slots_valid */
271 /* Vulkan doesn't specify a default */
272 key
->high_quality_derivatives
= false;
274 /* XXX Vulkan doesn't appear to specify */
275 key
->clamp_fragment_color
= false;
277 key
->nr_color_regions
=
278 render_pass
->subpasses
[info
->subpass
].color_count
;
280 key
->replicate_alpha
= key
->nr_color_regions
> 1 &&
281 info
->pMultisampleState
&&
282 info
->pMultisampleState
->alphaToCoverageEnable
;
284 if (info
->pMultisampleState
&& info
->pMultisampleState
->rasterizationSamples
> 1) {
285 /* We should probably pull this out of the shader, but it's fairly
286 * harmless to compute it and then let dead-code take care of it.
288 key
->persample_interp
=
289 (info
->pMultisampleState
->minSampleShading
*
290 info
->pMultisampleState
->rasterizationSamples
) > 1;
291 key
->multisample_fbo
= true;
296 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
297 struct brw_cs_prog_key
*key
)
299 memset(key
, 0, sizeof(*key
));
301 populate_sampler_prog_key(devinfo
, &key
->tex
);
305 anv_pipeline_compile(struct anv_pipeline
*pipeline
,
306 struct anv_shader_module
*module
,
307 const char *entrypoint
,
308 gl_shader_stage stage
,
309 const VkSpecializationInfo
*spec_info
,
310 struct brw_stage_prog_data
*prog_data
,
311 struct anv_pipeline_bind_map
*map
)
313 nir_shader
*nir
= anv_shader_compile_to_nir(pipeline
->device
,
314 module
, entrypoint
, stage
,
319 NIR_PASS_V(nir
, anv_nir_lower_push_constants
);
321 /* Figure out the number of parameters */
322 prog_data
->nr_params
= 0;
324 if (nir
->num_uniforms
> 0) {
325 /* If the shader uses any push constants at all, we'll just give
326 * them the maximum possible number
328 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
329 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
332 if (pipeline
->layout
&& pipeline
->layout
->stage
[stage
].has_dynamic_offsets
)
333 prog_data
->nr_params
+= MAX_DYNAMIC_BUFFERS
* 2;
335 if (nir
->info
->num_images
> 0) {
336 prog_data
->nr_params
+= nir
->info
->num_images
* BRW_IMAGE_PARAM_SIZE
;
337 pipeline
->needs_data_cache
= true;
340 if (stage
== MESA_SHADER_COMPUTE
)
341 ((struct brw_cs_prog_data
*)prog_data
)->thread_local_id_index
=
342 prog_data
->nr_params
++; /* The CS Thread ID uniform */
344 if (nir
->info
->num_ssbos
> 0)
345 pipeline
->needs_data_cache
= true;
347 if (prog_data
->nr_params
> 0) {
348 /* XXX: I think we're leaking this */
349 prog_data
->param
= (const union gl_constant_value
**)
350 malloc(prog_data
->nr_params
* sizeof(union gl_constant_value
*));
352 /* We now set the param values to be offsets into a
353 * anv_push_constant_data structure. Since the compiler doesn't
354 * actually dereference any of the gl_constant_value pointers in the
355 * params array, it doesn't really matter what we put here.
357 struct anv_push_constants
*null_data
= NULL
;
358 if (nir
->num_uniforms
> 0) {
359 /* Fill out the push constants section of the param array */
360 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++)
361 prog_data
->param
[i
] = (const union gl_constant_value
*)
362 &null_data
->client_data
[i
* sizeof(float)];
366 /* Set up dynamic offsets */
367 anv_nir_apply_dynamic_offsets(pipeline
, nir
, prog_data
);
369 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
370 if (pipeline
->layout
)
371 anv_nir_apply_pipeline_layout(pipeline
, nir
, prog_data
, map
);
373 /* nir_lower_io will only handle the push constants; we need to set this
374 * to the full number of possible uniforms.
376 nir
->num_uniforms
= prog_data
->nr_params
* 4;
382 anv_fill_binding_table(struct brw_stage_prog_data
*prog_data
, unsigned bias
)
384 prog_data
->binding_table
.size_bytes
= 0;
385 prog_data
->binding_table
.texture_start
= bias
;
386 prog_data
->binding_table
.gather_texture_start
= bias
;
387 prog_data
->binding_table
.ubo_start
= bias
;
388 prog_data
->binding_table
.ssbo_start
= bias
;
389 prog_data
->binding_table
.image_start
= bias
;
392 static struct anv_shader_bin
*
393 anv_pipeline_upload_kernel(struct anv_pipeline
*pipeline
,
394 struct anv_pipeline_cache
*cache
,
395 const void *key_data
, uint32_t key_size
,
396 const void *kernel_data
, uint32_t kernel_size
,
397 const struct brw_stage_prog_data
*prog_data
,
398 uint32_t prog_data_size
,
399 const struct anv_pipeline_bind_map
*bind_map
)
402 return anv_pipeline_cache_upload_kernel(cache
, key_data
, key_size
,
403 kernel_data
, kernel_size
,
404 prog_data
, prog_data_size
,
407 return anv_shader_bin_create(pipeline
->device
, key_data
, key_size
,
408 kernel_data
, kernel_size
,
409 prog_data
, prog_data_size
,
410 prog_data
->param
, bind_map
);
416 anv_pipeline_add_compiled_stage(struct anv_pipeline
*pipeline
,
417 gl_shader_stage stage
,
418 struct anv_shader_bin
*shader
)
420 pipeline
->shaders
[stage
] = shader
;
421 pipeline
->active_stages
|= mesa_to_vk_shader_stage(stage
);
425 anv_pipeline_compile_vs(struct anv_pipeline
*pipeline
,
426 struct anv_pipeline_cache
*cache
,
427 const VkGraphicsPipelineCreateInfo
*info
,
428 struct anv_shader_module
*module
,
429 const char *entrypoint
,
430 const VkSpecializationInfo
*spec_info
)
432 const struct brw_compiler
*compiler
=
433 pipeline
->device
->instance
->physicalDevice
.compiler
;
434 struct anv_pipeline_bind_map map
;
435 struct brw_vs_prog_key key
;
436 struct anv_shader_bin
*bin
= NULL
;
437 unsigned char sha1
[20];
439 populate_vs_prog_key(&pipeline
->device
->info
, &key
);
442 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
,
443 pipeline
->layout
, spec_info
);
444 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
448 struct brw_vs_prog_data prog_data
= { 0, };
449 struct anv_pipeline_binding surface_to_descriptor
[256];
450 struct anv_pipeline_binding sampler_to_descriptor
[256];
452 map
= (struct anv_pipeline_bind_map
) {
453 .surface_to_descriptor
= surface_to_descriptor
,
454 .sampler_to_descriptor
= sampler_to_descriptor
457 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
458 MESA_SHADER_VERTEX
, spec_info
,
459 &prog_data
.base
.base
, &map
);
461 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
463 anv_fill_binding_table(&prog_data
.base
.base
, 0);
465 void *mem_ctx
= ralloc_context(NULL
);
467 ralloc_steal(mem_ctx
, nir
);
469 prog_data
.inputs_read
= nir
->info
->inputs_read
;
470 prog_data
.double_inputs_read
= nir
->info
->double_inputs_read
;
472 brw_compute_vue_map(&pipeline
->device
->info
,
473 &prog_data
.base
.vue_map
,
474 nir
->info
->outputs_written
,
475 nir
->info
->separate_shader
);
478 const unsigned *shader_code
=
479 brw_compile_vs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
480 NULL
, false, -1, &code_size
, NULL
);
481 if (shader_code
== NULL
) {
482 ralloc_free(mem_ctx
);
483 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
486 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
487 shader_code
, code_size
,
488 &prog_data
.base
.base
, sizeof(prog_data
),
491 ralloc_free(mem_ctx
);
492 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
495 ralloc_free(mem_ctx
);
498 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_VERTEX
, bin
);
504 anv_pipeline_compile_gs(struct anv_pipeline
*pipeline
,
505 struct anv_pipeline_cache
*cache
,
506 const VkGraphicsPipelineCreateInfo
*info
,
507 struct anv_shader_module
*module
,
508 const char *entrypoint
,
509 const VkSpecializationInfo
*spec_info
)
511 const struct brw_compiler
*compiler
=
512 pipeline
->device
->instance
->physicalDevice
.compiler
;
513 struct anv_pipeline_bind_map map
;
514 struct brw_gs_prog_key key
;
515 struct anv_shader_bin
*bin
= NULL
;
516 unsigned char sha1
[20];
518 populate_gs_prog_key(&pipeline
->device
->info
, &key
);
521 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
,
522 pipeline
->layout
, spec_info
);
523 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
527 struct brw_gs_prog_data prog_data
= { 0, };
528 struct anv_pipeline_binding surface_to_descriptor
[256];
529 struct anv_pipeline_binding sampler_to_descriptor
[256];
531 map
= (struct anv_pipeline_bind_map
) {
532 .surface_to_descriptor
= surface_to_descriptor
,
533 .sampler_to_descriptor
= sampler_to_descriptor
536 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
537 MESA_SHADER_GEOMETRY
, spec_info
,
538 &prog_data
.base
.base
, &map
);
540 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
542 anv_fill_binding_table(&prog_data
.base
.base
, 0);
544 void *mem_ctx
= ralloc_context(NULL
);
546 ralloc_steal(mem_ctx
, nir
);
548 brw_compute_vue_map(&pipeline
->device
->info
,
549 &prog_data
.base
.vue_map
,
550 nir
->info
->outputs_written
,
551 nir
->info
->separate_shader
);
554 const unsigned *shader_code
=
555 brw_compile_gs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
556 NULL
, -1, &code_size
, NULL
);
557 if (shader_code
== NULL
) {
558 ralloc_free(mem_ctx
);
559 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
563 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
564 shader_code
, code_size
,
565 &prog_data
.base
.base
, sizeof(prog_data
),
568 ralloc_free(mem_ctx
);
569 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
572 ralloc_free(mem_ctx
);
575 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_GEOMETRY
, bin
);
581 anv_pipeline_compile_fs(struct anv_pipeline
*pipeline
,
582 struct anv_pipeline_cache
*cache
,
583 const VkGraphicsPipelineCreateInfo
*info
,
584 struct anv_shader_module
*module
,
585 const char *entrypoint
,
586 const VkSpecializationInfo
*spec_info
)
588 const struct brw_compiler
*compiler
=
589 pipeline
->device
->instance
->physicalDevice
.compiler
;
590 struct anv_pipeline_bind_map map
;
591 struct brw_wm_prog_key key
;
592 struct anv_shader_bin
*bin
= NULL
;
593 unsigned char sha1
[20];
595 populate_wm_prog_key(&pipeline
->device
->info
, info
, &key
);
598 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
,
599 pipeline
->layout
, spec_info
);
600 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
604 struct brw_wm_prog_data prog_data
= { 0, };
605 struct anv_pipeline_binding surface_to_descriptor
[256];
606 struct anv_pipeline_binding sampler_to_descriptor
[256];
608 map
= (struct anv_pipeline_bind_map
) {
609 .surface_to_descriptor
= surface_to_descriptor
+ 8,
610 .sampler_to_descriptor
= sampler_to_descriptor
613 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
614 MESA_SHADER_FRAGMENT
, spec_info
,
615 &prog_data
.base
, &map
);
617 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
619 unsigned num_rts
= 0;
620 struct anv_pipeline_binding rt_bindings
[8];
621 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
622 nir_foreach_variable_safe(var
, &nir
->outputs
) {
623 if (var
->data
.location
< FRAG_RESULT_DATA0
)
626 unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
627 if (rt
>= key
.nr_color_regions
) {
628 /* Out-of-bounds, throw it away */
629 var
->data
.mode
= nir_var_local
;
630 exec_node_remove(&var
->node
);
631 exec_list_push_tail(&impl
->locals
, &var
->node
);
635 /* Give it a new, compacted, location */
636 var
->data
.location
= FRAG_RESULT_DATA0
+ num_rts
;
639 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
640 assert(num_rts
+ array_len
<= 8);
642 for (unsigned i
= 0; i
< array_len
; i
++) {
643 rt_bindings
[num_rts
+ i
] = (struct anv_pipeline_binding
) {
644 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
650 num_rts
+= array_len
;
654 /* If we have no render targets, we need a null render target */
655 rt_bindings
[0] = (struct anv_pipeline_binding
) {
656 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
663 assert(num_rts
<= 8);
664 map
.surface_to_descriptor
-= num_rts
;
665 map
.surface_count
+= num_rts
;
666 assert(map
.surface_count
<= 256);
667 memcpy(map
.surface_to_descriptor
, rt_bindings
,
668 num_rts
* sizeof(*rt_bindings
));
670 anv_fill_binding_table(&prog_data
.base
, num_rts
);
672 void *mem_ctx
= ralloc_context(NULL
);
674 ralloc_steal(mem_ctx
, nir
);
677 const unsigned *shader_code
=
678 brw_compile_fs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
679 NULL
, -1, -1, true, false, NULL
, &code_size
, NULL
);
680 if (shader_code
== NULL
) {
681 ralloc_free(mem_ctx
);
682 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
685 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
686 shader_code
, code_size
,
687 &prog_data
.base
, sizeof(prog_data
),
690 ralloc_free(mem_ctx
);
691 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
694 ralloc_free(mem_ctx
);
697 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_FRAGMENT
, bin
);
703 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
704 struct anv_pipeline_cache
*cache
,
705 const VkComputePipelineCreateInfo
*info
,
706 struct anv_shader_module
*module
,
707 const char *entrypoint
,
708 const VkSpecializationInfo
*spec_info
)
710 const struct brw_compiler
*compiler
=
711 pipeline
->device
->instance
->physicalDevice
.compiler
;
712 struct anv_pipeline_bind_map map
;
713 struct brw_cs_prog_key key
;
714 struct anv_shader_bin
*bin
= NULL
;
715 unsigned char sha1
[20];
717 populate_cs_prog_key(&pipeline
->device
->info
, &key
);
720 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
,
721 pipeline
->layout
, spec_info
);
722 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
726 struct brw_cs_prog_data prog_data
= { 0, };
727 struct anv_pipeline_binding surface_to_descriptor
[256];
728 struct anv_pipeline_binding sampler_to_descriptor
[256];
730 map
= (struct anv_pipeline_bind_map
) {
731 .surface_to_descriptor
= surface_to_descriptor
,
732 .sampler_to_descriptor
= sampler_to_descriptor
735 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
736 MESA_SHADER_COMPUTE
, spec_info
,
737 &prog_data
.base
, &map
);
739 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
741 anv_fill_binding_table(&prog_data
.base
, 1);
743 void *mem_ctx
= ralloc_context(NULL
);
745 ralloc_steal(mem_ctx
, nir
);
748 const unsigned *shader_code
=
749 brw_compile_cs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
750 -1, &code_size
, NULL
);
751 if (shader_code
== NULL
) {
752 ralloc_free(mem_ctx
);
753 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
756 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
757 shader_code
, code_size
,
758 &prog_data
.base
, sizeof(prog_data
),
761 ralloc_free(mem_ctx
);
762 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
765 ralloc_free(mem_ctx
);
768 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_COMPUTE
, bin
);
774 * Copy pipeline state not marked as dynamic.
775 * Dynamic state is pipeline state which hasn't been provided at pipeline
776 * creation time, but is dynamically provided afterwards using various
777 * vkCmdSet* functions.
779 * The set of state considered "non_dynamic" is determined by the pieces of
780 * state that have their corresponding VkDynamicState enums omitted from
781 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
783 * @param[out] pipeline Destination non_dynamic state.
784 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
787 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
788 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
790 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
791 ANV_FROM_HANDLE(anv_render_pass
, pass
, pCreateInfo
->renderPass
);
792 struct anv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
794 pipeline
->dynamic_state
= default_dynamic_state
;
796 if (pCreateInfo
->pDynamicState
) {
797 /* Remove all of the states that are marked as dynamic */
798 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
799 for (uint32_t s
= 0; s
< count
; s
++)
800 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
803 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
805 /* Section 9.2 of the Vulkan 1.0.15 spec says:
807 * pViewportState is [...] NULL if the pipeline
808 * has rasterization disabled.
810 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
811 assert(pCreateInfo
->pViewportState
);
813 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
814 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
815 typed_memcpy(dynamic
->viewport
.viewports
,
816 pCreateInfo
->pViewportState
->pViewports
,
817 pCreateInfo
->pViewportState
->viewportCount
);
820 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
821 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
822 typed_memcpy(dynamic
->scissor
.scissors
,
823 pCreateInfo
->pViewportState
->pScissors
,
824 pCreateInfo
->pViewportState
->scissorCount
);
828 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
829 assert(pCreateInfo
->pRasterizationState
);
830 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
833 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
834 assert(pCreateInfo
->pRasterizationState
);
835 dynamic
->depth_bias
.bias
=
836 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
837 dynamic
->depth_bias
.clamp
=
838 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
839 dynamic
->depth_bias
.slope
=
840 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
843 /* Section 9.2 of the Vulkan 1.0.15 spec says:
845 * pColorBlendState is [...] NULL if the pipeline has rasterization
846 * disabled or if the subpass of the render pass the pipeline is
847 * created against does not use any color attachments.
849 bool uses_color_att
= false;
850 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
851 if (subpass
->color_attachments
[i
] != VK_ATTACHMENT_UNUSED
) {
852 uses_color_att
= true;
857 if (uses_color_att
&&
858 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
859 assert(pCreateInfo
->pColorBlendState
);
861 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
862 typed_memcpy(dynamic
->blend_constants
,
863 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
866 /* If there is no depthstencil attachment, then don't read
867 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
868 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
869 * no need to override the depthstencil defaults in
870 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
872 * Section 9.2 of the Vulkan 1.0.15 spec says:
874 * pDepthStencilState is [...] NULL if the pipeline has rasterization
875 * disabled or if the subpass of the render pass the pipeline is created
876 * against does not use a depth/stencil attachment.
878 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
879 subpass
->depth_stencil_attachment
!= VK_ATTACHMENT_UNUSED
) {
880 assert(pCreateInfo
->pDepthStencilState
);
882 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
883 dynamic
->depth_bounds
.min
=
884 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
885 dynamic
->depth_bounds
.max
=
886 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
889 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
890 dynamic
->stencil_compare_mask
.front
=
891 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
892 dynamic
->stencil_compare_mask
.back
=
893 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
896 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
897 dynamic
->stencil_write_mask
.front
=
898 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
899 dynamic
->stencil_write_mask
.back
=
900 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
903 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
904 dynamic
->stencil_reference
.front
=
905 pCreateInfo
->pDepthStencilState
->front
.reference
;
906 dynamic
->stencil_reference
.back
=
907 pCreateInfo
->pDepthStencilState
->back
.reference
;
911 pipeline
->dynamic_state_mask
= states
;
915 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
917 struct anv_render_pass
*renderpass
= NULL
;
918 struct anv_subpass
*subpass
= NULL
;
920 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
921 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
923 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
925 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
928 assert(info
->subpass
< renderpass
->subpass_count
);
929 subpass
= &renderpass
->subpasses
[info
->subpass
];
931 assert(info
->stageCount
>= 1);
932 assert(info
->pVertexInputState
);
933 assert(info
->pInputAssemblyState
);
934 assert(info
->pRasterizationState
);
935 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
936 assert(info
->pViewportState
);
937 assert(info
->pMultisampleState
);
939 if (subpass
&& subpass
->depth_stencil_attachment
!= VK_ATTACHMENT_UNUSED
)
940 assert(info
->pDepthStencilState
);
942 if (subpass
&& subpass
->color_count
> 0)
943 assert(info
->pColorBlendState
);
946 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
947 switch (info
->pStages
[i
].stage
) {
948 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
949 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
950 assert(info
->pTessellationState
);
959 * Calculate the desired L3 partitioning based on the current state of the
960 * pipeline. For now this simply returns the conservative defaults calculated
961 * by get_default_l3_weights(), but we could probably do better by gathering
962 * more statistics from the pipeline state (e.g. guess of expected URB usage
963 * and bound surfaces), or by using feed-back from performance counters.
966 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
968 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
970 const struct gen_l3_weights w
=
971 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
973 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
974 pipeline
->urb
.total_size
=
975 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
979 anv_pipeline_init(struct anv_pipeline
*pipeline
,
980 struct anv_device
*device
,
981 struct anv_pipeline_cache
*cache
,
982 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
983 const VkAllocationCallbacks
*alloc
)
988 anv_pipeline_validate_create_info(pCreateInfo
);
992 alloc
= &device
->alloc
;
994 pipeline
->device
= device
;
995 pipeline
->layout
= anv_pipeline_layout_from_handle(pCreateInfo
->layout
);
997 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
998 if (result
!= VK_SUCCESS
)
1001 pipeline
->batch
.alloc
= alloc
;
1002 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1003 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1004 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1006 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1007 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1008 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1010 pipeline
->needs_data_cache
= false;
1012 /* When we free the pipeline, we detect stages based on the NULL status
1013 * of various prog_data pointers. Make them NULL by default.
1015 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1017 pipeline
->active_stages
= 0;
1019 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
1020 struct anv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
1021 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
1022 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
1023 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
1024 modules
[stage
] = anv_shader_module_from_handle(pStages
[stage
]->module
);
1027 if (modules
[MESA_SHADER_VERTEX
]) {
1028 result
= anv_pipeline_compile_vs(pipeline
, cache
, pCreateInfo
,
1029 modules
[MESA_SHADER_VERTEX
],
1030 pStages
[MESA_SHADER_VERTEX
]->pName
,
1031 pStages
[MESA_SHADER_VERTEX
]->pSpecializationInfo
);
1032 if (result
!= VK_SUCCESS
)
1036 if (modules
[MESA_SHADER_TESS_CTRL
] || modules
[MESA_SHADER_TESS_EVAL
])
1037 anv_finishme("no tessellation support");
1039 if (modules
[MESA_SHADER_GEOMETRY
]) {
1040 result
= anv_pipeline_compile_gs(pipeline
, cache
, pCreateInfo
,
1041 modules
[MESA_SHADER_GEOMETRY
],
1042 pStages
[MESA_SHADER_GEOMETRY
]->pName
,
1043 pStages
[MESA_SHADER_GEOMETRY
]->pSpecializationInfo
);
1044 if (result
!= VK_SUCCESS
)
1048 if (modules
[MESA_SHADER_FRAGMENT
]) {
1049 result
= anv_pipeline_compile_fs(pipeline
, cache
, pCreateInfo
,
1050 modules
[MESA_SHADER_FRAGMENT
],
1051 pStages
[MESA_SHADER_FRAGMENT
]->pName
,
1052 pStages
[MESA_SHADER_FRAGMENT
]->pSpecializationInfo
);
1053 if (result
!= VK_SUCCESS
)
1057 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1059 anv_pipeline_setup_l3_config(pipeline
, false);
1061 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1062 pCreateInfo
->pVertexInputState
;
1064 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1066 pipeline
->vb_used
= 0;
1067 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1068 const VkVertexInputAttributeDescription
*desc
=
1069 &vi_info
->pVertexAttributeDescriptions
[i
];
1071 if (inputs_read
& (1 << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1072 pipeline
->vb_used
|= 1 << desc
->binding
;
1075 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1076 const VkVertexInputBindingDescription
*desc
=
1077 &vi_info
->pVertexBindingDescriptions
[i
];
1079 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
1081 /* Step rate is programmed per vertex element (attribute), not
1082 * binding. Set up a map of which bindings step per instance, for
1083 * reference by vertex element setup. */
1084 switch (desc
->inputRate
) {
1086 case VK_VERTEX_INPUT_RATE_VERTEX
:
1087 pipeline
->instancing_enable
[desc
->binding
] = false;
1089 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1090 pipeline
->instancing_enable
[desc
->binding
] = true;
1095 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1096 pCreateInfo
->pInputAssemblyState
;
1097 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1098 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];
1103 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1104 if (pipeline
->shaders
[s
])
1105 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
1108 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);