2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "anv_private.h"
34 #include "nir/spirv/nir_spirv.h"
36 /* Needed for SWIZZLE macros */
37 #include "program/prog_instruction.h"
41 VkResult
anv_CreateShaderModule(
43 const VkShaderModuleCreateInfo
* pCreateInfo
,
44 const VkAllocationCallbacks
* pAllocator
,
45 VkShaderModule
* pShaderModule
)
47 ANV_FROM_HANDLE(anv_device
, device
, _device
);
48 struct anv_shader_module
*module
;
50 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
51 assert(pCreateInfo
->flags
== 0);
53 module
= anv_alloc2(&device
->alloc
, pAllocator
,
54 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
55 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
57 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
60 module
->size
= pCreateInfo
->codeSize
;
61 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
63 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
65 *pShaderModule
= anv_shader_module_to_handle(module
);
70 void anv_DestroyShaderModule(
72 VkShaderModule _module
,
73 const VkAllocationCallbacks
* pAllocator
)
75 ANV_FROM_HANDLE(anv_device
, device
, _device
);
76 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
78 anv_free2(&device
->alloc
, pAllocator
, module
);
81 #define SPIR_V_MAGIC_NUMBER 0x07230203
83 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
84 * we can't do that yet because we don't have the ability to copy nir.
87 anv_shader_compile_to_nir(struct anv_device
*device
,
88 struct anv_shader_module
*module
,
89 const char *entrypoint_name
,
90 gl_shader_stage stage
,
91 const VkSpecializationInfo
*spec_info
)
93 if (strcmp(entrypoint_name
, "main") != 0) {
94 anv_finishme("Multiple shaders per module not really supported");
97 const struct brw_compiler
*compiler
=
98 device
->instance
->physicalDevice
.compiler
;
99 const nir_shader_compiler_options
*nir_options
=
100 compiler
->glsl_compiler_options
[stage
].NirOptions
;
103 nir_function
*entry_point
;
105 /* Some things such as our meta clear/blit code will give us a NIR
106 * shader directly. In that case, we just ignore the SPIR-V entirely
107 * and just use the NIR shader */
109 nir
->options
= nir_options
;
110 nir_validate_shader(nir
);
112 assert(exec_list_length(&nir
->functions
) == 1);
113 struct exec_node
*node
= exec_list_get_head(&nir
->functions
);
114 entry_point
= exec_node_data(nir_function
, node
, node
);
116 uint32_t *spirv
= (uint32_t *) module
->data
;
117 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
118 assert(module
->size
% 4 == 0);
120 uint32_t num_spec_entries
= 0;
121 struct nir_spirv_specialization
*spec_entries
= NULL
;
122 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
123 num_spec_entries
= spec_info
->mapEntryCount
;
124 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
125 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
126 const uint32_t *data
=
127 spec_info
->pData
+ spec_info
->pMapEntries
[i
].offset
;
128 assert((const void *)(data
+ 1) <=
129 spec_info
->pData
+ spec_info
->dataSize
);
131 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
132 spec_entries
[i
].data
= *data
;
136 entry_point
= spirv_to_nir(spirv
, module
->size
/ 4,
137 spec_entries
, num_spec_entries
,
138 stage
, entrypoint_name
, nir_options
);
139 nir
= entry_point
->shader
;
140 assert(nir
->stage
== stage
);
141 nir_validate_shader(nir
);
145 nir_lower_returns(nir
);
146 nir_validate_shader(nir
);
148 nir_inline_functions(nir
);
149 nir_validate_shader(nir
);
151 /* Pick off the single entrypoint that we want */
152 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
153 if (func
!= entry_point
)
154 exec_node_remove(&func
->node
);
156 assert(exec_list_length(&nir
->functions
) == 1);
157 entry_point
->name
= ralloc_strdup(entry_point
, "main");
159 nir_remove_dead_variables(nir
, nir_var_shader_in
);
160 nir_remove_dead_variables(nir
, nir_var_shader_out
);
161 nir_remove_dead_variables(nir
, nir_var_system_value
);
162 nir_validate_shader(nir
);
164 nir_lower_outputs_to_temporaries(entry_point
->shader
, entry_point
);
166 nir_lower_system_values(nir
);
167 nir_validate_shader(nir
);
170 /* Vulkan uses the separate-shader linking model */
171 nir
->info
.separate_shader
= true;
173 nir
= brw_preprocess_nir(nir
, compiler
->scalar_stage
[stage
]);
175 nir_shader_gather_info(nir
, entry_point
->impl
);
177 uint32_t indirect_mask
= 0;
178 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectInput
)
179 indirect_mask
|= (1 << nir_var_shader_in
);
180 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectTemp
)
181 indirect_mask
|= 1 << nir_var_local
;
183 nir_lower_indirect_derefs(nir
, indirect_mask
);
188 void anv_DestroyPipeline(
190 VkPipeline _pipeline
,
191 const VkAllocationCallbacks
* pAllocator
)
193 ANV_FROM_HANDLE(anv_device
, device
, _device
);
194 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
196 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
197 free(pipeline
->bindings
[s
].surface_to_descriptor
);
198 free(pipeline
->bindings
[s
].sampler_to_descriptor
);
201 anv_reloc_list_finish(&pipeline
->batch_relocs
,
202 pAllocator
? pAllocator
: &device
->alloc
);
203 if (pipeline
->blend_state
.map
)
204 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
205 anv_free2(&device
->alloc
, pAllocator
, pipeline
);
208 static const uint32_t vk_to_gen_primitive_type
[] = {
209 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
210 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
211 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
212 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
213 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
214 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
215 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
216 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
217 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
218 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
219 /* [VK_PRIMITIVE_TOPOLOGY_PATCH_LIST] = _3DPRIM_PATCHLIST_1 */
223 populate_sampler_prog_key(const struct brw_device_info
*devinfo
,
224 struct brw_sampler_prog_key_data
*key
)
226 /* XXX: Handle texture swizzle on HSW- */
227 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
228 /* Assume color sampler, no swizzling. (Works for BDW+) */
229 key
->swizzles
[i
] = SWIZZLE_XYZW
;
234 populate_vs_prog_key(const struct brw_device_info
*devinfo
,
235 struct brw_vs_prog_key
*key
)
237 memset(key
, 0, sizeof(*key
));
239 populate_sampler_prog_key(devinfo
, &key
->tex
);
241 /* XXX: Handle vertex input work-arounds */
243 /* XXX: Handle sampler_prog_key */
247 populate_gs_prog_key(const struct brw_device_info
*devinfo
,
248 struct brw_gs_prog_key
*key
)
250 memset(key
, 0, sizeof(*key
));
252 populate_sampler_prog_key(devinfo
, &key
->tex
);
256 populate_wm_prog_key(const struct brw_device_info
*devinfo
,
257 const VkGraphicsPipelineCreateInfo
*info
,
258 const struct anv_graphics_pipeline_create_info
*extra
,
259 struct brw_wm_prog_key
*key
)
261 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, info
->renderPass
);
263 memset(key
, 0, sizeof(*key
));
265 populate_sampler_prog_key(devinfo
, &key
->tex
);
267 /* TODO: Fill out key->input_slots_valid */
269 /* Vulkan doesn't specify a default */
270 key
->high_quality_derivatives
= false;
272 /* XXX Vulkan doesn't appear to specify */
273 key
->clamp_fragment_color
= false;
275 /* Vulkan always specifies upper-left coordinates */
276 key
->drawable_height
= 0;
277 key
->render_to_fbo
= false;
279 if (extra
&& extra
->color_attachment_count
>= 0) {
280 key
->nr_color_regions
= extra
->color_attachment_count
;
282 key
->nr_color_regions
=
283 render_pass
->subpasses
[info
->subpass
].color_count
;
286 key
->replicate_alpha
= key
->nr_color_regions
> 1 &&
287 info
->pMultisampleState
&&
288 info
->pMultisampleState
->alphaToCoverageEnable
;
290 if (info
->pMultisampleState
&& info
->pMultisampleState
->rasterizationSamples
> 1) {
291 /* We should probably pull this out of the shader, but it's fairly
292 * harmless to compute it and then let dead-code take care of it.
294 key
->persample_shading
= info
->pMultisampleState
->sampleShadingEnable
;
295 if (key
->persample_shading
)
296 key
->persample_2x
= info
->pMultisampleState
->rasterizationSamples
== 2;
298 key
->compute_pos_offset
= info
->pMultisampleState
->sampleShadingEnable
;
299 key
->compute_sample_id
= info
->pMultisampleState
->sampleShadingEnable
;
304 populate_cs_prog_key(const struct brw_device_info
*devinfo
,
305 struct brw_cs_prog_key
*key
)
307 memset(key
, 0, sizeof(*key
));
309 populate_sampler_prog_key(devinfo
, &key
->tex
);
313 anv_pipeline_compile(struct anv_pipeline
*pipeline
,
314 struct anv_shader_module
*module
,
315 const char *entrypoint
,
316 gl_shader_stage stage
,
317 const VkSpecializationInfo
*spec_info
,
318 struct brw_stage_prog_data
*prog_data
)
320 const struct brw_compiler
*compiler
=
321 pipeline
->device
->instance
->physicalDevice
.compiler
;
323 nir_shader
*nir
= anv_shader_compile_to_nir(pipeline
->device
,
324 module
, entrypoint
, stage
,
329 anv_nir_lower_push_constants(nir
, compiler
->scalar_stage
[stage
]);
331 /* Figure out the number of parameters */
332 prog_data
->nr_params
= 0;
334 if (nir
->num_uniforms
> 0) {
335 /* If the shader uses any push constants at all, we'll just give
336 * them the maximum possible number
338 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
341 if (pipeline
->layout
&& pipeline
->layout
->stage
[stage
].has_dynamic_offsets
)
342 prog_data
->nr_params
+= MAX_DYNAMIC_BUFFERS
* 2;
344 if (pipeline
->bindings
[stage
].image_count
> 0)
345 prog_data
->nr_params
+= pipeline
->bindings
[stage
].image_count
*
346 BRW_IMAGE_PARAM_SIZE
;
348 if (prog_data
->nr_params
> 0) {
349 /* XXX: I think we're leaking this */
350 prog_data
->param
= (const union gl_constant_value
**)
351 malloc(prog_data
->nr_params
* sizeof(union gl_constant_value
*));
353 /* We now set the param values to be offsets into a
354 * anv_push_constant_data structure. Since the compiler doesn't
355 * actually dereference any of the gl_constant_value pointers in the
356 * params array, it doesn't really matter what we put here.
358 struct anv_push_constants
*null_data
= NULL
;
359 if (nir
->num_uniforms
> 0) {
360 /* Fill out the push constants section of the param array */
361 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++)
362 prog_data
->param
[i
] = (const union gl_constant_value
*)
363 &null_data
->client_data
[i
* sizeof(float)];
367 /* Set up dynamic offsets */
368 anv_nir_apply_dynamic_offsets(pipeline
, nir
, prog_data
);
370 char surface_usage_mask
[256], sampler_usage_mask
[256];
371 zero(surface_usage_mask
);
372 zero(sampler_usage_mask
);
374 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
375 if (pipeline
->layout
)
376 anv_nir_apply_pipeline_layout(pipeline
, nir
, prog_data
);
378 /* All binding table offsets provided by apply_pipeline_layout() are
379 * relative to the start of the bindint table (plus MAX_RTS for VS).
383 case MESA_SHADER_FRAGMENT
:
386 case MESA_SHADER_COMPUTE
:
393 prog_data
->binding_table
.size_bytes
= 0;
394 prog_data
->binding_table
.texture_start
= bias
;
395 prog_data
->binding_table
.ubo_start
= bias
;
396 prog_data
->binding_table
.ssbo_start
= bias
;
397 prog_data
->binding_table
.image_start
= bias
;
399 /* Finish the optimization and compilation process */
400 if (nir
->stage
!= MESA_SHADER_VERTEX
&&
401 nir
->stage
!= MESA_SHADER_TESS_CTRL
&&
402 nir
->stage
!= MESA_SHADER_TESS_EVAL
&&
403 nir
->stage
!= MESA_SHADER_FRAGMENT
) {
404 nir
= brw_nir_lower_io(nir
, &pipeline
->device
->info
,
405 compiler
->scalar_stage
[stage
], false, NULL
);
408 /* nir_lower_io will only handle the push constants; we need to set this
409 * to the full number of possible uniforms.
411 nir
->num_uniforms
= prog_data
->nr_params
* 4;
417 anv_pipeline_add_compiled_stage(struct anv_pipeline
*pipeline
,
418 gl_shader_stage stage
,
419 struct brw_stage_prog_data
*prog_data
)
421 struct brw_device_info
*devinfo
= &pipeline
->device
->info
;
422 uint32_t max_threads
[] = {
423 [MESA_SHADER_VERTEX
] = devinfo
->max_vs_threads
,
424 [MESA_SHADER_TESS_CTRL
] = 0,
425 [MESA_SHADER_TESS_EVAL
] = 0,
426 [MESA_SHADER_GEOMETRY
] = devinfo
->max_gs_threads
,
427 [MESA_SHADER_FRAGMENT
] = devinfo
->max_wm_threads
,
428 [MESA_SHADER_COMPUTE
] = devinfo
->max_cs_threads
,
431 pipeline
->prog_data
[stage
] = prog_data
;
432 pipeline
->active_stages
|= mesa_to_vk_shader_stage(stage
);
433 pipeline
->scratch_start
[stage
] = pipeline
->total_scratch
;
434 pipeline
->total_scratch
=
435 align_u32(pipeline
->total_scratch
, 1024) +
436 prog_data
->total_scratch
* max_threads
[stage
];
440 anv_pipeline_compile_vs(struct anv_pipeline
*pipeline
,
441 struct anv_pipeline_cache
*cache
,
442 const VkGraphicsPipelineCreateInfo
*info
,
443 struct anv_shader_module
*module
,
444 const char *entrypoint
,
445 const VkSpecializationInfo
*spec_info
)
447 const struct brw_compiler
*compiler
=
448 pipeline
->device
->instance
->physicalDevice
.compiler
;
449 struct brw_vs_prog_data
*prog_data
= &pipeline
->vs_prog_data
;
450 struct brw_vs_prog_key key
;
452 unsigned char sha1
[20], *hash
;
454 populate_vs_prog_key(&pipeline
->device
->info
, &key
);
456 if (module
->size
> 0) {
458 anv_hash_shader(hash
, &key
, sizeof(key
), module
, entrypoint
, spec_info
);
459 kernel
= anv_pipeline_cache_search(cache
, hash
, prog_data
);
464 if (module
->size
== 0 || kernel
== NO_KERNEL
) {
465 memset(prog_data
, 0, sizeof(*prog_data
));
467 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
468 MESA_SHADER_VERTEX
, spec_info
,
469 &prog_data
->base
.base
);
471 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
473 void *mem_ctx
= ralloc_context(NULL
);
475 if (module
->nir
== NULL
)
476 ralloc_steal(mem_ctx
, nir
);
478 prog_data
->inputs_read
= nir
->info
.inputs_read
;
479 if (nir
->info
.outputs_written
& (1ull << VARYING_SLOT_PSIZ
))
480 pipeline
->writes_point_size
= true;
482 brw_compute_vue_map(&pipeline
->device
->info
,
483 &prog_data
->base
.vue_map
,
484 nir
->info
.outputs_written
,
485 nir
->info
.separate_shader
);
488 const unsigned *shader_code
=
489 brw_compile_vs(compiler
, NULL
, mem_ctx
, &key
, prog_data
, nir
,
490 NULL
, false, -1, &code_size
, NULL
);
491 if (shader_code
== NULL
) {
492 ralloc_free(mem_ctx
);
493 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
496 kernel
= anv_pipeline_cache_upload_kernel(cache
, hash
,
497 shader_code
, code_size
,
498 prog_data
, sizeof(*prog_data
));
499 ralloc_free(mem_ctx
);
502 if (prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
) {
503 pipeline
->vs_simd8
= kernel
;
504 pipeline
->vs_vec4
= NO_KERNEL
;
506 pipeline
->vs_simd8
= NO_KERNEL
;
507 pipeline
->vs_vec4
= kernel
;
510 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_VERTEX
,
511 &prog_data
->base
.base
);
517 anv_pipeline_compile_gs(struct anv_pipeline
*pipeline
,
518 struct anv_pipeline_cache
*cache
,
519 const VkGraphicsPipelineCreateInfo
*info
,
520 struct anv_shader_module
*module
,
521 const char *entrypoint
,
522 const VkSpecializationInfo
*spec_info
)
524 const struct brw_compiler
*compiler
=
525 pipeline
->device
->instance
->physicalDevice
.compiler
;
526 struct brw_gs_prog_data
*prog_data
= &pipeline
->gs_prog_data
;
527 struct brw_gs_prog_key key
;
529 unsigned char sha1
[20], *hash
;
531 populate_gs_prog_key(&pipeline
->device
->info
, &key
);
533 if (module
->size
> 0) {
535 anv_hash_shader(hash
, &key
, sizeof(key
), module
, entrypoint
, spec_info
);
536 kernel
= anv_pipeline_cache_search(cache
, hash
, prog_data
);
541 if (module
->size
== 0 || kernel
== NO_KERNEL
) {
542 memset(prog_data
, 0, sizeof(*prog_data
));
544 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
545 MESA_SHADER_GEOMETRY
, spec_info
,
546 &prog_data
->base
.base
);
548 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
550 void *mem_ctx
= ralloc_context(NULL
);
552 if (module
->nir
== NULL
)
553 ralloc_steal(mem_ctx
, nir
);
555 if (nir
->info
.outputs_written
& (1ull << VARYING_SLOT_PSIZ
))
556 pipeline
->writes_point_size
= true;
558 brw_compute_vue_map(&pipeline
->device
->info
,
559 &prog_data
->base
.vue_map
,
560 nir
->info
.outputs_written
,
561 nir
->info
.separate_shader
);
564 const unsigned *shader_code
=
565 brw_compile_gs(compiler
, NULL
, mem_ctx
, &key
, prog_data
, nir
,
566 NULL
, -1, &code_size
, NULL
);
567 if (shader_code
== NULL
) {
568 ralloc_free(mem_ctx
);
569 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
573 kernel
= anv_pipeline_cache_upload_kernel(cache
, hash
,
574 shader_code
, code_size
,
575 prog_data
, sizeof(*prog_data
));
577 ralloc_free(mem_ctx
);
580 pipeline
->gs_kernel
= kernel
;
582 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_GEOMETRY
,
583 &prog_data
->base
.base
);
589 anv_pipeline_compile_fs(struct anv_pipeline
*pipeline
,
590 struct anv_pipeline_cache
*cache
,
591 const VkGraphicsPipelineCreateInfo
*info
,
592 const struct anv_graphics_pipeline_create_info
*extra
,
593 struct anv_shader_module
*module
,
594 const char *entrypoint
,
595 const VkSpecializationInfo
*spec_info
)
597 const struct brw_compiler
*compiler
=
598 pipeline
->device
->instance
->physicalDevice
.compiler
;
599 struct brw_wm_prog_data
*prog_data
= &pipeline
->wm_prog_data
;
600 struct brw_wm_prog_key key
;
602 unsigned char sha1
[20], *hash
;
604 populate_wm_prog_key(&pipeline
->device
->info
, info
, extra
, &key
);
606 if (pipeline
->use_repclear
)
607 key
.nr_color_regions
= 1;
609 if (module
->size
> 0) {
611 anv_hash_shader(hash
, &key
, sizeof(key
), module
, entrypoint
, spec_info
);
612 kernel
= anv_pipeline_cache_search(cache
, hash
, prog_data
);
617 if (module
->size
== 0 || kernel
== NO_KERNEL
) {
618 memset(prog_data
, 0, sizeof(*prog_data
));
620 prog_data
->binding_table
.render_target_start
= 0;
622 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
623 MESA_SHADER_FRAGMENT
, spec_info
,
626 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
628 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
)->impl
;
629 nir_foreach_variable_safe(var
, &nir
->outputs
) {
630 if (var
->data
.location
< FRAG_RESULT_DATA0
)
633 unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
634 if (rt
>= key
.nr_color_regions
) {
635 var
->data
.mode
= nir_var_local
;
636 exec_node_remove(&var
->node
);
637 exec_list_push_tail(&impl
->locals
, &var
->node
);
641 void *mem_ctx
= ralloc_context(NULL
);
643 if (module
->nir
== NULL
)
644 ralloc_steal(mem_ctx
, nir
);
647 const unsigned *shader_code
=
648 brw_compile_fs(compiler
, NULL
, mem_ctx
, &key
, prog_data
, nir
,
649 NULL
, -1, -1, pipeline
->use_repclear
, &code_size
, NULL
);
650 if (shader_code
== NULL
) {
651 ralloc_free(mem_ctx
);
652 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
655 kernel
= anv_pipeline_cache_upload_kernel(cache
, hash
,
656 shader_code
, code_size
,
657 prog_data
, sizeof(*prog_data
));
659 ralloc_free(mem_ctx
);
663 pipeline
->ps_simd8
= NO_KERNEL
;
665 pipeline
->ps_simd8
= kernel
;
667 if (prog_data
->no_8
|| prog_data
->prog_offset_16
) {
668 pipeline
->ps_simd16
= kernel
+ prog_data
->prog_offset_16
;
670 pipeline
->ps_simd16
= NO_KERNEL
;
673 pipeline
->ps_ksp2
= 0;
674 pipeline
->ps_grf_start2
= 0;
675 if (pipeline
->ps_simd8
!= NO_KERNEL
) {
676 pipeline
->ps_ksp0
= pipeline
->ps_simd8
;
677 pipeline
->ps_grf_start0
= prog_data
->base
.dispatch_grf_start_reg
;
678 if (pipeline
->ps_simd16
!= NO_KERNEL
) {
679 pipeline
->ps_ksp2
= pipeline
->ps_simd16
;
680 pipeline
->ps_grf_start2
= prog_data
->dispatch_grf_start_reg_16
;
682 } else if (pipeline
->ps_simd16
!= NO_KERNEL
) {
683 pipeline
->ps_ksp0
= pipeline
->ps_simd16
;
684 pipeline
->ps_grf_start0
= prog_data
->dispatch_grf_start_reg_16
;
687 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_FRAGMENT
,
694 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
695 struct anv_pipeline_cache
*cache
,
696 const VkComputePipelineCreateInfo
*info
,
697 struct anv_shader_module
*module
,
698 const char *entrypoint
,
699 const VkSpecializationInfo
*spec_info
)
701 const struct brw_compiler
*compiler
=
702 pipeline
->device
->instance
->physicalDevice
.compiler
;
703 struct brw_cs_prog_data
*prog_data
= &pipeline
->cs_prog_data
;
704 struct brw_cs_prog_key key
;
706 unsigned char sha1
[20], *hash
;
708 populate_cs_prog_key(&pipeline
->device
->info
, &key
);
710 if (module
->size
> 0) {
712 anv_hash_shader(hash
, &key
, sizeof(key
), module
, entrypoint
, spec_info
);
713 kernel
= anv_pipeline_cache_search(cache
, hash
, prog_data
);
718 if (module
->size
== 0 || kernel
== NO_KERNEL
) {
719 memset(prog_data
, 0, sizeof(*prog_data
));
721 prog_data
->binding_table
.work_groups_start
= 0;
723 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
724 MESA_SHADER_COMPUTE
, spec_info
,
727 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
729 prog_data
->base
.total_shared
= nir
->num_shared
;
731 void *mem_ctx
= ralloc_context(NULL
);
733 if (module
->nir
== NULL
)
734 ralloc_steal(mem_ctx
, nir
);
737 const unsigned *shader_code
=
738 brw_compile_cs(compiler
, NULL
, mem_ctx
, &key
, prog_data
, nir
,
739 -1, &code_size
, NULL
);
740 if (shader_code
== NULL
) {
741 ralloc_free(mem_ctx
);
742 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
745 kernel
= anv_pipeline_cache_upload_kernel(cache
, hash
,
746 shader_code
, code_size
,
747 prog_data
, sizeof(*prog_data
));
748 ralloc_free(mem_ctx
);
751 pipeline
->cs_simd
= kernel
;
753 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_COMPUTE
,
759 static const int gen8_push_size
= 32 * 1024;
762 gen7_compute_urb_partition(struct anv_pipeline
*pipeline
)
764 const struct brw_device_info
*devinfo
= &pipeline
->device
->info
;
765 bool vs_present
= pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
;
766 unsigned vs_size
= vs_present
? pipeline
->vs_prog_data
.base
.urb_entry_size
: 1;
767 unsigned vs_entry_size_bytes
= vs_size
* 64;
768 bool gs_present
= pipeline
->active_stages
& VK_SHADER_STAGE_GEOMETRY_BIT
;
769 unsigned gs_size
= gs_present
? pipeline
->gs_prog_data
.base
.urb_entry_size
: 1;
770 unsigned gs_entry_size_bytes
= gs_size
* 64;
772 /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
774 * VS Number of URB Entries must be divisible by 8 if the VS URB Entry
775 * Allocation Size is less than 9 512-bit URB entries.
777 * Similar text exists for GS.
779 unsigned vs_granularity
= (vs_size
< 9) ? 8 : 1;
780 unsigned gs_granularity
= (gs_size
< 9) ? 8 : 1;
782 /* URB allocations must be done in 8k chunks. */
783 unsigned chunk_size_bytes
= 8192;
785 /* Determine the size of the URB in chunks. */
786 unsigned urb_chunks
= devinfo
->urb
.size
* 1024 / chunk_size_bytes
;
788 /* Reserve space for push constants */
789 unsigned push_constant_bytes
= gen8_push_size
;
790 unsigned push_constant_chunks
=
791 push_constant_bytes
/ chunk_size_bytes
;
793 /* Initially, assign each stage the minimum amount of URB space it needs,
794 * and make a note of how much additional space it "wants" (the amount of
795 * additional space it could actually make use of).
798 /* VS has a lower limit on the number of URB entries */
800 ALIGN(devinfo
->urb
.min_vs_entries
* vs_entry_size_bytes
,
801 chunk_size_bytes
) / chunk_size_bytes
;
803 ALIGN(devinfo
->urb
.max_vs_entries
* vs_entry_size_bytes
,
804 chunk_size_bytes
) / chunk_size_bytes
- vs_chunks
;
806 unsigned gs_chunks
= 0;
807 unsigned gs_wants
= 0;
809 /* There are two constraints on the minimum amount of URB space we can
812 * (1) We need room for at least 2 URB entries, since we always operate
813 * the GS in DUAL_OBJECT mode.
815 * (2) We can't allocate less than nr_gs_entries_granularity.
817 gs_chunks
= ALIGN(MAX2(gs_granularity
, 2) * gs_entry_size_bytes
,
818 chunk_size_bytes
) / chunk_size_bytes
;
820 ALIGN(devinfo
->urb
.max_gs_entries
* gs_entry_size_bytes
,
821 chunk_size_bytes
) / chunk_size_bytes
- gs_chunks
;
824 /* There should always be enough URB space to satisfy the minimum
825 * requirements of each stage.
827 unsigned total_needs
= push_constant_chunks
+ vs_chunks
+ gs_chunks
;
828 assert(total_needs
<= urb_chunks
);
830 /* Mete out remaining space (if any) in proportion to "wants". */
831 unsigned total_wants
= vs_wants
+ gs_wants
;
832 unsigned remaining_space
= urb_chunks
- total_needs
;
833 if (remaining_space
> total_wants
)
834 remaining_space
= total_wants
;
835 if (remaining_space
> 0) {
836 unsigned vs_additional
= (unsigned)
837 round(vs_wants
* (((double) remaining_space
) / total_wants
));
838 vs_chunks
+= vs_additional
;
839 remaining_space
-= vs_additional
;
840 gs_chunks
+= remaining_space
;
843 /* Sanity check that we haven't over-allocated. */
844 assert(push_constant_chunks
+ vs_chunks
+ gs_chunks
<= urb_chunks
);
846 /* Finally, compute the number of entries that can fit in the space
847 * allocated to each stage.
849 unsigned nr_vs_entries
= vs_chunks
* chunk_size_bytes
/ vs_entry_size_bytes
;
850 unsigned nr_gs_entries
= gs_chunks
* chunk_size_bytes
/ gs_entry_size_bytes
;
852 /* Since we rounded up when computing *_wants, this may be slightly more
853 * than the maximum allowed amount, so correct for that.
855 nr_vs_entries
= MIN2(nr_vs_entries
, devinfo
->urb
.max_vs_entries
);
856 nr_gs_entries
= MIN2(nr_gs_entries
, devinfo
->urb
.max_gs_entries
);
858 /* Ensure that we program a multiple of the granularity. */
859 nr_vs_entries
= ROUND_DOWN_TO(nr_vs_entries
, vs_granularity
);
860 nr_gs_entries
= ROUND_DOWN_TO(nr_gs_entries
, gs_granularity
);
862 /* Finally, sanity check to make sure we have at least the minimum number
863 * of entries needed for each stage.
865 assert(nr_vs_entries
>= devinfo
->urb
.min_vs_entries
);
867 assert(nr_gs_entries
>= 2);
869 /* Lay out the URB in the following order:
874 pipeline
->urb
.vs_start
= push_constant_chunks
;
875 pipeline
->urb
.vs_size
= vs_size
;
876 pipeline
->urb
.nr_vs_entries
= nr_vs_entries
;
878 pipeline
->urb
.gs_start
= push_constant_chunks
+ vs_chunks
;
879 pipeline
->urb
.gs_size
= gs_size
;
880 pipeline
->urb
.nr_gs_entries
= nr_gs_entries
;
884 anv_pipeline_init_dynamic_state(struct anv_pipeline
*pipeline
,
885 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
887 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
888 ANV_FROM_HANDLE(anv_render_pass
, pass
, pCreateInfo
->renderPass
);
889 struct anv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
891 pipeline
->dynamic_state
= default_dynamic_state
;
893 if (pCreateInfo
->pDynamicState
) {
894 /* Remove all of the states that are marked as dynamic */
895 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
896 for (uint32_t s
= 0; s
< count
; s
++)
897 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
900 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
902 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
903 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
904 typed_memcpy(dynamic
->viewport
.viewports
,
905 pCreateInfo
->pViewportState
->pViewports
,
906 pCreateInfo
->pViewportState
->viewportCount
);
909 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
910 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
911 typed_memcpy(dynamic
->scissor
.scissors
,
912 pCreateInfo
->pViewportState
->pScissors
,
913 pCreateInfo
->pViewportState
->scissorCount
);
916 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
917 assert(pCreateInfo
->pRasterizationState
);
918 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
921 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
922 assert(pCreateInfo
->pRasterizationState
);
923 dynamic
->depth_bias
.bias
=
924 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
925 dynamic
->depth_bias
.clamp
=
926 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
927 dynamic
->depth_bias
.slope
=
928 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
931 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
)) {
932 assert(pCreateInfo
->pColorBlendState
);
933 typed_memcpy(dynamic
->blend_constants
,
934 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
937 /* If there is no depthstencil attachment, then don't read
938 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
939 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
940 * no need to override the depthstencil defaults in
941 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
943 * From the Vulkan spec (20 Oct 2015, git-aa308cb):
945 * pDepthStencilState [...] may only be NULL if renderPass and subpass
946 * specify a subpass that has no depth/stencil attachment.
948 if (subpass
->depth_stencil_attachment
!= VK_ATTACHMENT_UNUSED
) {
949 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
950 assert(pCreateInfo
->pDepthStencilState
);
951 dynamic
->depth_bounds
.min
=
952 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
953 dynamic
->depth_bounds
.max
=
954 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
957 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
958 assert(pCreateInfo
->pDepthStencilState
);
959 dynamic
->stencil_compare_mask
.front
=
960 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
961 dynamic
->stencil_compare_mask
.back
=
962 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
965 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
966 assert(pCreateInfo
->pDepthStencilState
);
967 dynamic
->stencil_write_mask
.front
=
968 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
969 dynamic
->stencil_write_mask
.back
=
970 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
973 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
974 assert(pCreateInfo
->pDepthStencilState
);
975 dynamic
->stencil_reference
.front
=
976 pCreateInfo
->pDepthStencilState
->front
.reference
;
977 dynamic
->stencil_reference
.back
=
978 pCreateInfo
->pDepthStencilState
->back
.reference
;
982 pipeline
->dynamic_state_mask
= states
;
986 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
988 struct anv_render_pass
*renderpass
= NULL
;
989 struct anv_subpass
*subpass
= NULL
;
991 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
992 * present, as explained by the Vulkan (20 Oct 2015, git-aa308cb), Section
993 * 4.2 Graphics Pipeline.
995 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
997 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1000 if (renderpass
!= &anv_meta_dummy_renderpass
) {
1001 assert(info
->subpass
< renderpass
->subpass_count
);
1002 subpass
= &renderpass
->subpasses
[info
->subpass
];
1005 assert(info
->stageCount
>= 1);
1006 assert(info
->pVertexInputState
);
1007 assert(info
->pInputAssemblyState
);
1008 assert(info
->pViewportState
);
1009 assert(info
->pRasterizationState
);
1011 if (subpass
&& subpass
->depth_stencil_attachment
!= VK_ATTACHMENT_UNUSED
)
1012 assert(info
->pDepthStencilState
);
1014 if (subpass
&& subpass
->color_count
> 0)
1015 assert(info
->pColorBlendState
);
1017 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1018 switch (info
->pStages
[i
].stage
) {
1019 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1020 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1021 assert(info
->pTessellationState
);
1030 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1031 struct anv_device
*device
,
1032 struct anv_pipeline_cache
*cache
,
1033 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1034 const struct anv_graphics_pipeline_create_info
*extra
,
1035 const VkAllocationCallbacks
*alloc
)
1040 anv_pipeline_validate_create_info(pCreateInfo
);
1044 alloc
= &device
->alloc
;
1046 pipeline
->device
= device
;
1047 pipeline
->layout
= anv_pipeline_layout_from_handle(pCreateInfo
->layout
);
1049 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1050 if (result
!= VK_SUCCESS
)
1053 pipeline
->batch
.alloc
= alloc
;
1054 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1055 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1056 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1058 anv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
1060 if (pCreateInfo
->pTessellationState
)
1061 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_TESSELLATION_STATE_CREATE_INFO");
1063 pipeline
->use_repclear
= extra
&& extra
->use_repclear
;
1064 pipeline
->writes_point_size
= false;
1066 /* When we free the pipeline, we detect stages based on the NULL status
1067 * of various prog_data pointers. Make them NULL by default.
1069 memset(pipeline
->prog_data
, 0, sizeof(pipeline
->prog_data
));
1070 memset(pipeline
->scratch_start
, 0, sizeof(pipeline
->scratch_start
));
1071 memset(pipeline
->bindings
, 0, sizeof(pipeline
->bindings
));
1073 pipeline
->vs_simd8
= NO_KERNEL
;
1074 pipeline
->vs_vec4
= NO_KERNEL
;
1075 pipeline
->gs_kernel
= NO_KERNEL
;
1076 pipeline
->ps_ksp0
= NO_KERNEL
;
1078 pipeline
->active_stages
= 0;
1079 pipeline
->total_scratch
= 0;
1081 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
1082 ANV_FROM_HANDLE(anv_shader_module
, module
,
1083 pCreateInfo
->pStages
[i
].module
);
1085 switch (pCreateInfo
->pStages
[i
].stage
) {
1086 case VK_SHADER_STAGE_VERTEX_BIT
:
1087 anv_pipeline_compile_vs(pipeline
, cache
, pCreateInfo
, module
,
1088 pCreateInfo
->pStages
[i
].pName
,
1089 pCreateInfo
->pStages
[i
].pSpecializationInfo
);
1091 case VK_SHADER_STAGE_GEOMETRY_BIT
:
1092 anv_pipeline_compile_gs(pipeline
, cache
, pCreateInfo
, module
,
1093 pCreateInfo
->pStages
[i
].pName
,
1094 pCreateInfo
->pStages
[i
].pSpecializationInfo
);
1096 case VK_SHADER_STAGE_FRAGMENT_BIT
:
1097 anv_pipeline_compile_fs(pipeline
, cache
, pCreateInfo
, extra
, module
,
1098 pCreateInfo
->pStages
[i
].pName
,
1099 pCreateInfo
->pStages
[i
].pSpecializationInfo
);
1102 anv_finishme("Unsupported shader stage");
1106 if (!(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
)) {
1107 /* Vertex is only optional if disable_vs is set */
1108 assert(extra
->disable_vs
);
1109 memset(&pipeline
->vs_prog_data
, 0, sizeof(pipeline
->vs_prog_data
));
1112 gen7_compute_urb_partition(pipeline
);
1114 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1115 pCreateInfo
->pVertexInputState
;
1117 uint64_t inputs_read
;
1118 if (extra
&& extra
->disable_vs
) {
1119 /* If the VS is disabled, just assume the user knows what they're
1120 * doing and apply the layout blindly. This can only come from
1121 * meta, so this *should* be safe.
1123 inputs_read
= ~0ull;
1125 inputs_read
= pipeline
->vs_prog_data
.inputs_read
;
1128 pipeline
->vb_used
= 0;
1129 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1130 const VkVertexInputAttributeDescription
*desc
=
1131 &vi_info
->pVertexAttributeDescriptions
[i
];
1133 if (inputs_read
& (1 << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1134 pipeline
->vb_used
|= 1 << desc
->binding
;
1137 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1138 const VkVertexInputBindingDescription
*desc
=
1139 &vi_info
->pVertexBindingDescriptions
[i
];
1141 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
1143 /* Step rate is programmed per vertex element (attribute), not
1144 * binding. Set up a map of which bindings step per instance, for
1145 * reference by vertex element setup. */
1146 switch (desc
->inputRate
) {
1148 case VK_VERTEX_INPUT_RATE_VERTEX
:
1149 pipeline
->instancing_enable
[desc
->binding
] = false;
1151 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1152 pipeline
->instancing_enable
[desc
->binding
] = true;
1157 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1158 pCreateInfo
->pInputAssemblyState
;
1159 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1160 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];
1162 if (extra
&& extra
->use_rectlist
)
1163 pipeline
->topology
= _3DPRIM_RECTLIST
;
1165 while (anv_block_pool_size(&device
->scratch_block_pool
) <
1166 pipeline
->total_scratch
)
1167 anv_block_pool_alloc(&device
->scratch_block_pool
);
1173 anv_graphics_pipeline_create(
1175 VkPipelineCache _cache
,
1176 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1177 const struct anv_graphics_pipeline_create_info
*extra
,
1178 const VkAllocationCallbacks
*pAllocator
,
1179 VkPipeline
*pPipeline
)
1181 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1182 ANV_FROM_HANDLE(anv_pipeline_cache
, cache
, _cache
);
1185 cache
= &device
->default_pipeline_cache
;
1187 switch (device
->info
.gen
) {
1189 if (device
->info
.is_haswell
)
1190 return gen75_graphics_pipeline_create(_device
, cache
, pCreateInfo
, extra
, pAllocator
, pPipeline
);
1192 return gen7_graphics_pipeline_create(_device
, cache
, pCreateInfo
, extra
, pAllocator
, pPipeline
);
1194 return gen8_graphics_pipeline_create(_device
, cache
, pCreateInfo
, extra
, pAllocator
, pPipeline
);
1196 return gen9_graphics_pipeline_create(_device
, cache
, pCreateInfo
, extra
, pAllocator
, pPipeline
);
1198 unreachable("unsupported gen\n");
1202 VkResult
anv_CreateGraphicsPipelines(
1204 VkPipelineCache pipelineCache
,
1206 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
1207 const VkAllocationCallbacks
* pAllocator
,
1208 VkPipeline
* pPipelines
)
1210 VkResult result
= VK_SUCCESS
;
1213 for (; i
< count
; i
++) {
1214 result
= anv_graphics_pipeline_create(_device
,
1217 NULL
, pAllocator
, &pPipelines
[i
]);
1218 if (result
!= VK_SUCCESS
) {
1219 for (unsigned j
= 0; j
< i
; j
++) {
1220 anv_DestroyPipeline(_device
, pPipelines
[j
], pAllocator
);
1230 static VkResult
anv_compute_pipeline_create(
1232 VkPipelineCache _cache
,
1233 const VkComputePipelineCreateInfo
* pCreateInfo
,
1234 const VkAllocationCallbacks
* pAllocator
,
1235 VkPipeline
* pPipeline
)
1237 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1238 ANV_FROM_HANDLE(anv_pipeline_cache
, cache
, _cache
);
1241 cache
= &device
->default_pipeline_cache
;
1243 switch (device
->info
.gen
) {
1245 if (device
->info
.is_haswell
)
1246 return gen75_compute_pipeline_create(_device
, cache
, pCreateInfo
, pAllocator
, pPipeline
);
1248 return gen7_compute_pipeline_create(_device
, cache
, pCreateInfo
, pAllocator
, pPipeline
);
1250 return gen8_compute_pipeline_create(_device
, cache
, pCreateInfo
, pAllocator
, pPipeline
);
1252 return gen9_compute_pipeline_create(_device
, cache
, pCreateInfo
, pAllocator
, pPipeline
);
1254 unreachable("unsupported gen\n");
1258 VkResult
anv_CreateComputePipelines(
1260 VkPipelineCache pipelineCache
,
1262 const VkComputePipelineCreateInfo
* pCreateInfos
,
1263 const VkAllocationCallbacks
* pAllocator
,
1264 VkPipeline
* pPipelines
)
1266 VkResult result
= VK_SUCCESS
;
1269 for (; i
< count
; i
++) {
1270 result
= anv_compute_pipeline_create(_device
, pipelineCache
,
1272 pAllocator
, &pPipelines
[i
]);
1273 if (result
!= VK_SUCCESS
) {
1274 for (unsigned j
= 0; j
< i
; j
++) {
1275 anv_DestroyPipeline(_device
, pPipelines
[j
], pAllocator
);