projects / mesa.git / blob
? search:


3723423617bdb3448c454fbf1bfbe7237dad73d5
[mesa.git] / src / intel / vulkan / anv_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "util/mesa-sha1.h"
31 #include "anv_private.h"
32 #include "brw_nir.h"
33 #include "anv_nir.h"
34 #include "spirv/nir_spirv.h"
35
36 /* Needed for SWIZZLE macros */
37 #include "program/prog_instruction.h"
38
39 // Shader functions
40
41 VkResult anv_CreateShaderModule(
42 VkDevice _device,
43 const VkShaderModuleCreateInfo* pCreateInfo,
44 const VkAllocationCallbacks* pAllocator,
45 VkShaderModule* pShaderModule)
46 {
47 ANV_FROM_HANDLE(anv_device, device, _device);
48 struct anv_shader_module *module;
49
50 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
51 assert(pCreateInfo->flags == 0);
52
53 module = anv_alloc2(&device->alloc, pAllocator,
54 sizeof(*module) + pCreateInfo->codeSize, 8,
55 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
56 if (module == NULL)
57 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
58
59 module->nir = NULL;
60 module->size = pCreateInfo->codeSize;
61 memcpy(module->data, pCreateInfo->pCode, module->size);
62
63 _mesa_sha1_compute(module->data, module->size, module->sha1);
64
65 *pShaderModule = anv_shader_module_to_handle(module);
66
67 return VK_SUCCESS;
68 }
69
70 void anv_DestroyShaderModule(
71 VkDevice _device,
72 VkShaderModule _module,
73 const VkAllocationCallbacks* pAllocator)
74 {
75 ANV_FROM_HANDLE(anv_device, device, _device);
76 ANV_FROM_HANDLE(anv_shader_module, module, _module);
77
78 anv_free2(&device->alloc, pAllocator, module);
79 }
80
81 #define SPIR_V_MAGIC_NUMBER 0x07230203
82
83 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
84 * we can't do that yet because we don't have the ability to copy nir.
85 */
86 static nir_shader *
87 anv_shader_compile_to_nir(struct anv_device *device,
88 struct anv_shader_module *module,
89 const char *entrypoint_name,
90 gl_shader_stage stage,
91 const VkSpecializationInfo *spec_info)
92 {
93 if (strcmp(entrypoint_name, "main") != 0) {
94 anv_finishme("Multiple shaders per module not really supported");
95 }
96
97 const struct brw_compiler *compiler =
98 device->instance->physicalDevice.compiler;
99 const nir_shader_compiler_options *nir_options =
100 compiler->glsl_compiler_options[stage].NirOptions;
101
102 nir_shader *nir;
103 nir_function *entry_point;
104 if (module->nir) {
105 /* Some things such as our meta clear/blit code will give us a NIR
106 * shader directly. In that case, we just ignore the SPIR-V entirely
107 * and just use the NIR shader */
108 nir = module->nir;
109 nir->options = nir_options;
110 nir_validate_shader(nir);
111
112 assert(exec_list_length(&nir->functions) == 1);
113 struct exec_node *node = exec_list_get_head(&nir->functions);
114 entry_point = exec_node_data(nir_function, node, node);
115 } else {
116 uint32_t *spirv = (uint32_t *) module->data;
117 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
118 assert(module->size % 4 == 0);
119
120 uint32_t num_spec_entries = 0;
121 struct nir_spirv_specialization *spec_entries = NULL;
122 if (spec_info && spec_info->mapEntryCount > 0) {
123 num_spec_entries = spec_info->mapEntryCount;
124 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
125 for (uint32_t i = 0; i < num_spec_entries; i++) {
126 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
127 const void *data = spec_info->pData + entry.offset;
128 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
129
130 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
131 spec_entries[i].data = *(const uint32_t *)data;
132 }
133 }
134
135 entry_point = spirv_to_nir(spirv, module->size / 4,
136 spec_entries, num_spec_entries,
137 stage, entrypoint_name, nir_options);
138 nir = entry_point->shader;
139 assert(nir->stage == stage);
140 nir_validate_shader(nir);
141
142 free(spec_entries);
143
144 if (stage == MESA_SHADER_FRAGMENT) {
145 nir_lower_wpos_center(nir);
146 nir_validate_shader(nir);
147 }
148
149 nir_lower_returns(nir);
150 nir_validate_shader(nir);
151
152 nir_inline_functions(nir);
153 nir_validate_shader(nir);
154
155 /* Pick off the single entrypoint that we want */
156 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
157 if (func != entry_point)
158 exec_node_remove(&func->node);
159 }
160 assert(exec_list_length(&nir->functions) == 1);
161 entry_point->name = ralloc_strdup(entry_point, "main");
162
163 nir_remove_dead_variables(nir, nir_var_shader_in);
164 nir_remove_dead_variables(nir, nir_var_shader_out);
165 nir_remove_dead_variables(nir, nir_var_system_value);
166 nir_validate_shader(nir);
167
168 nir_propagate_invariant(nir);
169 nir_validate_shader(nir);
170
171 nir_lower_io_to_temporaries(entry_point->shader, entry_point, true, false);
172
173 nir_lower_system_values(nir);
174 nir_validate_shader(nir);
175 }
176
177 /* Vulkan uses the separate-shader linking model */
178 nir->info.separate_shader = true;
179
180 nir = brw_preprocess_nir(compiler, nir);
181
182 nir_shader_gather_info(nir, entry_point->impl);
183
184 nir_variable_mode indirect_mask = 0;
185 if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput)
186 indirect_mask |= nir_var_shader_in;
187 if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
188 indirect_mask |= nir_var_local;
189
190 nir_lower_indirect_derefs(nir, indirect_mask);
191
192 return nir;
193 }
194
195 void anv_DestroyPipeline(
196 VkDevice _device,
197 VkPipeline _pipeline,
198 const VkAllocationCallbacks* pAllocator)
199 {
200 ANV_FROM_HANDLE(anv_device, device, _device);
201 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
202
203 anv_reloc_list_finish(&pipeline->batch_relocs,
204 pAllocator ? pAllocator : &device->alloc);
205 if (pipeline->blend_state.map)
206 anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
207 anv_free2(&device->alloc, pAllocator, pipeline);
208 }
209
210 static const uint32_t vk_to_gen_primitive_type[] = {
211 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
212 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
213 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
214 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
215 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
216 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
217 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
218 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
219 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
220 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
221 /* [VK_PRIMITIVE_TOPOLOGY_PATCH_LIST] = _3DPRIM_PATCHLIST_1 */
222 };
223
224 static void
225 populate_sampler_prog_key(const struct brw_device_info *devinfo,
226 struct brw_sampler_prog_key_data *key)
227 {
228 /* XXX: Handle texture swizzle on HSW- */
229 for (int i = 0; i < MAX_SAMPLERS; i++) {
230 /* Assume color sampler, no swizzling. (Works for BDW+) */
231 key->swizzles[i] = SWIZZLE_XYZW;
232 }
233 }
234
235 static void
236 populate_vs_prog_key(const struct brw_device_info *devinfo,
237 struct brw_vs_prog_key *key)
238 {
239 memset(key, 0, sizeof(*key));
240
241 populate_sampler_prog_key(devinfo, &key->tex);
242
243 /* XXX: Handle vertex input work-arounds */
244
245 /* XXX: Handle sampler_prog_key */
246 }
247
248 static void
249 populate_gs_prog_key(const struct brw_device_info *devinfo,
250 struct brw_gs_prog_key *key)
251 {
252 memset(key, 0, sizeof(*key));
253
254 populate_sampler_prog_key(devinfo, &key->tex);
255 }
256
257 static void
258 populate_wm_prog_key(const struct brw_device_info *devinfo,
259 const VkGraphicsPipelineCreateInfo *info,
260 const struct anv_graphics_pipeline_create_info *extra,
261 struct brw_wm_prog_key *key)
262 {
263 ANV_FROM_HANDLE(anv_render_pass, render_pass, info->renderPass);
264
265 memset(key, 0, sizeof(*key));
266
267 populate_sampler_prog_key(devinfo, &key->tex);
268
269 /* TODO: Fill out key->input_slots_valid */
270
271 /* Vulkan doesn't specify a default */
272 key->high_quality_derivatives = false;
273
274 /* XXX Vulkan doesn't appear to specify */
275 key->clamp_fragment_color = false;
276
277 if (extra && extra->color_attachment_count >= 0) {
278 key->nr_color_regions = extra->color_attachment_count;
279 } else {
280 key->nr_color_regions =
281 render_pass->subpasses[info->subpass].color_count;
282 }
283
284 key->replicate_alpha = key->nr_color_regions > 1 &&
285 info->pMultisampleState &&
286 info->pMultisampleState->alphaToCoverageEnable;
287
288 if (info->pMultisampleState && info->pMultisampleState->rasterizationSamples > 1) {
289 /* We should probably pull this out of the shader, but it's fairly
290 * harmless to compute it and then let dead-code take care of it.
291 */
292 key->persample_interp =
293 (info->pMultisampleState->minSampleShading *
294 info->pMultisampleState->rasterizationSamples) > 1;
295 key->multisample_fbo = true;
296 }
297 }
298
299 static void
300 populate_cs_prog_key(const struct brw_device_info *devinfo,
301 struct brw_cs_prog_key *key)
302 {
303 memset(key, 0, sizeof(*key));
304
305 populate_sampler_prog_key(devinfo, &key->tex);
306 }
307
308 static nir_shader *
309 anv_pipeline_compile(struct anv_pipeline *pipeline,
310 struct anv_shader_module *module,
311 const char *entrypoint,
312 gl_shader_stage stage,
313 const VkSpecializationInfo *spec_info,
314 struct brw_stage_prog_data *prog_data,
315 struct anv_pipeline_bind_map *map)
316 {
317 nir_shader *nir = anv_shader_compile_to_nir(pipeline->device,
318 module, entrypoint, stage,
319 spec_info);
320 if (nir == NULL)
321 return NULL;
322
323 anv_nir_lower_push_constants(nir);
324
325 /* Figure out the number of parameters */
326 prog_data->nr_params = 0;
327
328 if (nir->num_uniforms > 0) {
329 /* If the shader uses any push constants at all, we'll just give
330 * them the maximum possible number
331 */
332 assert(nir->num_uniforms <= MAX_PUSH_CONSTANTS_SIZE);
333 prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
334 }
335
336 if (pipeline->layout && pipeline->layout->stage[stage].has_dynamic_offsets)
337 prog_data->nr_params += MAX_DYNAMIC_BUFFERS * 2;
338
339 if (nir->info.num_images > 0) {
340 prog_data->nr_params += nir->info.num_images * BRW_IMAGE_PARAM_SIZE;
341 pipeline->needs_data_cache = true;
342 }
343
344 if (stage == MESA_SHADER_COMPUTE)
345 ((struct brw_cs_prog_data *)prog_data)->thread_local_id_index =
346 prog_data->nr_params++; /* The CS Thread ID uniform */
347
348 if (nir->info.num_ssbos > 0)
349 pipeline->needs_data_cache = true;
350
351 if (prog_data->nr_params > 0) {
352 /* XXX: I think we're leaking this */
353 prog_data->param = (const union gl_constant_value **)
354 malloc(prog_data->nr_params * sizeof(union gl_constant_value *));
355
356 /* We now set the param values to be offsets into a
357 * anv_push_constant_data structure. Since the compiler doesn't
358 * actually dereference any of the gl_constant_value pointers in the
359 * params array, it doesn't really matter what we put here.
360 */
361 struct anv_push_constants *null_data = NULL;
362 if (nir->num_uniforms > 0) {
363 /* Fill out the push constants section of the param array */
364 for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++)
365 prog_data->param[i] = (const union gl_constant_value *)
366 &null_data->client_data[i * sizeof(float)];
367 }
368 }
369
370 /* Set up dynamic offsets */
371 anv_nir_apply_dynamic_offsets(pipeline, nir, prog_data);
372
373 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
374 if (pipeline->layout)
375 anv_nir_apply_pipeline_layout(pipeline, nir, prog_data, map);
376
377 /* nir_lower_io will only handle the push constants; we need to set this
378 * to the full number of possible uniforms.
379 */
380 nir->num_uniforms = prog_data->nr_params * 4;
381
382 return nir;
383 }
384
385 static void
386 anv_fill_binding_table(struct brw_stage_prog_data *prog_data, unsigned bias)
387 {
388 prog_data->binding_table.size_bytes = 0;
389 prog_data->binding_table.texture_start = bias;
390 prog_data->binding_table.ubo_start = bias;
391 prog_data->binding_table.ssbo_start = bias;
392 prog_data->binding_table.image_start = bias;
393 }
394
395 static void
396 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
397 gl_shader_stage stage,
398 const struct brw_stage_prog_data *prog_data,
399 struct anv_pipeline_bind_map *map)
400 {
401 pipeline->prog_data[stage] = prog_data;
402 pipeline->active_stages |= mesa_to_vk_shader_stage(stage);
403 pipeline->bindings[stage] = *map;
404 }
405
406 static VkResult
407 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
408 struct anv_pipeline_cache *cache,
409 const VkGraphicsPipelineCreateInfo *info,
410 struct anv_shader_module *module,
411 const char *entrypoint,
412 const VkSpecializationInfo *spec_info)
413 {
414 const struct brw_compiler *compiler =
415 pipeline->device->instance->physicalDevice.compiler;
416 const struct brw_stage_prog_data *stage_prog_data;
417 struct anv_pipeline_bind_map map;
418 struct brw_vs_prog_key key;
419 uint32_t kernel = NO_KERNEL;
420 unsigned char sha1[20];
421
422 populate_vs_prog_key(&pipeline->device->info, &key);
423
424 if (module->size > 0) {
425 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, spec_info);
426 kernel = anv_pipeline_cache_search(cache, sha1, &stage_prog_data, &map);
427 }
428
429 if (kernel == NO_KERNEL) {
430 struct brw_vs_prog_data prog_data = { 0, };
431 struct anv_pipeline_binding surface_to_descriptor[256];
432 struct anv_pipeline_binding sampler_to_descriptor[256];
433
434 map = (struct anv_pipeline_bind_map) {
435 .surface_to_descriptor = surface_to_descriptor,
436 .sampler_to_descriptor = sampler_to_descriptor
437 };
438
439 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
440 MESA_SHADER_VERTEX, spec_info,
441 &prog_data.base.base, &map);
442 if (nir == NULL)
443 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
444
445 anv_fill_binding_table(&prog_data.base.base, 0);
446
447 void *mem_ctx = ralloc_context(NULL);
448
449 if (module->nir == NULL)
450 ralloc_steal(mem_ctx, nir);
451
452 prog_data.inputs_read = nir->info.inputs_read;
453
454 brw_compute_vue_map(&pipeline->device->info,
455 &prog_data.base.vue_map,
456 nir->info.outputs_written,
457 nir->info.separate_shader);
458
459 unsigned code_size;
460 const unsigned *shader_code =
461 brw_compile_vs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
462 NULL, false, -1, &code_size, NULL);
463 if (shader_code == NULL) {
464 ralloc_free(mem_ctx);
465 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
466 }
467
468 stage_prog_data = &prog_data.base.base;
469 kernel = anv_pipeline_cache_upload_kernel(cache,
470 module->size > 0 ? sha1 : NULL,
471 shader_code, code_size,
472 &stage_prog_data, sizeof(prog_data),
473 &map);
474 ralloc_free(mem_ctx);
475 }
476
477 const struct brw_vs_prog_data *vs_prog_data =
478 (const struct brw_vs_prog_data *) stage_prog_data;
479
480 if (vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8) {
481 pipeline->vs_simd8 = kernel;
482 pipeline->vs_vec4 = NO_KERNEL;
483 } else {
484 pipeline->vs_simd8 = NO_KERNEL;
485 pipeline->vs_vec4 = kernel;
486 }
487
488 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX,
489 stage_prog_data, &map);
490
491 return VK_SUCCESS;
492 }
493
494 static VkResult
495 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
496 struct anv_pipeline_cache *cache,
497 const VkGraphicsPipelineCreateInfo *info,
498 struct anv_shader_module *module,
499 const char *entrypoint,
500 const VkSpecializationInfo *spec_info)
501 {
502 const struct brw_compiler *compiler =
503 pipeline->device->instance->physicalDevice.compiler;
504 const struct brw_stage_prog_data *stage_prog_data;
505 struct anv_pipeline_bind_map map;
506 struct brw_gs_prog_key key;
507 uint32_t kernel = NO_KERNEL;
508 unsigned char sha1[20];
509
510 populate_gs_prog_key(&pipeline->device->info, &key);
511
512 if (module->size > 0) {
513 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, spec_info);
514 kernel = anv_pipeline_cache_search(cache, sha1, &stage_prog_data, &map);
515 }
516
517 if (kernel == NO_KERNEL) {
518 struct brw_gs_prog_data prog_data = { 0, };
519 struct anv_pipeline_binding surface_to_descriptor[256];
520 struct anv_pipeline_binding sampler_to_descriptor[256];
521
522 map = (struct anv_pipeline_bind_map) {
523 .surface_to_descriptor = surface_to_descriptor,
524 .sampler_to_descriptor = sampler_to_descriptor
525 };
526
527 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
528 MESA_SHADER_GEOMETRY, spec_info,
529 &prog_data.base.base, &map);
530 if (nir == NULL)
531 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
532
533 anv_fill_binding_table(&prog_data.base.base, 0);
534
535 void *mem_ctx = ralloc_context(NULL);
536
537 if (module->nir == NULL)
538 ralloc_steal(mem_ctx, nir);
539
540 brw_compute_vue_map(&pipeline->device->info,
541 &prog_data.base.vue_map,
542 nir->info.outputs_written,
543 nir->info.separate_shader);
544
545 unsigned code_size;
546 const unsigned *shader_code =
547 brw_compile_gs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
548 NULL, -1, &code_size, NULL);
549 if (shader_code == NULL) {
550 ralloc_free(mem_ctx);
551 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
552 }
553
554 /* TODO: SIMD8 GS */
555 stage_prog_data = &prog_data.base.base;
556 kernel = anv_pipeline_cache_upload_kernel(cache,
557 module->size > 0 ? sha1 : NULL,
558 shader_code, code_size,
559 &stage_prog_data, sizeof(prog_data),
560 &map);
561
562 ralloc_free(mem_ctx);
563 }
564
565 pipeline->gs_kernel = kernel;
566
567 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY,
568 stage_prog_data, &map);
569
570 return VK_SUCCESS;
571 }
572
573 static VkResult
574 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
575 struct anv_pipeline_cache *cache,
576 const VkGraphicsPipelineCreateInfo *info,
577 const struct anv_graphics_pipeline_create_info *extra,
578 struct anv_shader_module *module,
579 const char *entrypoint,
580 const VkSpecializationInfo *spec_info)
581 {
582 const struct brw_compiler *compiler =
583 pipeline->device->instance->physicalDevice.compiler;
584 const struct brw_stage_prog_data *stage_prog_data;
585 struct anv_pipeline_bind_map map;
586 struct brw_wm_prog_key key;
587 unsigned char sha1[20];
588
589 populate_wm_prog_key(&pipeline->device->info, info, extra, &key);
590
591 if (module->size > 0) {
592 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, spec_info);
593 pipeline->ps_ksp0 =
594 anv_pipeline_cache_search(cache, sha1, &stage_prog_data, &map);
595 }
596
597 if (pipeline->ps_ksp0 == NO_KERNEL) {
598 struct brw_wm_prog_data prog_data = { 0, };
599 struct anv_pipeline_binding surface_to_descriptor[256];
600 struct anv_pipeline_binding sampler_to_descriptor[256];
601
602 map = (struct anv_pipeline_bind_map) {
603 .surface_to_descriptor = surface_to_descriptor + 8,
604 .sampler_to_descriptor = sampler_to_descriptor
605 };
606
607 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
608 MESA_SHADER_FRAGMENT, spec_info,
609 &prog_data.base, &map);
610 if (nir == NULL)
611 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
612
613 unsigned num_rts = 0;
614 struct anv_pipeline_binding rt_bindings[8];
615 nir_function_impl *impl = nir_shader_get_entrypoint(nir)->impl;
616 nir_foreach_variable_safe(var, &nir->outputs) {
617 if (var->data.location < FRAG_RESULT_DATA0)
618 continue;
619
620 unsigned rt = var->data.location - FRAG_RESULT_DATA0;
621 if (rt >= key.nr_color_regions) {
622 /* Out-of-bounds, throw it away */
623 var->data.mode = nir_var_local;
624 exec_node_remove(&var->node);
625 exec_list_push_tail(&impl->locals, &var->node);
626 continue;
627 }
628
629 /* Give it a new, compacted, location */
630 var->data.location = FRAG_RESULT_DATA0 + num_rts;
631
632 unsigned array_len =
633 glsl_type_is_array(var->type) ? glsl_get_length(var->type) : 1;
634 assert(num_rts + array_len <= 8);
635
636 for (unsigned i = 0; i < array_len; i++) {
637 rt_bindings[num_rts] = (struct anv_pipeline_binding) {
638 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
639 .binding = 0,
640 .index = rt + i,
641 };
642 }
643
644 num_rts += array_len;
645 }
646
647 if (pipeline->use_repclear) {
648 assert(num_rts == 1);
649 key.nr_color_regions = 1;
650 }
651
652 if (num_rts == 0) {
653 /* If we have no render targets, we need a null render target */
654 rt_bindings[0] = (struct anv_pipeline_binding) {
655 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
656 .binding = 0,
657 .index = UINT8_MAX,
658 };
659 num_rts = 1;
660 }
661
662 assert(num_rts <= 8);
663 map.surface_to_descriptor -= num_rts;
664 map.surface_count += num_rts;
665 assert(map.surface_count <= 256);
666 memcpy(map.surface_to_descriptor, rt_bindings,
667 num_rts * sizeof(*rt_bindings));
668
669 anv_fill_binding_table(&prog_data.base, num_rts);
670
671 void *mem_ctx = ralloc_context(NULL);
672
673 if (module->nir == NULL)
674 ralloc_steal(mem_ctx, nir);
675
676 unsigned code_size;
677 const unsigned *shader_code =
678 brw_compile_fs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
679 NULL, -1, -1, true, pipeline->use_repclear,
680 &code_size, NULL);
681 if (shader_code == NULL) {
682 ralloc_free(mem_ctx);
683 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
684 }
685
686 stage_prog_data = &prog_data.base;
687 pipeline->ps_ksp0 =
688 anv_pipeline_cache_upload_kernel(cache,
689 module->size > 0 ? sha1 : NULL,
690 shader_code, code_size,
691 &stage_prog_data, sizeof(prog_data),
692 &map);
693
694 ralloc_free(mem_ctx);
695 }
696
697 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT,
698 stage_prog_data, &map);
699
700 return VK_SUCCESS;
701 }
702
703 VkResult
704 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
705 struct anv_pipeline_cache *cache,
706 const VkComputePipelineCreateInfo *info,
707 struct anv_shader_module *module,
708 const char *entrypoint,
709 const VkSpecializationInfo *spec_info)
710 {
711 const struct brw_compiler *compiler =
712 pipeline->device->instance->physicalDevice.compiler;
713 const struct brw_stage_prog_data *stage_prog_data;
714 struct anv_pipeline_bind_map map;
715 struct brw_cs_prog_key key;
716 uint32_t kernel = NO_KERNEL;
717 unsigned char sha1[20];
718
719 populate_cs_prog_key(&pipeline->device->info, &key);
720
721 if (module->size > 0) {
722 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, spec_info);
723 kernel = anv_pipeline_cache_search(cache, sha1, &stage_prog_data, &map);
724 }
725
726 if (module->size == 0 || kernel == NO_KERNEL) {
727 struct brw_cs_prog_data prog_data = { 0, };
728 struct anv_pipeline_binding surface_to_descriptor[256];
729 struct anv_pipeline_binding sampler_to_descriptor[256];
730
731 map = (struct anv_pipeline_bind_map) {
732 .surface_to_descriptor = surface_to_descriptor,
733 .sampler_to_descriptor = sampler_to_descriptor
734 };
735
736 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
737 MESA_SHADER_COMPUTE, spec_info,
738 &prog_data.base, &map);
739 if (nir == NULL)
740 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
741
742 anv_fill_binding_table(&prog_data.base, 1);
743
744 void *mem_ctx = ralloc_context(NULL);
745
746 if (module->nir == NULL)
747 ralloc_steal(mem_ctx, nir);
748
749 unsigned code_size;
750 const unsigned *shader_code =
751 brw_compile_cs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
752 -1, &code_size, NULL);
753 if (shader_code == NULL) {
754 ralloc_free(mem_ctx);
755 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
756 }
757
758 stage_prog_data = &prog_data.base;
759 kernel = anv_pipeline_cache_upload_kernel(cache,
760 module->size > 0 ? sha1 : NULL,
761 shader_code, code_size,
762 &stage_prog_data, sizeof(prog_data),
763 &map);
764
765 ralloc_free(mem_ctx);
766 }
767
768 pipeline->cs_simd = kernel;
769
770 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE,
771 stage_prog_data, &map);
772
773 return VK_SUCCESS;
774 }
775
776
777 void
778 anv_setup_pipeline_l3_config(struct anv_pipeline *pipeline)
779 {
780 const struct brw_device_info *devinfo = &pipeline->device->info;
781 switch (devinfo->gen) {
782 case 7:
783 if (devinfo->is_haswell)
784 gen75_setup_pipeline_l3_config(pipeline);
785 else
786 gen7_setup_pipeline_l3_config(pipeline);
787 break;
788 case 8:
789 gen8_setup_pipeline_l3_config(pipeline);
790 break;
791 case 9:
792 gen9_setup_pipeline_l3_config(pipeline);
793 break;
794 default:
795 unreachable("unsupported gen\n");
796 }
797 }
798
799 void
800 anv_compute_urb_partition(struct anv_pipeline *pipeline)
801 {
802 const struct brw_device_info *devinfo = &pipeline->device->info;
803
804 bool vs_present = pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT;
805 unsigned vs_size = vs_present ?
806 get_vs_prog_data(pipeline)->base.urb_entry_size : 1;
807 unsigned vs_entry_size_bytes = vs_size * 64;
808 bool gs_present = pipeline->active_stages & VK_SHADER_STAGE_GEOMETRY_BIT;
809 unsigned gs_size = gs_present ?
810 get_gs_prog_data(pipeline)->base.urb_entry_size : 1;
811 unsigned gs_entry_size_bytes = gs_size * 64;
812
813 /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
814 *
815 * VS Number of URB Entries must be divisible by 8 if the VS URB Entry
816 * Allocation Size is less than 9 512-bit URB entries.
817 *
818 * Similar text exists for GS.
819 */
820 unsigned vs_granularity = (vs_size < 9) ? 8 : 1;
821 unsigned gs_granularity = (gs_size < 9) ? 8 : 1;
822
823 /* URB allocations must be done in 8k chunks. */
824 unsigned chunk_size_bytes = 8192;
825
826 /* Determine the size of the URB in chunks. */
827 unsigned urb_chunks = pipeline->urb.total_size * 1024 / chunk_size_bytes;
828
829 /* Reserve space for push constants */
830 unsigned push_constant_kb;
831 if (pipeline->device->info.gen >= 8)
832 push_constant_kb = 32;
833 else if (pipeline->device->info.is_haswell)
834 push_constant_kb = pipeline->device->info.gt == 3 ? 32 : 16;
835 else
836 push_constant_kb = 16;
837
838 unsigned push_constant_bytes = push_constant_kb * 1024;
839 unsigned push_constant_chunks =
840 push_constant_bytes / chunk_size_bytes;
841
842 /* Initially, assign each stage the minimum amount of URB space it needs,
843 * and make a note of how much additional space it "wants" (the amount of
844 * additional space it could actually make use of).
845 */
846
847 /* VS has a lower limit on the number of URB entries */
848 unsigned vs_chunks =
849 ALIGN(devinfo->urb.min_vs_entries * vs_entry_size_bytes,
850 chunk_size_bytes) / chunk_size_bytes;
851 unsigned vs_wants =
852 ALIGN(devinfo->urb.max_vs_entries * vs_entry_size_bytes,
853 chunk_size_bytes) / chunk_size_bytes - vs_chunks;
854
855 unsigned gs_chunks = 0;
856 unsigned gs_wants = 0;
857 if (gs_present) {
858 /* There are two constraints on the minimum amount of URB space we can
859 * allocate:
860 *
861 * (1) We need room for at least 2 URB entries, since we always operate
862 * the GS in DUAL_OBJECT mode.
863 *
864 * (2) We can't allocate less than nr_gs_entries_granularity.
865 */
866 gs_chunks = ALIGN(MAX2(gs_granularity, 2) * gs_entry_size_bytes,
867 chunk_size_bytes) / chunk_size_bytes;
868 gs_wants =
869 ALIGN(devinfo->urb.max_gs_entries * gs_entry_size_bytes,
870 chunk_size_bytes) / chunk_size_bytes - gs_chunks;
871 }
872
873 /* There should always be enough URB space to satisfy the minimum
874 * requirements of each stage.
875 */
876 unsigned total_needs = push_constant_chunks + vs_chunks + gs_chunks;
877 assert(total_needs <= urb_chunks);
878
879 /* Mete out remaining space (if any) in proportion to "wants". */
880 unsigned total_wants = vs_wants + gs_wants;
881 unsigned remaining_space = urb_chunks - total_needs;
882 if (remaining_space > total_wants)
883 remaining_space = total_wants;
884 if (remaining_space > 0) {
885 unsigned vs_additional = (unsigned)
886 round(vs_wants * (((double) remaining_space) / total_wants));
887 vs_chunks += vs_additional;
888 remaining_space -= vs_additional;
889 gs_chunks += remaining_space;
890 }
891
892 /* Sanity check that we haven't over-allocated. */
893 assert(push_constant_chunks + vs_chunks + gs_chunks <= urb_chunks);
894
895 /* Finally, compute the number of entries that can fit in the space
896 * allocated to each stage.
897 */
898 unsigned nr_vs_entries = vs_chunks * chunk_size_bytes / vs_entry_size_bytes;
899 unsigned nr_gs_entries = gs_chunks * chunk_size_bytes / gs_entry_size_bytes;
900
901 /* Since we rounded up when computing *_wants, this may be slightly more
902 * than the maximum allowed amount, so correct for that.
903 */
904 nr_vs_entries = MIN2(nr_vs_entries, devinfo->urb.max_vs_entries);
905 nr_gs_entries = MIN2(nr_gs_entries, devinfo->urb.max_gs_entries);
906
907 /* Ensure that we program a multiple of the granularity. */
908 nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, vs_granularity);
909 nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, gs_granularity);
910
911 /* Finally, sanity check to make sure we have at least the minimum number
912 * of entries needed for each stage.
913 */
914 assert(nr_vs_entries >= devinfo->urb.min_vs_entries);
915 if (gs_present)
916 assert(nr_gs_entries >= 2);
917
918 /* Lay out the URB in the following order:
919 * - push constants
920 * - VS
921 * - GS
922 */
923 pipeline->urb.start[MESA_SHADER_VERTEX] = push_constant_chunks;
924 pipeline->urb.size[MESA_SHADER_VERTEX] = vs_size;
925 pipeline->urb.entries[MESA_SHADER_VERTEX] = nr_vs_entries;
926
927 pipeline->urb.start[MESA_SHADER_GEOMETRY] = push_constant_chunks + vs_chunks;
928 pipeline->urb.size[MESA_SHADER_GEOMETRY] = gs_size;
929 pipeline->urb.entries[MESA_SHADER_GEOMETRY] = nr_gs_entries;
930
931 pipeline->urb.start[MESA_SHADER_TESS_CTRL] = push_constant_chunks;
932 pipeline->urb.size[MESA_SHADER_TESS_CTRL] = 1;
933 pipeline->urb.entries[MESA_SHADER_TESS_CTRL] = 0;
934
935 pipeline->urb.start[MESA_SHADER_TESS_EVAL] = push_constant_chunks;
936 pipeline->urb.size[MESA_SHADER_TESS_EVAL] = 1;
937 pipeline->urb.entries[MESA_SHADER_TESS_EVAL] = 0;
938 }
939
940 /**
941 * Copy pipeline state not marked as dynamic.
942 * Dynamic state is pipeline state which hasn't been provided at pipeline
943 * creation time, but is dynamically provided afterwards using various
944 * vkCmdSet* functions.
945 *
946 * The set of state considered "non_dynamic" is determined by the pieces of
947 * state that have their corresponding VkDynamicState enums omitted from
948 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
949 *
950 * @param[out] pipeline Destination non_dynamic state.
951 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
952 */
953 static void
954 copy_non_dynamic_state(struct anv_pipeline *pipeline,
955 const VkGraphicsPipelineCreateInfo *pCreateInfo)
956 {
957 anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
958 ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
959 struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
960
961 pipeline->dynamic_state = default_dynamic_state;
962
963 if (pCreateInfo->pDynamicState) {
964 /* Remove all of the states that are marked as dynamic */
965 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
966 for (uint32_t s = 0; s < count; s++)
967 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
968 }
969
970 struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
971
972 /* Section 9.2 of the Vulkan 1.0.15 spec says:
973 *
974 * pViewportState is [...] NULL if the pipeline
975 * has rasterization disabled.
976 */
977 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
978 assert(pCreateInfo->pViewportState);
979
980 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
981 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
982 typed_memcpy(dynamic->viewport.viewports,
983 pCreateInfo->pViewportState->pViewports,
984 pCreateInfo->pViewportState->viewportCount);
985 }
986
987 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
988 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
989 typed_memcpy(dynamic->scissor.scissors,
990 pCreateInfo->pViewportState->pScissors,
991 pCreateInfo->pViewportState->scissorCount);
992 }
993 }
994
995 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
996 assert(pCreateInfo->pRasterizationState);
997 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
998 }
999
1000 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1001 assert(pCreateInfo->pRasterizationState);
1002 dynamic->depth_bias.bias =
1003 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1004 dynamic->depth_bias.clamp =
1005 pCreateInfo->pRasterizationState->depthBiasClamp;
1006 dynamic->depth_bias.slope =
1007 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1008 }
1009
1010 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1011 *
1012 * pColorBlendState is [...] NULL if the pipeline has rasterization
1013 * disabled or if the subpass of the render pass the pipeline is
1014 * created against does not use any color attachments.
1015 */
1016 bool uses_color_att = false;
1017 for (unsigned i = 0; i < subpass->color_count; ++i) {
1018 if (subpass->color_attachments[i] != VK_ATTACHMENT_UNUSED) {
1019 uses_color_att = true;
1020 break;
1021 }
1022 }
1023
1024 if (uses_color_att &&
1025 !pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1026 assert(pCreateInfo->pColorBlendState);
1027
1028 if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
1029 typed_memcpy(dynamic->blend_constants,
1030 pCreateInfo->pColorBlendState->blendConstants, 4);
1031 }
1032
1033 /* If there is no depthstencil attachment, then don't read
1034 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1035 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1036 * no need to override the depthstencil defaults in
1037 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1038 *
1039 * Section 9.2 of the Vulkan 1.0.15 spec says:
1040 *
1041 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1042 * disabled or if the subpass of the render pass the pipeline is created
1043 * against does not use a depth/stencil attachment.
1044 */
1045 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1046 subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
1047 assert(pCreateInfo->pDepthStencilState);
1048
1049 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1050 dynamic->depth_bounds.min =
1051 pCreateInfo->pDepthStencilState->minDepthBounds;
1052 dynamic->depth_bounds.max =
1053 pCreateInfo->pDepthStencilState->maxDepthBounds;
1054 }
1055
1056 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1057 dynamic->stencil_compare_mask.front =
1058 pCreateInfo->pDepthStencilState->front.compareMask;
1059 dynamic->stencil_compare_mask.back =
1060 pCreateInfo->pDepthStencilState->back.compareMask;
1061 }
1062
1063 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1064 dynamic->stencil_write_mask.front =
1065 pCreateInfo->pDepthStencilState->front.writeMask;
1066 dynamic->stencil_write_mask.back =
1067 pCreateInfo->pDepthStencilState->back.writeMask;
1068 }
1069
1070 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1071 dynamic->stencil_reference.front =
1072 pCreateInfo->pDepthStencilState->front.reference;
1073 dynamic->stencil_reference.back =
1074 pCreateInfo->pDepthStencilState->back.reference;
1075 }
1076 }
1077
1078 pipeline->dynamic_state_mask = states;
1079 }
1080
1081 static void
1082 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
1083 {
1084 struct anv_render_pass *renderpass = NULL;
1085 struct anv_subpass *subpass = NULL;
1086
1087 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1088 * present, as explained by the Vulkan (20 Oct 2015, git-aa308cb), Section
1089 * 4.2 Graphics Pipeline.
1090 */
1091 assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
1092
1093 renderpass = anv_render_pass_from_handle(info->renderPass);
1094 assert(renderpass);
1095
1096 if (renderpass != &anv_meta_dummy_renderpass) {
1097 assert(info->subpass < renderpass->subpass_count);
1098 subpass = &renderpass->subpasses[info->subpass];
1099 }
1100
1101 assert(info->stageCount >= 1);
1102 assert(info->pVertexInputState);
1103 assert(info->pInputAssemblyState);
1104 assert(info->pViewportState);
1105 assert(info->pRasterizationState);
1106
1107 if (subpass && subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED)
1108 assert(info->pDepthStencilState);
1109
1110 if (subpass && subpass->color_count > 0)
1111 assert(info->pColorBlendState);
1112
1113 for (uint32_t i = 0; i < info->stageCount; ++i) {
1114 switch (info->pStages[i].stage) {
1115 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
1116 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
1117 assert(info->pTessellationState);
1118 break;
1119 default:
1120 break;
1121 }
1122 }
1123 }
1124
1125 VkResult
1126 anv_pipeline_init(struct anv_pipeline *pipeline,
1127 struct anv_device *device,
1128 struct anv_pipeline_cache *cache,
1129 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1130 const struct anv_graphics_pipeline_create_info *extra,
1131 const VkAllocationCallbacks *alloc)
1132 {
1133 VkResult result;
1134
1135 anv_validate {
1136 anv_pipeline_validate_create_info(pCreateInfo);
1137 }
1138
1139 if (alloc == NULL)
1140 alloc = &device->alloc;
1141
1142 pipeline->device = device;
1143 pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
1144
1145 result = anv_reloc_list_init(&pipeline->batch_relocs, alloc);
1146 if (result != VK_SUCCESS)
1147 return result;
1148
1149 pipeline->batch.alloc = alloc;
1150 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
1151 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
1152 pipeline->batch.relocs = &pipeline->batch_relocs;
1153
1154 copy_non_dynamic_state(pipeline, pCreateInfo);
1155 pipeline->depth_clamp_enable = pCreateInfo->pRasterizationState &&
1156 pCreateInfo->pRasterizationState->depthClampEnable;
1157
1158 pipeline->use_repclear = extra && extra->use_repclear;
1159
1160 pipeline->needs_data_cache = false;
1161
1162 /* When we free the pipeline, we detect stages based on the NULL status
1163 * of various prog_data pointers. Make them NULL by default.
1164 */
1165 memset(pipeline->prog_data, 0, sizeof(pipeline->prog_data));
1166 memset(pipeline->bindings, 0, sizeof(pipeline->bindings));
1167
1168 pipeline->vs_simd8 = NO_KERNEL;
1169 pipeline->vs_vec4 = NO_KERNEL;
1170 pipeline->gs_kernel = NO_KERNEL;
1171 pipeline->ps_ksp0 = NO_KERNEL;
1172
1173 pipeline->active_stages = 0;
1174
1175 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1176 struct anv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1177 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1178 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1179 pStages[stage] = &pCreateInfo->pStages[i];
1180 modules[stage] = anv_shader_module_from_handle(pStages[stage]->module);
1181 }
1182
1183 if (modules[MESA_SHADER_VERTEX]) {
1184 anv_pipeline_compile_vs(pipeline, cache, pCreateInfo,
1185 modules[MESA_SHADER_VERTEX],
1186 pStages[MESA_SHADER_VERTEX]->pName,
1187 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo);
1188 }
1189
1190 if (modules[MESA_SHADER_TESS_CTRL] || modules[MESA_SHADER_TESS_EVAL])
1191 anv_finishme("no tessellation support");
1192
1193 if (modules[MESA_SHADER_GEOMETRY]) {
1194 anv_pipeline_compile_gs(pipeline, cache, pCreateInfo,
1195 modules[MESA_SHADER_GEOMETRY],
1196 pStages[MESA_SHADER_GEOMETRY]->pName,
1197 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo);
1198 }
1199
1200 if (modules[MESA_SHADER_FRAGMENT]) {
1201 anv_pipeline_compile_fs(pipeline, cache, pCreateInfo, extra,
1202 modules[MESA_SHADER_FRAGMENT],
1203 pStages[MESA_SHADER_FRAGMENT]->pName,
1204 pStages[MESA_SHADER_FRAGMENT]->pSpecializationInfo);
1205 }
1206
1207 if (!(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT)) {
1208 /* Vertex is only optional if disable_vs is set */
1209 assert(extra->disable_vs);
1210 }
1211
1212 anv_setup_pipeline_l3_config(pipeline);
1213 anv_compute_urb_partition(pipeline);
1214
1215 const VkPipelineVertexInputStateCreateInfo *vi_info =
1216 pCreateInfo->pVertexInputState;
1217
1218 uint64_t inputs_read;
1219 if (extra && extra->disable_vs) {
1220 /* If the VS is disabled, just assume the user knows what they're
1221 * doing and apply the layout blindly. This can only come from
1222 * meta, so this *should* be safe.
1223 */
1224 inputs_read = ~0ull;
1225 } else {
1226 inputs_read = get_vs_prog_data(pipeline)->inputs_read;
1227 }
1228
1229 pipeline->vb_used = 0;
1230 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1231 const VkVertexInputAttributeDescription *desc =
1232 &vi_info->pVertexAttributeDescriptions[i];
1233
1234 if (inputs_read & (1 << (VERT_ATTRIB_GENERIC0 + desc->location)))
1235 pipeline->vb_used |= 1 << desc->binding;
1236 }
1237
1238 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1239 const VkVertexInputBindingDescription *desc =
1240 &vi_info->pVertexBindingDescriptions[i];
1241
1242 pipeline->binding_stride[desc->binding] = desc->stride;
1243
1244 /* Step rate is programmed per vertex element (attribute), not
1245 * binding. Set up a map of which bindings step per instance, for
1246 * reference by vertex element setup. */
1247 switch (desc->inputRate) {
1248 default:
1249 case VK_VERTEX_INPUT_RATE_VERTEX:
1250 pipeline->instancing_enable[desc->binding] = false;
1251 break;
1252 case VK_VERTEX_INPUT_RATE_INSTANCE:
1253 pipeline->instancing_enable[desc->binding] = true;
1254 break;
1255 }
1256 }
1257
1258 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1259 pCreateInfo->pInputAssemblyState;
1260 pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1261 pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1262
1263 if (extra && extra->use_rectlist)
1264 pipeline->topology = _3DPRIM_RECTLIST;
1265
1266 return VK_SUCCESS;
1267 }
1268
1269 VkResult
1270 anv_graphics_pipeline_create(
1271 VkDevice _device,
1272 VkPipelineCache _cache,
1273 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1274 const struct anv_graphics_pipeline_create_info *extra,
1275 const VkAllocationCallbacks *pAllocator,
1276 VkPipeline *pPipeline)
1277 {
1278 ANV_FROM_HANDLE(anv_device, device, _device);
1279 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
1280
1281 if (cache == NULL)
1282 cache = &device->default_pipeline_cache;
1283
1284 switch (device->info.gen) {
1285 case 7:
1286 if (device->info.is_haswell)
1287 return gen75_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1288 else
1289 return gen7_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1290 case 8:
1291 return gen8_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1292 case 9:
1293 return gen9_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1294 default:
1295 unreachable("unsupported gen\n");
1296 }
1297 }
1298
1299 VkResult anv_CreateGraphicsPipelines(
1300 VkDevice _device,
1301 VkPipelineCache pipelineCache,
1302 uint32_t count,
1303 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1304 const VkAllocationCallbacks* pAllocator,
1305 VkPipeline* pPipelines)
1306 {
1307 VkResult result = VK_SUCCESS;
1308
1309 unsigned i = 0;
1310 for (; i < count; i++) {
1311 result = anv_graphics_pipeline_create(_device,
1312 pipelineCache,
1313 &pCreateInfos[i],
1314 NULL, pAllocator, &pPipelines[i]);
1315 if (result != VK_SUCCESS) {
1316 for (unsigned j = 0; j < i; j++) {
1317 anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1318 }
1319
1320 return result;
1321 }
1322 }
1323
1324 return VK_SUCCESS;
1325 }
1326
1327 static VkResult anv_compute_pipeline_create(
1328 VkDevice _device,
1329 VkPipelineCache _cache,
1330 const VkComputePipelineCreateInfo* pCreateInfo,
1331 const VkAllocationCallbacks* pAllocator,
1332 VkPipeline* pPipeline)
1333 {
1334 ANV_FROM_HANDLE(anv_device, device, _device);
1335 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
1336
1337 if (cache == NULL)
1338 cache = &device->default_pipeline_cache;
1339
1340 switch (device->info.gen) {
1341 case 7:
1342 if (device->info.is_haswell)
1343 return gen75_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1344 else
1345 return gen7_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1346 case 8:
1347 return gen8_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1348 case 9:
1349 return gen9_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1350 default:
1351 unreachable("unsupported gen\n");
1352 }
1353 }
1354
1355 VkResult anv_CreateComputePipelines(
1356 VkDevice _device,
1357 VkPipelineCache pipelineCache,
1358 uint32_t count,
1359 const VkComputePipelineCreateInfo* pCreateInfos,
1360 const VkAllocationCallbacks* pAllocator,
1361 VkPipeline* pPipelines)
1362 {
1363 VkResult result = VK_SUCCESS;
1364
1365 unsigned i = 0;
1366 for (; i < count; i++) {
1367 result = anv_compute_pipeline_create(_device, pipelineCache,
1368 &pCreateInfos[i],
1369 pAllocator, &pPipelines[i]);
1370 if (result != VK_SUCCESS) {
1371 for (unsigned j = 0; j < i; j++) {
1372 anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1373 }
1374
1375 return result;
1376 }
1377 }
1378
1379 return VK_SUCCESS;
1380 }