2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "common/gen_l3_config.h"
32 #include "anv_private.h"
33 #include "compiler/brw_nir.h"
35 #include "spirv/nir_spirv.h"
38 /* Needed for SWIZZLE macros */
39 #include "program/prog_instruction.h"
43 VkResult
anv_CreateShaderModule(
45 const VkShaderModuleCreateInfo
* pCreateInfo
,
46 const VkAllocationCallbacks
* pAllocator
,
47 VkShaderModule
* pShaderModule
)
49 ANV_FROM_HANDLE(anv_device
, device
, _device
);
50 struct anv_shader_module
*module
;
52 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
53 assert(pCreateInfo
->flags
== 0);
55 module
= vk_alloc2(&device
->alloc
, pAllocator
,
56 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
57 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
59 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
61 module
->size
= pCreateInfo
->codeSize
;
62 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
64 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
66 *pShaderModule
= anv_shader_module_to_handle(module
);
71 void anv_DestroyShaderModule(
73 VkShaderModule _module
,
74 const VkAllocationCallbacks
* pAllocator
)
76 ANV_FROM_HANDLE(anv_device
, device
, _device
);
77 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
82 vk_free2(&device
->alloc
, pAllocator
, module
);
85 #define SPIR_V_MAGIC_NUMBER 0x07230203
87 static const uint64_t stage_to_debug
[] = {
88 [MESA_SHADER_VERTEX
] = DEBUG_VS
,
89 [MESA_SHADER_TESS_CTRL
] = DEBUG_TCS
,
90 [MESA_SHADER_TESS_EVAL
] = DEBUG_TES
,
91 [MESA_SHADER_GEOMETRY
] = DEBUG_GS
,
92 [MESA_SHADER_FRAGMENT
] = DEBUG_WM
,
93 [MESA_SHADER_COMPUTE
] = DEBUG_CS
,
96 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
97 * we can't do that yet because we don't have the ability to copy nir.
100 anv_shader_compile_to_nir(struct anv_device
*device
,
102 const struct anv_shader_module
*module
,
103 const char *entrypoint_name
,
104 gl_shader_stage stage
,
105 const VkSpecializationInfo
*spec_info
)
107 const struct brw_compiler
*compiler
=
108 device
->instance
->physicalDevice
.compiler
;
109 const nir_shader_compiler_options
*nir_options
=
110 compiler
->glsl_compiler_options
[stage
].NirOptions
;
112 uint32_t *spirv
= (uint32_t *) module
->data
;
113 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
114 assert(module
->size
% 4 == 0);
116 uint32_t num_spec_entries
= 0;
117 struct nir_spirv_specialization
*spec_entries
= NULL
;
118 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
119 num_spec_entries
= spec_info
->mapEntryCount
;
120 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
121 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
122 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
123 const void *data
= spec_info
->pData
+ entry
.offset
;
124 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
126 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
127 if (spec_info
->dataSize
== 8)
128 spec_entries
[i
].data64
= *(const uint64_t *)data
;
130 spec_entries
[i
].data32
= *(const uint32_t *)data
;
134 struct spirv_to_nir_options spirv_options
= {
135 .lower_workgroup_access_to_offsets
= true,
137 .device_group
= true,
138 .draw_parameters
= true,
139 .float64
= device
->instance
->physicalDevice
.info
.gen
>= 8,
140 .image_write_without_format
= true,
141 .int16
= device
->instance
->physicalDevice
.info
.gen
>= 8,
142 .int64
= device
->instance
->physicalDevice
.info
.gen
>= 8,
145 .post_depth_coverage
= device
->instance
->physicalDevice
.info
.gen
>= 9,
146 .shader_viewport_index_layer
= true,
147 .stencil_export
= device
->instance
->physicalDevice
.info
.gen
>= 9,
148 .storage_8bit
= device
->instance
->physicalDevice
.info
.gen
>= 8,
149 .storage_16bit
= device
->instance
->physicalDevice
.info
.gen
>= 8,
150 .subgroup_arithmetic
= true,
151 .subgroup_basic
= true,
152 .subgroup_ballot
= true,
153 .subgroup_quad
= true,
154 .subgroup_shuffle
= true,
155 .subgroup_vote
= true,
156 .tessellation
= true,
157 .variable_pointers
= true,
159 .ubo_ptr_type
= glsl_vector_type(GLSL_TYPE_UINT
, 2),
160 .ssbo_ptr_type
= glsl_vector_type(GLSL_TYPE_UINT
, 2),
161 .push_const_ptr_type
= glsl_uint_type(),
162 .shared_ptr_type
= glsl_uint_type(),
165 nir_function
*entry_point
=
166 spirv_to_nir(spirv
, module
->size
/ 4,
167 spec_entries
, num_spec_entries
,
168 stage
, entrypoint_name
, &spirv_options
, nir_options
);
169 nir_shader
*nir
= entry_point
->shader
;
170 assert(nir
->info
.stage
== stage
);
171 nir_validate_shader(nir
, "after spirv_to_nir");
172 ralloc_steal(mem_ctx
, nir
);
176 if (unlikely(INTEL_DEBUG
& stage_to_debug
[stage
])) {
177 fprintf(stderr
, "NIR (from SPIR-V) for %s shader:\n",
178 gl_shader_stage_name(stage
));
179 nir_print_shader(nir
, stderr
);
182 /* We have to lower away local constant initializers right before we
183 * inline functions. That way they get properly initialized at the top
184 * of the function and not at the top of its caller.
186 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_function_temp
);
187 NIR_PASS_V(nir
, nir_lower_returns
);
188 NIR_PASS_V(nir
, nir_inline_functions
);
189 NIR_PASS_V(nir
, nir_opt_deref
);
191 /* Pick off the single entrypoint that we want */
192 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
193 if (func
!= entry_point
)
194 exec_node_remove(&func
->node
);
196 assert(exec_list_length(&nir
->functions
) == 1);
198 /* Now that we've deleted all but the main function, we can go ahead and
199 * lower the rest of the constant initializers. We do this here so that
200 * nir_remove_dead_variables and split_per_member_structs below see the
201 * corresponding stores.
203 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
205 /* Split member structs. We do this before lower_io_to_temporaries so that
206 * it doesn't lower system values to temporaries by accident.
208 NIR_PASS_V(nir
, nir_split_var_copies
);
209 NIR_PASS_V(nir
, nir_split_per_member_structs
);
211 NIR_PASS_V(nir
, nir_remove_dead_variables
,
212 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
214 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ubo
| nir_var_ssbo
,
215 nir_address_format_vk_index_offset
);
217 NIR_PASS_V(nir
, nir_propagate_invariant
);
218 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
219 entry_point
->impl
, true, false);
221 /* Vulkan uses the separate-shader linking model */
222 nir
->info
.separate_shader
= true;
224 nir
= brw_preprocess_nir(compiler
, nir
);
229 void anv_DestroyPipeline(
231 VkPipeline _pipeline
,
232 const VkAllocationCallbacks
* pAllocator
)
234 ANV_FROM_HANDLE(anv_device
, device
, _device
);
235 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
240 anv_reloc_list_finish(&pipeline
->batch_relocs
,
241 pAllocator
? pAllocator
: &device
->alloc
);
242 if (pipeline
->blend_state
.map
)
243 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
245 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
246 if (pipeline
->shaders
[s
])
247 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
250 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
253 static const uint32_t vk_to_gen_primitive_type
[] = {
254 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
255 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
256 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
257 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
258 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
259 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
260 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
261 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
262 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
263 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
267 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
268 struct brw_sampler_prog_key_data
*key
)
270 /* Almost all multisampled textures are compressed. The only time when we
271 * don't compress a multisampled texture is for 16x MSAA with a surface
272 * width greater than 8k which is a bit of an edge case. Since the sampler
273 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
274 * to tell the compiler to always assume compression.
276 key
->compressed_multisample_layout_mask
= ~0;
278 /* SkyLake added support for 16x MSAA. With this came a new message for
279 * reading from a 16x MSAA surface with compression. The new message was
280 * needed because now the MCS data is 64 bits instead of 32 or lower as is
281 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
282 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
283 * so we can just use it unconditionally. This may not be quite as
284 * efficient but it saves us from recompiling.
286 if (devinfo
->gen
>= 9)
289 /* XXX: Handle texture swizzle on HSW- */
290 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
291 /* Assume color sampler, no swizzling. (Works for BDW+) */
292 key
->swizzles
[i
] = SWIZZLE_XYZW
;
297 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
298 struct brw_vs_prog_key
*key
)
300 memset(key
, 0, sizeof(*key
));
302 populate_sampler_prog_key(devinfo
, &key
->tex
);
304 /* XXX: Handle vertex input work-arounds */
306 /* XXX: Handle sampler_prog_key */
310 populate_tcs_prog_key(const struct gen_device_info
*devinfo
,
311 unsigned input_vertices
,
312 struct brw_tcs_prog_key
*key
)
314 memset(key
, 0, sizeof(*key
));
316 populate_sampler_prog_key(devinfo
, &key
->tex
);
318 key
->input_vertices
= input_vertices
;
322 populate_tes_prog_key(const struct gen_device_info
*devinfo
,
323 struct brw_tes_prog_key
*key
)
325 memset(key
, 0, sizeof(*key
));
327 populate_sampler_prog_key(devinfo
, &key
->tex
);
331 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
332 struct brw_gs_prog_key
*key
)
334 memset(key
, 0, sizeof(*key
));
336 populate_sampler_prog_key(devinfo
, &key
->tex
);
340 populate_wm_prog_key(const struct gen_device_info
*devinfo
,
341 const struct anv_subpass
*subpass
,
342 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
343 struct brw_wm_prog_key
*key
)
345 memset(key
, 0, sizeof(*key
));
347 populate_sampler_prog_key(devinfo
, &key
->tex
);
349 /* We set this to 0 here and set to the actual value before we call
352 key
->input_slots_valid
= 0;
354 /* Vulkan doesn't specify a default */
355 key
->high_quality_derivatives
= false;
357 /* XXX Vulkan doesn't appear to specify */
358 key
->clamp_fragment_color
= false;
360 assert(subpass
->color_count
<= MAX_RTS
);
361 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
362 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
363 key
->color_outputs_valid
|= (1 << i
);
366 key
->nr_color_regions
= util_bitcount(key
->color_outputs_valid
);
368 key
->replicate_alpha
= key
->nr_color_regions
> 1 &&
369 ms_info
&& ms_info
->alphaToCoverageEnable
;
372 /* We should probably pull this out of the shader, but it's fairly
373 * harmless to compute it and then let dead-code take care of it.
375 if (ms_info
->rasterizationSamples
> 1) {
376 key
->persample_interp
=
377 (ms_info
->minSampleShading
* ms_info
->rasterizationSamples
) > 1;
378 key
->multisample_fbo
= true;
381 key
->frag_coord_adds_sample_pos
= ms_info
->sampleShadingEnable
;
386 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
387 struct brw_cs_prog_key
*key
)
389 memset(key
, 0, sizeof(*key
));
391 populate_sampler_prog_key(devinfo
, &key
->tex
);
394 struct anv_pipeline_stage
{
395 gl_shader_stage stage
;
397 const struct anv_shader_module
*module
;
398 const char *entrypoint
;
399 const VkSpecializationInfo
*spec_info
;
401 unsigned char shader_sha1
[20];
403 union brw_any_prog_key key
;
406 gl_shader_stage stage
;
407 unsigned char sha1
[20];
412 struct anv_pipeline_binding surface_to_descriptor
[256];
413 struct anv_pipeline_binding sampler_to_descriptor
[256];
414 struct anv_pipeline_bind_map bind_map
;
416 union brw_any_prog_data prog_data
;
420 anv_pipeline_hash_shader(const struct anv_shader_module
*module
,
421 const char *entrypoint
,
422 gl_shader_stage stage
,
423 const VkSpecializationInfo
*spec_info
,
424 unsigned char *sha1_out
)
426 struct mesa_sha1 ctx
;
427 _mesa_sha1_init(&ctx
);
429 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
430 _mesa_sha1_update(&ctx
, entrypoint
, strlen(entrypoint
));
431 _mesa_sha1_update(&ctx
, &stage
, sizeof(stage
));
433 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
434 spec_info
->mapEntryCount
*
435 sizeof(*spec_info
->pMapEntries
));
436 _mesa_sha1_update(&ctx
, spec_info
->pData
,
437 spec_info
->dataSize
);
440 _mesa_sha1_final(&ctx
, sha1_out
);
444 anv_pipeline_hash_graphics(struct anv_pipeline
*pipeline
,
445 struct anv_pipeline_layout
*layout
,
446 struct anv_pipeline_stage
*stages
,
447 unsigned char *sha1_out
)
449 struct mesa_sha1 ctx
;
450 _mesa_sha1_init(&ctx
);
452 _mesa_sha1_update(&ctx
, &pipeline
->subpass
->view_mask
,
453 sizeof(pipeline
->subpass
->view_mask
));
456 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
458 const bool rba
= pipeline
->device
->robust_buffer_access
;
459 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
461 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
462 if (stages
[s
].entrypoint
) {
463 _mesa_sha1_update(&ctx
, stages
[s
].shader_sha1
,
464 sizeof(stages
[s
].shader_sha1
));
465 _mesa_sha1_update(&ctx
, &stages
[s
].key
, brw_prog_key_size(s
));
469 _mesa_sha1_final(&ctx
, sha1_out
);
473 anv_pipeline_hash_compute(struct anv_pipeline
*pipeline
,
474 struct anv_pipeline_layout
*layout
,
475 struct anv_pipeline_stage
*stage
,
476 unsigned char *sha1_out
)
478 struct mesa_sha1 ctx
;
479 _mesa_sha1_init(&ctx
);
482 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
484 const bool rba
= pipeline
->device
->robust_buffer_access
;
485 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
487 _mesa_sha1_update(&ctx
, stage
->shader_sha1
,
488 sizeof(stage
->shader_sha1
));
489 _mesa_sha1_update(&ctx
, &stage
->key
.cs
, sizeof(stage
->key
.cs
));
491 _mesa_sha1_final(&ctx
, sha1_out
);
495 anv_pipeline_stage_get_nir(struct anv_pipeline
*pipeline
,
496 struct anv_pipeline_cache
*cache
,
498 struct anv_pipeline_stage
*stage
)
500 const struct brw_compiler
*compiler
=
501 pipeline
->device
->instance
->physicalDevice
.compiler
;
502 const nir_shader_compiler_options
*nir_options
=
503 compiler
->glsl_compiler_options
[stage
->stage
].NirOptions
;
506 nir
= anv_device_search_for_nir(pipeline
->device
, cache
,
511 assert(nir
->info
.stage
== stage
->stage
);
515 nir
= anv_shader_compile_to_nir(pipeline
->device
,
522 anv_device_upload_nir(pipeline
->device
, cache
, nir
, stage
->shader_sha1
);
530 anv_pipeline_lower_nir(struct anv_pipeline
*pipeline
,
532 struct anv_pipeline_stage
*stage
,
533 struct anv_pipeline_layout
*layout
)
535 const struct brw_compiler
*compiler
=
536 pipeline
->device
->instance
->physicalDevice
.compiler
;
538 struct brw_stage_prog_data
*prog_data
= &stage
->prog_data
.base
;
539 nir_shader
*nir
= stage
->nir
;
541 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
542 NIR_PASS_V(nir
, nir_lower_wpos_center
, pipeline
->sample_shading_enable
);
543 NIR_PASS_V(nir
, anv_nir_lower_input_attachments
);
546 NIR_PASS_V(nir
, anv_nir_lower_ycbcr_textures
, layout
);
548 NIR_PASS_V(nir
, anv_nir_lower_push_constants
);
550 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
551 NIR_PASS_V(nir
, anv_nir_lower_multiview
, pipeline
->subpass
->view_mask
);
553 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
554 prog_data
->total_shared
= nir
->num_shared
;
556 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
558 if (nir
->num_uniforms
> 0) {
559 assert(prog_data
->nr_params
== 0);
561 /* If the shader uses any push constants at all, we'll just give
562 * them the maximum possible number
564 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
565 nir
->num_uniforms
= MAX_PUSH_CONSTANTS_SIZE
;
566 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
567 prog_data
->param
= ralloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
569 /* We now set the param values to be offsets into a
570 * anv_push_constant_data structure. Since the compiler doesn't
571 * actually dereference any of the gl_constant_value pointers in the
572 * params array, it doesn't really matter what we put here.
574 struct anv_push_constants
*null_data
= NULL
;
575 /* Fill out the push constants section of the param array */
576 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++) {
577 prog_data
->param
[i
] = ANV_PARAM_PUSH(
578 (uintptr_t)&null_data
->client_data
[i
* sizeof(float)]);
582 if (nir
->info
.num_ssbos
> 0 || nir
->info
.num_images
> 0)
583 pipeline
->needs_data_cache
= true;
585 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, compiler
->devinfo
);
587 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
589 anv_nir_apply_pipeline_layout(&pipeline
->device
->instance
->physicalDevice
,
590 pipeline
->device
->robust_buffer_access
,
591 layout
, nir
, prog_data
,
593 NIR_PASS_V(nir
, nir_opt_constant_folding
);
596 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
597 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
599 assert(nir
->num_uniforms
== prog_data
->nr_params
* 4);
605 anv_fill_binding_table(struct brw_stage_prog_data
*prog_data
, unsigned bias
)
607 prog_data
->binding_table
.size_bytes
= 0;
608 prog_data
->binding_table
.texture_start
= bias
;
609 prog_data
->binding_table
.gather_texture_start
= bias
;
610 prog_data
->binding_table
.ubo_start
= bias
;
611 prog_data
->binding_table
.ssbo_start
= bias
;
612 prog_data
->binding_table
.image_start
= bias
;
616 anv_pipeline_link_vs(const struct brw_compiler
*compiler
,
617 struct anv_pipeline_stage
*vs_stage
,
618 struct anv_pipeline_stage
*next_stage
)
620 anv_fill_binding_table(&vs_stage
->prog_data
.vs
.base
.base
, 0);
623 brw_nir_link_shaders(compiler
, &vs_stage
->nir
, &next_stage
->nir
);
626 static const unsigned *
627 anv_pipeline_compile_vs(const struct brw_compiler
*compiler
,
629 struct anv_pipeline_stage
*vs_stage
)
631 brw_compute_vue_map(compiler
->devinfo
,
632 &vs_stage
->prog_data
.vs
.base
.vue_map
,
633 vs_stage
->nir
->info
.outputs_written
,
634 vs_stage
->nir
->info
.separate_shader
);
636 return brw_compile_vs(compiler
, NULL
, mem_ctx
, &vs_stage
->key
.vs
,
637 &vs_stage
->prog_data
.vs
, vs_stage
->nir
, -1, NULL
);
641 merge_tess_info(struct shader_info
*tes_info
,
642 const struct shader_info
*tcs_info
)
644 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
646 * "PointMode. Controls generation of points rather than triangles
647 * or lines. This functionality defaults to disabled, and is
648 * enabled if either shader stage includes the execution mode.
650 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
651 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
652 * and OutputVertices, it says:
654 * "One mode must be set in at least one of the tessellation
657 * So, the fields can be set in either the TCS or TES, but they must
658 * agree if set in both. Our backend looks at TES, so bitwise-or in
659 * the values from the TCS.
661 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
662 tes_info
->tess
.tcs_vertices_out
== 0 ||
663 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
664 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
666 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
667 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
668 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
669 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
671 assert(tcs_info
->tess
.primitive_mode
== 0 ||
672 tes_info
->tess
.primitive_mode
== 0 ||
673 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
674 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
675 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
676 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
680 anv_pipeline_link_tcs(const struct brw_compiler
*compiler
,
681 struct anv_pipeline_stage
*tcs_stage
,
682 struct anv_pipeline_stage
*tes_stage
)
684 assert(tes_stage
&& tes_stage
->stage
== MESA_SHADER_TESS_EVAL
);
686 anv_fill_binding_table(&tcs_stage
->prog_data
.tcs
.base
.base
, 0);
688 brw_nir_link_shaders(compiler
, &tcs_stage
->nir
, &tes_stage
->nir
);
690 nir_lower_patch_vertices(tes_stage
->nir
,
691 tcs_stage
->nir
->info
.tess
.tcs_vertices_out
,
694 /* Copy TCS info into the TES info */
695 merge_tess_info(&tes_stage
->nir
->info
, &tcs_stage
->nir
->info
);
697 anv_fill_binding_table(&tcs_stage
->prog_data
.tcs
.base
.base
, 0);
698 anv_fill_binding_table(&tes_stage
->prog_data
.tes
.base
.base
, 0);
700 /* Whacking the key after cache lookup is a bit sketchy, but all of
701 * this comes from the SPIR-V, which is part of the hash used for the
702 * pipeline cache. So it should be safe.
704 tcs_stage
->key
.tcs
.tes_primitive_mode
=
705 tes_stage
->nir
->info
.tess
.primitive_mode
;
706 tcs_stage
->key
.tcs
.quads_workaround
=
707 compiler
->devinfo
->gen
< 9 &&
708 tes_stage
->nir
->info
.tess
.primitive_mode
== 7 /* GL_QUADS */ &&
709 tes_stage
->nir
->info
.tess
.spacing
== TESS_SPACING_EQUAL
;
712 static const unsigned *
713 anv_pipeline_compile_tcs(const struct brw_compiler
*compiler
,
715 struct anv_pipeline_stage
*tcs_stage
,
716 struct anv_pipeline_stage
*prev_stage
)
718 tcs_stage
->key
.tcs
.outputs_written
=
719 tcs_stage
->nir
->info
.outputs_written
;
720 tcs_stage
->key
.tcs
.patch_outputs_written
=
721 tcs_stage
->nir
->info
.patch_outputs_written
;
723 return brw_compile_tcs(compiler
, NULL
, mem_ctx
, &tcs_stage
->key
.tcs
,
724 &tcs_stage
->prog_data
.tcs
, tcs_stage
->nir
,
729 anv_pipeline_link_tes(const struct brw_compiler
*compiler
,
730 struct anv_pipeline_stage
*tes_stage
,
731 struct anv_pipeline_stage
*next_stage
)
733 anv_fill_binding_table(&tes_stage
->prog_data
.tes
.base
.base
, 0);
736 brw_nir_link_shaders(compiler
, &tes_stage
->nir
, &next_stage
->nir
);
739 static const unsigned *
740 anv_pipeline_compile_tes(const struct brw_compiler
*compiler
,
742 struct anv_pipeline_stage
*tes_stage
,
743 struct anv_pipeline_stage
*tcs_stage
)
745 tes_stage
->key
.tes
.inputs_read
=
746 tcs_stage
->nir
->info
.outputs_written
;
747 tes_stage
->key
.tes
.patch_inputs_read
=
748 tcs_stage
->nir
->info
.patch_outputs_written
;
750 return brw_compile_tes(compiler
, NULL
, mem_ctx
, &tes_stage
->key
.tes
,
751 &tcs_stage
->prog_data
.tcs
.base
.vue_map
,
752 &tes_stage
->prog_data
.tes
, tes_stage
->nir
,
757 anv_pipeline_link_gs(const struct brw_compiler
*compiler
,
758 struct anv_pipeline_stage
*gs_stage
,
759 struct anv_pipeline_stage
*next_stage
)
761 anv_fill_binding_table(&gs_stage
->prog_data
.gs
.base
.base
, 0);
764 brw_nir_link_shaders(compiler
, &gs_stage
->nir
, &next_stage
->nir
);
767 static const unsigned *
768 anv_pipeline_compile_gs(const struct brw_compiler
*compiler
,
770 struct anv_pipeline_stage
*gs_stage
,
771 struct anv_pipeline_stage
*prev_stage
)
773 brw_compute_vue_map(compiler
->devinfo
,
774 &gs_stage
->prog_data
.gs
.base
.vue_map
,
775 gs_stage
->nir
->info
.outputs_written
,
776 gs_stage
->nir
->info
.separate_shader
);
778 return brw_compile_gs(compiler
, NULL
, mem_ctx
, &gs_stage
->key
.gs
,
779 &gs_stage
->prog_data
.gs
, gs_stage
->nir
,
784 anv_pipeline_link_fs(const struct brw_compiler
*compiler
,
785 struct anv_pipeline_stage
*stage
)
787 unsigned num_rts
= 0;
788 const int max_rt
= FRAG_RESULT_DATA7
- FRAG_RESULT_DATA0
+ 1;
789 struct anv_pipeline_binding rt_bindings
[max_rt
];
790 nir_function_impl
*impl
= nir_shader_get_entrypoint(stage
->nir
);
791 int rt_to_bindings
[max_rt
];
792 memset(rt_to_bindings
, -1, sizeof(rt_to_bindings
));
793 bool rt_used
[max_rt
];
794 memset(rt_used
, 0, sizeof(rt_used
));
796 /* Flag used render targets */
797 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
798 if (var
->data
.location
< FRAG_RESULT_DATA0
)
801 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
802 /* Unused or out-of-bounds */
803 if (rt
>= MAX_RTS
|| !(stage
->key
.wm
.color_outputs_valid
& (1 << rt
)))
806 const unsigned array_len
=
807 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
808 assert(rt
+ array_len
<= max_rt
);
810 for (unsigned i
= 0; i
< array_len
; i
++)
811 rt_used
[rt
+ i
] = true;
814 /* Set new, compacted, location */
815 for (unsigned i
= 0; i
< max_rt
; i
++) {
819 rt_to_bindings
[i
] = num_rts
;
820 rt_bindings
[rt_to_bindings
[i
]] = (struct anv_pipeline_binding
) {
821 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
828 bool deleted_output
= false;
829 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
830 if (var
->data
.location
< FRAG_RESULT_DATA0
)
833 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
835 !(stage
->key
.wm
.color_outputs_valid
& (1 << rt
))) {
836 /* Unused or out-of-bounds, throw it away */
837 deleted_output
= true;
838 var
->data
.mode
= nir_var_function_temp
;
839 exec_node_remove(&var
->node
);
840 exec_list_push_tail(&impl
->locals
, &var
->node
);
844 /* Give it the new location */
845 assert(rt_to_bindings
[rt
] != -1);
846 var
->data
.location
= rt_to_bindings
[rt
] + FRAG_RESULT_DATA0
;
850 nir_fixup_deref_modes(stage
->nir
);
853 /* If we have no render targets, we need a null render target */
854 rt_bindings
[0] = (struct anv_pipeline_binding
) {
855 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
862 /* Now that we've determined the actual number of render targets, adjust
863 * the key accordingly.
865 stage
->key
.wm
.nr_color_regions
= num_rts
;
866 stage
->key
.wm
.color_outputs_valid
= (1 << num_rts
) - 1;
868 assert(num_rts
<= max_rt
);
869 assert(stage
->bind_map
.surface_count
== 0);
870 typed_memcpy(stage
->bind_map
.surface_to_descriptor
,
871 rt_bindings
, num_rts
);
872 stage
->bind_map
.surface_count
+= num_rts
;
874 anv_fill_binding_table(&stage
->prog_data
.wm
.base
, 0);
877 static const unsigned *
878 anv_pipeline_compile_fs(const struct brw_compiler
*compiler
,
880 struct anv_pipeline_stage
*fs_stage
,
881 struct anv_pipeline_stage
*prev_stage
)
883 /* TODO: we could set this to 0 based on the information in nir_shader, but
884 * we need this before we call spirv_to_nir.
887 fs_stage
->key
.wm
.input_slots_valid
=
888 prev_stage
->prog_data
.vue
.vue_map
.slots_valid
;
890 const unsigned *code
=
891 brw_compile_fs(compiler
, NULL
, mem_ctx
, &fs_stage
->key
.wm
,
892 &fs_stage
->prog_data
.wm
, fs_stage
->nir
,
893 NULL
, -1, -1, -1, true, false, NULL
, NULL
);
895 if (fs_stage
->key
.wm
.nr_color_regions
== 0 &&
896 !fs_stage
->prog_data
.wm
.has_side_effects
&&
897 !fs_stage
->prog_data
.wm
.uses_kill
&&
898 fs_stage
->prog_data
.wm
.computed_depth_mode
== BRW_PSCDEPTH_OFF
&&
899 !fs_stage
->prog_data
.wm
.computed_stencil
) {
900 /* This fragment shader has no outputs and no side effects. Go ahead
901 * and return the code pointer so we don't accidentally think the
902 * compile failed but zero out prog_data which will set program_size to
903 * zero and disable the stage.
905 memset(&fs_stage
->prog_data
, 0, sizeof(fs_stage
->prog_data
));
912 anv_pipeline_compile_graphics(struct anv_pipeline
*pipeline
,
913 struct anv_pipeline_cache
*cache
,
914 const VkGraphicsPipelineCreateInfo
*info
)
916 const struct brw_compiler
*compiler
=
917 pipeline
->device
->instance
->physicalDevice
.compiler
;
918 struct anv_pipeline_stage stages
[MESA_SHADER_STAGES
] = {};
920 pipeline
->active_stages
= 0;
923 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
924 const VkPipelineShaderStageCreateInfo
*sinfo
= &info
->pStages
[i
];
925 gl_shader_stage stage
= vk_to_mesa_shader_stage(sinfo
->stage
);
927 pipeline
->active_stages
|= sinfo
->stage
;
929 stages
[stage
].stage
= stage
;
930 stages
[stage
].module
= anv_shader_module_from_handle(sinfo
->module
);
931 stages
[stage
].entrypoint
= sinfo
->pName
;
932 stages
[stage
].spec_info
= sinfo
->pSpecializationInfo
;
933 anv_pipeline_hash_shader(stages
[stage
].module
,
934 stages
[stage
].entrypoint
,
936 stages
[stage
].spec_info
,
937 stages
[stage
].shader_sha1
);
939 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
941 case MESA_SHADER_VERTEX
:
942 populate_vs_prog_key(devinfo
, &stages
[stage
].key
.vs
);
944 case MESA_SHADER_TESS_CTRL
:
945 populate_tcs_prog_key(devinfo
,
946 info
->pTessellationState
->patchControlPoints
,
947 &stages
[stage
].key
.tcs
);
949 case MESA_SHADER_TESS_EVAL
:
950 populate_tes_prog_key(devinfo
, &stages
[stage
].key
.tes
);
952 case MESA_SHADER_GEOMETRY
:
953 populate_gs_prog_key(devinfo
, &stages
[stage
].key
.gs
);
955 case MESA_SHADER_FRAGMENT
:
956 populate_wm_prog_key(devinfo
, pipeline
->subpass
,
957 info
->pMultisampleState
,
958 &stages
[stage
].key
.wm
);
961 unreachable("Invalid graphics shader stage");
965 if (pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
)
966 pipeline
->active_stages
|= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
968 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
970 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
972 unsigned char sha1
[20];
973 anv_pipeline_hash_graphics(pipeline
, layout
, stages
, sha1
);
976 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
977 if (!stages
[s
].entrypoint
)
980 stages
[s
].cache_key
.stage
= s
;
981 memcpy(stages
[s
].cache_key
.sha1
, sha1
, sizeof(sha1
));
983 struct anv_shader_bin
*bin
=
984 anv_device_search_for_kernel(pipeline
->device
, cache
,
985 &stages
[s
].cache_key
,
986 sizeof(stages
[s
].cache_key
));
989 pipeline
->shaders
[s
] = bin
;
993 if (found
== __builtin_popcount(pipeline
->active_stages
)) {
994 /* We found all our shaders in the cache. We're done. */
996 } else if (found
> 0) {
997 /* We found some but not all of our shaders. This shouldn't happen
998 * most of the time but it can if we have a partially populated
1001 assert(found
< __builtin_popcount(pipeline
->active_stages
));
1003 vk_debug_report(&pipeline
->device
->instance
->debug_report_callbacks
,
1004 VK_DEBUG_REPORT_WARNING_BIT_EXT
|
1005 VK_DEBUG_REPORT_PERFORMANCE_WARNING_BIT_EXT
,
1006 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT
,
1007 (uint64_t)(uintptr_t)cache
,
1009 "Found a partial pipeline in the cache. This is "
1010 "most likely caused by an incomplete pipeline cache "
1011 "import or export");
1013 /* We're going to have to recompile anyway, so just throw away our
1014 * references to the shaders in the cache. We'll get them out of the
1015 * cache again as part of the compilation process.
1017 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1018 if (pipeline
->shaders
[s
]) {
1019 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1020 pipeline
->shaders
[s
] = NULL
;
1025 void *pipeline_ctx
= ralloc_context(NULL
);
1027 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1028 if (!stages
[s
].entrypoint
)
1031 assert(stages
[s
].stage
== s
);
1032 assert(pipeline
->shaders
[s
] == NULL
);
1034 stages
[s
].bind_map
= (struct anv_pipeline_bind_map
) {
1035 .surface_to_descriptor
= stages
[s
].surface_to_descriptor
,
1036 .sampler_to_descriptor
= stages
[s
].sampler_to_descriptor
1039 stages
[s
].nir
= anv_pipeline_stage_get_nir(pipeline
, cache
,
1042 if (stages
[s
].nir
== NULL
) {
1043 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1048 /* Walk backwards to link */
1049 struct anv_pipeline_stage
*next_stage
= NULL
;
1050 for (int s
= MESA_SHADER_STAGES
- 1; s
>= 0; s
--) {
1051 if (!stages
[s
].entrypoint
)
1055 case MESA_SHADER_VERTEX
:
1056 anv_pipeline_link_vs(compiler
, &stages
[s
], next_stage
);
1058 case MESA_SHADER_TESS_CTRL
:
1059 anv_pipeline_link_tcs(compiler
, &stages
[s
], next_stage
);
1061 case MESA_SHADER_TESS_EVAL
:
1062 anv_pipeline_link_tes(compiler
, &stages
[s
], next_stage
);
1064 case MESA_SHADER_GEOMETRY
:
1065 anv_pipeline_link_gs(compiler
, &stages
[s
], next_stage
);
1067 case MESA_SHADER_FRAGMENT
:
1068 anv_pipeline_link_fs(compiler
, &stages
[s
]);
1071 unreachable("Invalid graphics shader stage");
1074 next_stage
= &stages
[s
];
1077 struct anv_pipeline_stage
*prev_stage
= NULL
;
1078 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1079 if (!stages
[s
].entrypoint
)
1082 void *stage_ctx
= ralloc_context(NULL
);
1084 anv_pipeline_lower_nir(pipeline
, stage_ctx
, &stages
[s
], layout
);
1086 const unsigned *code
;
1088 case MESA_SHADER_VERTEX
:
1089 code
= anv_pipeline_compile_vs(compiler
, stage_ctx
, &stages
[s
]);
1091 case MESA_SHADER_TESS_CTRL
:
1092 code
= anv_pipeline_compile_tcs(compiler
, stage_ctx
,
1093 &stages
[s
], prev_stage
);
1095 case MESA_SHADER_TESS_EVAL
:
1096 code
= anv_pipeline_compile_tes(compiler
, stage_ctx
,
1097 &stages
[s
], prev_stage
);
1099 case MESA_SHADER_GEOMETRY
:
1100 code
= anv_pipeline_compile_gs(compiler
, stage_ctx
,
1101 &stages
[s
], prev_stage
);
1103 case MESA_SHADER_FRAGMENT
:
1104 code
= anv_pipeline_compile_fs(compiler
, stage_ctx
,
1105 &stages
[s
], prev_stage
);
1108 unreachable("Invalid graphics shader stage");
1111 ralloc_free(stage_ctx
);
1112 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1116 struct anv_shader_bin
*bin
=
1117 anv_device_upload_kernel(pipeline
->device
, cache
,
1118 &stages
[s
].cache_key
,
1119 sizeof(stages
[s
].cache_key
),
1120 code
, stages
[s
].prog_data
.base
.program_size
,
1121 stages
[s
].nir
->constant_data
,
1122 stages
[s
].nir
->constant_data_size
,
1123 &stages
[s
].prog_data
.base
,
1124 brw_prog_data_size(s
),
1125 &stages
[s
].bind_map
);
1127 ralloc_free(stage_ctx
);
1128 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1132 pipeline
->shaders
[s
] = bin
;
1133 ralloc_free(stage_ctx
);
1135 prev_stage
= &stages
[s
];
1138 ralloc_free(pipeline_ctx
);
1142 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
] &&
1143 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->prog_data
->program_size
== 0) {
1144 /* This can happen if we decided to implicitly disable the fragment
1145 * shader. See anv_pipeline_compile_fs().
1147 anv_shader_bin_unref(pipeline
->device
,
1148 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
1149 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] = NULL
;
1150 pipeline
->active_stages
&= ~VK_SHADER_STAGE_FRAGMENT_BIT
;
1156 ralloc_free(pipeline_ctx
);
1158 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1159 if (pipeline
->shaders
[s
])
1160 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1167 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1168 struct anv_pipeline_cache
*cache
,
1169 const VkComputePipelineCreateInfo
*info
,
1170 const struct anv_shader_module
*module
,
1171 const char *entrypoint
,
1172 const VkSpecializationInfo
*spec_info
)
1174 const struct brw_compiler
*compiler
=
1175 pipeline
->device
->instance
->physicalDevice
.compiler
;
1177 struct anv_pipeline_stage stage
= {
1178 .stage
= MESA_SHADER_COMPUTE
,
1180 .entrypoint
= entrypoint
,
1181 .spec_info
= spec_info
,
1183 .stage
= MESA_SHADER_COMPUTE
,
1186 anv_pipeline_hash_shader(stage
.module
,
1188 MESA_SHADER_COMPUTE
,
1192 struct anv_shader_bin
*bin
= NULL
;
1194 populate_cs_prog_key(&pipeline
->device
->info
, &stage
.key
.cs
);
1196 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1198 anv_pipeline_hash_compute(pipeline
, layout
, &stage
, stage
.cache_key
.sha1
);
1199 bin
= anv_device_search_for_kernel(pipeline
->device
, cache
, &stage
.cache_key
,
1200 sizeof(stage
.cache_key
));
1203 stage
.bind_map
= (struct anv_pipeline_bind_map
) {
1204 .surface_to_descriptor
= stage
.surface_to_descriptor
,
1205 .sampler_to_descriptor
= stage
.sampler_to_descriptor
1208 void *mem_ctx
= ralloc_context(NULL
);
1210 stage
.nir
= anv_pipeline_stage_get_nir(pipeline
, cache
, mem_ctx
, &stage
);
1211 if (stage
.nir
== NULL
) {
1212 ralloc_free(mem_ctx
);
1213 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1216 anv_pipeline_lower_nir(pipeline
, mem_ctx
, &stage
, layout
);
1218 NIR_PASS_V(stage
.nir
, anv_nir_add_base_work_group_id
,
1219 &stage
.prog_data
.cs
);
1221 anv_fill_binding_table(&stage
.prog_data
.cs
.base
, 1);
1223 const unsigned *shader_code
=
1224 brw_compile_cs(compiler
, NULL
, mem_ctx
, &stage
.key
.cs
,
1225 &stage
.prog_data
.cs
, stage
.nir
, -1, NULL
);
1226 if (shader_code
== NULL
) {
1227 ralloc_free(mem_ctx
);
1228 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1231 const unsigned code_size
= stage
.prog_data
.base
.program_size
;
1232 bin
= anv_device_upload_kernel(pipeline
->device
, cache
,
1233 &stage
.cache_key
, sizeof(stage
.cache_key
),
1234 shader_code
, code_size
,
1235 stage
.nir
->constant_data
,
1236 stage
.nir
->constant_data_size
,
1237 &stage
.prog_data
.base
,
1238 sizeof(stage
.prog_data
.cs
),
1241 ralloc_free(mem_ctx
);
1242 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1245 ralloc_free(mem_ctx
);
1248 pipeline
->active_stages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1249 pipeline
->shaders
[MESA_SHADER_COMPUTE
] = bin
;
1255 * Copy pipeline state not marked as dynamic.
1256 * Dynamic state is pipeline state which hasn't been provided at pipeline
1257 * creation time, but is dynamically provided afterwards using various
1258 * vkCmdSet* functions.
1260 * The set of state considered "non_dynamic" is determined by the pieces of
1261 * state that have their corresponding VkDynamicState enums omitted from
1262 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1264 * @param[out] pipeline Destination non_dynamic state.
1265 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1268 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
1269 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1271 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
1272 struct anv_subpass
*subpass
= pipeline
->subpass
;
1274 pipeline
->dynamic_state
= default_dynamic_state
;
1276 if (pCreateInfo
->pDynamicState
) {
1277 /* Remove all of the states that are marked as dynamic */
1278 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1279 for (uint32_t s
= 0; s
< count
; s
++)
1280 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1283 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1285 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1287 * pViewportState is [...] NULL if the pipeline
1288 * has rasterization disabled.
1290 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1291 assert(pCreateInfo
->pViewportState
);
1293 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1294 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
1295 typed_memcpy(dynamic
->viewport
.viewports
,
1296 pCreateInfo
->pViewportState
->pViewports
,
1297 pCreateInfo
->pViewportState
->viewportCount
);
1300 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1301 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
1302 typed_memcpy(dynamic
->scissor
.scissors
,
1303 pCreateInfo
->pViewportState
->pScissors
,
1304 pCreateInfo
->pViewportState
->scissorCount
);
1308 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1309 assert(pCreateInfo
->pRasterizationState
);
1310 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1313 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1314 assert(pCreateInfo
->pRasterizationState
);
1315 dynamic
->depth_bias
.bias
=
1316 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1317 dynamic
->depth_bias
.clamp
=
1318 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1319 dynamic
->depth_bias
.slope
=
1320 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1323 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1325 * pColorBlendState is [...] NULL if the pipeline has rasterization
1326 * disabled or if the subpass of the render pass the pipeline is
1327 * created against does not use any color attachments.
1329 bool uses_color_att
= false;
1330 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1331 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1332 uses_color_att
= true;
1337 if (uses_color_att
&&
1338 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1339 assert(pCreateInfo
->pColorBlendState
);
1341 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
1342 typed_memcpy(dynamic
->blend_constants
,
1343 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1346 /* If there is no depthstencil attachment, then don't read
1347 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1348 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1349 * no need to override the depthstencil defaults in
1350 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1352 * Section 9.2 of the Vulkan 1.0.15 spec says:
1354 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1355 * disabled or if the subpass of the render pass the pipeline is created
1356 * against does not use a depth/stencil attachment.
1358 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1359 subpass
->depth_stencil_attachment
) {
1360 assert(pCreateInfo
->pDepthStencilState
);
1362 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1363 dynamic
->depth_bounds
.min
=
1364 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1365 dynamic
->depth_bounds
.max
=
1366 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1369 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1370 dynamic
->stencil_compare_mask
.front
=
1371 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1372 dynamic
->stencil_compare_mask
.back
=
1373 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1376 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1377 dynamic
->stencil_write_mask
.front
=
1378 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1379 dynamic
->stencil_write_mask
.back
=
1380 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1383 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1384 dynamic
->stencil_reference
.front
=
1385 pCreateInfo
->pDepthStencilState
->front
.reference
;
1386 dynamic
->stencil_reference
.back
=
1387 pCreateInfo
->pDepthStencilState
->back
.reference
;
1391 pipeline
->dynamic_state_mask
= states
;
1395 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1398 struct anv_render_pass
*renderpass
= NULL
;
1399 struct anv_subpass
*subpass
= NULL
;
1401 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1402 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1404 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1406 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1409 assert(info
->subpass
< renderpass
->subpass_count
);
1410 subpass
= &renderpass
->subpasses
[info
->subpass
];
1412 assert(info
->stageCount
>= 1);
1413 assert(info
->pVertexInputState
);
1414 assert(info
->pInputAssemblyState
);
1415 assert(info
->pRasterizationState
);
1416 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1417 assert(info
->pViewportState
);
1418 assert(info
->pMultisampleState
);
1420 if (subpass
&& subpass
->depth_stencil_attachment
)
1421 assert(info
->pDepthStencilState
);
1423 if (subpass
&& subpass
->color_count
> 0) {
1424 bool all_color_unused
= true;
1425 for (int i
= 0; i
< subpass
->color_count
; i
++) {
1426 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
1427 all_color_unused
= false;
1429 /* pColorBlendState is ignored if the pipeline has rasterization
1430 * disabled or if the subpass of the render pass the pipeline is
1431 * created against does not use any color attachments.
1433 assert(info
->pColorBlendState
|| all_color_unused
);
1437 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1438 switch (info
->pStages
[i
].stage
) {
1439 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1440 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1441 assert(info
->pTessellationState
);
1451 * Calculate the desired L3 partitioning based on the current state of the
1452 * pipeline. For now this simply returns the conservative defaults calculated
1453 * by get_default_l3_weights(), but we could probably do better by gathering
1454 * more statistics from the pipeline state (e.g. guess of expected URB usage
1455 * and bound surfaces), or by using feed-back from performance counters.
1458 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1460 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1462 const struct gen_l3_weights w
=
1463 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
1465 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
1466 pipeline
->urb
.total_size
=
1467 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
1471 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1472 struct anv_device
*device
,
1473 struct anv_pipeline_cache
*cache
,
1474 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1475 const VkAllocationCallbacks
*alloc
)
1479 anv_pipeline_validate_create_info(pCreateInfo
);
1482 alloc
= &device
->alloc
;
1484 pipeline
->device
= device
;
1486 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, pCreateInfo
->renderPass
);
1487 assert(pCreateInfo
->subpass
< render_pass
->subpass_count
);
1488 pipeline
->subpass
= &render_pass
->subpasses
[pCreateInfo
->subpass
];
1490 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1491 if (result
!= VK_SUCCESS
)
1494 pipeline
->batch
.alloc
= alloc
;
1495 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1496 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1497 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1498 pipeline
->batch
.status
= VK_SUCCESS
;
1500 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1501 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1502 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1504 pipeline
->sample_shading_enable
= pCreateInfo
->pMultisampleState
&&
1505 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
1507 pipeline
->needs_data_cache
= false;
1509 /* When we free the pipeline, we detect stages based on the NULL status
1510 * of various prog_data pointers. Make them NULL by default.
1512 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1514 result
= anv_pipeline_compile_graphics(pipeline
, cache
, pCreateInfo
);
1515 if (result
!= VK_SUCCESS
) {
1516 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);
1520 assert(pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1522 anv_pipeline_setup_l3_config(pipeline
, false);
1524 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1525 pCreateInfo
->pVertexInputState
;
1527 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1529 pipeline
->vb_used
= 0;
1530 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1531 const VkVertexInputAttributeDescription
*desc
=
1532 &vi_info
->pVertexAttributeDescriptions
[i
];
1534 if (inputs_read
& (1ull << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1535 pipeline
->vb_used
|= 1 << desc
->binding
;
1538 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1539 const VkVertexInputBindingDescription
*desc
=
1540 &vi_info
->pVertexBindingDescriptions
[i
];
1542 pipeline
->vb
[desc
->binding
].stride
= desc
->stride
;
1544 /* Step rate is programmed per vertex element (attribute), not
1545 * binding. Set up a map of which bindings step per instance, for
1546 * reference by vertex element setup. */
1547 switch (desc
->inputRate
) {
1549 case VK_VERTEX_INPUT_RATE_VERTEX
:
1550 pipeline
->vb
[desc
->binding
].instanced
= false;
1552 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1553 pipeline
->vb
[desc
->binding
].instanced
= true;
1557 pipeline
->vb
[desc
->binding
].instance_divisor
= 1;
1560 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*vi_div_state
=
1561 vk_find_struct_const(vi_info
->pNext
,
1562 PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
1564 for (uint32_t i
= 0; i
< vi_div_state
->vertexBindingDivisorCount
; i
++) {
1565 const VkVertexInputBindingDivisorDescriptionEXT
*desc
=
1566 &vi_div_state
->pVertexBindingDivisors
[i
];
1568 pipeline
->vb
[desc
->binding
].instance_divisor
= desc
->divisor
;
1572 /* Our implementation of VK_KHR_multiview uses instancing to draw the
1573 * different views. If the client asks for instancing, we need to multiply
1574 * the instance divisor by the number of views ensure that we repeat the
1575 * client's per-instance data once for each view.
1577 if (pipeline
->subpass
->view_mask
) {
1578 const uint32_t view_count
= anv_subpass_view_count(pipeline
->subpass
);
1579 for (uint32_t vb
= 0; vb
< MAX_VBS
; vb
++) {
1580 if (pipeline
->vb
[vb
].instanced
)
1581 pipeline
->vb
[vb
].instance_divisor
*= view_count
;
1585 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1586 pCreateInfo
->pInputAssemblyState
;
1587 const VkPipelineTessellationStateCreateInfo
*tess_info
=
1588 pCreateInfo
->pTessellationState
;
1589 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1591 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1592 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
1594 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];