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anv/clear: Handle ClearImage on 3-D images
[mesa.git] / src / intel / vulkan / anv_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "util/mesa-sha1.h"
31 #include "anv_private.h"
32 #include "brw_nir.h"
33 #include "anv_nir.h"
34 #include "spirv/nir_spirv.h"
35
36 /* Needed for SWIZZLE macros */
37 #include "program/prog_instruction.h"
38
39 // Shader functions
40
41 VkResult anv_CreateShaderModule(
42 VkDevice _device,
43 const VkShaderModuleCreateInfo* pCreateInfo,
44 const VkAllocationCallbacks* pAllocator,
45 VkShaderModule* pShaderModule)
46 {
47 ANV_FROM_HANDLE(anv_device, device, _device);
48 struct anv_shader_module *module;
49
50 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
51 assert(pCreateInfo->flags == 0);
52
53 module = anv_alloc2(&device->alloc, pAllocator,
54 sizeof(*module) + pCreateInfo->codeSize, 8,
55 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
56 if (module == NULL)
57 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
58
59 module->nir = NULL;
60 module->size = pCreateInfo->codeSize;
61 memcpy(module->data, pCreateInfo->pCode, module->size);
62
63 _mesa_sha1_compute(module->data, module->size, module->sha1);
64
65 *pShaderModule = anv_shader_module_to_handle(module);
66
67 return VK_SUCCESS;
68 }
69
70 void anv_DestroyShaderModule(
71 VkDevice _device,
72 VkShaderModule _module,
73 const VkAllocationCallbacks* pAllocator)
74 {
75 ANV_FROM_HANDLE(anv_device, device, _device);
76 ANV_FROM_HANDLE(anv_shader_module, module, _module);
77
78 anv_free2(&device->alloc, pAllocator, module);
79 }
80
81 #define SPIR_V_MAGIC_NUMBER 0x07230203
82
83 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
84 * we can't do that yet because we don't have the ability to copy nir.
85 */
86 static nir_shader *
87 anv_shader_compile_to_nir(struct anv_device *device,
88 struct anv_shader_module *module,
89 const char *entrypoint_name,
90 gl_shader_stage stage,
91 const VkSpecializationInfo *spec_info)
92 {
93 if (strcmp(entrypoint_name, "main") != 0) {
94 anv_finishme("Multiple shaders per module not really supported");
95 }
96
97 const struct brw_compiler *compiler =
98 device->instance->physicalDevice.compiler;
99 const nir_shader_compiler_options *nir_options =
100 compiler->glsl_compiler_options[stage].NirOptions;
101
102 nir_shader *nir;
103 nir_function *entry_point;
104 if (module->nir) {
105 /* Some things such as our meta clear/blit code will give us a NIR
106 * shader directly. In that case, we just ignore the SPIR-V entirely
107 * and just use the NIR shader */
108 nir = module->nir;
109 nir->options = nir_options;
110 nir_validate_shader(nir);
111
112 assert(exec_list_length(&nir->functions) == 1);
113 struct exec_node *node = exec_list_get_head(&nir->functions);
114 entry_point = exec_node_data(nir_function, node, node);
115 } else {
116 uint32_t *spirv = (uint32_t *) module->data;
117 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
118 assert(module->size % 4 == 0);
119
120 uint32_t num_spec_entries = 0;
121 struct nir_spirv_specialization *spec_entries = NULL;
122 if (spec_info && spec_info->mapEntryCount > 0) {
123 num_spec_entries = spec_info->mapEntryCount;
124 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
125 for (uint32_t i = 0; i < num_spec_entries; i++) {
126 const uint32_t *data =
127 spec_info->pData + spec_info->pMapEntries[i].offset;
128 assert((const void *)(data + 1) <=
129 spec_info->pData + spec_info->dataSize);
130
131 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
132 spec_entries[i].data = *data;
133 }
134 }
135
136 entry_point = spirv_to_nir(spirv, module->size / 4,
137 spec_entries, num_spec_entries,
138 stage, entrypoint_name, nir_options);
139 nir = entry_point->shader;
140 assert(nir->stage == stage);
141 nir_validate_shader(nir);
142
143 free(spec_entries);
144
145 if (stage == MESA_SHADER_FRAGMENT) {
146 nir_lower_wpos_center(nir);
147 nir_validate_shader(nir);
148 }
149
150 nir_lower_returns(nir);
151 nir_validate_shader(nir);
152
153 nir_inline_functions(nir);
154 nir_validate_shader(nir);
155
156 /* Pick off the single entrypoint that we want */
157 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
158 if (func != entry_point)
159 exec_node_remove(&func->node);
160 }
161 assert(exec_list_length(&nir->functions) == 1);
162 entry_point->name = ralloc_strdup(entry_point, "main");
163
164 nir_remove_dead_variables(nir, nir_var_shader_in);
165 nir_remove_dead_variables(nir, nir_var_shader_out);
166 nir_remove_dead_variables(nir, nir_var_system_value);
167 nir_validate_shader(nir);
168
169 nir_lower_io_to_temporaries(entry_point->shader, entry_point, true, false);
170
171 nir_lower_system_values(nir);
172 nir_validate_shader(nir);
173 }
174
175 /* Vulkan uses the separate-shader linking model */
176 nir->info.separate_shader = true;
177
178 nir = brw_preprocess_nir(compiler, nir);
179
180 nir_shader_gather_info(nir, entry_point->impl);
181
182 nir_variable_mode indirect_mask = 0;
183 if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput)
184 indirect_mask |= nir_var_shader_in;
185 if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
186 indirect_mask |= nir_var_local;
187
188 nir_lower_indirect_derefs(nir, indirect_mask);
189
190 return nir;
191 }
192
193 void anv_DestroyPipeline(
194 VkDevice _device,
195 VkPipeline _pipeline,
196 const VkAllocationCallbacks* pAllocator)
197 {
198 ANV_FROM_HANDLE(anv_device, device, _device);
199 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
200
201 anv_reloc_list_finish(&pipeline->batch_relocs,
202 pAllocator ? pAllocator : &device->alloc);
203 if (pipeline->blend_state.map)
204 anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
205 anv_free2(&device->alloc, pAllocator, pipeline);
206 }
207
208 static const uint32_t vk_to_gen_primitive_type[] = {
209 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
210 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
211 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
212 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
213 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
214 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
215 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
216 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
217 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
218 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
219 /* [VK_PRIMITIVE_TOPOLOGY_PATCH_LIST] = _3DPRIM_PATCHLIST_1 */
220 };
221
222 static void
223 populate_sampler_prog_key(const struct brw_device_info *devinfo,
224 struct brw_sampler_prog_key_data *key)
225 {
226 /* XXX: Handle texture swizzle on HSW- */
227 for (int i = 0; i < MAX_SAMPLERS; i++) {
228 /* Assume color sampler, no swizzling. (Works for BDW+) */
229 key->swizzles[i] = SWIZZLE_XYZW;
230 }
231 }
232
233 static void
234 populate_vs_prog_key(const struct brw_device_info *devinfo,
235 struct brw_vs_prog_key *key)
236 {
237 memset(key, 0, sizeof(*key));
238
239 populate_sampler_prog_key(devinfo, &key->tex);
240
241 /* XXX: Handle vertex input work-arounds */
242
243 /* XXX: Handle sampler_prog_key */
244 }
245
246 static void
247 populate_gs_prog_key(const struct brw_device_info *devinfo,
248 struct brw_gs_prog_key *key)
249 {
250 memset(key, 0, sizeof(*key));
251
252 populate_sampler_prog_key(devinfo, &key->tex);
253 }
254
255 static void
256 populate_wm_prog_key(const struct brw_device_info *devinfo,
257 const VkGraphicsPipelineCreateInfo *info,
258 const struct anv_graphics_pipeline_create_info *extra,
259 struct brw_wm_prog_key *key)
260 {
261 ANV_FROM_HANDLE(anv_render_pass, render_pass, info->renderPass);
262
263 memset(key, 0, sizeof(*key));
264
265 populate_sampler_prog_key(devinfo, &key->tex);
266
267 /* TODO: Fill out key->input_slots_valid */
268
269 /* Vulkan doesn't specify a default */
270 key->high_quality_derivatives = false;
271
272 /* XXX Vulkan doesn't appear to specify */
273 key->clamp_fragment_color = false;
274
275 if (extra && extra->color_attachment_count >= 0) {
276 key->nr_color_regions = extra->color_attachment_count;
277 } else {
278 key->nr_color_regions =
279 render_pass->subpasses[info->subpass].color_count;
280 }
281
282 key->replicate_alpha = key->nr_color_regions > 1 &&
283 info->pMultisampleState &&
284 info->pMultisampleState->alphaToCoverageEnable;
285
286 if (info->pMultisampleState && info->pMultisampleState->rasterizationSamples > 1) {
287 /* We should probably pull this out of the shader, but it's fairly
288 * harmless to compute it and then let dead-code take care of it.
289 */
290 key->persample_interp =
291 (info->pMultisampleState->minSampleShading *
292 info->pMultisampleState->rasterizationSamples) > 1;
293 key->multisample_fbo = true;
294 }
295 }
296
297 static void
298 populate_cs_prog_key(const struct brw_device_info *devinfo,
299 struct brw_cs_prog_key *key)
300 {
301 memset(key, 0, sizeof(*key));
302
303 populate_sampler_prog_key(devinfo, &key->tex);
304 }
305
306 static nir_shader *
307 anv_pipeline_compile(struct anv_pipeline *pipeline,
308 struct anv_shader_module *module,
309 const char *entrypoint,
310 gl_shader_stage stage,
311 const VkSpecializationInfo *spec_info,
312 struct brw_stage_prog_data *prog_data,
313 struct anv_pipeline_bind_map *map)
314 {
315 nir_shader *nir = anv_shader_compile_to_nir(pipeline->device,
316 module, entrypoint, stage,
317 spec_info);
318 if (nir == NULL)
319 return NULL;
320
321 anv_nir_lower_push_constants(nir);
322
323 /* Figure out the number of parameters */
324 prog_data->nr_params = 0;
325
326 if (nir->num_uniforms > 0) {
327 /* If the shader uses any push constants at all, we'll just give
328 * them the maximum possible number
329 */
330 prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
331 }
332
333 if (pipeline->layout && pipeline->layout->stage[stage].has_dynamic_offsets)
334 prog_data->nr_params += MAX_DYNAMIC_BUFFERS * 2;
335
336 if (nir->info.num_images > 0) {
337 prog_data->nr_params += nir->info.num_images * BRW_IMAGE_PARAM_SIZE;
338 pipeline->needs_data_cache = true;
339 }
340
341 if (stage == MESA_SHADER_COMPUTE)
342 ((struct brw_cs_prog_data *)prog_data)->thread_local_id_index =
343 prog_data->nr_params++; /* The CS Thread ID uniform */
344
345 if (nir->info.num_ssbos > 0)
346 pipeline->needs_data_cache = true;
347
348 if (prog_data->nr_params > 0) {
349 /* XXX: I think we're leaking this */
350 prog_data->param = (const union gl_constant_value **)
351 malloc(prog_data->nr_params * sizeof(union gl_constant_value *));
352
353 /* We now set the param values to be offsets into a
354 * anv_push_constant_data structure. Since the compiler doesn't
355 * actually dereference any of the gl_constant_value pointers in the
356 * params array, it doesn't really matter what we put here.
357 */
358 struct anv_push_constants *null_data = NULL;
359 if (nir->num_uniforms > 0) {
360 /* Fill out the push constants section of the param array */
361 for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++)
362 prog_data->param[i] = (const union gl_constant_value *)
363 &null_data->client_data[i * sizeof(float)];
364 }
365 }
366
367 /* Set up dynamic offsets */
368 anv_nir_apply_dynamic_offsets(pipeline, nir, prog_data);
369
370 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
371 if (pipeline->layout)
372 anv_nir_apply_pipeline_layout(pipeline, nir, prog_data, map);
373
374 /* nir_lower_io will only handle the push constants; we need to set this
375 * to the full number of possible uniforms.
376 */
377 nir->num_uniforms = prog_data->nr_params * 4;
378
379 return nir;
380 }
381
382 static void
383 anv_fill_binding_table(struct brw_stage_prog_data *prog_data, unsigned bias)
384 {
385 prog_data->binding_table.size_bytes = 0;
386 prog_data->binding_table.texture_start = bias;
387 prog_data->binding_table.ubo_start = bias;
388 prog_data->binding_table.ssbo_start = bias;
389 prog_data->binding_table.image_start = bias;
390 }
391
392 static void
393 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
394 gl_shader_stage stage,
395 const struct brw_stage_prog_data *prog_data,
396 struct anv_pipeline_bind_map *map)
397 {
398 struct brw_device_info *devinfo = &pipeline->device->info;
399 uint32_t max_threads[] = {
400 [MESA_SHADER_VERTEX] = devinfo->max_vs_threads,
401 [MESA_SHADER_TESS_CTRL] = devinfo->max_hs_threads,
402 [MESA_SHADER_TESS_EVAL] = devinfo->max_ds_threads,
403 [MESA_SHADER_GEOMETRY] = devinfo->max_gs_threads,
404 [MESA_SHADER_FRAGMENT] = devinfo->max_wm_threads,
405 [MESA_SHADER_COMPUTE] = devinfo->max_cs_threads,
406 };
407
408 pipeline->prog_data[stage] = prog_data;
409 pipeline->active_stages |= mesa_to_vk_shader_stage(stage);
410 pipeline->scratch_start[stage] = pipeline->total_scratch;
411 pipeline->total_scratch =
412 align_u32(pipeline->total_scratch, 1024) +
413 prog_data->total_scratch * max_threads[stage];
414 pipeline->bindings[stage] = *map;
415 }
416
417 static VkResult
418 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
419 struct anv_pipeline_cache *cache,
420 const VkGraphicsPipelineCreateInfo *info,
421 struct anv_shader_module *module,
422 const char *entrypoint,
423 const VkSpecializationInfo *spec_info)
424 {
425 const struct brw_compiler *compiler =
426 pipeline->device->instance->physicalDevice.compiler;
427 const struct brw_stage_prog_data *stage_prog_data;
428 struct anv_pipeline_bind_map map;
429 struct brw_vs_prog_key key;
430 uint32_t kernel = NO_KERNEL;
431 unsigned char sha1[20];
432
433 populate_vs_prog_key(&pipeline->device->info, &key);
434
435 if (module->size > 0) {
436 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, spec_info);
437 kernel = anv_pipeline_cache_search(cache, sha1, &stage_prog_data, &map);
438 }
439
440 if (kernel == NO_KERNEL) {
441 struct brw_vs_prog_data prog_data = { 0, };
442 struct anv_pipeline_binding surface_to_descriptor[256];
443 struct anv_pipeline_binding sampler_to_descriptor[256];
444
445 map = (struct anv_pipeline_bind_map) {
446 .surface_to_descriptor = surface_to_descriptor,
447 .sampler_to_descriptor = sampler_to_descriptor
448 };
449
450 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
451 MESA_SHADER_VERTEX, spec_info,
452 &prog_data.base.base, &map);
453 if (nir == NULL)
454 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
455
456 anv_fill_binding_table(&prog_data.base.base, 0);
457
458 void *mem_ctx = ralloc_context(NULL);
459
460 if (module->nir == NULL)
461 ralloc_steal(mem_ctx, nir);
462
463 prog_data.inputs_read = nir->info.inputs_read;
464
465 brw_compute_vue_map(&pipeline->device->info,
466 &prog_data.base.vue_map,
467 nir->info.outputs_written,
468 nir->info.separate_shader);
469
470 unsigned code_size;
471 const unsigned *shader_code =
472 brw_compile_vs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
473 NULL, false, -1, &code_size, NULL);
474 if (shader_code == NULL) {
475 ralloc_free(mem_ctx);
476 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
477 }
478
479 stage_prog_data = &prog_data.base.base;
480 kernel = anv_pipeline_cache_upload_kernel(cache,
481 module->size > 0 ? sha1 : NULL,
482 shader_code, code_size,
483 &stage_prog_data, sizeof(prog_data),
484 &map);
485 ralloc_free(mem_ctx);
486 }
487
488 const struct brw_vs_prog_data *vs_prog_data =
489 (const struct brw_vs_prog_data *) stage_prog_data;
490
491 if (vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8) {
492 pipeline->vs_simd8 = kernel;
493 pipeline->vs_vec4 = NO_KERNEL;
494 } else {
495 pipeline->vs_simd8 = NO_KERNEL;
496 pipeline->vs_vec4 = kernel;
497 }
498
499 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX,
500 stage_prog_data, &map);
501
502 return VK_SUCCESS;
503 }
504
505 static VkResult
506 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
507 struct anv_pipeline_cache *cache,
508 const VkGraphicsPipelineCreateInfo *info,
509 struct anv_shader_module *module,
510 const char *entrypoint,
511 const VkSpecializationInfo *spec_info)
512 {
513 const struct brw_compiler *compiler =
514 pipeline->device->instance->physicalDevice.compiler;
515 const struct brw_stage_prog_data *stage_prog_data;
516 struct anv_pipeline_bind_map map;
517 struct brw_gs_prog_key key;
518 uint32_t kernel = NO_KERNEL;
519 unsigned char sha1[20];
520
521 populate_gs_prog_key(&pipeline->device->info, &key);
522
523 if (module->size > 0) {
524 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, spec_info);
525 kernel = anv_pipeline_cache_search(cache, sha1, &stage_prog_data, &map);
526 }
527
528 if (kernel == NO_KERNEL) {
529 struct brw_gs_prog_data prog_data = { 0, };
530 struct anv_pipeline_binding surface_to_descriptor[256];
531 struct anv_pipeline_binding sampler_to_descriptor[256];
532
533 map = (struct anv_pipeline_bind_map) {
534 .surface_to_descriptor = surface_to_descriptor,
535 .sampler_to_descriptor = sampler_to_descriptor
536 };
537
538 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
539 MESA_SHADER_GEOMETRY, spec_info,
540 &prog_data.base.base, &map);
541 if (nir == NULL)
542 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
543
544 anv_fill_binding_table(&prog_data.base.base, 0);
545
546 void *mem_ctx = ralloc_context(NULL);
547
548 if (module->nir == NULL)
549 ralloc_steal(mem_ctx, nir);
550
551 brw_compute_vue_map(&pipeline->device->info,
552 &prog_data.base.vue_map,
553 nir->info.outputs_written,
554 nir->info.separate_shader);
555
556 unsigned code_size;
557 const unsigned *shader_code =
558 brw_compile_gs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
559 NULL, -1, &code_size, NULL);
560 if (shader_code == NULL) {
561 ralloc_free(mem_ctx);
562 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
563 }
564
565 /* TODO: SIMD8 GS */
566 stage_prog_data = &prog_data.base.base;
567 kernel = anv_pipeline_cache_upload_kernel(cache,
568 module->size > 0 ? sha1 : NULL,
569 shader_code, code_size,
570 &stage_prog_data, sizeof(prog_data),
571 &map);
572
573 ralloc_free(mem_ctx);
574 }
575
576 pipeline->gs_kernel = kernel;
577
578 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY,
579 stage_prog_data, &map);
580
581 return VK_SUCCESS;
582 }
583
584 static VkResult
585 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
586 struct anv_pipeline_cache *cache,
587 const VkGraphicsPipelineCreateInfo *info,
588 const struct anv_graphics_pipeline_create_info *extra,
589 struct anv_shader_module *module,
590 const char *entrypoint,
591 const VkSpecializationInfo *spec_info)
592 {
593 const struct brw_compiler *compiler =
594 pipeline->device->instance->physicalDevice.compiler;
595 const struct brw_stage_prog_data *stage_prog_data;
596 struct anv_pipeline_bind_map map;
597 struct brw_wm_prog_key key;
598 unsigned char sha1[20];
599
600 populate_wm_prog_key(&pipeline->device->info, info, extra, &key);
601
602 if (module->size > 0) {
603 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, spec_info);
604 pipeline->ps_ksp0 =
605 anv_pipeline_cache_search(cache, sha1, &stage_prog_data, &map);
606 }
607
608 if (pipeline->ps_ksp0 == NO_KERNEL) {
609 struct brw_wm_prog_data prog_data = { 0, };
610 struct anv_pipeline_binding surface_to_descriptor[256];
611 struct anv_pipeline_binding sampler_to_descriptor[256];
612
613 map = (struct anv_pipeline_bind_map) {
614 .surface_to_descriptor = surface_to_descriptor + 8,
615 .sampler_to_descriptor = sampler_to_descriptor
616 };
617
618 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
619 MESA_SHADER_FRAGMENT, spec_info,
620 &prog_data.base, &map);
621 if (nir == NULL)
622 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
623
624 unsigned num_rts = 0;
625 struct anv_pipeline_binding rt_bindings[8];
626 nir_function_impl *impl = nir_shader_get_entrypoint(nir)->impl;
627 nir_foreach_variable_safe(var, &nir->outputs) {
628 if (var->data.location < FRAG_RESULT_DATA0)
629 continue;
630
631 unsigned rt = var->data.location - FRAG_RESULT_DATA0;
632 if (rt >= key.nr_color_regions) {
633 /* Out-of-bounds, throw it away */
634 var->data.mode = nir_var_local;
635 exec_node_remove(&var->node);
636 exec_list_push_tail(&impl->locals, &var->node);
637 continue;
638 }
639
640 /* Give it a new, compacted, location */
641 var->data.location = FRAG_RESULT_DATA0 + num_rts;
642
643 unsigned array_len =
644 glsl_type_is_array(var->type) ? glsl_get_length(var->type) : 1;
645 assert(num_rts + array_len <= 8);
646
647 for (unsigned i = 0; i < array_len; i++) {
648 rt_bindings[num_rts] = (struct anv_pipeline_binding) {
649 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
650 .offset = rt + i,
651 };
652 }
653
654 num_rts += array_len;
655 }
656
657 if (pipeline->use_repclear) {
658 assert(num_rts == 1);
659 key.nr_color_regions = 1;
660 }
661
662 if (num_rts == 0) {
663 /* If we have no render targets, we need a null render target */
664 rt_bindings[0] = (struct anv_pipeline_binding) {
665 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
666 .offset = UINT16_MAX,
667 };
668 num_rts = 1;
669 }
670
671 assert(num_rts <= 8);
672 map.surface_to_descriptor -= num_rts;
673 map.surface_count += num_rts;
674 assert(map.surface_count <= 256);
675 memcpy(map.surface_to_descriptor, rt_bindings,
676 num_rts * sizeof(*rt_bindings));
677
678 anv_fill_binding_table(&prog_data.base, num_rts);
679
680 void *mem_ctx = ralloc_context(NULL);
681
682 if (module->nir == NULL)
683 ralloc_steal(mem_ctx, nir);
684
685 unsigned code_size;
686 const unsigned *shader_code =
687 brw_compile_fs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
688 NULL, -1, -1, true, pipeline->use_repclear,
689 &code_size, NULL);
690 if (shader_code == NULL) {
691 ralloc_free(mem_ctx);
692 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
693 }
694
695 stage_prog_data = &prog_data.base;
696 pipeline->ps_ksp0 =
697 anv_pipeline_cache_upload_kernel(cache,
698 module->size > 0 ? sha1 : NULL,
699 shader_code, code_size,
700 &stage_prog_data, sizeof(prog_data),
701 &map);
702
703 ralloc_free(mem_ctx);
704 }
705
706 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT,
707 stage_prog_data, &map);
708
709 return VK_SUCCESS;
710 }
711
712 VkResult
713 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
714 struct anv_pipeline_cache *cache,
715 const VkComputePipelineCreateInfo *info,
716 struct anv_shader_module *module,
717 const char *entrypoint,
718 const VkSpecializationInfo *spec_info)
719 {
720 const struct brw_compiler *compiler =
721 pipeline->device->instance->physicalDevice.compiler;
722 const struct brw_stage_prog_data *stage_prog_data;
723 struct anv_pipeline_bind_map map;
724 struct brw_cs_prog_key key;
725 uint32_t kernel = NO_KERNEL;
726 unsigned char sha1[20];
727
728 populate_cs_prog_key(&pipeline->device->info, &key);
729
730 if (module->size > 0) {
731 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, spec_info);
732 kernel = anv_pipeline_cache_search(cache, sha1, &stage_prog_data, &map);
733 }
734
735 if (module->size == 0 || kernel == NO_KERNEL) {
736 struct brw_cs_prog_data prog_data = { 0, };
737 struct anv_pipeline_binding surface_to_descriptor[256];
738 struct anv_pipeline_binding sampler_to_descriptor[256];
739
740 map = (struct anv_pipeline_bind_map) {
741 .surface_to_descriptor = surface_to_descriptor,
742 .sampler_to_descriptor = sampler_to_descriptor
743 };
744
745 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
746 MESA_SHADER_COMPUTE, spec_info,
747 &prog_data.base, &map);
748 if (nir == NULL)
749 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
750
751 anv_fill_binding_table(&prog_data.base, 1);
752
753 void *mem_ctx = ralloc_context(NULL);
754
755 if (module->nir == NULL)
756 ralloc_steal(mem_ctx, nir);
757
758 unsigned code_size;
759 const unsigned *shader_code =
760 brw_compile_cs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
761 -1, &code_size, NULL);
762 if (shader_code == NULL) {
763 ralloc_free(mem_ctx);
764 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
765 }
766
767 stage_prog_data = &prog_data.base;
768 kernel = anv_pipeline_cache_upload_kernel(cache,
769 module->size > 0 ? sha1 : NULL,
770 shader_code, code_size,
771 &stage_prog_data, sizeof(prog_data),
772 &map);
773
774 ralloc_free(mem_ctx);
775 }
776
777 pipeline->cs_simd = kernel;
778
779 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE,
780 stage_prog_data, &map);
781
782 return VK_SUCCESS;
783 }
784
785
786 void
787 anv_setup_pipeline_l3_config(struct anv_pipeline *pipeline)
788 {
789 const struct brw_device_info *devinfo = &pipeline->device->info;
790 switch (devinfo->gen) {
791 case 7:
792 if (devinfo->is_haswell)
793 gen75_setup_pipeline_l3_config(pipeline);
794 else
795 gen7_setup_pipeline_l3_config(pipeline);
796 break;
797 case 8:
798 gen8_setup_pipeline_l3_config(pipeline);
799 break;
800 case 9:
801 gen9_setup_pipeline_l3_config(pipeline);
802 break;
803 default:
804 unreachable("unsupported gen\n");
805 }
806 }
807
808 void
809 anv_compute_urb_partition(struct anv_pipeline *pipeline)
810 {
811 const struct brw_device_info *devinfo = &pipeline->device->info;
812
813 bool vs_present = pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT;
814 unsigned vs_size = vs_present ?
815 get_vs_prog_data(pipeline)->base.urb_entry_size : 1;
816 unsigned vs_entry_size_bytes = vs_size * 64;
817 bool gs_present = pipeline->active_stages & VK_SHADER_STAGE_GEOMETRY_BIT;
818 unsigned gs_size = gs_present ?
819 get_gs_prog_data(pipeline)->base.urb_entry_size : 1;
820 unsigned gs_entry_size_bytes = gs_size * 64;
821
822 /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
823 *
824 * VS Number of URB Entries must be divisible by 8 if the VS URB Entry
825 * Allocation Size is less than 9 512-bit URB entries.
826 *
827 * Similar text exists for GS.
828 */
829 unsigned vs_granularity = (vs_size < 9) ? 8 : 1;
830 unsigned gs_granularity = (gs_size < 9) ? 8 : 1;
831
832 /* URB allocations must be done in 8k chunks. */
833 unsigned chunk_size_bytes = 8192;
834
835 /* Determine the size of the URB in chunks. */
836 unsigned urb_chunks = pipeline->urb.total_size * 1024 / chunk_size_bytes;
837
838 /* Reserve space for push constants */
839 unsigned push_constant_kb;
840 if (pipeline->device->info.gen >= 8)
841 push_constant_kb = 32;
842 else if (pipeline->device->info.is_haswell)
843 push_constant_kb = pipeline->device->info.gt == 3 ? 32 : 16;
844 else
845 push_constant_kb = 16;
846
847 unsigned push_constant_bytes = push_constant_kb * 1024;
848 unsigned push_constant_chunks =
849 push_constant_bytes / chunk_size_bytes;
850
851 /* Initially, assign each stage the minimum amount of URB space it needs,
852 * and make a note of how much additional space it "wants" (the amount of
853 * additional space it could actually make use of).
854 */
855
856 /* VS has a lower limit on the number of URB entries */
857 unsigned vs_chunks =
858 ALIGN(devinfo->urb.min_vs_entries * vs_entry_size_bytes,
859 chunk_size_bytes) / chunk_size_bytes;
860 unsigned vs_wants =
861 ALIGN(devinfo->urb.max_vs_entries * vs_entry_size_bytes,
862 chunk_size_bytes) / chunk_size_bytes - vs_chunks;
863
864 unsigned gs_chunks = 0;
865 unsigned gs_wants = 0;
866 if (gs_present) {
867 /* There are two constraints on the minimum amount of URB space we can
868 * allocate:
869 *
870 * (1) We need room for at least 2 URB entries, since we always operate
871 * the GS in DUAL_OBJECT mode.
872 *
873 * (2) We can't allocate less than nr_gs_entries_granularity.
874 */
875 gs_chunks = ALIGN(MAX2(gs_granularity, 2) * gs_entry_size_bytes,
876 chunk_size_bytes) / chunk_size_bytes;
877 gs_wants =
878 ALIGN(devinfo->urb.max_gs_entries * gs_entry_size_bytes,
879 chunk_size_bytes) / chunk_size_bytes - gs_chunks;
880 }
881
882 /* There should always be enough URB space to satisfy the minimum
883 * requirements of each stage.
884 */
885 unsigned total_needs = push_constant_chunks + vs_chunks + gs_chunks;
886 assert(total_needs <= urb_chunks);
887
888 /* Mete out remaining space (if any) in proportion to "wants". */
889 unsigned total_wants = vs_wants + gs_wants;
890 unsigned remaining_space = urb_chunks - total_needs;
891 if (remaining_space > total_wants)
892 remaining_space = total_wants;
893 if (remaining_space > 0) {
894 unsigned vs_additional = (unsigned)
895 round(vs_wants * (((double) remaining_space) / total_wants));
896 vs_chunks += vs_additional;
897 remaining_space -= vs_additional;
898 gs_chunks += remaining_space;
899 }
900
901 /* Sanity check that we haven't over-allocated. */
902 assert(push_constant_chunks + vs_chunks + gs_chunks <= urb_chunks);
903
904 /* Finally, compute the number of entries that can fit in the space
905 * allocated to each stage.
906 */
907 unsigned nr_vs_entries = vs_chunks * chunk_size_bytes / vs_entry_size_bytes;
908 unsigned nr_gs_entries = gs_chunks * chunk_size_bytes / gs_entry_size_bytes;
909
910 /* Since we rounded up when computing *_wants, this may be slightly more
911 * than the maximum allowed amount, so correct for that.
912 */
913 nr_vs_entries = MIN2(nr_vs_entries, devinfo->urb.max_vs_entries);
914 nr_gs_entries = MIN2(nr_gs_entries, devinfo->urb.max_gs_entries);
915
916 /* Ensure that we program a multiple of the granularity. */
917 nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, vs_granularity);
918 nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, gs_granularity);
919
920 /* Finally, sanity check to make sure we have at least the minimum number
921 * of entries needed for each stage.
922 */
923 assert(nr_vs_entries >= devinfo->urb.min_vs_entries);
924 if (gs_present)
925 assert(nr_gs_entries >= 2);
926
927 /* Lay out the URB in the following order:
928 * - push constants
929 * - VS
930 * - GS
931 */
932 pipeline->urb.start[MESA_SHADER_VERTEX] = push_constant_chunks;
933 pipeline->urb.size[MESA_SHADER_VERTEX] = vs_size;
934 pipeline->urb.entries[MESA_SHADER_VERTEX] = nr_vs_entries;
935
936 pipeline->urb.start[MESA_SHADER_GEOMETRY] = push_constant_chunks + vs_chunks;
937 pipeline->urb.size[MESA_SHADER_GEOMETRY] = gs_size;
938 pipeline->urb.entries[MESA_SHADER_GEOMETRY] = nr_gs_entries;
939
940 pipeline->urb.start[MESA_SHADER_TESS_CTRL] = push_constant_chunks;
941 pipeline->urb.size[MESA_SHADER_TESS_CTRL] = 1;
942 pipeline->urb.entries[MESA_SHADER_TESS_CTRL] = 0;
943
944 pipeline->urb.start[MESA_SHADER_TESS_EVAL] = push_constant_chunks;
945 pipeline->urb.size[MESA_SHADER_TESS_EVAL] = 1;
946 pipeline->urb.entries[MESA_SHADER_TESS_EVAL] = 0;
947 }
948
949 static void
950 anv_pipeline_init_dynamic_state(struct anv_pipeline *pipeline,
951 const VkGraphicsPipelineCreateInfo *pCreateInfo)
952 {
953 anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
954 ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
955 struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
956
957 pipeline->dynamic_state = default_dynamic_state;
958
959 if (pCreateInfo->pDynamicState) {
960 /* Remove all of the states that are marked as dynamic */
961 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
962 for (uint32_t s = 0; s < count; s++)
963 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
964 }
965
966 struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
967
968 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
969 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
970 typed_memcpy(dynamic->viewport.viewports,
971 pCreateInfo->pViewportState->pViewports,
972 pCreateInfo->pViewportState->viewportCount);
973 }
974
975 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
976 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
977 typed_memcpy(dynamic->scissor.scissors,
978 pCreateInfo->pViewportState->pScissors,
979 pCreateInfo->pViewportState->scissorCount);
980 }
981
982 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
983 assert(pCreateInfo->pRasterizationState);
984 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
985 }
986
987 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
988 assert(pCreateInfo->pRasterizationState);
989 dynamic->depth_bias.bias =
990 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
991 dynamic->depth_bias.clamp =
992 pCreateInfo->pRasterizationState->depthBiasClamp;
993 dynamic->depth_bias.slope =
994 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
995 }
996
997 if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
998 assert(pCreateInfo->pColorBlendState);
999 typed_memcpy(dynamic->blend_constants,
1000 pCreateInfo->pColorBlendState->blendConstants, 4);
1001 }
1002
1003 /* If there is no depthstencil attachment, then don't read
1004 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1005 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1006 * no need to override the depthstencil defaults in
1007 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1008 *
1009 * From the Vulkan spec (20 Oct 2015, git-aa308cb):
1010 *
1011 * pDepthStencilState [...] may only be NULL if renderPass and subpass
1012 * specify a subpass that has no depth/stencil attachment.
1013 */
1014 if (subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
1015 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1016 assert(pCreateInfo->pDepthStencilState);
1017 dynamic->depth_bounds.min =
1018 pCreateInfo->pDepthStencilState->minDepthBounds;
1019 dynamic->depth_bounds.max =
1020 pCreateInfo->pDepthStencilState->maxDepthBounds;
1021 }
1022
1023 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1024 assert(pCreateInfo->pDepthStencilState);
1025 dynamic->stencil_compare_mask.front =
1026 pCreateInfo->pDepthStencilState->front.compareMask;
1027 dynamic->stencil_compare_mask.back =
1028 pCreateInfo->pDepthStencilState->back.compareMask;
1029 }
1030
1031 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1032 assert(pCreateInfo->pDepthStencilState);
1033 dynamic->stencil_write_mask.front =
1034 pCreateInfo->pDepthStencilState->front.writeMask;
1035 dynamic->stencil_write_mask.back =
1036 pCreateInfo->pDepthStencilState->back.writeMask;
1037 }
1038
1039 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1040 assert(pCreateInfo->pDepthStencilState);
1041 dynamic->stencil_reference.front =
1042 pCreateInfo->pDepthStencilState->front.reference;
1043 dynamic->stencil_reference.back =
1044 pCreateInfo->pDepthStencilState->back.reference;
1045 }
1046 }
1047
1048 pipeline->dynamic_state_mask = states;
1049 }
1050
1051 static void
1052 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
1053 {
1054 struct anv_render_pass *renderpass = NULL;
1055 struct anv_subpass *subpass = NULL;
1056
1057 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1058 * present, as explained by the Vulkan (20 Oct 2015, git-aa308cb), Section
1059 * 4.2 Graphics Pipeline.
1060 */
1061 assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
1062
1063 renderpass = anv_render_pass_from_handle(info->renderPass);
1064 assert(renderpass);
1065
1066 if (renderpass != &anv_meta_dummy_renderpass) {
1067 assert(info->subpass < renderpass->subpass_count);
1068 subpass = &renderpass->subpasses[info->subpass];
1069 }
1070
1071 assert(info->stageCount >= 1);
1072 assert(info->pVertexInputState);
1073 assert(info->pInputAssemblyState);
1074 assert(info->pViewportState);
1075 assert(info->pRasterizationState);
1076
1077 if (subpass && subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED)
1078 assert(info->pDepthStencilState);
1079
1080 if (subpass && subpass->color_count > 0)
1081 assert(info->pColorBlendState);
1082
1083 for (uint32_t i = 0; i < info->stageCount; ++i) {
1084 switch (info->pStages[i].stage) {
1085 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
1086 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
1087 assert(info->pTessellationState);
1088 break;
1089 default:
1090 break;
1091 }
1092 }
1093 }
1094
1095 VkResult
1096 anv_pipeline_init(struct anv_pipeline *pipeline,
1097 struct anv_device *device,
1098 struct anv_pipeline_cache *cache,
1099 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1100 const struct anv_graphics_pipeline_create_info *extra,
1101 const VkAllocationCallbacks *alloc)
1102 {
1103 VkResult result;
1104
1105 anv_validate {
1106 anv_pipeline_validate_create_info(pCreateInfo);
1107 }
1108
1109 if (alloc == NULL)
1110 alloc = &device->alloc;
1111
1112 pipeline->device = device;
1113 pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
1114
1115 result = anv_reloc_list_init(&pipeline->batch_relocs, alloc);
1116 if (result != VK_SUCCESS)
1117 return result;
1118
1119 pipeline->batch.alloc = alloc;
1120 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
1121 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
1122 pipeline->batch.relocs = &pipeline->batch_relocs;
1123
1124 anv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1125
1126 pipeline->use_repclear = extra && extra->use_repclear;
1127
1128 pipeline->needs_data_cache = false;
1129
1130 /* When we free the pipeline, we detect stages based on the NULL status
1131 * of various prog_data pointers. Make them NULL by default.
1132 */
1133 memset(pipeline->prog_data, 0, sizeof(pipeline->prog_data));
1134 memset(pipeline->scratch_start, 0, sizeof(pipeline->scratch_start));
1135 memset(pipeline->bindings, 0, sizeof(pipeline->bindings));
1136
1137 pipeline->vs_simd8 = NO_KERNEL;
1138 pipeline->vs_vec4 = NO_KERNEL;
1139 pipeline->gs_kernel = NO_KERNEL;
1140 pipeline->ps_ksp0 = NO_KERNEL;
1141
1142 pipeline->active_stages = 0;
1143 pipeline->total_scratch = 0;
1144
1145 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1146 struct anv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1147 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1148 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1149 pStages[stage] = &pCreateInfo->pStages[i];
1150 modules[stage] = anv_shader_module_from_handle(pStages[stage]->module);
1151 }
1152
1153 if (modules[MESA_SHADER_VERTEX]) {
1154 anv_pipeline_compile_vs(pipeline, cache, pCreateInfo,
1155 modules[MESA_SHADER_VERTEX],
1156 pStages[MESA_SHADER_VERTEX]->pName,
1157 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo);
1158 }
1159
1160 if (modules[MESA_SHADER_TESS_CTRL] || modules[MESA_SHADER_TESS_EVAL])
1161 anv_finishme("no tessellation support");
1162
1163 if (modules[MESA_SHADER_GEOMETRY]) {
1164 anv_pipeline_compile_gs(pipeline, cache, pCreateInfo,
1165 modules[MESA_SHADER_GEOMETRY],
1166 pStages[MESA_SHADER_GEOMETRY]->pName,
1167 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo);
1168 }
1169
1170 if (modules[MESA_SHADER_FRAGMENT]) {
1171 anv_pipeline_compile_fs(pipeline, cache, pCreateInfo, extra,
1172 modules[MESA_SHADER_FRAGMENT],
1173 pStages[MESA_SHADER_FRAGMENT]->pName,
1174 pStages[MESA_SHADER_FRAGMENT]->pSpecializationInfo);
1175 }
1176
1177 if (!(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT)) {
1178 /* Vertex is only optional if disable_vs is set */
1179 assert(extra->disable_vs);
1180 }
1181
1182 anv_setup_pipeline_l3_config(pipeline);
1183 anv_compute_urb_partition(pipeline);
1184
1185 const VkPipelineVertexInputStateCreateInfo *vi_info =
1186 pCreateInfo->pVertexInputState;
1187
1188 uint64_t inputs_read;
1189 if (extra && extra->disable_vs) {
1190 /* If the VS is disabled, just assume the user knows what they're
1191 * doing and apply the layout blindly. This can only come from
1192 * meta, so this *should* be safe.
1193 */
1194 inputs_read = ~0ull;
1195 } else {
1196 inputs_read = get_vs_prog_data(pipeline)->inputs_read;
1197 }
1198
1199 pipeline->vb_used = 0;
1200 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1201 const VkVertexInputAttributeDescription *desc =
1202 &vi_info->pVertexAttributeDescriptions[i];
1203
1204 if (inputs_read & (1 << (VERT_ATTRIB_GENERIC0 + desc->location)))
1205 pipeline->vb_used |= 1 << desc->binding;
1206 }
1207
1208 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1209 const VkVertexInputBindingDescription *desc =
1210 &vi_info->pVertexBindingDescriptions[i];
1211
1212 pipeline->binding_stride[desc->binding] = desc->stride;
1213
1214 /* Step rate is programmed per vertex element (attribute), not
1215 * binding. Set up a map of which bindings step per instance, for
1216 * reference by vertex element setup. */
1217 switch (desc->inputRate) {
1218 default:
1219 case VK_VERTEX_INPUT_RATE_VERTEX:
1220 pipeline->instancing_enable[desc->binding] = false;
1221 break;
1222 case VK_VERTEX_INPUT_RATE_INSTANCE:
1223 pipeline->instancing_enable[desc->binding] = true;
1224 break;
1225 }
1226 }
1227
1228 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1229 pCreateInfo->pInputAssemblyState;
1230 pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1231 pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1232
1233 if (extra && extra->use_rectlist)
1234 pipeline->topology = _3DPRIM_RECTLIST;
1235
1236 while (anv_block_pool_size(&device->scratch_block_pool) <
1237 pipeline->total_scratch)
1238 anv_block_pool_alloc(&device->scratch_block_pool);
1239
1240 return VK_SUCCESS;
1241 }
1242
1243 VkResult
1244 anv_graphics_pipeline_create(
1245 VkDevice _device,
1246 VkPipelineCache _cache,
1247 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1248 const struct anv_graphics_pipeline_create_info *extra,
1249 const VkAllocationCallbacks *pAllocator,
1250 VkPipeline *pPipeline)
1251 {
1252 ANV_FROM_HANDLE(anv_device, device, _device);
1253 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
1254
1255 if (cache == NULL)
1256 cache = &device->default_pipeline_cache;
1257
1258 switch (device->info.gen) {
1259 case 7:
1260 if (device->info.is_haswell)
1261 return gen75_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1262 else
1263 return gen7_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1264 case 8:
1265 return gen8_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1266 case 9:
1267 return gen9_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1268 default:
1269 unreachable("unsupported gen\n");
1270 }
1271 }
1272
1273 VkResult anv_CreateGraphicsPipelines(
1274 VkDevice _device,
1275 VkPipelineCache pipelineCache,
1276 uint32_t count,
1277 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1278 const VkAllocationCallbacks* pAllocator,
1279 VkPipeline* pPipelines)
1280 {
1281 VkResult result = VK_SUCCESS;
1282
1283 unsigned i = 0;
1284 for (; i < count; i++) {
1285 result = anv_graphics_pipeline_create(_device,
1286 pipelineCache,
1287 &pCreateInfos[i],
1288 NULL, pAllocator, &pPipelines[i]);
1289 if (result != VK_SUCCESS) {
1290 for (unsigned j = 0; j < i; j++) {
1291 anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1292 }
1293
1294 return result;
1295 }
1296 }
1297
1298 return VK_SUCCESS;
1299 }
1300
1301 static VkResult anv_compute_pipeline_create(
1302 VkDevice _device,
1303 VkPipelineCache _cache,
1304 const VkComputePipelineCreateInfo* pCreateInfo,
1305 const VkAllocationCallbacks* pAllocator,
1306 VkPipeline* pPipeline)
1307 {
1308 ANV_FROM_HANDLE(anv_device, device, _device);
1309 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
1310
1311 if (cache == NULL)
1312 cache = &device->default_pipeline_cache;
1313
1314 switch (device->info.gen) {
1315 case 7:
1316 if (device->info.is_haswell)
1317 return gen75_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1318 else
1319 return gen7_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1320 case 8:
1321 return gen8_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1322 case 9:
1323 return gen9_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1324 default:
1325 unreachable("unsupported gen\n");
1326 }
1327 }
1328
1329 VkResult anv_CreateComputePipelines(
1330 VkDevice _device,
1331 VkPipelineCache pipelineCache,
1332 uint32_t count,
1333 const VkComputePipelineCreateInfo* pCreateInfos,
1334 const VkAllocationCallbacks* pAllocator,
1335 VkPipeline* pPipelines)
1336 {
1337 VkResult result = VK_SUCCESS;
1338
1339 unsigned i = 0;
1340 for (; i < count; i++) {
1341 result = anv_compute_pipeline_create(_device, pipelineCache,
1342 &pCreateInfos[i],
1343 pAllocator, &pPipelines[i]);
1344 if (result != VK_SUCCESS) {
1345 for (unsigned j = 0; j < i; j++) {
1346 anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1347 }
1348
1349 return result;
1350 }
1351 }
1352
1353 return VK_SUCCESS;
1354 }