2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "common/gen_l3_config.h"
32 #include "anv_private.h"
33 #include "compiler/brw_nir.h"
35 #include "spirv/nir_spirv.h"
37 /* Needed for SWIZZLE macros */
38 #include "program/prog_instruction.h"
42 VkResult
anv_CreateShaderModule(
44 const VkShaderModuleCreateInfo
* pCreateInfo
,
45 const VkAllocationCallbacks
* pAllocator
,
46 VkShaderModule
* pShaderModule
)
48 ANV_FROM_HANDLE(anv_device
, device
, _device
);
49 struct anv_shader_module
*module
;
51 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
52 assert(pCreateInfo
->flags
== 0);
54 module
= vk_alloc2(&device
->alloc
, pAllocator
,
55 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
56 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
58 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
60 module
->size
= pCreateInfo
->codeSize
;
61 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
63 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
65 *pShaderModule
= anv_shader_module_to_handle(module
);
70 void anv_DestroyShaderModule(
72 VkShaderModule _module
,
73 const VkAllocationCallbacks
* pAllocator
)
75 ANV_FROM_HANDLE(anv_device
, device
, _device
);
76 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
81 vk_free2(&device
->alloc
, pAllocator
, module
);
84 #define SPIR_V_MAGIC_NUMBER 0x07230203
86 static const uint64_t stage_to_debug
[] = {
87 [MESA_SHADER_VERTEX
] = DEBUG_VS
,
88 [MESA_SHADER_TESS_CTRL
] = DEBUG_TCS
,
89 [MESA_SHADER_TESS_EVAL
] = DEBUG_TES
,
90 [MESA_SHADER_GEOMETRY
] = DEBUG_GS
,
91 [MESA_SHADER_FRAGMENT
] = DEBUG_WM
,
92 [MESA_SHADER_COMPUTE
] = DEBUG_CS
,
95 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
96 * we can't do that yet because we don't have the ability to copy nir.
99 anv_shader_compile_to_nir(struct anv_pipeline
*pipeline
,
101 struct anv_shader_module
*module
,
102 const char *entrypoint_name
,
103 gl_shader_stage stage
,
104 const VkSpecializationInfo
*spec_info
)
106 const struct anv_device
*device
= pipeline
->device
;
108 const struct brw_compiler
*compiler
=
109 device
->instance
->physicalDevice
.compiler
;
110 const nir_shader_compiler_options
*nir_options
=
111 compiler
->glsl_compiler_options
[stage
].NirOptions
;
113 uint32_t *spirv
= (uint32_t *) module
->data
;
114 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
115 assert(module
->size
% 4 == 0);
117 uint32_t num_spec_entries
= 0;
118 struct nir_spirv_specialization
*spec_entries
= NULL
;
119 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
120 num_spec_entries
= spec_info
->mapEntryCount
;
121 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
122 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
123 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
124 const void *data
= spec_info
->pData
+ entry
.offset
;
125 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
127 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
128 if (spec_info
->dataSize
== 8)
129 spec_entries
[i
].data64
= *(const uint64_t *)data
;
131 spec_entries
[i
].data32
= *(const uint32_t *)data
;
135 struct spirv_to_nir_options spirv_options
= {
136 .lower_workgroup_access_to_offsets
= true,
138 .float64
= device
->instance
->physicalDevice
.info
.gen
>= 8,
139 .int64
= device
->instance
->physicalDevice
.info
.gen
>= 8,
140 .tessellation
= true,
141 .device_group
= true,
142 .draw_parameters
= true,
143 .image_write_without_format
= true,
145 .variable_pointers
= true,
146 .storage_16bit
= device
->instance
->physicalDevice
.info
.gen
>= 8,
147 .int16
= device
->instance
->physicalDevice
.info
.gen
>= 8,
148 .shader_viewport_index_layer
= true,
149 .subgroup_arithmetic
= true,
150 .subgroup_basic
= true,
151 .subgroup_ballot
= true,
152 .subgroup_quad
= true,
153 .subgroup_shuffle
= true,
154 .subgroup_vote
= true,
155 .stencil_export
= device
->instance
->physicalDevice
.info
.gen
>= 9,
159 nir_function
*entry_point
=
160 spirv_to_nir(spirv
, module
->size
/ 4,
161 spec_entries
, num_spec_entries
,
162 stage
, entrypoint_name
, &spirv_options
, nir_options
);
163 nir_shader
*nir
= entry_point
->shader
;
164 assert(nir
->info
.stage
== stage
);
165 nir_validate_shader(nir
);
166 ralloc_steal(mem_ctx
, nir
);
170 if (unlikely(INTEL_DEBUG
& stage_to_debug
[stage
])) {
171 fprintf(stderr
, "NIR (from SPIR-V) for %s shader:\n",
172 gl_shader_stage_name(stage
));
173 nir_print_shader(nir
, stderr
);
176 /* We have to lower away local constant initializers right before we
177 * inline functions. That way they get properly initialized at the top
178 * of the function and not at the top of its caller.
180 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_local
);
181 NIR_PASS_V(nir
, nir_lower_returns
);
182 NIR_PASS_V(nir
, nir_inline_functions
);
183 NIR_PASS_V(nir
, nir_copy_prop
);
185 /* Pick off the single entrypoint that we want */
186 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
187 if (func
!= entry_point
)
188 exec_node_remove(&func
->node
);
190 assert(exec_list_length(&nir
->functions
) == 1);
191 entry_point
->name
= ralloc_strdup(entry_point
, "main");
193 /* Now that we've deleted all but the main function, we can go ahead and
194 * lower the rest of the constant initializers. We do this here so that
195 * nir_remove_dead_variables and split_per_member_structs below see the
196 * corresponding stores.
198 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
200 /* Split member structs. We do this before lower_io_to_temporaries so that
201 * it doesn't lower system values to temporaries by accident.
203 NIR_PASS_V(nir
, nir_split_var_copies
);
204 NIR_PASS_V(nir
, nir_split_per_member_structs
);
206 NIR_PASS_V(nir
, nir_remove_dead_variables
,
207 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
209 if (stage
== MESA_SHADER_FRAGMENT
)
210 NIR_PASS_V(nir
, nir_lower_wpos_center
, pipeline
->sample_shading_enable
);
212 NIR_PASS_V(nir
, nir_propagate_invariant
);
213 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
214 entry_point
->impl
, true, false);
216 /* Vulkan uses the separate-shader linking model */
217 nir
->info
.separate_shader
= true;
219 nir
= brw_preprocess_nir(compiler
, nir
);
221 if (stage
== MESA_SHADER_FRAGMENT
)
222 NIR_PASS_V(nir
, anv_nir_lower_input_attachments
);
227 void anv_DestroyPipeline(
229 VkPipeline _pipeline
,
230 const VkAllocationCallbacks
* pAllocator
)
232 ANV_FROM_HANDLE(anv_device
, device
, _device
);
233 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
238 anv_reloc_list_finish(&pipeline
->batch_relocs
,
239 pAllocator
? pAllocator
: &device
->alloc
);
240 if (pipeline
->blend_state
.map
)
241 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
243 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
244 if (pipeline
->shaders
[s
])
245 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
248 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
251 static const uint32_t vk_to_gen_primitive_type
[] = {
252 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
253 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
254 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
255 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
256 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
257 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
258 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
259 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
260 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
261 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
265 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
266 struct brw_sampler_prog_key_data
*key
)
268 /* Almost all multisampled textures are compressed. The only time when we
269 * don't compress a multisampled texture is for 16x MSAA with a surface
270 * width greater than 8k which is a bit of an edge case. Since the sampler
271 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
272 * to tell the compiler to always assume compression.
274 key
->compressed_multisample_layout_mask
= ~0;
276 /* SkyLake added support for 16x MSAA. With this came a new message for
277 * reading from a 16x MSAA surface with compression. The new message was
278 * needed because now the MCS data is 64 bits instead of 32 or lower as is
279 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
280 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
281 * so we can just use it unconditionally. This may not be quite as
282 * efficient but it saves us from recompiling.
284 if (devinfo
->gen
>= 9)
287 /* XXX: Handle texture swizzle on HSW- */
288 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
289 /* Assume color sampler, no swizzling. (Works for BDW+) */
290 key
->swizzles
[i
] = SWIZZLE_XYZW
;
295 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
296 struct brw_vs_prog_key
*key
)
298 memset(key
, 0, sizeof(*key
));
300 populate_sampler_prog_key(devinfo
, &key
->tex
);
302 /* XXX: Handle vertex input work-arounds */
304 /* XXX: Handle sampler_prog_key */
308 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
309 struct brw_gs_prog_key
*key
)
311 memset(key
, 0, sizeof(*key
));
313 populate_sampler_prog_key(devinfo
, &key
->tex
);
317 populate_wm_prog_key(const struct anv_pipeline
*pipeline
,
318 const VkGraphicsPipelineCreateInfo
*info
,
319 struct brw_wm_prog_key
*key
)
321 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
323 memset(key
, 0, sizeof(*key
));
325 populate_sampler_prog_key(devinfo
, &key
->tex
);
327 /* TODO: we could set this to 0 based on the information in nir_shader, but
328 * this function is called before spirv_to_nir. */
329 const struct brw_vue_map
*vue_map
=
330 &anv_pipeline_get_last_vue_prog_data(pipeline
)->vue_map
;
331 key
->input_slots_valid
= vue_map
->slots_valid
;
333 /* Vulkan doesn't specify a default */
334 key
->high_quality_derivatives
= false;
336 /* XXX Vulkan doesn't appear to specify */
337 key
->clamp_fragment_color
= false;
339 key
->nr_color_regions
= pipeline
->subpass
->color_count
;
341 key
->replicate_alpha
= key
->nr_color_regions
> 1 &&
342 info
->pMultisampleState
&&
343 info
->pMultisampleState
->alphaToCoverageEnable
;
345 if (info
->pMultisampleState
) {
346 /* We should probably pull this out of the shader, but it's fairly
347 * harmless to compute it and then let dead-code take care of it.
349 if (info
->pMultisampleState
->rasterizationSamples
> 1) {
350 key
->persample_interp
=
351 (info
->pMultisampleState
->minSampleShading
*
352 info
->pMultisampleState
->rasterizationSamples
) > 1;
353 key
->multisample_fbo
= true;
356 key
->frag_coord_adds_sample_pos
=
357 info
->pMultisampleState
->sampleShadingEnable
;
362 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
363 struct brw_cs_prog_key
*key
)
365 memset(key
, 0, sizeof(*key
));
367 populate_sampler_prog_key(devinfo
, &key
->tex
);
371 anv_pipeline_hash_shader(struct anv_pipeline
*pipeline
,
372 struct anv_pipeline_layout
*layout
,
373 struct anv_shader_module
*module
,
374 const char *entrypoint
,
375 gl_shader_stage stage
,
376 const VkSpecializationInfo
*spec_info
,
377 const void *key
, size_t key_size
,
378 unsigned char *sha1_out
)
380 struct mesa_sha1 ctx
;
382 _mesa_sha1_init(&ctx
);
383 if (stage
!= MESA_SHADER_COMPUTE
) {
384 _mesa_sha1_update(&ctx
, &pipeline
->subpass
->view_mask
,
385 sizeof(pipeline
->subpass
->view_mask
));
388 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
389 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
390 _mesa_sha1_update(&ctx
, entrypoint
, strlen(entrypoint
));
391 _mesa_sha1_update(&ctx
, &stage
, sizeof(stage
));
393 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
394 spec_info
->mapEntryCount
* sizeof(*spec_info
->pMapEntries
));
395 _mesa_sha1_update(&ctx
, spec_info
->pData
, spec_info
->dataSize
);
397 _mesa_sha1_update(&ctx
, key
, key_size
);
398 _mesa_sha1_final(&ctx
, sha1_out
);
402 anv_pipeline_compile(struct anv_pipeline
*pipeline
,
404 struct anv_pipeline_layout
*layout
,
405 struct anv_shader_module
*module
,
406 const char *entrypoint
,
407 gl_shader_stage stage
,
408 const VkSpecializationInfo
*spec_info
,
409 struct brw_stage_prog_data
*prog_data
,
410 struct anv_pipeline_bind_map
*map
)
412 const struct brw_compiler
*compiler
=
413 pipeline
->device
->instance
->physicalDevice
.compiler
;
415 nir_shader
*nir
= anv_shader_compile_to_nir(pipeline
, mem_ctx
,
416 module
, entrypoint
, stage
,
421 NIR_PASS_V(nir
, anv_nir_lower_ycbcr_textures
, layout
);
423 NIR_PASS_V(nir
, anv_nir_lower_push_constants
);
425 if (stage
!= MESA_SHADER_COMPUTE
)
426 NIR_PASS_V(nir
, anv_nir_lower_multiview
, pipeline
->subpass
->view_mask
);
428 if (stage
== MESA_SHADER_COMPUTE
)
429 prog_data
->total_shared
= nir
->num_shared
;
431 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
433 if (nir
->num_uniforms
> 0) {
434 assert(prog_data
->nr_params
== 0);
436 /* If the shader uses any push constants at all, we'll just give
437 * them the maximum possible number
439 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
440 nir
->num_uniforms
= MAX_PUSH_CONSTANTS_SIZE
;
441 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
442 prog_data
->param
= ralloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
444 /* We now set the param values to be offsets into a
445 * anv_push_constant_data structure. Since the compiler doesn't
446 * actually dereference any of the gl_constant_value pointers in the
447 * params array, it doesn't really matter what we put here.
449 struct anv_push_constants
*null_data
= NULL
;
450 /* Fill out the push constants section of the param array */
451 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++) {
452 prog_data
->param
[i
] = ANV_PARAM_PUSH(
453 (uintptr_t)&null_data
->client_data
[i
* sizeof(float)]);
457 if (nir
->info
.num_ssbos
> 0 || nir
->info
.num_images
> 0)
458 pipeline
->needs_data_cache
= true;
460 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
462 anv_nir_apply_pipeline_layout(pipeline
, layout
, nir
, prog_data
, map
);
464 if (stage
!= MESA_SHADER_COMPUTE
)
465 brw_nir_analyze_ubo_ranges(compiler
, nir
, prog_data
->ubo_ranges
);
467 assert(nir
->num_uniforms
== prog_data
->nr_params
* 4);
473 anv_fill_binding_table(struct brw_stage_prog_data
*prog_data
, unsigned bias
)
475 prog_data
->binding_table
.size_bytes
= 0;
476 prog_data
->binding_table
.texture_start
= bias
;
477 prog_data
->binding_table
.gather_texture_start
= bias
;
478 prog_data
->binding_table
.ubo_start
= bias
;
479 prog_data
->binding_table
.ssbo_start
= bias
;
480 prog_data
->binding_table
.image_start
= bias
;
483 static struct anv_shader_bin
*
484 anv_pipeline_upload_kernel(struct anv_pipeline
*pipeline
,
485 struct anv_pipeline_cache
*cache
,
486 const void *key_data
, uint32_t key_size
,
487 const void *kernel_data
, uint32_t kernel_size
,
488 const struct brw_stage_prog_data
*prog_data
,
489 uint32_t prog_data_size
,
490 const struct anv_pipeline_bind_map
*bind_map
)
493 return anv_pipeline_cache_upload_kernel(cache
, key_data
, key_size
,
494 kernel_data
, kernel_size
,
495 prog_data
, prog_data_size
,
498 return anv_shader_bin_create(pipeline
->device
, key_data
, key_size
,
499 kernel_data
, kernel_size
,
500 prog_data
, prog_data_size
,
501 prog_data
->param
, bind_map
);
507 anv_pipeline_add_compiled_stage(struct anv_pipeline
*pipeline
,
508 gl_shader_stage stage
,
509 struct anv_shader_bin
*shader
)
511 pipeline
->shaders
[stage
] = shader
;
515 anv_pipeline_compile_vs(struct anv_pipeline
*pipeline
,
516 struct anv_pipeline_cache
*cache
,
517 const VkGraphicsPipelineCreateInfo
*info
,
518 struct anv_shader_module
*module
,
519 const char *entrypoint
,
520 const VkSpecializationInfo
*spec_info
)
522 const struct brw_compiler
*compiler
=
523 pipeline
->device
->instance
->physicalDevice
.compiler
;
524 struct brw_vs_prog_key key
;
525 struct anv_shader_bin
*bin
= NULL
;
526 unsigned char sha1
[20];
528 populate_vs_prog_key(&pipeline
->device
->info
, &key
);
530 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
533 anv_pipeline_hash_shader(pipeline
, layout
, module
, entrypoint
,
534 MESA_SHADER_VERTEX
, spec_info
,
535 &key
, sizeof(key
), sha1
);
536 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
540 struct brw_vs_prog_data prog_data
= {};
541 struct anv_pipeline_binding surface_to_descriptor
[256];
542 struct anv_pipeline_binding sampler_to_descriptor
[256];
544 struct anv_pipeline_bind_map map
= {
545 .surface_to_descriptor
= surface_to_descriptor
,
546 .sampler_to_descriptor
= sampler_to_descriptor
549 void *mem_ctx
= ralloc_context(NULL
);
551 nir_shader
*nir
= anv_pipeline_compile(pipeline
, mem_ctx
, layout
,
553 MESA_SHADER_VERTEX
, spec_info
,
554 &prog_data
.base
.base
, &map
);
556 ralloc_free(mem_ctx
);
557 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
560 anv_fill_binding_table(&prog_data
.base
.base
, 0);
562 brw_compute_vue_map(&pipeline
->device
->info
,
563 &prog_data
.base
.vue_map
,
564 nir
->info
.outputs_written
,
565 nir
->info
.separate_shader
);
567 const unsigned *shader_code
=
568 brw_compile_vs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
570 if (shader_code
== NULL
) {
571 ralloc_free(mem_ctx
);
572 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
575 unsigned code_size
= prog_data
.base
.base
.program_size
;
576 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
577 shader_code
, code_size
,
578 &prog_data
.base
.base
, sizeof(prog_data
),
581 ralloc_free(mem_ctx
);
582 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
585 ralloc_free(mem_ctx
);
588 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_VERTEX
, bin
);
594 merge_tess_info(struct shader_info
*tes_info
,
595 const struct shader_info
*tcs_info
)
597 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
599 * "PointMode. Controls generation of points rather than triangles
600 * or lines. This functionality defaults to disabled, and is
601 * enabled if either shader stage includes the execution mode.
603 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
604 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
605 * and OutputVertices, it says:
607 * "One mode must be set in at least one of the tessellation
610 * So, the fields can be set in either the TCS or TES, but they must
611 * agree if set in both. Our backend looks at TES, so bitwise-or in
612 * the values from the TCS.
614 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
615 tes_info
->tess
.tcs_vertices_out
== 0 ||
616 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
617 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
619 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
620 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
621 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
622 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
624 assert(tcs_info
->tess
.primitive_mode
== 0 ||
625 tes_info
->tess
.primitive_mode
== 0 ||
626 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
627 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
628 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
629 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
633 anv_pipeline_compile_tcs_tes(struct anv_pipeline
*pipeline
,
634 struct anv_pipeline_cache
*cache
,
635 const VkGraphicsPipelineCreateInfo
*info
,
636 struct anv_shader_module
*tcs_module
,
637 const char *tcs_entrypoint
,
638 const VkSpecializationInfo
*tcs_spec_info
,
639 struct anv_shader_module
*tes_module
,
640 const char *tes_entrypoint
,
641 const VkSpecializationInfo
*tes_spec_info
)
643 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
644 const struct brw_compiler
*compiler
=
645 pipeline
->device
->instance
->physicalDevice
.compiler
;
646 struct brw_tcs_prog_key tcs_key
= {};
647 struct brw_tes_prog_key tes_key
= {};
648 struct anv_shader_bin
*tcs_bin
= NULL
;
649 struct anv_shader_bin
*tes_bin
= NULL
;
650 unsigned char tcs_sha1
[40];
651 unsigned char tes_sha1
[40];
653 populate_sampler_prog_key(&pipeline
->device
->info
, &tcs_key
.tex
);
654 populate_sampler_prog_key(&pipeline
->device
->info
, &tes_key
.tex
);
655 tcs_key
.input_vertices
= info
->pTessellationState
->patchControlPoints
;
657 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
660 anv_pipeline_hash_shader(pipeline
, layout
, tcs_module
, tcs_entrypoint
,
661 MESA_SHADER_TESS_CTRL
, tcs_spec_info
,
662 &tcs_key
, sizeof(tcs_key
), tcs_sha1
);
663 anv_pipeline_hash_shader(pipeline
, layout
, tes_module
, tes_entrypoint
,
664 MESA_SHADER_TESS_EVAL
, tes_spec_info
,
665 &tes_key
, sizeof(tes_key
), tes_sha1
);
666 memcpy(&tcs_sha1
[20], tes_sha1
, 20);
667 memcpy(&tes_sha1
[20], tcs_sha1
, 20);
668 tcs_bin
= anv_pipeline_cache_search(cache
, tcs_sha1
, sizeof(tcs_sha1
));
669 tes_bin
= anv_pipeline_cache_search(cache
, tes_sha1
, sizeof(tes_sha1
));
672 if (tcs_bin
== NULL
|| tes_bin
== NULL
) {
673 struct brw_tcs_prog_data tcs_prog_data
= {};
674 struct brw_tes_prog_data tes_prog_data
= {};
675 struct anv_pipeline_binding tcs_surface_to_descriptor
[256];
676 struct anv_pipeline_binding tcs_sampler_to_descriptor
[256];
677 struct anv_pipeline_binding tes_surface_to_descriptor
[256];
678 struct anv_pipeline_binding tes_sampler_to_descriptor
[256];
680 struct anv_pipeline_bind_map tcs_map
= {
681 .surface_to_descriptor
= tcs_surface_to_descriptor
,
682 .sampler_to_descriptor
= tcs_sampler_to_descriptor
684 struct anv_pipeline_bind_map tes_map
= {
685 .surface_to_descriptor
= tes_surface_to_descriptor
,
686 .sampler_to_descriptor
= tes_sampler_to_descriptor
689 void *mem_ctx
= ralloc_context(NULL
);
691 nir_shader
*tcs_nir
=
692 anv_pipeline_compile(pipeline
, mem_ctx
, layout
,
693 tcs_module
, tcs_entrypoint
,
694 MESA_SHADER_TESS_CTRL
, tcs_spec_info
,
695 &tcs_prog_data
.base
.base
, &tcs_map
);
696 nir_shader
*tes_nir
=
697 anv_pipeline_compile(pipeline
, mem_ctx
, layout
,
698 tes_module
, tes_entrypoint
,
699 MESA_SHADER_TESS_EVAL
, tes_spec_info
,
700 &tes_prog_data
.base
.base
, &tes_map
);
701 if (tcs_nir
== NULL
|| tes_nir
== NULL
) {
702 ralloc_free(mem_ctx
);
703 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
706 nir_lower_tes_patch_vertices(tes_nir
,
707 tcs_nir
->info
.tess
.tcs_vertices_out
);
709 /* Copy TCS info into the TES info */
710 merge_tess_info(&tes_nir
->info
, &tcs_nir
->info
);
712 anv_fill_binding_table(&tcs_prog_data
.base
.base
, 0);
713 anv_fill_binding_table(&tes_prog_data
.base
.base
, 0);
715 /* Whacking the key after cache lookup is a bit sketchy, but all of
716 * this comes from the SPIR-V, which is part of the hash used for the
717 * pipeline cache. So it should be safe.
719 tcs_key
.tes_primitive_mode
= tes_nir
->info
.tess
.primitive_mode
;
720 tcs_key
.outputs_written
= tcs_nir
->info
.outputs_written
;
721 tcs_key
.patch_outputs_written
= tcs_nir
->info
.patch_outputs_written
;
722 tcs_key
.quads_workaround
=
724 tes_nir
->info
.tess
.primitive_mode
== 7 /* GL_QUADS */ &&
725 tes_nir
->info
.tess
.spacing
== TESS_SPACING_EQUAL
;
727 tes_key
.inputs_read
= tcs_key
.outputs_written
;
728 tes_key
.patch_inputs_read
= tcs_key
.patch_outputs_written
;
730 const int shader_time_index
= -1;
731 const unsigned *shader_code
;
734 brw_compile_tcs(compiler
, NULL
, mem_ctx
, &tcs_key
, &tcs_prog_data
,
735 tcs_nir
, shader_time_index
, NULL
);
736 if (shader_code
== NULL
) {
737 ralloc_free(mem_ctx
);
738 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
741 unsigned code_size
= tcs_prog_data
.base
.base
.program_size
;
742 tcs_bin
= anv_pipeline_upload_kernel(pipeline
, cache
,
743 tcs_sha1
, sizeof(tcs_sha1
),
744 shader_code
, code_size
,
745 &tcs_prog_data
.base
.base
,
746 sizeof(tcs_prog_data
),
749 ralloc_free(mem_ctx
);
750 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
754 brw_compile_tes(compiler
, NULL
, mem_ctx
, &tes_key
,
755 &tcs_prog_data
.base
.vue_map
, &tes_prog_data
, tes_nir
,
756 NULL
, shader_time_index
, NULL
);
757 if (shader_code
== NULL
) {
758 ralloc_free(mem_ctx
);
759 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
762 code_size
= tes_prog_data
.base
.base
.program_size
;
763 tes_bin
= anv_pipeline_upload_kernel(pipeline
, cache
,
764 tes_sha1
, sizeof(tes_sha1
),
765 shader_code
, code_size
,
766 &tes_prog_data
.base
.base
,
767 sizeof(tes_prog_data
),
770 ralloc_free(mem_ctx
);
771 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
774 ralloc_free(mem_ctx
);
777 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_TESS_CTRL
, tcs_bin
);
778 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_TESS_EVAL
, tes_bin
);
784 anv_pipeline_compile_gs(struct anv_pipeline
*pipeline
,
785 struct anv_pipeline_cache
*cache
,
786 const VkGraphicsPipelineCreateInfo
*info
,
787 struct anv_shader_module
*module
,
788 const char *entrypoint
,
789 const VkSpecializationInfo
*spec_info
)
791 const struct brw_compiler
*compiler
=
792 pipeline
->device
->instance
->physicalDevice
.compiler
;
793 struct brw_gs_prog_key key
;
794 struct anv_shader_bin
*bin
= NULL
;
795 unsigned char sha1
[20];
797 populate_gs_prog_key(&pipeline
->device
->info
, &key
);
799 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
802 anv_pipeline_hash_shader(pipeline
, layout
, module
, entrypoint
,
803 MESA_SHADER_GEOMETRY
, spec_info
,
804 &key
, sizeof(key
), sha1
);
805 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
809 struct brw_gs_prog_data prog_data
= {};
810 struct anv_pipeline_binding surface_to_descriptor
[256];
811 struct anv_pipeline_binding sampler_to_descriptor
[256];
813 struct anv_pipeline_bind_map map
= {
814 .surface_to_descriptor
= surface_to_descriptor
,
815 .sampler_to_descriptor
= sampler_to_descriptor
818 void *mem_ctx
= ralloc_context(NULL
);
820 nir_shader
*nir
= anv_pipeline_compile(pipeline
, mem_ctx
, layout
,
822 MESA_SHADER_GEOMETRY
, spec_info
,
823 &prog_data
.base
.base
, &map
);
825 ralloc_free(mem_ctx
);
826 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
829 anv_fill_binding_table(&prog_data
.base
.base
, 0);
831 brw_compute_vue_map(&pipeline
->device
->info
,
832 &prog_data
.base
.vue_map
,
833 nir
->info
.outputs_written
,
834 nir
->info
.separate_shader
);
836 const unsigned *shader_code
=
837 brw_compile_gs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
839 if (shader_code
== NULL
) {
840 ralloc_free(mem_ctx
);
841 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
845 const unsigned code_size
= prog_data
.base
.base
.program_size
;
846 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
847 shader_code
, code_size
,
848 &prog_data
.base
.base
, sizeof(prog_data
),
851 ralloc_free(mem_ctx
);
852 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
855 ralloc_free(mem_ctx
);
858 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_GEOMETRY
, bin
);
864 anv_pipeline_compile_fs(struct anv_pipeline
*pipeline
,
865 struct anv_pipeline_cache
*cache
,
866 const VkGraphicsPipelineCreateInfo
*info
,
867 struct anv_shader_module
*module
,
868 const char *entrypoint
,
869 const VkSpecializationInfo
*spec_info
)
871 const struct brw_compiler
*compiler
=
872 pipeline
->device
->instance
->physicalDevice
.compiler
;
873 struct brw_wm_prog_key key
;
874 struct anv_shader_bin
*bin
= NULL
;
875 unsigned char sha1
[20];
877 populate_wm_prog_key(pipeline
, info
, &key
);
879 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
882 anv_pipeline_hash_shader(pipeline
, layout
, module
, entrypoint
,
883 MESA_SHADER_FRAGMENT
, spec_info
,
884 &key
, sizeof(key
), sha1
);
885 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
889 struct brw_wm_prog_data prog_data
= {};
890 struct anv_pipeline_binding surface_to_descriptor
[256];
891 struct anv_pipeline_binding sampler_to_descriptor
[256];
893 struct anv_pipeline_bind_map map
= {
894 .surface_to_descriptor
= surface_to_descriptor
+ 8,
895 .sampler_to_descriptor
= sampler_to_descriptor
898 void *mem_ctx
= ralloc_context(NULL
);
900 nir_shader
*nir
= anv_pipeline_compile(pipeline
, mem_ctx
, layout
,
902 MESA_SHADER_FRAGMENT
, spec_info
,
903 &prog_data
.base
, &map
);
905 ralloc_free(mem_ctx
);
906 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
909 unsigned num_rts
= 0;
910 const int max_rt
= FRAG_RESULT_DATA7
- FRAG_RESULT_DATA0
+ 1;
911 struct anv_pipeline_binding rt_bindings
[max_rt
];
912 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
913 int rt_to_bindings
[max_rt
];
914 memset(rt_to_bindings
, -1, sizeof(rt_to_bindings
));
915 bool rt_used
[max_rt
];
916 memset(rt_used
, 0, sizeof(rt_used
));
918 /* Flag used render targets */
919 nir_foreach_variable_safe(var
, &nir
->outputs
) {
920 if (var
->data
.location
< FRAG_RESULT_DATA0
)
923 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
925 if (rt
>= key
.nr_color_regions
)
928 const unsigned array_len
=
929 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
930 assert(rt
+ array_len
<= max_rt
);
932 for (unsigned i
= 0; i
< array_len
; i
++)
933 rt_used
[rt
+ i
] = true;
936 /* Set new, compacted, location */
937 for (unsigned i
= 0; i
< max_rt
; i
++) {
941 rt_to_bindings
[i
] = num_rts
;
942 rt_bindings
[rt_to_bindings
[i
]] = (struct anv_pipeline_binding
) {
943 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
950 nir_foreach_variable_safe(var
, &nir
->outputs
) {
951 if (var
->data
.location
< FRAG_RESULT_DATA0
)
954 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
955 if (rt
>= key
.nr_color_regions
) {
956 /* Out-of-bounds, throw it away */
957 var
->data
.mode
= nir_var_local
;
958 exec_node_remove(&var
->node
);
959 exec_list_push_tail(&impl
->locals
, &var
->node
);
963 /* Give it the new location */
964 assert(rt_to_bindings
[rt
] != -1);
965 var
->data
.location
= rt_to_bindings
[rt
] + FRAG_RESULT_DATA0
;
969 /* If we have no render targets, we need a null render target */
970 rt_bindings
[0] = (struct anv_pipeline_binding
) {
971 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
978 assert(num_rts
<= max_rt
);
979 map
.surface_to_descriptor
-= num_rts
;
980 map
.surface_count
+= num_rts
;
981 assert(map
.surface_count
<= 256);
982 memcpy(map
.surface_to_descriptor
, rt_bindings
,
983 num_rts
* sizeof(*rt_bindings
));
985 anv_fill_binding_table(&prog_data
.base
, num_rts
);
987 const unsigned *shader_code
=
988 brw_compile_fs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
989 NULL
, -1, -1, true, false, NULL
, NULL
);
990 if (shader_code
== NULL
) {
991 ralloc_free(mem_ctx
);
992 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
995 unsigned code_size
= prog_data
.base
.program_size
;
996 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
997 shader_code
, code_size
,
998 &prog_data
.base
, sizeof(prog_data
),
1001 ralloc_free(mem_ctx
);
1002 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1005 ralloc_free(mem_ctx
);
1008 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_FRAGMENT
, bin
);
1014 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1015 struct anv_pipeline_cache
*cache
,
1016 const VkComputePipelineCreateInfo
*info
,
1017 struct anv_shader_module
*module
,
1018 const char *entrypoint
,
1019 const VkSpecializationInfo
*spec_info
)
1021 const struct brw_compiler
*compiler
=
1022 pipeline
->device
->instance
->physicalDevice
.compiler
;
1023 struct brw_cs_prog_key key
;
1024 struct anv_shader_bin
*bin
= NULL
;
1025 unsigned char sha1
[20];
1027 populate_cs_prog_key(&pipeline
->device
->info
, &key
);
1029 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1032 anv_pipeline_hash_shader(pipeline
, layout
, module
, entrypoint
,
1033 MESA_SHADER_COMPUTE
, spec_info
,
1034 &key
, sizeof(key
), sha1
);
1035 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
1039 struct brw_cs_prog_data prog_data
= {};
1040 struct anv_pipeline_binding surface_to_descriptor
[256];
1041 struct anv_pipeline_binding sampler_to_descriptor
[256];
1043 struct anv_pipeline_bind_map map
= {
1044 .surface_to_descriptor
= surface_to_descriptor
,
1045 .sampler_to_descriptor
= sampler_to_descriptor
1048 void *mem_ctx
= ralloc_context(NULL
);
1050 nir_shader
*nir
= anv_pipeline_compile(pipeline
, mem_ctx
, layout
,
1052 MESA_SHADER_COMPUTE
, spec_info
,
1053 &prog_data
.base
, &map
);
1055 ralloc_free(mem_ctx
);
1056 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1059 NIR_PASS_V(nir
, anv_nir_add_base_work_group_id
, &prog_data
);
1061 anv_fill_binding_table(&prog_data
.base
, 1);
1063 const unsigned *shader_code
=
1064 brw_compile_cs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
1066 if (shader_code
== NULL
) {
1067 ralloc_free(mem_ctx
);
1068 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1071 const unsigned code_size
= prog_data
.base
.program_size
;
1072 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
1073 shader_code
, code_size
,
1074 &prog_data
.base
, sizeof(prog_data
),
1077 ralloc_free(mem_ctx
);
1078 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1081 ralloc_free(mem_ctx
);
1084 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_COMPUTE
, bin
);
1090 * Copy pipeline state not marked as dynamic.
1091 * Dynamic state is pipeline state which hasn't been provided at pipeline
1092 * creation time, but is dynamically provided afterwards using various
1093 * vkCmdSet* functions.
1095 * The set of state considered "non_dynamic" is determined by the pieces of
1096 * state that have their corresponding VkDynamicState enums omitted from
1097 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1099 * @param[out] pipeline Destination non_dynamic state.
1100 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1103 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
1104 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1106 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
1107 struct anv_subpass
*subpass
= pipeline
->subpass
;
1109 pipeline
->dynamic_state
= default_dynamic_state
;
1111 if (pCreateInfo
->pDynamicState
) {
1112 /* Remove all of the states that are marked as dynamic */
1113 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1114 for (uint32_t s
= 0; s
< count
; s
++)
1115 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1118 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1120 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1122 * pViewportState is [...] NULL if the pipeline
1123 * has rasterization disabled.
1125 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1126 assert(pCreateInfo
->pViewportState
);
1128 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1129 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
1130 typed_memcpy(dynamic
->viewport
.viewports
,
1131 pCreateInfo
->pViewportState
->pViewports
,
1132 pCreateInfo
->pViewportState
->viewportCount
);
1135 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1136 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
1137 typed_memcpy(dynamic
->scissor
.scissors
,
1138 pCreateInfo
->pViewportState
->pScissors
,
1139 pCreateInfo
->pViewportState
->scissorCount
);
1143 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1144 assert(pCreateInfo
->pRasterizationState
);
1145 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1148 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1149 assert(pCreateInfo
->pRasterizationState
);
1150 dynamic
->depth_bias
.bias
=
1151 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1152 dynamic
->depth_bias
.clamp
=
1153 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1154 dynamic
->depth_bias
.slope
=
1155 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1158 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1160 * pColorBlendState is [...] NULL if the pipeline has rasterization
1161 * disabled or if the subpass of the render pass the pipeline is
1162 * created against does not use any color attachments.
1164 bool uses_color_att
= false;
1165 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1166 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1167 uses_color_att
= true;
1172 if (uses_color_att
&&
1173 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1174 assert(pCreateInfo
->pColorBlendState
);
1176 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
1177 typed_memcpy(dynamic
->blend_constants
,
1178 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1181 /* If there is no depthstencil attachment, then don't read
1182 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1183 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1184 * no need to override the depthstencil defaults in
1185 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1187 * Section 9.2 of the Vulkan 1.0.15 spec says:
1189 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1190 * disabled or if the subpass of the render pass the pipeline is created
1191 * against does not use a depth/stencil attachment.
1193 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1194 subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1195 assert(pCreateInfo
->pDepthStencilState
);
1197 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1198 dynamic
->depth_bounds
.min
=
1199 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1200 dynamic
->depth_bounds
.max
=
1201 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1204 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1205 dynamic
->stencil_compare_mask
.front
=
1206 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1207 dynamic
->stencil_compare_mask
.back
=
1208 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1211 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1212 dynamic
->stencil_write_mask
.front
=
1213 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1214 dynamic
->stencil_write_mask
.back
=
1215 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1218 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1219 dynamic
->stencil_reference
.front
=
1220 pCreateInfo
->pDepthStencilState
->front
.reference
;
1221 dynamic
->stencil_reference
.back
=
1222 pCreateInfo
->pDepthStencilState
->back
.reference
;
1226 pipeline
->dynamic_state_mask
= states
;
1230 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1233 struct anv_render_pass
*renderpass
= NULL
;
1234 struct anv_subpass
*subpass
= NULL
;
1236 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1237 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1239 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1241 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1244 assert(info
->subpass
< renderpass
->subpass_count
);
1245 subpass
= &renderpass
->subpasses
[info
->subpass
];
1247 assert(info
->stageCount
>= 1);
1248 assert(info
->pVertexInputState
);
1249 assert(info
->pInputAssemblyState
);
1250 assert(info
->pRasterizationState
);
1251 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1252 assert(info
->pViewportState
);
1253 assert(info
->pMultisampleState
);
1255 if (subpass
&& subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
)
1256 assert(info
->pDepthStencilState
);
1258 if (subpass
&& subpass
->color_count
> 0) {
1259 bool all_color_unused
= true;
1260 for (int i
= 0; i
< subpass
->color_count
; i
++) {
1261 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
1262 all_color_unused
= false;
1264 /* pColorBlendState is ignored if the pipeline has rasterization
1265 * disabled or if the subpass of the render pass the pipeline is
1266 * created against does not use any color attachments.
1268 assert(info
->pColorBlendState
|| all_color_unused
);
1272 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1273 switch (info
->pStages
[i
].stage
) {
1274 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1275 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1276 assert(info
->pTessellationState
);
1286 * Calculate the desired L3 partitioning based on the current state of the
1287 * pipeline. For now this simply returns the conservative defaults calculated
1288 * by get_default_l3_weights(), but we could probably do better by gathering
1289 * more statistics from the pipeline state (e.g. guess of expected URB usage
1290 * and bound surfaces), or by using feed-back from performance counters.
1293 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1295 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1297 const struct gen_l3_weights w
=
1298 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
1300 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
1301 pipeline
->urb
.total_size
=
1302 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
1306 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1307 struct anv_device
*device
,
1308 struct anv_pipeline_cache
*cache
,
1309 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1310 const VkAllocationCallbacks
*alloc
)
1314 anv_pipeline_validate_create_info(pCreateInfo
);
1317 alloc
= &device
->alloc
;
1319 pipeline
->device
= device
;
1321 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, pCreateInfo
->renderPass
);
1322 assert(pCreateInfo
->subpass
< render_pass
->subpass_count
);
1323 pipeline
->subpass
= &render_pass
->subpasses
[pCreateInfo
->subpass
];
1325 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1326 if (result
!= VK_SUCCESS
)
1329 pipeline
->batch
.alloc
= alloc
;
1330 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1331 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1332 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1333 pipeline
->batch
.status
= VK_SUCCESS
;
1335 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1336 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1337 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1339 pipeline
->sample_shading_enable
= pCreateInfo
->pMultisampleState
&&
1340 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
1342 pipeline
->needs_data_cache
= false;
1344 /* When we free the pipeline, we detect stages based on the NULL status
1345 * of various prog_data pointers. Make them NULL by default.
1347 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1349 pipeline
->active_stages
= 0;
1351 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = {};
1352 struct anv_shader_module
*modules
[MESA_SHADER_STAGES
] = {};
1353 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
1354 VkShaderStageFlagBits vk_stage
= pCreateInfo
->pStages
[i
].stage
;
1355 gl_shader_stage stage
= vk_to_mesa_shader_stage(vk_stage
);
1356 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
1357 modules
[stage
] = anv_shader_module_from_handle(pStages
[stage
]->module
);
1358 pipeline
->active_stages
|= vk_stage
;
1361 if (pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
)
1362 pipeline
->active_stages
|= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
1364 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1366 if (modules
[MESA_SHADER_VERTEX
]) {
1367 result
= anv_pipeline_compile_vs(pipeline
, cache
, pCreateInfo
,
1368 modules
[MESA_SHADER_VERTEX
],
1369 pStages
[MESA_SHADER_VERTEX
]->pName
,
1370 pStages
[MESA_SHADER_VERTEX
]->pSpecializationInfo
);
1371 if (result
!= VK_SUCCESS
)
1375 if (modules
[MESA_SHADER_TESS_EVAL
]) {
1376 result
= anv_pipeline_compile_tcs_tes(pipeline
, cache
, pCreateInfo
,
1377 modules
[MESA_SHADER_TESS_CTRL
],
1378 pStages
[MESA_SHADER_TESS_CTRL
]->pName
,
1379 pStages
[MESA_SHADER_TESS_CTRL
]->pSpecializationInfo
,
1380 modules
[MESA_SHADER_TESS_EVAL
],
1381 pStages
[MESA_SHADER_TESS_EVAL
]->pName
,
1382 pStages
[MESA_SHADER_TESS_EVAL
]->pSpecializationInfo
);
1383 if (result
!= VK_SUCCESS
)
1387 if (modules
[MESA_SHADER_GEOMETRY
]) {
1388 result
= anv_pipeline_compile_gs(pipeline
, cache
, pCreateInfo
,
1389 modules
[MESA_SHADER_GEOMETRY
],
1390 pStages
[MESA_SHADER_GEOMETRY
]->pName
,
1391 pStages
[MESA_SHADER_GEOMETRY
]->pSpecializationInfo
);
1392 if (result
!= VK_SUCCESS
)
1396 if (modules
[MESA_SHADER_FRAGMENT
]) {
1397 result
= anv_pipeline_compile_fs(pipeline
, cache
, pCreateInfo
,
1398 modules
[MESA_SHADER_FRAGMENT
],
1399 pStages
[MESA_SHADER_FRAGMENT
]->pName
,
1400 pStages
[MESA_SHADER_FRAGMENT
]->pSpecializationInfo
);
1401 if (result
!= VK_SUCCESS
)
1405 assert(pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1407 anv_pipeline_setup_l3_config(pipeline
, false);
1409 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1410 pCreateInfo
->pVertexInputState
;
1412 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1414 pipeline
->vb_used
= 0;
1415 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1416 const VkVertexInputAttributeDescription
*desc
=
1417 &vi_info
->pVertexAttributeDescriptions
[i
];
1419 if (inputs_read
& (1ull << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1420 pipeline
->vb_used
|= 1 << desc
->binding
;
1423 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1424 const VkVertexInputBindingDescription
*desc
=
1425 &vi_info
->pVertexBindingDescriptions
[i
];
1427 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
1429 /* Step rate is programmed per vertex element (attribute), not
1430 * binding. Set up a map of which bindings step per instance, for
1431 * reference by vertex element setup. */
1432 switch (desc
->inputRate
) {
1434 case VK_VERTEX_INPUT_RATE_VERTEX
:
1435 pipeline
->instancing_enable
[desc
->binding
] = false;
1437 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1438 pipeline
->instancing_enable
[desc
->binding
] = true;
1443 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1444 pCreateInfo
->pInputAssemblyState
;
1445 const VkPipelineTessellationStateCreateInfo
*tess_info
=
1446 pCreateInfo
->pTessellationState
;
1447 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1449 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1450 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
1452 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];
1457 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1458 if (pipeline
->shaders
[s
])
1459 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
1462 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);