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anv: enable VK_EXT_shader_viewport_index_layer
[mesa.git] / src / intel / vulkan / anv_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "util/mesa-sha1.h"
31 #include "common/gen_l3_config.h"
32 #include "anv_private.h"
33 #include "compiler/brw_nir.h"
34 #include "anv_nir.h"
35 #include "spirv/nir_spirv.h"
36
37 /* Needed for SWIZZLE macros */
38 #include "program/prog_instruction.h"
39
40 // Shader functions
41
42 VkResult anv_CreateShaderModule(
43 VkDevice _device,
44 const VkShaderModuleCreateInfo* pCreateInfo,
45 const VkAllocationCallbacks* pAllocator,
46 VkShaderModule* pShaderModule)
47 {
48 ANV_FROM_HANDLE(anv_device, device, _device);
49 struct anv_shader_module *module;
50
51 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
52 assert(pCreateInfo->flags == 0);
53
54 module = vk_alloc2(&device->alloc, pAllocator,
55 sizeof(*module) + pCreateInfo->codeSize, 8,
56 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
57 if (module == NULL)
58 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
59
60 module->size = pCreateInfo->codeSize;
61 memcpy(module->data, pCreateInfo->pCode, module->size);
62
63 _mesa_sha1_compute(module->data, module->size, module->sha1);
64
65 *pShaderModule = anv_shader_module_to_handle(module);
66
67 return VK_SUCCESS;
68 }
69
70 void anv_DestroyShaderModule(
71 VkDevice _device,
72 VkShaderModule _module,
73 const VkAllocationCallbacks* pAllocator)
74 {
75 ANV_FROM_HANDLE(anv_device, device, _device);
76 ANV_FROM_HANDLE(anv_shader_module, module, _module);
77
78 if (!module)
79 return;
80
81 vk_free2(&device->alloc, pAllocator, module);
82 }
83
84 #define SPIR_V_MAGIC_NUMBER 0x07230203
85
86 static const uint64_t stage_to_debug[] = {
87 [MESA_SHADER_VERTEX] = DEBUG_VS,
88 [MESA_SHADER_TESS_CTRL] = DEBUG_TCS,
89 [MESA_SHADER_TESS_EVAL] = DEBUG_TES,
90 [MESA_SHADER_GEOMETRY] = DEBUG_GS,
91 [MESA_SHADER_FRAGMENT] = DEBUG_WM,
92 [MESA_SHADER_COMPUTE] = DEBUG_CS,
93 };
94
95 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
96 * we can't do that yet because we don't have the ability to copy nir.
97 */
98 static nir_shader *
99 anv_shader_compile_to_nir(struct anv_pipeline *pipeline,
100 void *mem_ctx,
101 struct anv_shader_module *module,
102 const char *entrypoint_name,
103 gl_shader_stage stage,
104 const VkSpecializationInfo *spec_info)
105 {
106 const struct anv_device *device = pipeline->device;
107
108 const struct brw_compiler *compiler =
109 device->instance->physicalDevice.compiler;
110 const nir_shader_compiler_options *nir_options =
111 compiler->glsl_compiler_options[stage].NirOptions;
112
113 uint32_t *spirv = (uint32_t *) module->data;
114 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
115 assert(module->size % 4 == 0);
116
117 uint32_t num_spec_entries = 0;
118 struct nir_spirv_specialization *spec_entries = NULL;
119 if (spec_info && spec_info->mapEntryCount > 0) {
120 num_spec_entries = spec_info->mapEntryCount;
121 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
122 for (uint32_t i = 0; i < num_spec_entries; i++) {
123 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
124 const void *data = spec_info->pData + entry.offset;
125 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
126
127 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
128 if (spec_info->dataSize == 8)
129 spec_entries[i].data64 = *(const uint64_t *)data;
130 else
131 spec_entries[i].data32 = *(const uint32_t *)data;
132 }
133 }
134
135 struct spirv_to_nir_options spirv_options = {
136 .lower_workgroup_access_to_offsets = true,
137 .caps = {
138 .float64 = device->instance->physicalDevice.info.gen >= 8,
139 .int64 = device->instance->physicalDevice.info.gen >= 8,
140 .tessellation = true,
141 .device_group = true,
142 .draw_parameters = true,
143 .image_write_without_format = true,
144 .multiview = true,
145 .variable_pointers = true,
146 .storage_16bit = device->instance->physicalDevice.info.gen >= 8,
147 .shader_viewport_index_layer = true,
148 .subgroup_arithmetic = true,
149 .subgroup_basic = true,
150 .subgroup_ballot = true,
151 .subgroup_quad = true,
152 .subgroup_shuffle = true,
153 .subgroup_vote = true,
154 },
155 };
156
157 nir_function *entry_point =
158 spirv_to_nir(spirv, module->size / 4,
159 spec_entries, num_spec_entries,
160 stage, entrypoint_name, &spirv_options, nir_options);
161 nir_shader *nir = entry_point->shader;
162 assert(nir->info.stage == stage);
163 nir_validate_shader(nir);
164 ralloc_steal(mem_ctx, nir);
165
166 free(spec_entries);
167
168 if (unlikely(INTEL_DEBUG & stage_to_debug[stage])) {
169 fprintf(stderr, "NIR (from SPIR-V) for %s shader:\n",
170 gl_shader_stage_name(stage));
171 nir_print_shader(nir, stderr);
172 }
173
174 /* We have to lower away local constant initializers right before we
175 * inline functions. That way they get properly initialized at the top
176 * of the function and not at the top of its caller.
177 */
178 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
179 NIR_PASS_V(nir, nir_lower_returns);
180 NIR_PASS_V(nir, nir_inline_functions);
181
182 /* Pick off the single entrypoint that we want */
183 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
184 if (func != entry_point)
185 exec_node_remove(&func->node);
186 }
187 assert(exec_list_length(&nir->functions) == 1);
188 entry_point->name = ralloc_strdup(entry_point, "main");
189
190 /* Now that we've deleted all but the main function, we can go ahead and
191 * lower the rest of the constant initializers. We do this here so that
192 * nir_remove_dead_variables and split_per_member_structs below see the
193 * corresponding stores.
194 */
195 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
196
197 NIR_PASS_V(nir, nir_remove_dead_variables,
198 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
199
200 if (stage == MESA_SHADER_FRAGMENT)
201 NIR_PASS_V(nir, nir_lower_wpos_center, pipeline->sample_shading_enable);
202
203 NIR_PASS_V(nir, nir_propagate_invariant);
204 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
205 entry_point->impl, true, false);
206
207 /* Vulkan uses the separate-shader linking model */
208 nir->info.separate_shader = true;
209
210 nir = brw_preprocess_nir(compiler, nir);
211
212 if (stage == MESA_SHADER_FRAGMENT)
213 NIR_PASS_V(nir, anv_nir_lower_input_attachments);
214
215 return nir;
216 }
217
218 void anv_DestroyPipeline(
219 VkDevice _device,
220 VkPipeline _pipeline,
221 const VkAllocationCallbacks* pAllocator)
222 {
223 ANV_FROM_HANDLE(anv_device, device, _device);
224 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
225
226 if (!pipeline)
227 return;
228
229 anv_reloc_list_finish(&pipeline->batch_relocs,
230 pAllocator ? pAllocator : &device->alloc);
231 if (pipeline->blend_state.map)
232 anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
233
234 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
235 if (pipeline->shaders[s])
236 anv_shader_bin_unref(device, pipeline->shaders[s]);
237 }
238
239 vk_free2(&device->alloc, pAllocator, pipeline);
240 }
241
242 static const uint32_t vk_to_gen_primitive_type[] = {
243 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
244 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
245 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
246 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
247 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
248 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
249 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
250 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
251 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
252 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
253 };
254
255 static void
256 populate_sampler_prog_key(const struct gen_device_info *devinfo,
257 struct brw_sampler_prog_key_data *key)
258 {
259 /* Almost all multisampled textures are compressed. The only time when we
260 * don't compress a multisampled texture is for 16x MSAA with a surface
261 * width greater than 8k which is a bit of an edge case. Since the sampler
262 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
263 * to tell the compiler to always assume compression.
264 */
265 key->compressed_multisample_layout_mask = ~0;
266
267 /* SkyLake added support for 16x MSAA. With this came a new message for
268 * reading from a 16x MSAA surface with compression. The new message was
269 * needed because now the MCS data is 64 bits instead of 32 or lower as is
270 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
271 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
272 * so we can just use it unconditionally. This may not be quite as
273 * efficient but it saves us from recompiling.
274 */
275 if (devinfo->gen >= 9)
276 key->msaa_16 = ~0;
277
278 /* XXX: Handle texture swizzle on HSW- */
279 for (int i = 0; i < MAX_SAMPLERS; i++) {
280 /* Assume color sampler, no swizzling. (Works for BDW+) */
281 key->swizzles[i] = SWIZZLE_XYZW;
282 }
283 }
284
285 static void
286 populate_vs_prog_key(const struct gen_device_info *devinfo,
287 struct brw_vs_prog_key *key)
288 {
289 memset(key, 0, sizeof(*key));
290
291 populate_sampler_prog_key(devinfo, &key->tex);
292
293 /* XXX: Handle vertex input work-arounds */
294
295 /* XXX: Handle sampler_prog_key */
296 }
297
298 static void
299 populate_gs_prog_key(const struct gen_device_info *devinfo,
300 struct brw_gs_prog_key *key)
301 {
302 memset(key, 0, sizeof(*key));
303
304 populate_sampler_prog_key(devinfo, &key->tex);
305 }
306
307 static void
308 populate_wm_prog_key(const struct anv_pipeline *pipeline,
309 const VkGraphicsPipelineCreateInfo *info,
310 struct brw_wm_prog_key *key)
311 {
312 const struct gen_device_info *devinfo = &pipeline->device->info;
313
314 memset(key, 0, sizeof(*key));
315
316 populate_sampler_prog_key(devinfo, &key->tex);
317
318 /* TODO: we could set this to 0 based on the information in nir_shader, but
319 * this function is called before spirv_to_nir. */
320 const struct brw_vue_map *vue_map =
321 &anv_pipeline_get_last_vue_prog_data(pipeline)->vue_map;
322 key->input_slots_valid = vue_map->slots_valid;
323
324 /* Vulkan doesn't specify a default */
325 key->high_quality_derivatives = false;
326
327 /* XXX Vulkan doesn't appear to specify */
328 key->clamp_fragment_color = false;
329
330 key->nr_color_regions = pipeline->subpass->color_count;
331
332 key->replicate_alpha = key->nr_color_regions > 1 &&
333 info->pMultisampleState &&
334 info->pMultisampleState->alphaToCoverageEnable;
335
336 if (info->pMultisampleState) {
337 /* We should probably pull this out of the shader, but it's fairly
338 * harmless to compute it and then let dead-code take care of it.
339 */
340 if (info->pMultisampleState->rasterizationSamples > 1) {
341 key->persample_interp =
342 (info->pMultisampleState->minSampleShading *
343 info->pMultisampleState->rasterizationSamples) > 1;
344 key->multisample_fbo = true;
345 }
346
347 key->frag_coord_adds_sample_pos =
348 info->pMultisampleState->sampleShadingEnable;
349 }
350 }
351
352 static void
353 populate_cs_prog_key(const struct gen_device_info *devinfo,
354 struct brw_cs_prog_key *key)
355 {
356 memset(key, 0, sizeof(*key));
357
358 populate_sampler_prog_key(devinfo, &key->tex);
359 }
360
361 static void
362 anv_pipeline_hash_shader(struct anv_pipeline *pipeline,
363 struct anv_pipeline_layout *layout,
364 struct anv_shader_module *module,
365 const char *entrypoint,
366 gl_shader_stage stage,
367 const VkSpecializationInfo *spec_info,
368 const void *key, size_t key_size,
369 unsigned char *sha1_out)
370 {
371 struct mesa_sha1 ctx;
372
373 _mesa_sha1_init(&ctx);
374 if (stage != MESA_SHADER_COMPUTE) {
375 _mesa_sha1_update(&ctx, &pipeline->subpass->view_mask,
376 sizeof(pipeline->subpass->view_mask));
377 }
378 if (layout)
379 _mesa_sha1_update(&ctx, layout->sha1, sizeof(layout->sha1));
380 _mesa_sha1_update(&ctx, module->sha1, sizeof(module->sha1));
381 _mesa_sha1_update(&ctx, entrypoint, strlen(entrypoint));
382 _mesa_sha1_update(&ctx, &stage, sizeof(stage));
383 if (spec_info) {
384 _mesa_sha1_update(&ctx, spec_info->pMapEntries,
385 spec_info->mapEntryCount * sizeof(*spec_info->pMapEntries));
386 _mesa_sha1_update(&ctx, spec_info->pData, spec_info->dataSize);
387 }
388 _mesa_sha1_update(&ctx, key, key_size);
389 _mesa_sha1_final(&ctx, sha1_out);
390 }
391
392 static nir_shader *
393 anv_pipeline_compile(struct anv_pipeline *pipeline,
394 void *mem_ctx,
395 struct anv_pipeline_layout *layout,
396 struct anv_shader_module *module,
397 const char *entrypoint,
398 gl_shader_stage stage,
399 const VkSpecializationInfo *spec_info,
400 struct brw_stage_prog_data *prog_data,
401 struct anv_pipeline_bind_map *map)
402 {
403 const struct brw_compiler *compiler =
404 pipeline->device->instance->physicalDevice.compiler;
405
406 nir_shader *nir = anv_shader_compile_to_nir(pipeline, mem_ctx,
407 module, entrypoint, stage,
408 spec_info);
409 if (nir == NULL)
410 return NULL;
411
412 NIR_PASS_V(nir, anv_nir_lower_ycbcr_textures, layout);
413
414 NIR_PASS_V(nir, anv_nir_lower_push_constants);
415
416 if (stage != MESA_SHADER_COMPUTE)
417 NIR_PASS_V(nir, anv_nir_lower_multiview, pipeline->subpass->view_mask);
418
419 if (stage == MESA_SHADER_COMPUTE)
420 prog_data->total_shared = nir->num_shared;
421
422 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
423
424 if (nir->num_uniforms > 0) {
425 assert(prog_data->nr_params == 0);
426
427 /* If the shader uses any push constants at all, we'll just give
428 * them the maximum possible number
429 */
430 assert(nir->num_uniforms <= MAX_PUSH_CONSTANTS_SIZE);
431 nir->num_uniforms = MAX_PUSH_CONSTANTS_SIZE;
432 prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
433 prog_data->param = ralloc_array(mem_ctx, uint32_t, prog_data->nr_params);
434
435 /* We now set the param values to be offsets into a
436 * anv_push_constant_data structure. Since the compiler doesn't
437 * actually dereference any of the gl_constant_value pointers in the
438 * params array, it doesn't really matter what we put here.
439 */
440 struct anv_push_constants *null_data = NULL;
441 /* Fill out the push constants section of the param array */
442 for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++) {
443 prog_data->param[i] = ANV_PARAM_PUSH(
444 (uintptr_t)&null_data->client_data[i * sizeof(float)]);
445 }
446 }
447
448 if (nir->info.num_ssbos > 0 || nir->info.num_images > 0)
449 pipeline->needs_data_cache = true;
450
451 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
452 if (layout)
453 anv_nir_apply_pipeline_layout(pipeline, layout, nir, prog_data, map);
454
455 if (stage != MESA_SHADER_COMPUTE)
456 brw_nir_analyze_ubo_ranges(compiler, nir, prog_data->ubo_ranges);
457
458 assert(nir->num_uniforms == prog_data->nr_params * 4);
459
460 return nir;
461 }
462
463 static void
464 anv_fill_binding_table(struct brw_stage_prog_data *prog_data, unsigned bias)
465 {
466 prog_data->binding_table.size_bytes = 0;
467 prog_data->binding_table.texture_start = bias;
468 prog_data->binding_table.gather_texture_start = bias;
469 prog_data->binding_table.ubo_start = bias;
470 prog_data->binding_table.ssbo_start = bias;
471 prog_data->binding_table.image_start = bias;
472 }
473
474 static struct anv_shader_bin *
475 anv_pipeline_upload_kernel(struct anv_pipeline *pipeline,
476 struct anv_pipeline_cache *cache,
477 const void *key_data, uint32_t key_size,
478 const void *kernel_data, uint32_t kernel_size,
479 const struct brw_stage_prog_data *prog_data,
480 uint32_t prog_data_size,
481 const struct anv_pipeline_bind_map *bind_map)
482 {
483 if (cache) {
484 return anv_pipeline_cache_upload_kernel(cache, key_data, key_size,
485 kernel_data, kernel_size,
486 prog_data, prog_data_size,
487 bind_map);
488 } else {
489 return anv_shader_bin_create(pipeline->device, key_data, key_size,
490 kernel_data, kernel_size,
491 prog_data, prog_data_size,
492 prog_data->param, bind_map);
493 }
494 }
495
496
497 static void
498 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
499 gl_shader_stage stage,
500 struct anv_shader_bin *shader)
501 {
502 pipeline->shaders[stage] = shader;
503 }
504
505 static VkResult
506 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
507 struct anv_pipeline_cache *cache,
508 const VkGraphicsPipelineCreateInfo *info,
509 struct anv_shader_module *module,
510 const char *entrypoint,
511 const VkSpecializationInfo *spec_info)
512 {
513 const struct brw_compiler *compiler =
514 pipeline->device->instance->physicalDevice.compiler;
515 struct brw_vs_prog_key key;
516 struct anv_shader_bin *bin = NULL;
517 unsigned char sha1[20];
518
519 populate_vs_prog_key(&pipeline->device->info, &key);
520
521 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
522
523 if (cache) {
524 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
525 MESA_SHADER_VERTEX, spec_info,
526 &key, sizeof(key), sha1);
527 bin = anv_pipeline_cache_search(cache, sha1, 20);
528 }
529
530 if (bin == NULL) {
531 struct brw_vs_prog_data prog_data = {};
532 struct anv_pipeline_binding surface_to_descriptor[256];
533 struct anv_pipeline_binding sampler_to_descriptor[256];
534
535 struct anv_pipeline_bind_map map = {
536 .surface_to_descriptor = surface_to_descriptor,
537 .sampler_to_descriptor = sampler_to_descriptor
538 };
539
540 void *mem_ctx = ralloc_context(NULL);
541
542 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
543 module, entrypoint,
544 MESA_SHADER_VERTEX, spec_info,
545 &prog_data.base.base, &map);
546 if (nir == NULL) {
547 ralloc_free(mem_ctx);
548 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
549 }
550
551 anv_fill_binding_table(&prog_data.base.base, 0);
552
553 brw_compute_vue_map(&pipeline->device->info,
554 &prog_data.base.vue_map,
555 nir->info.outputs_written,
556 nir->info.separate_shader);
557
558 const unsigned *shader_code =
559 brw_compile_vs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
560 -1, NULL);
561 if (shader_code == NULL) {
562 ralloc_free(mem_ctx);
563 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
564 }
565
566 unsigned code_size = prog_data.base.base.program_size;
567 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
568 shader_code, code_size,
569 &prog_data.base.base, sizeof(prog_data),
570 &map);
571 if (!bin) {
572 ralloc_free(mem_ctx);
573 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
574 }
575
576 ralloc_free(mem_ctx);
577 }
578
579 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX, bin);
580
581 return VK_SUCCESS;
582 }
583
584 static void
585 merge_tess_info(struct shader_info *tes_info,
586 const struct shader_info *tcs_info)
587 {
588 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
589 *
590 * "PointMode. Controls generation of points rather than triangles
591 * or lines. This functionality defaults to disabled, and is
592 * enabled if either shader stage includes the execution mode.
593 *
594 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
595 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
596 * and OutputVertices, it says:
597 *
598 * "One mode must be set in at least one of the tessellation
599 * shader stages."
600 *
601 * So, the fields can be set in either the TCS or TES, but they must
602 * agree if set in both. Our backend looks at TES, so bitwise-or in
603 * the values from the TCS.
604 */
605 assert(tcs_info->tess.tcs_vertices_out == 0 ||
606 tes_info->tess.tcs_vertices_out == 0 ||
607 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
608 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
609
610 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
611 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
612 tcs_info->tess.spacing == tes_info->tess.spacing);
613 tes_info->tess.spacing |= tcs_info->tess.spacing;
614
615 assert(tcs_info->tess.primitive_mode == 0 ||
616 tes_info->tess.primitive_mode == 0 ||
617 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
618 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
619 tes_info->tess.ccw |= tcs_info->tess.ccw;
620 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
621 }
622
623 static VkResult
624 anv_pipeline_compile_tcs_tes(struct anv_pipeline *pipeline,
625 struct anv_pipeline_cache *cache,
626 const VkGraphicsPipelineCreateInfo *info,
627 struct anv_shader_module *tcs_module,
628 const char *tcs_entrypoint,
629 const VkSpecializationInfo *tcs_spec_info,
630 struct anv_shader_module *tes_module,
631 const char *tes_entrypoint,
632 const VkSpecializationInfo *tes_spec_info)
633 {
634 const struct gen_device_info *devinfo = &pipeline->device->info;
635 const struct brw_compiler *compiler =
636 pipeline->device->instance->physicalDevice.compiler;
637 struct brw_tcs_prog_key tcs_key = {};
638 struct brw_tes_prog_key tes_key = {};
639 struct anv_shader_bin *tcs_bin = NULL;
640 struct anv_shader_bin *tes_bin = NULL;
641 unsigned char tcs_sha1[40];
642 unsigned char tes_sha1[40];
643
644 populate_sampler_prog_key(&pipeline->device->info, &tcs_key.tex);
645 populate_sampler_prog_key(&pipeline->device->info, &tes_key.tex);
646 tcs_key.input_vertices = info->pTessellationState->patchControlPoints;
647
648 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
649
650 if (cache) {
651 anv_pipeline_hash_shader(pipeline, layout, tcs_module, tcs_entrypoint,
652 MESA_SHADER_TESS_CTRL, tcs_spec_info,
653 &tcs_key, sizeof(tcs_key), tcs_sha1);
654 anv_pipeline_hash_shader(pipeline, layout, tes_module, tes_entrypoint,
655 MESA_SHADER_TESS_EVAL, tes_spec_info,
656 &tes_key, sizeof(tes_key), tes_sha1);
657 memcpy(&tcs_sha1[20], tes_sha1, 20);
658 memcpy(&tes_sha1[20], tcs_sha1, 20);
659 tcs_bin = anv_pipeline_cache_search(cache, tcs_sha1, sizeof(tcs_sha1));
660 tes_bin = anv_pipeline_cache_search(cache, tes_sha1, sizeof(tes_sha1));
661 }
662
663 if (tcs_bin == NULL || tes_bin == NULL) {
664 struct brw_tcs_prog_data tcs_prog_data = {};
665 struct brw_tes_prog_data tes_prog_data = {};
666 struct anv_pipeline_binding tcs_surface_to_descriptor[256];
667 struct anv_pipeline_binding tcs_sampler_to_descriptor[256];
668 struct anv_pipeline_binding tes_surface_to_descriptor[256];
669 struct anv_pipeline_binding tes_sampler_to_descriptor[256];
670
671 struct anv_pipeline_bind_map tcs_map = {
672 .surface_to_descriptor = tcs_surface_to_descriptor,
673 .sampler_to_descriptor = tcs_sampler_to_descriptor
674 };
675 struct anv_pipeline_bind_map tes_map = {
676 .surface_to_descriptor = tes_surface_to_descriptor,
677 .sampler_to_descriptor = tes_sampler_to_descriptor
678 };
679
680 void *mem_ctx = ralloc_context(NULL);
681
682 nir_shader *tcs_nir =
683 anv_pipeline_compile(pipeline, mem_ctx, layout,
684 tcs_module, tcs_entrypoint,
685 MESA_SHADER_TESS_CTRL, tcs_spec_info,
686 &tcs_prog_data.base.base, &tcs_map);
687 nir_shader *tes_nir =
688 anv_pipeline_compile(pipeline, mem_ctx, layout,
689 tes_module, tes_entrypoint,
690 MESA_SHADER_TESS_EVAL, tes_spec_info,
691 &tes_prog_data.base.base, &tes_map);
692 if (tcs_nir == NULL || tes_nir == NULL) {
693 ralloc_free(mem_ctx);
694 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
695 }
696
697 nir_lower_tes_patch_vertices(tes_nir,
698 tcs_nir->info.tess.tcs_vertices_out);
699
700 /* Copy TCS info into the TES info */
701 merge_tess_info(&tes_nir->info, &tcs_nir->info);
702
703 anv_fill_binding_table(&tcs_prog_data.base.base, 0);
704 anv_fill_binding_table(&tes_prog_data.base.base, 0);
705
706 /* Whacking the key after cache lookup is a bit sketchy, but all of
707 * this comes from the SPIR-V, which is part of the hash used for the
708 * pipeline cache. So it should be safe.
709 */
710 tcs_key.tes_primitive_mode = tes_nir->info.tess.primitive_mode;
711 tcs_key.outputs_written = tcs_nir->info.outputs_written;
712 tcs_key.patch_outputs_written = tcs_nir->info.patch_outputs_written;
713 tcs_key.quads_workaround =
714 devinfo->gen < 9 &&
715 tes_nir->info.tess.primitive_mode == 7 /* GL_QUADS */ &&
716 tes_nir->info.tess.spacing == TESS_SPACING_EQUAL;
717
718 tes_key.inputs_read = tcs_key.outputs_written;
719 tes_key.patch_inputs_read = tcs_key.patch_outputs_written;
720
721 const int shader_time_index = -1;
722 const unsigned *shader_code;
723
724 shader_code =
725 brw_compile_tcs(compiler, NULL, mem_ctx, &tcs_key, &tcs_prog_data,
726 tcs_nir, shader_time_index, NULL);
727 if (shader_code == NULL) {
728 ralloc_free(mem_ctx);
729 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
730 }
731
732 unsigned code_size = tcs_prog_data.base.base.program_size;
733 tcs_bin = anv_pipeline_upload_kernel(pipeline, cache,
734 tcs_sha1, sizeof(tcs_sha1),
735 shader_code, code_size,
736 &tcs_prog_data.base.base,
737 sizeof(tcs_prog_data),
738 &tcs_map);
739 if (!tcs_bin) {
740 ralloc_free(mem_ctx);
741 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
742 }
743
744 shader_code =
745 brw_compile_tes(compiler, NULL, mem_ctx, &tes_key,
746 &tcs_prog_data.base.vue_map, &tes_prog_data, tes_nir,
747 NULL, shader_time_index, NULL);
748 if (shader_code == NULL) {
749 ralloc_free(mem_ctx);
750 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
751 }
752
753 code_size = tes_prog_data.base.base.program_size;
754 tes_bin = anv_pipeline_upload_kernel(pipeline, cache,
755 tes_sha1, sizeof(tes_sha1),
756 shader_code, code_size,
757 &tes_prog_data.base.base,
758 sizeof(tes_prog_data),
759 &tes_map);
760 if (!tes_bin) {
761 ralloc_free(mem_ctx);
762 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
763 }
764
765 ralloc_free(mem_ctx);
766 }
767
768 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_TESS_CTRL, tcs_bin);
769 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_TESS_EVAL, tes_bin);
770
771 return VK_SUCCESS;
772 }
773
774 static VkResult
775 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
776 struct anv_pipeline_cache *cache,
777 const VkGraphicsPipelineCreateInfo *info,
778 struct anv_shader_module *module,
779 const char *entrypoint,
780 const VkSpecializationInfo *spec_info)
781 {
782 const struct brw_compiler *compiler =
783 pipeline->device->instance->physicalDevice.compiler;
784 struct brw_gs_prog_key key;
785 struct anv_shader_bin *bin = NULL;
786 unsigned char sha1[20];
787
788 populate_gs_prog_key(&pipeline->device->info, &key);
789
790 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
791
792 if (cache) {
793 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
794 MESA_SHADER_GEOMETRY, spec_info,
795 &key, sizeof(key), sha1);
796 bin = anv_pipeline_cache_search(cache, sha1, 20);
797 }
798
799 if (bin == NULL) {
800 struct brw_gs_prog_data prog_data = {};
801 struct anv_pipeline_binding surface_to_descriptor[256];
802 struct anv_pipeline_binding sampler_to_descriptor[256];
803
804 struct anv_pipeline_bind_map map = {
805 .surface_to_descriptor = surface_to_descriptor,
806 .sampler_to_descriptor = sampler_to_descriptor
807 };
808
809 void *mem_ctx = ralloc_context(NULL);
810
811 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
812 module, entrypoint,
813 MESA_SHADER_GEOMETRY, spec_info,
814 &prog_data.base.base, &map);
815 if (nir == NULL) {
816 ralloc_free(mem_ctx);
817 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
818 }
819
820 anv_fill_binding_table(&prog_data.base.base, 0);
821
822 brw_compute_vue_map(&pipeline->device->info,
823 &prog_data.base.vue_map,
824 nir->info.outputs_written,
825 nir->info.separate_shader);
826
827 const unsigned *shader_code =
828 brw_compile_gs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
829 NULL, -1, NULL);
830 if (shader_code == NULL) {
831 ralloc_free(mem_ctx);
832 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
833 }
834
835 /* TODO: SIMD8 GS */
836 const unsigned code_size = prog_data.base.base.program_size;
837 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
838 shader_code, code_size,
839 &prog_data.base.base, sizeof(prog_data),
840 &map);
841 if (!bin) {
842 ralloc_free(mem_ctx);
843 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
844 }
845
846 ralloc_free(mem_ctx);
847 }
848
849 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY, bin);
850
851 return VK_SUCCESS;
852 }
853
854 static VkResult
855 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
856 struct anv_pipeline_cache *cache,
857 const VkGraphicsPipelineCreateInfo *info,
858 struct anv_shader_module *module,
859 const char *entrypoint,
860 const VkSpecializationInfo *spec_info)
861 {
862 const struct brw_compiler *compiler =
863 pipeline->device->instance->physicalDevice.compiler;
864 struct brw_wm_prog_key key;
865 struct anv_shader_bin *bin = NULL;
866 unsigned char sha1[20];
867
868 populate_wm_prog_key(pipeline, info, &key);
869
870 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
871
872 if (cache) {
873 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
874 MESA_SHADER_FRAGMENT, spec_info,
875 &key, sizeof(key), sha1);
876 bin = anv_pipeline_cache_search(cache, sha1, 20);
877 }
878
879 if (bin == NULL) {
880 struct brw_wm_prog_data prog_data = {};
881 struct anv_pipeline_binding surface_to_descriptor[256];
882 struct anv_pipeline_binding sampler_to_descriptor[256];
883
884 struct anv_pipeline_bind_map map = {
885 .surface_to_descriptor = surface_to_descriptor + 8,
886 .sampler_to_descriptor = sampler_to_descriptor
887 };
888
889 void *mem_ctx = ralloc_context(NULL);
890
891 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
892 module, entrypoint,
893 MESA_SHADER_FRAGMENT, spec_info,
894 &prog_data.base, &map);
895 if (nir == NULL) {
896 ralloc_free(mem_ctx);
897 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
898 }
899
900 unsigned num_rts = 0;
901 const int max_rt = FRAG_RESULT_DATA7 - FRAG_RESULT_DATA0 + 1;
902 struct anv_pipeline_binding rt_bindings[max_rt];
903 nir_function_impl *impl = nir_shader_get_entrypoint(nir);
904 int rt_to_bindings[max_rt];
905 memset(rt_to_bindings, -1, sizeof(rt_to_bindings));
906 bool rt_used[max_rt];
907 memset(rt_used, 0, sizeof(rt_used));
908
909 /* Flag used render targets */
910 nir_foreach_variable_safe(var, &nir->outputs) {
911 if (var->data.location < FRAG_RESULT_DATA0)
912 continue;
913
914 const unsigned rt = var->data.location - FRAG_RESULT_DATA0;
915 /* Out-of-bounds */
916 if (rt >= key.nr_color_regions)
917 continue;
918
919 const unsigned array_len =
920 glsl_type_is_array(var->type) ? glsl_get_length(var->type) : 1;
921 assert(rt + array_len <= max_rt);
922
923 for (unsigned i = 0; i < array_len; i++)
924 rt_used[rt + i] = true;
925 }
926
927 /* Set new, compacted, location */
928 for (unsigned i = 0; i < max_rt; i++) {
929 if (!rt_used[i])
930 continue;
931
932 rt_to_bindings[i] = num_rts;
933 rt_bindings[rt_to_bindings[i]] = (struct anv_pipeline_binding) {
934 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
935 .binding = 0,
936 .index = i,
937 };
938 num_rts++;
939 }
940
941 nir_foreach_variable_safe(var, &nir->outputs) {
942 if (var->data.location < FRAG_RESULT_DATA0)
943 continue;
944
945 const unsigned rt = var->data.location - FRAG_RESULT_DATA0;
946 if (rt >= key.nr_color_regions) {
947 /* Out-of-bounds, throw it away */
948 var->data.mode = nir_var_local;
949 exec_node_remove(&var->node);
950 exec_list_push_tail(&impl->locals, &var->node);
951 continue;
952 }
953
954 /* Give it the new location */
955 assert(rt_to_bindings[rt] != -1);
956 var->data.location = rt_to_bindings[rt] + FRAG_RESULT_DATA0;
957 }
958
959 if (num_rts == 0) {
960 /* If we have no render targets, we need a null render target */
961 rt_bindings[0] = (struct anv_pipeline_binding) {
962 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
963 .binding = 0,
964 .index = UINT32_MAX,
965 };
966 num_rts = 1;
967 }
968
969 assert(num_rts <= max_rt);
970 map.surface_to_descriptor -= num_rts;
971 map.surface_count += num_rts;
972 assert(map.surface_count <= 256);
973 memcpy(map.surface_to_descriptor, rt_bindings,
974 num_rts * sizeof(*rt_bindings));
975
976 anv_fill_binding_table(&prog_data.base, num_rts);
977
978 const unsigned *shader_code =
979 brw_compile_fs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
980 NULL, -1, -1, true, false, NULL, NULL);
981 if (shader_code == NULL) {
982 ralloc_free(mem_ctx);
983 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
984 }
985
986 unsigned code_size = prog_data.base.program_size;
987 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
988 shader_code, code_size,
989 &prog_data.base, sizeof(prog_data),
990 &map);
991 if (!bin) {
992 ralloc_free(mem_ctx);
993 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
994 }
995
996 ralloc_free(mem_ctx);
997 }
998
999 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT, bin);
1000
1001 return VK_SUCCESS;
1002 }
1003
1004 VkResult
1005 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
1006 struct anv_pipeline_cache *cache,
1007 const VkComputePipelineCreateInfo *info,
1008 struct anv_shader_module *module,
1009 const char *entrypoint,
1010 const VkSpecializationInfo *spec_info)
1011 {
1012 const struct brw_compiler *compiler =
1013 pipeline->device->instance->physicalDevice.compiler;
1014 struct brw_cs_prog_key key;
1015 struct anv_shader_bin *bin = NULL;
1016 unsigned char sha1[20];
1017
1018 populate_cs_prog_key(&pipeline->device->info, &key);
1019
1020 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
1021
1022 if (cache) {
1023 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
1024 MESA_SHADER_COMPUTE, spec_info,
1025 &key, sizeof(key), sha1);
1026 bin = anv_pipeline_cache_search(cache, sha1, 20);
1027 }
1028
1029 if (bin == NULL) {
1030 struct brw_cs_prog_data prog_data = {};
1031 struct anv_pipeline_binding surface_to_descriptor[256];
1032 struct anv_pipeline_binding sampler_to_descriptor[256];
1033
1034 struct anv_pipeline_bind_map map = {
1035 .surface_to_descriptor = surface_to_descriptor,
1036 .sampler_to_descriptor = sampler_to_descriptor
1037 };
1038
1039 void *mem_ctx = ralloc_context(NULL);
1040
1041 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
1042 module, entrypoint,
1043 MESA_SHADER_COMPUTE, spec_info,
1044 &prog_data.base, &map);
1045 if (nir == NULL) {
1046 ralloc_free(mem_ctx);
1047 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1048 }
1049
1050 NIR_PASS_V(nir, anv_nir_add_base_work_group_id, &prog_data);
1051
1052 anv_fill_binding_table(&prog_data.base, 1);
1053
1054 const unsigned *shader_code =
1055 brw_compile_cs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
1056 -1, NULL);
1057 if (shader_code == NULL) {
1058 ralloc_free(mem_ctx);
1059 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1060 }
1061
1062 const unsigned code_size = prog_data.base.program_size;
1063 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
1064 shader_code, code_size,
1065 &prog_data.base, sizeof(prog_data),
1066 &map);
1067 if (!bin) {
1068 ralloc_free(mem_ctx);
1069 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1070 }
1071
1072 ralloc_free(mem_ctx);
1073 }
1074
1075 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE, bin);
1076
1077 return VK_SUCCESS;
1078 }
1079
1080 /**
1081 * Copy pipeline state not marked as dynamic.
1082 * Dynamic state is pipeline state which hasn't been provided at pipeline
1083 * creation time, but is dynamically provided afterwards using various
1084 * vkCmdSet* functions.
1085 *
1086 * The set of state considered "non_dynamic" is determined by the pieces of
1087 * state that have their corresponding VkDynamicState enums omitted from
1088 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1089 *
1090 * @param[out] pipeline Destination non_dynamic state.
1091 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1092 */
1093 static void
1094 copy_non_dynamic_state(struct anv_pipeline *pipeline,
1095 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1096 {
1097 anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
1098 struct anv_subpass *subpass = pipeline->subpass;
1099
1100 pipeline->dynamic_state = default_dynamic_state;
1101
1102 if (pCreateInfo->pDynamicState) {
1103 /* Remove all of the states that are marked as dynamic */
1104 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1105 for (uint32_t s = 0; s < count; s++)
1106 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1107 }
1108
1109 struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
1110
1111 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1112 *
1113 * pViewportState is [...] NULL if the pipeline
1114 * has rasterization disabled.
1115 */
1116 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1117 assert(pCreateInfo->pViewportState);
1118
1119 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1120 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1121 typed_memcpy(dynamic->viewport.viewports,
1122 pCreateInfo->pViewportState->pViewports,
1123 pCreateInfo->pViewportState->viewportCount);
1124 }
1125
1126 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1127 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1128 typed_memcpy(dynamic->scissor.scissors,
1129 pCreateInfo->pViewportState->pScissors,
1130 pCreateInfo->pViewportState->scissorCount);
1131 }
1132 }
1133
1134 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1135 assert(pCreateInfo->pRasterizationState);
1136 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1137 }
1138
1139 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1140 assert(pCreateInfo->pRasterizationState);
1141 dynamic->depth_bias.bias =
1142 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1143 dynamic->depth_bias.clamp =
1144 pCreateInfo->pRasterizationState->depthBiasClamp;
1145 dynamic->depth_bias.slope =
1146 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1147 }
1148
1149 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1150 *
1151 * pColorBlendState is [...] NULL if the pipeline has rasterization
1152 * disabled or if the subpass of the render pass the pipeline is
1153 * created against does not use any color attachments.
1154 */
1155 bool uses_color_att = false;
1156 for (unsigned i = 0; i < subpass->color_count; ++i) {
1157 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1158 uses_color_att = true;
1159 break;
1160 }
1161 }
1162
1163 if (uses_color_att &&
1164 !pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1165 assert(pCreateInfo->pColorBlendState);
1166
1167 if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
1168 typed_memcpy(dynamic->blend_constants,
1169 pCreateInfo->pColorBlendState->blendConstants, 4);
1170 }
1171
1172 /* If there is no depthstencil attachment, then don't read
1173 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1174 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1175 * no need to override the depthstencil defaults in
1176 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1177 *
1178 * Section 9.2 of the Vulkan 1.0.15 spec says:
1179 *
1180 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1181 * disabled or if the subpass of the render pass the pipeline is created
1182 * against does not use a depth/stencil attachment.
1183 */
1184 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1185 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1186 assert(pCreateInfo->pDepthStencilState);
1187
1188 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1189 dynamic->depth_bounds.min =
1190 pCreateInfo->pDepthStencilState->minDepthBounds;
1191 dynamic->depth_bounds.max =
1192 pCreateInfo->pDepthStencilState->maxDepthBounds;
1193 }
1194
1195 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1196 dynamic->stencil_compare_mask.front =
1197 pCreateInfo->pDepthStencilState->front.compareMask;
1198 dynamic->stencil_compare_mask.back =
1199 pCreateInfo->pDepthStencilState->back.compareMask;
1200 }
1201
1202 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1203 dynamic->stencil_write_mask.front =
1204 pCreateInfo->pDepthStencilState->front.writeMask;
1205 dynamic->stencil_write_mask.back =
1206 pCreateInfo->pDepthStencilState->back.writeMask;
1207 }
1208
1209 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1210 dynamic->stencil_reference.front =
1211 pCreateInfo->pDepthStencilState->front.reference;
1212 dynamic->stencil_reference.back =
1213 pCreateInfo->pDepthStencilState->back.reference;
1214 }
1215 }
1216
1217 pipeline->dynamic_state_mask = states;
1218 }
1219
1220 static void
1221 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
1222 {
1223 #ifdef DEBUG
1224 struct anv_render_pass *renderpass = NULL;
1225 struct anv_subpass *subpass = NULL;
1226
1227 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1228 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1229 */
1230 assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
1231
1232 renderpass = anv_render_pass_from_handle(info->renderPass);
1233 assert(renderpass);
1234
1235 assert(info->subpass < renderpass->subpass_count);
1236 subpass = &renderpass->subpasses[info->subpass];
1237
1238 assert(info->stageCount >= 1);
1239 assert(info->pVertexInputState);
1240 assert(info->pInputAssemblyState);
1241 assert(info->pRasterizationState);
1242 if (!info->pRasterizationState->rasterizerDiscardEnable) {
1243 assert(info->pViewportState);
1244 assert(info->pMultisampleState);
1245
1246 if (subpass && subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
1247 assert(info->pDepthStencilState);
1248
1249 if (subpass && subpass->color_count > 0)
1250 assert(info->pColorBlendState);
1251 }
1252
1253 for (uint32_t i = 0; i < info->stageCount; ++i) {
1254 switch (info->pStages[i].stage) {
1255 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
1256 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
1257 assert(info->pTessellationState);
1258 break;
1259 default:
1260 break;
1261 }
1262 }
1263 #endif
1264 }
1265
1266 /**
1267 * Calculate the desired L3 partitioning based on the current state of the
1268 * pipeline. For now this simply returns the conservative defaults calculated
1269 * by get_default_l3_weights(), but we could probably do better by gathering
1270 * more statistics from the pipeline state (e.g. guess of expected URB usage
1271 * and bound surfaces), or by using feed-back from performance counters.
1272 */
1273 void
1274 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm)
1275 {
1276 const struct gen_device_info *devinfo = &pipeline->device->info;
1277
1278 const struct gen_l3_weights w =
1279 gen_get_default_l3_weights(devinfo, pipeline->needs_data_cache, needs_slm);
1280
1281 pipeline->urb.l3_config = gen_get_l3_config(devinfo, w);
1282 pipeline->urb.total_size =
1283 gen_get_l3_config_urb_size(devinfo, pipeline->urb.l3_config);
1284 }
1285
1286 VkResult
1287 anv_pipeline_init(struct anv_pipeline *pipeline,
1288 struct anv_device *device,
1289 struct anv_pipeline_cache *cache,
1290 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1291 const VkAllocationCallbacks *alloc)
1292 {
1293 VkResult result;
1294
1295 anv_pipeline_validate_create_info(pCreateInfo);
1296
1297 if (alloc == NULL)
1298 alloc = &device->alloc;
1299
1300 pipeline->device = device;
1301
1302 ANV_FROM_HANDLE(anv_render_pass, render_pass, pCreateInfo->renderPass);
1303 assert(pCreateInfo->subpass < render_pass->subpass_count);
1304 pipeline->subpass = &render_pass->subpasses[pCreateInfo->subpass];
1305
1306 result = anv_reloc_list_init(&pipeline->batch_relocs, alloc);
1307 if (result != VK_SUCCESS)
1308 return result;
1309
1310 pipeline->batch.alloc = alloc;
1311 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
1312 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
1313 pipeline->batch.relocs = &pipeline->batch_relocs;
1314 pipeline->batch.status = VK_SUCCESS;
1315
1316 copy_non_dynamic_state(pipeline, pCreateInfo);
1317 pipeline->depth_clamp_enable = pCreateInfo->pRasterizationState &&
1318 pCreateInfo->pRasterizationState->depthClampEnable;
1319
1320 pipeline->sample_shading_enable = pCreateInfo->pMultisampleState &&
1321 pCreateInfo->pMultisampleState->sampleShadingEnable;
1322
1323 pipeline->needs_data_cache = false;
1324
1325 /* When we free the pipeline, we detect stages based on the NULL status
1326 * of various prog_data pointers. Make them NULL by default.
1327 */
1328 memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
1329
1330 pipeline->active_stages = 0;
1331
1332 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = {};
1333 struct anv_shader_module *modules[MESA_SHADER_STAGES] = {};
1334 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1335 VkShaderStageFlagBits vk_stage = pCreateInfo->pStages[i].stage;
1336 gl_shader_stage stage = vk_to_mesa_shader_stage(vk_stage);
1337 pStages[stage] = &pCreateInfo->pStages[i];
1338 modules[stage] = anv_shader_module_from_handle(pStages[stage]->module);
1339 pipeline->active_stages |= vk_stage;
1340 }
1341
1342 if (pipeline->active_stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT)
1343 pipeline->active_stages |= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT;
1344
1345 assert(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT);
1346
1347 if (modules[MESA_SHADER_VERTEX]) {
1348 result = anv_pipeline_compile_vs(pipeline, cache, pCreateInfo,
1349 modules[MESA_SHADER_VERTEX],
1350 pStages[MESA_SHADER_VERTEX]->pName,
1351 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo);
1352 if (result != VK_SUCCESS)
1353 goto compile_fail;
1354 }
1355
1356 if (modules[MESA_SHADER_TESS_EVAL]) {
1357 result = anv_pipeline_compile_tcs_tes(pipeline, cache, pCreateInfo,
1358 modules[MESA_SHADER_TESS_CTRL],
1359 pStages[MESA_SHADER_TESS_CTRL]->pName,
1360 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
1361 modules[MESA_SHADER_TESS_EVAL],
1362 pStages[MESA_SHADER_TESS_EVAL]->pName,
1363 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo);
1364 if (result != VK_SUCCESS)
1365 goto compile_fail;
1366 }
1367
1368 if (modules[MESA_SHADER_GEOMETRY]) {
1369 result = anv_pipeline_compile_gs(pipeline, cache, pCreateInfo,
1370 modules[MESA_SHADER_GEOMETRY],
1371 pStages[MESA_SHADER_GEOMETRY]->pName,
1372 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo);
1373 if (result != VK_SUCCESS)
1374 goto compile_fail;
1375 }
1376
1377 if (modules[MESA_SHADER_FRAGMENT]) {
1378 result = anv_pipeline_compile_fs(pipeline, cache, pCreateInfo,
1379 modules[MESA_SHADER_FRAGMENT],
1380 pStages[MESA_SHADER_FRAGMENT]->pName,
1381 pStages[MESA_SHADER_FRAGMENT]->pSpecializationInfo);
1382 if (result != VK_SUCCESS)
1383 goto compile_fail;
1384 }
1385
1386 assert(pipeline->shaders[MESA_SHADER_VERTEX]);
1387
1388 anv_pipeline_setup_l3_config(pipeline, false);
1389
1390 const VkPipelineVertexInputStateCreateInfo *vi_info =
1391 pCreateInfo->pVertexInputState;
1392
1393 const uint64_t inputs_read = get_vs_prog_data(pipeline)->inputs_read;
1394
1395 pipeline->vb_used = 0;
1396 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1397 const VkVertexInputAttributeDescription *desc =
1398 &vi_info->pVertexAttributeDescriptions[i];
1399
1400 if (inputs_read & (1ull << (VERT_ATTRIB_GENERIC0 + desc->location)))
1401 pipeline->vb_used |= 1 << desc->binding;
1402 }
1403
1404 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1405 const VkVertexInputBindingDescription *desc =
1406 &vi_info->pVertexBindingDescriptions[i];
1407
1408 pipeline->binding_stride[desc->binding] = desc->stride;
1409
1410 /* Step rate is programmed per vertex element (attribute), not
1411 * binding. Set up a map of which bindings step per instance, for
1412 * reference by vertex element setup. */
1413 switch (desc->inputRate) {
1414 default:
1415 case VK_VERTEX_INPUT_RATE_VERTEX:
1416 pipeline->instancing_enable[desc->binding] = false;
1417 break;
1418 case VK_VERTEX_INPUT_RATE_INSTANCE:
1419 pipeline->instancing_enable[desc->binding] = true;
1420 break;
1421 }
1422 }
1423
1424 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1425 pCreateInfo->pInputAssemblyState;
1426 const VkPipelineTessellationStateCreateInfo *tess_info =
1427 pCreateInfo->pTessellationState;
1428 pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1429
1430 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
1431 pipeline->topology = _3DPRIM_PATCHLIST(tess_info->patchControlPoints);
1432 else
1433 pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1434
1435 return VK_SUCCESS;
1436
1437 compile_fail:
1438 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
1439 if (pipeline->shaders[s])
1440 anv_shader_bin_unref(device, pipeline->shaders[s]);
1441 }
1442
1443 anv_reloc_list_finish(&pipeline->batch_relocs, alloc);
1444
1445 return result;
1446 }