2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "anv_private.h"
34 #include "spirv/nir_spirv.h"
36 /* Needed for SWIZZLE macros */
37 #include "program/prog_instruction.h"
41 VkResult
anv_CreateShaderModule(
43 const VkShaderModuleCreateInfo
* pCreateInfo
,
44 const VkAllocationCallbacks
* pAllocator
,
45 VkShaderModule
* pShaderModule
)
47 ANV_FROM_HANDLE(anv_device
, device
, _device
);
48 struct anv_shader_module
*module
;
50 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
51 assert(pCreateInfo
->flags
== 0);
53 module
= anv_alloc2(&device
->alloc
, pAllocator
,
54 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
55 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
57 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
60 module
->size
= pCreateInfo
->codeSize
;
61 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
63 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
65 *pShaderModule
= anv_shader_module_to_handle(module
);
70 void anv_DestroyShaderModule(
72 VkShaderModule _module
,
73 const VkAllocationCallbacks
* pAllocator
)
75 ANV_FROM_HANDLE(anv_device
, device
, _device
);
76 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
78 anv_free2(&device
->alloc
, pAllocator
, module
);
81 #define SPIR_V_MAGIC_NUMBER 0x07230203
83 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
84 * we can't do that yet because we don't have the ability to copy nir.
87 anv_shader_compile_to_nir(struct anv_device
*device
,
88 struct anv_shader_module
*module
,
89 const char *entrypoint_name
,
90 gl_shader_stage stage
,
91 const VkSpecializationInfo
*spec_info
)
93 if (strcmp(entrypoint_name
, "main") != 0) {
94 anv_finishme("Multiple shaders per module not really supported");
97 const struct brw_compiler
*compiler
=
98 device
->instance
->physicalDevice
.compiler
;
99 const nir_shader_compiler_options
*nir_options
=
100 compiler
->glsl_compiler_options
[stage
].NirOptions
;
103 nir_function
*entry_point
;
105 /* Some things such as our meta clear/blit code will give us a NIR
106 * shader directly. In that case, we just ignore the SPIR-V entirely
107 * and just use the NIR shader */
109 nir
->options
= nir_options
;
110 nir_validate_shader(nir
);
112 assert(exec_list_length(&nir
->functions
) == 1);
113 struct exec_node
*node
= exec_list_get_head(&nir
->functions
);
114 entry_point
= exec_node_data(nir_function
, node
, node
);
116 uint32_t *spirv
= (uint32_t *) module
->data
;
117 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
118 assert(module
->size
% 4 == 0);
120 uint32_t num_spec_entries
= 0;
121 struct nir_spirv_specialization
*spec_entries
= NULL
;
122 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
123 num_spec_entries
= spec_info
->mapEntryCount
;
124 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
125 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
126 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
127 const void *data
= spec_info
->pData
+ entry
.offset
;
128 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
130 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
131 spec_entries
[i
].data
= *(const uint32_t *)data
;
135 entry_point
= spirv_to_nir(spirv
, module
->size
/ 4,
136 spec_entries
, num_spec_entries
,
137 stage
, entrypoint_name
, nir_options
);
138 nir
= entry_point
->shader
;
139 assert(nir
->stage
== stage
);
140 nir_validate_shader(nir
);
144 if (stage
== MESA_SHADER_FRAGMENT
) {
145 nir_lower_wpos_center(nir
);
146 nir_validate_shader(nir
);
149 nir_lower_returns(nir
);
150 nir_validate_shader(nir
);
152 nir_inline_functions(nir
);
153 nir_validate_shader(nir
);
155 /* Pick off the single entrypoint that we want */
156 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
157 if (func
!= entry_point
)
158 exec_node_remove(&func
->node
);
160 assert(exec_list_length(&nir
->functions
) == 1);
161 entry_point
->name
= ralloc_strdup(entry_point
, "main");
163 nir_remove_dead_variables(nir
, nir_var_shader_in
);
164 nir_remove_dead_variables(nir
, nir_var_shader_out
);
165 nir_remove_dead_variables(nir
, nir_var_system_value
);
166 nir_validate_shader(nir
);
168 nir_propagate_invariant(nir
);
169 nir_validate_shader(nir
);
171 nir_lower_io_to_temporaries(entry_point
->shader
, entry_point
, true, false);
173 nir_lower_system_values(nir
);
174 nir_validate_shader(nir
);
177 /* Vulkan uses the separate-shader linking model */
178 nir
->info
.separate_shader
= true;
180 nir
= brw_preprocess_nir(compiler
, nir
);
182 nir_shader_gather_info(nir
, entry_point
->impl
);
184 nir_variable_mode indirect_mask
= 0;
185 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectInput
)
186 indirect_mask
|= nir_var_shader_in
;
187 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectTemp
)
188 indirect_mask
|= nir_var_local
;
190 nir_lower_indirect_derefs(nir
, indirect_mask
);
195 void anv_DestroyPipeline(
197 VkPipeline _pipeline
,
198 const VkAllocationCallbacks
* pAllocator
)
200 ANV_FROM_HANDLE(anv_device
, device
, _device
);
201 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
203 anv_reloc_list_finish(&pipeline
->batch_relocs
,
204 pAllocator
? pAllocator
: &device
->alloc
);
205 if (pipeline
->blend_state
.map
)
206 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
207 anv_free2(&device
->alloc
, pAllocator
, pipeline
);
210 static const uint32_t vk_to_gen_primitive_type
[] = {
211 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
212 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
213 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
214 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
215 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
216 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
217 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
218 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
219 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
220 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
221 /* [VK_PRIMITIVE_TOPOLOGY_PATCH_LIST] = _3DPRIM_PATCHLIST_1 */
225 populate_sampler_prog_key(const struct brw_device_info
*devinfo
,
226 struct brw_sampler_prog_key_data
*key
)
228 /* XXX: Handle texture swizzle on HSW- */
229 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
230 /* Assume color sampler, no swizzling. (Works for BDW+) */
231 key
->swizzles
[i
] = SWIZZLE_XYZW
;
236 populate_vs_prog_key(const struct brw_device_info
*devinfo
,
237 struct brw_vs_prog_key
*key
)
239 memset(key
, 0, sizeof(*key
));
241 populate_sampler_prog_key(devinfo
, &key
->tex
);
243 /* XXX: Handle vertex input work-arounds */
245 /* XXX: Handle sampler_prog_key */
249 populate_gs_prog_key(const struct brw_device_info
*devinfo
,
250 struct brw_gs_prog_key
*key
)
252 memset(key
, 0, sizeof(*key
));
254 populate_sampler_prog_key(devinfo
, &key
->tex
);
258 populate_wm_prog_key(const struct brw_device_info
*devinfo
,
259 const VkGraphicsPipelineCreateInfo
*info
,
260 const struct anv_graphics_pipeline_create_info
*extra
,
261 struct brw_wm_prog_key
*key
)
263 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, info
->renderPass
);
265 memset(key
, 0, sizeof(*key
));
267 populate_sampler_prog_key(devinfo
, &key
->tex
);
269 /* TODO: Fill out key->input_slots_valid */
271 /* Vulkan doesn't specify a default */
272 key
->high_quality_derivatives
= false;
274 /* XXX Vulkan doesn't appear to specify */
275 key
->clamp_fragment_color
= false;
277 if (extra
&& extra
->color_attachment_count
>= 0) {
278 key
->nr_color_regions
= extra
->color_attachment_count
;
280 key
->nr_color_regions
=
281 render_pass
->subpasses
[info
->subpass
].color_count
;
284 key
->replicate_alpha
= key
->nr_color_regions
> 1 &&
285 info
->pMultisampleState
&&
286 info
->pMultisampleState
->alphaToCoverageEnable
;
288 if (info
->pMultisampleState
&& info
->pMultisampleState
->rasterizationSamples
> 1) {
289 /* We should probably pull this out of the shader, but it's fairly
290 * harmless to compute it and then let dead-code take care of it.
292 key
->persample_interp
=
293 (info
->pMultisampleState
->minSampleShading
*
294 info
->pMultisampleState
->rasterizationSamples
) > 1;
295 key
->multisample_fbo
= true;
300 populate_cs_prog_key(const struct brw_device_info
*devinfo
,
301 struct brw_cs_prog_key
*key
)
303 memset(key
, 0, sizeof(*key
));
305 populate_sampler_prog_key(devinfo
, &key
->tex
);
309 anv_pipeline_compile(struct anv_pipeline
*pipeline
,
310 struct anv_shader_module
*module
,
311 const char *entrypoint
,
312 gl_shader_stage stage
,
313 const VkSpecializationInfo
*spec_info
,
314 struct brw_stage_prog_data
*prog_data
,
315 struct anv_pipeline_bind_map
*map
)
317 nir_shader
*nir
= anv_shader_compile_to_nir(pipeline
->device
,
318 module
, entrypoint
, stage
,
323 anv_nir_lower_push_constants(nir
);
325 /* Figure out the number of parameters */
326 prog_data
->nr_params
= 0;
328 if (nir
->num_uniforms
> 0) {
329 /* If the shader uses any push constants at all, we'll just give
330 * them the maximum possible number
332 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
333 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
336 if (pipeline
->layout
&& pipeline
->layout
->stage
[stage
].has_dynamic_offsets
)
337 prog_data
->nr_params
+= MAX_DYNAMIC_BUFFERS
* 2;
339 if (nir
->info
.num_images
> 0) {
340 prog_data
->nr_params
+= nir
->info
.num_images
* BRW_IMAGE_PARAM_SIZE
;
341 pipeline
->needs_data_cache
= true;
344 if (stage
== MESA_SHADER_COMPUTE
)
345 ((struct brw_cs_prog_data
*)prog_data
)->thread_local_id_index
=
346 prog_data
->nr_params
++; /* The CS Thread ID uniform */
348 if (nir
->info
.num_ssbos
> 0)
349 pipeline
->needs_data_cache
= true;
351 if (prog_data
->nr_params
> 0) {
352 /* XXX: I think we're leaking this */
353 prog_data
->param
= (const union gl_constant_value
**)
354 malloc(prog_data
->nr_params
* sizeof(union gl_constant_value
*));
356 /* We now set the param values to be offsets into a
357 * anv_push_constant_data structure. Since the compiler doesn't
358 * actually dereference any of the gl_constant_value pointers in the
359 * params array, it doesn't really matter what we put here.
361 struct anv_push_constants
*null_data
= NULL
;
362 if (nir
->num_uniforms
> 0) {
363 /* Fill out the push constants section of the param array */
364 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++)
365 prog_data
->param
[i
] = (const union gl_constant_value
*)
366 &null_data
->client_data
[i
* sizeof(float)];
370 /* Set up dynamic offsets */
371 anv_nir_apply_dynamic_offsets(pipeline
, nir
, prog_data
);
373 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
374 if (pipeline
->layout
)
375 anv_nir_apply_pipeline_layout(pipeline
, nir
, prog_data
, map
);
377 /* nir_lower_io will only handle the push constants; we need to set this
378 * to the full number of possible uniforms.
380 nir
->num_uniforms
= prog_data
->nr_params
* 4;
386 anv_fill_binding_table(struct brw_stage_prog_data
*prog_data
, unsigned bias
)
388 prog_data
->binding_table
.size_bytes
= 0;
389 prog_data
->binding_table
.texture_start
= bias
;
390 prog_data
->binding_table
.gather_texture_start
= bias
;
391 prog_data
->binding_table
.ubo_start
= bias
;
392 prog_data
->binding_table
.ssbo_start
= bias
;
393 prog_data
->binding_table
.image_start
= bias
;
397 anv_pipeline_add_compiled_stage(struct anv_pipeline
*pipeline
,
398 gl_shader_stage stage
,
399 const struct brw_stage_prog_data
*prog_data
,
400 struct anv_pipeline_bind_map
*map
)
402 pipeline
->prog_data
[stage
] = prog_data
;
403 pipeline
->active_stages
|= mesa_to_vk_shader_stage(stage
);
404 pipeline
->bindings
[stage
] = *map
;
408 anv_pipeline_compile_vs(struct anv_pipeline
*pipeline
,
409 struct anv_pipeline_cache
*cache
,
410 const VkGraphicsPipelineCreateInfo
*info
,
411 struct anv_shader_module
*module
,
412 const char *entrypoint
,
413 const VkSpecializationInfo
*spec_info
)
415 const struct brw_compiler
*compiler
=
416 pipeline
->device
->instance
->physicalDevice
.compiler
;
417 const struct brw_stage_prog_data
*stage_prog_data
;
418 struct anv_pipeline_bind_map map
;
419 struct brw_vs_prog_key key
;
420 uint32_t kernel
= NO_KERNEL
;
421 unsigned char sha1
[20];
423 populate_vs_prog_key(&pipeline
->device
->info
, &key
);
425 if (module
->size
> 0) {
426 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
, spec_info
);
427 kernel
= anv_pipeline_cache_search(cache
, sha1
, &stage_prog_data
, &map
);
430 if (kernel
== NO_KERNEL
) {
431 struct brw_vs_prog_data prog_data
= { 0, };
432 struct anv_pipeline_binding surface_to_descriptor
[256];
433 struct anv_pipeline_binding sampler_to_descriptor
[256];
435 map
= (struct anv_pipeline_bind_map
) {
436 .surface_to_descriptor
= surface_to_descriptor
,
437 .sampler_to_descriptor
= sampler_to_descriptor
440 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
441 MESA_SHADER_VERTEX
, spec_info
,
442 &prog_data
.base
.base
, &map
);
444 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
446 anv_fill_binding_table(&prog_data
.base
.base
, 0);
448 void *mem_ctx
= ralloc_context(NULL
);
450 if (module
->nir
== NULL
)
451 ralloc_steal(mem_ctx
, nir
);
453 prog_data
.inputs_read
= nir
->info
.inputs_read
;
455 brw_compute_vue_map(&pipeline
->device
->info
,
456 &prog_data
.base
.vue_map
,
457 nir
->info
.outputs_written
,
458 nir
->info
.separate_shader
);
461 const unsigned *shader_code
=
462 brw_compile_vs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
463 NULL
, false, -1, &code_size
, NULL
);
464 if (shader_code
== NULL
) {
465 ralloc_free(mem_ctx
);
466 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
469 stage_prog_data
= &prog_data
.base
.base
;
470 kernel
= anv_pipeline_cache_upload_kernel(cache
,
471 module
->size
> 0 ? sha1
: NULL
,
472 shader_code
, code_size
,
473 &stage_prog_data
, sizeof(prog_data
),
475 ralloc_free(mem_ctx
);
478 const struct brw_vs_prog_data
*vs_prog_data
=
479 (const struct brw_vs_prog_data
*) stage_prog_data
;
481 if (vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
) {
482 pipeline
->vs_simd8
= kernel
;
483 pipeline
->vs_vec4
= NO_KERNEL
;
485 pipeline
->vs_simd8
= NO_KERNEL
;
486 pipeline
->vs_vec4
= kernel
;
489 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_VERTEX
,
490 stage_prog_data
, &map
);
496 anv_pipeline_compile_gs(struct anv_pipeline
*pipeline
,
497 struct anv_pipeline_cache
*cache
,
498 const VkGraphicsPipelineCreateInfo
*info
,
499 struct anv_shader_module
*module
,
500 const char *entrypoint
,
501 const VkSpecializationInfo
*spec_info
)
503 const struct brw_compiler
*compiler
=
504 pipeline
->device
->instance
->physicalDevice
.compiler
;
505 const struct brw_stage_prog_data
*stage_prog_data
;
506 struct anv_pipeline_bind_map map
;
507 struct brw_gs_prog_key key
;
508 uint32_t kernel
= NO_KERNEL
;
509 unsigned char sha1
[20];
511 populate_gs_prog_key(&pipeline
->device
->info
, &key
);
513 if (module
->size
> 0) {
514 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
, spec_info
);
515 kernel
= anv_pipeline_cache_search(cache
, sha1
, &stage_prog_data
, &map
);
518 if (kernel
== NO_KERNEL
) {
519 struct brw_gs_prog_data prog_data
= { 0, };
520 struct anv_pipeline_binding surface_to_descriptor
[256];
521 struct anv_pipeline_binding sampler_to_descriptor
[256];
523 map
= (struct anv_pipeline_bind_map
) {
524 .surface_to_descriptor
= surface_to_descriptor
,
525 .sampler_to_descriptor
= sampler_to_descriptor
528 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
529 MESA_SHADER_GEOMETRY
, spec_info
,
530 &prog_data
.base
.base
, &map
);
532 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
534 anv_fill_binding_table(&prog_data
.base
.base
, 0);
536 void *mem_ctx
= ralloc_context(NULL
);
538 if (module
->nir
== NULL
)
539 ralloc_steal(mem_ctx
, nir
);
541 brw_compute_vue_map(&pipeline
->device
->info
,
542 &prog_data
.base
.vue_map
,
543 nir
->info
.outputs_written
,
544 nir
->info
.separate_shader
);
547 const unsigned *shader_code
=
548 brw_compile_gs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
549 NULL
, -1, &code_size
, NULL
);
550 if (shader_code
== NULL
) {
551 ralloc_free(mem_ctx
);
552 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
556 stage_prog_data
= &prog_data
.base
.base
;
557 kernel
= anv_pipeline_cache_upload_kernel(cache
,
558 module
->size
> 0 ? sha1
: NULL
,
559 shader_code
, code_size
,
560 &stage_prog_data
, sizeof(prog_data
),
563 ralloc_free(mem_ctx
);
566 pipeline
->gs_kernel
= kernel
;
568 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_GEOMETRY
,
569 stage_prog_data
, &map
);
575 anv_pipeline_compile_fs(struct anv_pipeline
*pipeline
,
576 struct anv_pipeline_cache
*cache
,
577 const VkGraphicsPipelineCreateInfo
*info
,
578 const struct anv_graphics_pipeline_create_info
*extra
,
579 struct anv_shader_module
*module
,
580 const char *entrypoint
,
581 const VkSpecializationInfo
*spec_info
)
583 const struct brw_compiler
*compiler
=
584 pipeline
->device
->instance
->physicalDevice
.compiler
;
585 const struct brw_stage_prog_data
*stage_prog_data
;
586 struct anv_pipeline_bind_map map
;
587 struct brw_wm_prog_key key
;
588 unsigned char sha1
[20];
590 populate_wm_prog_key(&pipeline
->device
->info
, info
, extra
, &key
);
592 if (module
->size
> 0) {
593 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
, spec_info
);
595 anv_pipeline_cache_search(cache
, sha1
, &stage_prog_data
, &map
);
598 if (pipeline
->ps_ksp0
== NO_KERNEL
) {
599 struct brw_wm_prog_data prog_data
= { 0, };
600 struct anv_pipeline_binding surface_to_descriptor
[256];
601 struct anv_pipeline_binding sampler_to_descriptor
[256];
603 map
= (struct anv_pipeline_bind_map
) {
604 .surface_to_descriptor
= surface_to_descriptor
+ 8,
605 .sampler_to_descriptor
= sampler_to_descriptor
608 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
609 MESA_SHADER_FRAGMENT
, spec_info
,
610 &prog_data
.base
, &map
);
612 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
614 unsigned num_rts
= 0;
615 struct anv_pipeline_binding rt_bindings
[8];
616 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
)->impl
;
617 nir_foreach_variable_safe(var
, &nir
->outputs
) {
618 if (var
->data
.location
< FRAG_RESULT_DATA0
)
621 unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
622 if (rt
>= key
.nr_color_regions
) {
623 /* Out-of-bounds, throw it away */
624 var
->data
.mode
= nir_var_local
;
625 exec_node_remove(&var
->node
);
626 exec_list_push_tail(&impl
->locals
, &var
->node
);
630 /* Give it a new, compacted, location */
631 var
->data
.location
= FRAG_RESULT_DATA0
+ num_rts
;
634 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
635 assert(num_rts
+ array_len
<= 8);
637 for (unsigned i
= 0; i
< array_len
; i
++) {
638 rt_bindings
[num_rts
] = (struct anv_pipeline_binding
) {
639 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
645 num_rts
+= array_len
;
648 if (pipeline
->use_repclear
) {
649 assert(num_rts
== 1);
650 key
.nr_color_regions
= 1;
654 /* If we have no render targets, we need a null render target */
655 rt_bindings
[0] = (struct anv_pipeline_binding
) {
656 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
663 assert(num_rts
<= 8);
664 map
.surface_to_descriptor
-= num_rts
;
665 map
.surface_count
+= num_rts
;
666 assert(map
.surface_count
<= 256);
667 memcpy(map
.surface_to_descriptor
, rt_bindings
,
668 num_rts
* sizeof(*rt_bindings
));
670 anv_fill_binding_table(&prog_data
.base
, num_rts
);
672 void *mem_ctx
= ralloc_context(NULL
);
674 if (module
->nir
== NULL
)
675 ralloc_steal(mem_ctx
, nir
);
678 const unsigned *shader_code
=
679 brw_compile_fs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
680 NULL
, -1, -1, true, pipeline
->use_repclear
,
682 if (shader_code
== NULL
) {
683 ralloc_free(mem_ctx
);
684 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
687 stage_prog_data
= &prog_data
.base
;
689 anv_pipeline_cache_upload_kernel(cache
,
690 module
->size
> 0 ? sha1
: NULL
,
691 shader_code
, code_size
,
692 &stage_prog_data
, sizeof(prog_data
),
695 ralloc_free(mem_ctx
);
698 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_FRAGMENT
,
699 stage_prog_data
, &map
);
705 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
706 struct anv_pipeline_cache
*cache
,
707 const VkComputePipelineCreateInfo
*info
,
708 struct anv_shader_module
*module
,
709 const char *entrypoint
,
710 const VkSpecializationInfo
*spec_info
)
712 const struct brw_compiler
*compiler
=
713 pipeline
->device
->instance
->physicalDevice
.compiler
;
714 const struct brw_stage_prog_data
*stage_prog_data
;
715 struct anv_pipeline_bind_map map
;
716 struct brw_cs_prog_key key
;
717 uint32_t kernel
= NO_KERNEL
;
718 unsigned char sha1
[20];
720 populate_cs_prog_key(&pipeline
->device
->info
, &key
);
722 if (module
->size
> 0) {
723 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
, spec_info
);
724 kernel
= anv_pipeline_cache_search(cache
, sha1
, &stage_prog_data
, &map
);
727 if (module
->size
== 0 || kernel
== NO_KERNEL
) {
728 struct brw_cs_prog_data prog_data
= { 0, };
729 struct anv_pipeline_binding surface_to_descriptor
[256];
730 struct anv_pipeline_binding sampler_to_descriptor
[256];
732 map
= (struct anv_pipeline_bind_map
) {
733 .surface_to_descriptor
= surface_to_descriptor
,
734 .sampler_to_descriptor
= sampler_to_descriptor
737 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
738 MESA_SHADER_COMPUTE
, spec_info
,
739 &prog_data
.base
, &map
);
741 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
743 anv_fill_binding_table(&prog_data
.base
, 1);
745 void *mem_ctx
= ralloc_context(NULL
);
747 if (module
->nir
== NULL
)
748 ralloc_steal(mem_ctx
, nir
);
751 const unsigned *shader_code
=
752 brw_compile_cs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
753 -1, &code_size
, NULL
);
754 if (shader_code
== NULL
) {
755 ralloc_free(mem_ctx
);
756 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
759 stage_prog_data
= &prog_data
.base
;
760 kernel
= anv_pipeline_cache_upload_kernel(cache
,
761 module
->size
> 0 ? sha1
: NULL
,
762 shader_code
, code_size
,
763 &stage_prog_data
, sizeof(prog_data
),
766 ralloc_free(mem_ctx
);
769 pipeline
->cs_simd
= kernel
;
771 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_COMPUTE
,
772 stage_prog_data
, &map
);
779 anv_setup_pipeline_l3_config(struct anv_pipeline
*pipeline
)
781 const struct brw_device_info
*devinfo
= &pipeline
->device
->info
;
782 switch (devinfo
->gen
) {
784 if (devinfo
->is_haswell
)
785 gen75_setup_pipeline_l3_config(pipeline
);
787 gen7_setup_pipeline_l3_config(pipeline
);
790 gen8_setup_pipeline_l3_config(pipeline
);
793 gen9_setup_pipeline_l3_config(pipeline
);
796 unreachable("unsupported gen\n");
801 anv_compute_urb_partition(struct anv_pipeline
*pipeline
)
803 const struct brw_device_info
*devinfo
= &pipeline
->device
->info
;
805 bool vs_present
= pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
;
806 unsigned vs_size
= vs_present
?
807 get_vs_prog_data(pipeline
)->base
.urb_entry_size
: 1;
808 unsigned vs_entry_size_bytes
= vs_size
* 64;
809 bool gs_present
= pipeline
->active_stages
& VK_SHADER_STAGE_GEOMETRY_BIT
;
810 unsigned gs_size
= gs_present
?
811 get_gs_prog_data(pipeline
)->base
.urb_entry_size
: 1;
812 unsigned gs_entry_size_bytes
= gs_size
* 64;
814 /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
816 * VS Number of URB Entries must be divisible by 8 if the VS URB Entry
817 * Allocation Size is less than 9 512-bit URB entries.
819 * Similar text exists for GS.
821 unsigned vs_granularity
= (vs_size
< 9) ? 8 : 1;
822 unsigned gs_granularity
= (gs_size
< 9) ? 8 : 1;
824 /* URB allocations must be done in 8k chunks. */
825 unsigned chunk_size_bytes
= 8192;
827 /* Determine the size of the URB in chunks. */
828 unsigned urb_chunks
= pipeline
->urb
.total_size
* 1024 / chunk_size_bytes
;
830 /* Reserve space for push constants */
831 unsigned push_constant_kb
;
832 if (pipeline
->device
->info
.gen
>= 8)
833 push_constant_kb
= 32;
834 else if (pipeline
->device
->info
.is_haswell
)
835 push_constant_kb
= pipeline
->device
->info
.gt
== 3 ? 32 : 16;
837 push_constant_kb
= 16;
839 unsigned push_constant_bytes
= push_constant_kb
* 1024;
840 unsigned push_constant_chunks
=
841 push_constant_bytes
/ chunk_size_bytes
;
843 /* Initially, assign each stage the minimum amount of URB space it needs,
844 * and make a note of how much additional space it "wants" (the amount of
845 * additional space it could actually make use of).
848 /* VS has a lower limit on the number of URB entries */
850 ALIGN(devinfo
->urb
.min_vs_entries
* vs_entry_size_bytes
,
851 chunk_size_bytes
) / chunk_size_bytes
;
853 ALIGN(devinfo
->urb
.max_vs_entries
* vs_entry_size_bytes
,
854 chunk_size_bytes
) / chunk_size_bytes
- vs_chunks
;
856 unsigned gs_chunks
= 0;
857 unsigned gs_wants
= 0;
859 /* There are two constraints on the minimum amount of URB space we can
862 * (1) We need room for at least 2 URB entries, since we always operate
863 * the GS in DUAL_OBJECT mode.
865 * (2) We can't allocate less than nr_gs_entries_granularity.
867 gs_chunks
= ALIGN(MAX2(gs_granularity
, 2) * gs_entry_size_bytes
,
868 chunk_size_bytes
) / chunk_size_bytes
;
870 ALIGN(devinfo
->urb
.max_gs_entries
* gs_entry_size_bytes
,
871 chunk_size_bytes
) / chunk_size_bytes
- gs_chunks
;
874 /* There should always be enough URB space to satisfy the minimum
875 * requirements of each stage.
877 unsigned total_needs
= push_constant_chunks
+ vs_chunks
+ gs_chunks
;
878 assert(total_needs
<= urb_chunks
);
880 /* Mete out remaining space (if any) in proportion to "wants". */
881 unsigned total_wants
= vs_wants
+ gs_wants
;
882 unsigned remaining_space
= urb_chunks
- total_needs
;
883 if (remaining_space
> total_wants
)
884 remaining_space
= total_wants
;
885 if (remaining_space
> 0) {
886 unsigned vs_additional
= (unsigned)
887 round(vs_wants
* (((double) remaining_space
) / total_wants
));
888 vs_chunks
+= vs_additional
;
889 remaining_space
-= vs_additional
;
890 gs_chunks
+= remaining_space
;
893 /* Sanity check that we haven't over-allocated. */
894 assert(push_constant_chunks
+ vs_chunks
+ gs_chunks
<= urb_chunks
);
896 /* Finally, compute the number of entries that can fit in the space
897 * allocated to each stage.
899 unsigned nr_vs_entries
= vs_chunks
* chunk_size_bytes
/ vs_entry_size_bytes
;
900 unsigned nr_gs_entries
= gs_chunks
* chunk_size_bytes
/ gs_entry_size_bytes
;
902 /* Since we rounded up when computing *_wants, this may be slightly more
903 * than the maximum allowed amount, so correct for that.
905 nr_vs_entries
= MIN2(nr_vs_entries
, devinfo
->urb
.max_vs_entries
);
906 nr_gs_entries
= MIN2(nr_gs_entries
, devinfo
->urb
.max_gs_entries
);
908 /* Ensure that we program a multiple of the granularity. */
909 nr_vs_entries
= ROUND_DOWN_TO(nr_vs_entries
, vs_granularity
);
910 nr_gs_entries
= ROUND_DOWN_TO(nr_gs_entries
, gs_granularity
);
912 /* Finally, sanity check to make sure we have at least the minimum number
913 * of entries needed for each stage.
915 assert(nr_vs_entries
>= devinfo
->urb
.min_vs_entries
);
917 assert(nr_gs_entries
>= 2);
919 /* Lay out the URB in the following order:
924 pipeline
->urb
.start
[MESA_SHADER_VERTEX
] = push_constant_chunks
;
925 pipeline
->urb
.size
[MESA_SHADER_VERTEX
] = vs_size
;
926 pipeline
->urb
.entries
[MESA_SHADER_VERTEX
] = nr_vs_entries
;
928 pipeline
->urb
.start
[MESA_SHADER_GEOMETRY
] = push_constant_chunks
+ vs_chunks
;
929 pipeline
->urb
.size
[MESA_SHADER_GEOMETRY
] = gs_size
;
930 pipeline
->urb
.entries
[MESA_SHADER_GEOMETRY
] = nr_gs_entries
;
932 pipeline
->urb
.start
[MESA_SHADER_TESS_CTRL
] = push_constant_chunks
;
933 pipeline
->urb
.size
[MESA_SHADER_TESS_CTRL
] = 1;
934 pipeline
->urb
.entries
[MESA_SHADER_TESS_CTRL
] = 0;
936 pipeline
->urb
.start
[MESA_SHADER_TESS_EVAL
] = push_constant_chunks
;
937 pipeline
->urb
.size
[MESA_SHADER_TESS_EVAL
] = 1;
938 pipeline
->urb
.entries
[MESA_SHADER_TESS_EVAL
] = 0;
942 * Copy pipeline state not marked as dynamic.
943 * Dynamic state is pipeline state which hasn't been provided at pipeline
944 * creation time, but is dynamically provided afterwards using various
945 * vkCmdSet* functions.
947 * The set of state considered "non_dynamic" is determined by the pieces of
948 * state that have their corresponding VkDynamicState enums omitted from
949 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
951 * @param[out] pipeline Destination non_dynamic state.
952 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
955 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
956 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
958 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
959 ANV_FROM_HANDLE(anv_render_pass
, pass
, pCreateInfo
->renderPass
);
960 struct anv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
962 pipeline
->dynamic_state
= default_dynamic_state
;
964 if (pCreateInfo
->pDynamicState
) {
965 /* Remove all of the states that are marked as dynamic */
966 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
967 for (uint32_t s
= 0; s
< count
; s
++)
968 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
971 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
973 /* Section 9.2 of the Vulkan 1.0.15 spec says:
975 * pViewportState is [...] NULL if the pipeline
976 * has rasterization disabled.
978 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
979 assert(pCreateInfo
->pViewportState
);
981 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
982 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
983 typed_memcpy(dynamic
->viewport
.viewports
,
984 pCreateInfo
->pViewportState
->pViewports
,
985 pCreateInfo
->pViewportState
->viewportCount
);
988 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
989 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
990 typed_memcpy(dynamic
->scissor
.scissors
,
991 pCreateInfo
->pViewportState
->pScissors
,
992 pCreateInfo
->pViewportState
->scissorCount
);
996 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
997 assert(pCreateInfo
->pRasterizationState
);
998 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1001 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1002 assert(pCreateInfo
->pRasterizationState
);
1003 dynamic
->depth_bias
.bias
=
1004 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1005 dynamic
->depth_bias
.clamp
=
1006 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1007 dynamic
->depth_bias
.slope
=
1008 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1011 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1013 * pColorBlendState is [...] NULL if the pipeline has rasterization
1014 * disabled or if the subpass of the render pass the pipeline is
1015 * created against does not use any color attachments.
1017 bool uses_color_att
= false;
1018 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1019 if (subpass
->color_attachments
[i
] != VK_ATTACHMENT_UNUSED
) {
1020 uses_color_att
= true;
1025 if (uses_color_att
&&
1026 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1027 assert(pCreateInfo
->pColorBlendState
);
1029 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
1030 typed_memcpy(dynamic
->blend_constants
,
1031 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1034 /* If there is no depthstencil attachment, then don't read
1035 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1036 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1037 * no need to override the depthstencil defaults in
1038 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1040 * Section 9.2 of the Vulkan 1.0.15 spec says:
1042 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1043 * disabled or if the subpass of the render pass the pipeline is created
1044 * against does not use a depth/stencil attachment.
1046 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1047 subpass
->depth_stencil_attachment
!= VK_ATTACHMENT_UNUSED
) {
1048 assert(pCreateInfo
->pDepthStencilState
);
1050 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1051 dynamic
->depth_bounds
.min
=
1052 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1053 dynamic
->depth_bounds
.max
=
1054 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1057 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1058 dynamic
->stencil_compare_mask
.front
=
1059 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1060 dynamic
->stencil_compare_mask
.back
=
1061 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1064 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1065 dynamic
->stencil_write_mask
.front
=
1066 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1067 dynamic
->stencil_write_mask
.back
=
1068 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1071 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1072 dynamic
->stencil_reference
.front
=
1073 pCreateInfo
->pDepthStencilState
->front
.reference
;
1074 dynamic
->stencil_reference
.back
=
1075 pCreateInfo
->pDepthStencilState
->back
.reference
;
1079 pipeline
->dynamic_state_mask
= states
;
1083 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1085 struct anv_render_pass
*renderpass
= NULL
;
1086 struct anv_subpass
*subpass
= NULL
;
1088 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1089 * present, as explained by the Vulkan (20 Oct 2015, git-aa308cb), Section
1090 * 4.2 Graphics Pipeline.
1092 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1094 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1097 if (renderpass
!= &anv_meta_dummy_renderpass
) {
1098 assert(info
->subpass
< renderpass
->subpass_count
);
1099 subpass
= &renderpass
->subpasses
[info
->subpass
];
1102 assert(info
->stageCount
>= 1);
1103 assert(info
->pVertexInputState
);
1104 assert(info
->pInputAssemblyState
);
1105 assert(info
->pViewportState
);
1106 assert(info
->pRasterizationState
);
1108 if (subpass
&& subpass
->depth_stencil_attachment
!= VK_ATTACHMENT_UNUSED
)
1109 assert(info
->pDepthStencilState
);
1111 if (subpass
&& subpass
->color_count
> 0)
1112 assert(info
->pColorBlendState
);
1114 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1115 switch (info
->pStages
[i
].stage
) {
1116 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1117 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1118 assert(info
->pTessellationState
);
1127 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1128 struct anv_device
*device
,
1129 struct anv_pipeline_cache
*cache
,
1130 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1131 const struct anv_graphics_pipeline_create_info
*extra
,
1132 const VkAllocationCallbacks
*alloc
)
1137 anv_pipeline_validate_create_info(pCreateInfo
);
1141 alloc
= &device
->alloc
;
1143 pipeline
->device
= device
;
1144 pipeline
->layout
= anv_pipeline_layout_from_handle(pCreateInfo
->layout
);
1146 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1147 if (result
!= VK_SUCCESS
)
1150 pipeline
->batch
.alloc
= alloc
;
1151 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1152 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1153 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1155 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1156 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1157 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1159 pipeline
->use_repclear
= extra
&& extra
->use_repclear
;
1161 pipeline
->needs_data_cache
= false;
1163 /* When we free the pipeline, we detect stages based on the NULL status
1164 * of various prog_data pointers. Make them NULL by default.
1166 memset(pipeline
->prog_data
, 0, sizeof(pipeline
->prog_data
));
1167 memset(pipeline
->bindings
, 0, sizeof(pipeline
->bindings
));
1169 pipeline
->vs_simd8
= NO_KERNEL
;
1170 pipeline
->vs_vec4
= NO_KERNEL
;
1171 pipeline
->gs_kernel
= NO_KERNEL
;
1172 pipeline
->ps_ksp0
= NO_KERNEL
;
1174 pipeline
->active_stages
= 0;
1176 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
1177 struct anv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
1178 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
1179 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
1180 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
1181 modules
[stage
] = anv_shader_module_from_handle(pStages
[stage
]->module
);
1184 if (modules
[MESA_SHADER_VERTEX
]) {
1185 anv_pipeline_compile_vs(pipeline
, cache
, pCreateInfo
,
1186 modules
[MESA_SHADER_VERTEX
],
1187 pStages
[MESA_SHADER_VERTEX
]->pName
,
1188 pStages
[MESA_SHADER_VERTEX
]->pSpecializationInfo
);
1191 if (modules
[MESA_SHADER_TESS_CTRL
] || modules
[MESA_SHADER_TESS_EVAL
])
1192 anv_finishme("no tessellation support");
1194 if (modules
[MESA_SHADER_GEOMETRY
]) {
1195 anv_pipeline_compile_gs(pipeline
, cache
, pCreateInfo
,
1196 modules
[MESA_SHADER_GEOMETRY
],
1197 pStages
[MESA_SHADER_GEOMETRY
]->pName
,
1198 pStages
[MESA_SHADER_GEOMETRY
]->pSpecializationInfo
);
1201 if (modules
[MESA_SHADER_FRAGMENT
]) {
1202 anv_pipeline_compile_fs(pipeline
, cache
, pCreateInfo
, extra
,
1203 modules
[MESA_SHADER_FRAGMENT
],
1204 pStages
[MESA_SHADER_FRAGMENT
]->pName
,
1205 pStages
[MESA_SHADER_FRAGMENT
]->pSpecializationInfo
);
1208 if (!(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
)) {
1209 /* Vertex is only optional if disable_vs is set */
1210 assert(extra
->disable_vs
);
1213 anv_setup_pipeline_l3_config(pipeline
);
1214 anv_compute_urb_partition(pipeline
);
1216 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1217 pCreateInfo
->pVertexInputState
;
1219 uint64_t inputs_read
;
1220 if (extra
&& extra
->disable_vs
) {
1221 /* If the VS is disabled, just assume the user knows what they're
1222 * doing and apply the layout blindly. This can only come from
1223 * meta, so this *should* be safe.
1225 inputs_read
= ~0ull;
1227 inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1230 pipeline
->vb_used
= 0;
1231 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1232 const VkVertexInputAttributeDescription
*desc
=
1233 &vi_info
->pVertexAttributeDescriptions
[i
];
1235 if (inputs_read
& (1 << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1236 pipeline
->vb_used
|= 1 << desc
->binding
;
1239 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1240 const VkVertexInputBindingDescription
*desc
=
1241 &vi_info
->pVertexBindingDescriptions
[i
];
1243 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
1245 /* Step rate is programmed per vertex element (attribute), not
1246 * binding. Set up a map of which bindings step per instance, for
1247 * reference by vertex element setup. */
1248 switch (desc
->inputRate
) {
1250 case VK_VERTEX_INPUT_RATE_VERTEX
:
1251 pipeline
->instancing_enable
[desc
->binding
] = false;
1253 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1254 pipeline
->instancing_enable
[desc
->binding
] = true;
1259 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1260 pCreateInfo
->pInputAssemblyState
;
1261 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1262 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];
1264 if (extra
&& extra
->use_rectlist
)
1265 pipeline
->topology
= _3DPRIM_RECTLIST
;
1271 anv_graphics_pipeline_create(
1273 VkPipelineCache _cache
,
1274 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1275 const struct anv_graphics_pipeline_create_info
*extra
,
1276 const VkAllocationCallbacks
*pAllocator
,
1277 VkPipeline
*pPipeline
)
1279 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1280 ANV_FROM_HANDLE(anv_pipeline_cache
, cache
, _cache
);
1283 cache
= &device
->default_pipeline_cache
;
1285 switch (device
->info
.gen
) {
1287 if (device
->info
.is_haswell
)
1288 return gen75_graphics_pipeline_create(_device
, cache
, pCreateInfo
, extra
, pAllocator
, pPipeline
);
1290 return gen7_graphics_pipeline_create(_device
, cache
, pCreateInfo
, extra
, pAllocator
, pPipeline
);
1292 return gen8_graphics_pipeline_create(_device
, cache
, pCreateInfo
, extra
, pAllocator
, pPipeline
);
1294 return gen9_graphics_pipeline_create(_device
, cache
, pCreateInfo
, extra
, pAllocator
, pPipeline
);
1296 unreachable("unsupported gen\n");
1300 VkResult
anv_CreateGraphicsPipelines(
1302 VkPipelineCache pipelineCache
,
1304 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
1305 const VkAllocationCallbacks
* pAllocator
,
1306 VkPipeline
* pPipelines
)
1308 VkResult result
= VK_SUCCESS
;
1311 for (; i
< count
; i
++) {
1312 result
= anv_graphics_pipeline_create(_device
,
1315 NULL
, pAllocator
, &pPipelines
[i
]);
1316 if (result
!= VK_SUCCESS
) {
1317 for (unsigned j
= 0; j
< i
; j
++) {
1318 anv_DestroyPipeline(_device
, pPipelines
[j
], pAllocator
);
1328 static VkResult
anv_compute_pipeline_create(
1330 VkPipelineCache _cache
,
1331 const VkComputePipelineCreateInfo
* pCreateInfo
,
1332 const VkAllocationCallbacks
* pAllocator
,
1333 VkPipeline
* pPipeline
)
1335 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1336 ANV_FROM_HANDLE(anv_pipeline_cache
, cache
, _cache
);
1339 cache
= &device
->default_pipeline_cache
;
1341 switch (device
->info
.gen
) {
1343 if (device
->info
.is_haswell
)
1344 return gen75_compute_pipeline_create(_device
, cache
, pCreateInfo
, pAllocator
, pPipeline
);
1346 return gen7_compute_pipeline_create(_device
, cache
, pCreateInfo
, pAllocator
, pPipeline
);
1348 return gen8_compute_pipeline_create(_device
, cache
, pCreateInfo
, pAllocator
, pPipeline
);
1350 return gen9_compute_pipeline_create(_device
, cache
, pCreateInfo
, pAllocator
, pPipeline
);
1352 unreachable("unsupported gen\n");
1356 VkResult
anv_CreateComputePipelines(
1358 VkPipelineCache pipelineCache
,
1360 const VkComputePipelineCreateInfo
* pCreateInfos
,
1361 const VkAllocationCallbacks
* pAllocator
,
1362 VkPipeline
* pPipelines
)
1364 VkResult result
= VK_SUCCESS
;
1367 for (; i
< count
; i
++) {
1368 result
= anv_compute_pipeline_create(_device
, pipelineCache
,
1370 pAllocator
, &pPipelines
[i
]);
1371 if (result
!= VK_SUCCESS
) {
1372 for (unsigned j
= 0; j
< i
; j
++) {
1373 anv_DestroyPipeline(_device
, pPipelines
[j
], pAllocator
);