2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "common/gen_l3_config.h"
32 #include "anv_private.h"
33 #include "compiler/brw_nir.h"
35 #include "spirv/nir_spirv.h"
37 /* Needed for SWIZZLE macros */
38 #include "program/prog_instruction.h"
42 VkResult
anv_CreateShaderModule(
44 const VkShaderModuleCreateInfo
* pCreateInfo
,
45 const VkAllocationCallbacks
* pAllocator
,
46 VkShaderModule
* pShaderModule
)
48 ANV_FROM_HANDLE(anv_device
, device
, _device
);
49 struct anv_shader_module
*module
;
51 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
52 assert(pCreateInfo
->flags
== 0);
54 module
= vk_alloc2(&device
->alloc
, pAllocator
,
55 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
56 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
58 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
60 module
->size
= pCreateInfo
->codeSize
;
61 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
63 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
65 *pShaderModule
= anv_shader_module_to_handle(module
);
70 void anv_DestroyShaderModule(
72 VkShaderModule _module
,
73 const VkAllocationCallbacks
* pAllocator
)
75 ANV_FROM_HANDLE(anv_device
, device
, _device
);
76 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
81 vk_free2(&device
->alloc
, pAllocator
, module
);
84 #define SPIR_V_MAGIC_NUMBER 0x07230203
86 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
87 * we can't do that yet because we don't have the ability to copy nir.
90 anv_shader_compile_to_nir(struct anv_pipeline
*pipeline
,
91 struct anv_shader_module
*module
,
92 const char *entrypoint_name
,
93 gl_shader_stage stage
,
94 const VkSpecializationInfo
*spec_info
)
96 const struct anv_device
*device
= pipeline
->device
;
98 const struct brw_compiler
*compiler
=
99 device
->instance
->physicalDevice
.compiler
;
100 const nir_shader_compiler_options
*nir_options
=
101 compiler
->glsl_compiler_options
[stage
].NirOptions
;
103 uint32_t *spirv
= (uint32_t *) module
->data
;
104 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
105 assert(module
->size
% 4 == 0);
107 uint32_t num_spec_entries
= 0;
108 struct nir_spirv_specialization
*spec_entries
= NULL
;
109 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
110 num_spec_entries
= spec_info
->mapEntryCount
;
111 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
112 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
113 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
114 const void *data
= spec_info
->pData
+ entry
.offset
;
115 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
117 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
118 if (spec_info
->dataSize
== 8)
119 spec_entries
[i
].data64
= *(const uint64_t *)data
;
121 spec_entries
[i
].data32
= *(const uint32_t *)data
;
125 const struct nir_spirv_supported_extensions supported_ext
= {
126 .float64
= device
->instance
->physicalDevice
.info
.gen
>= 8,
127 .int64
= device
->instance
->physicalDevice
.info
.gen
>= 8,
128 .tessellation
= true,
129 .draw_parameters
= true,
130 .image_write_without_format
= true,
133 nir_function
*entry_point
=
134 spirv_to_nir(spirv
, module
->size
/ 4,
135 spec_entries
, num_spec_entries
,
136 stage
, entrypoint_name
, &supported_ext
, nir_options
);
137 nir_shader
*nir
= entry_point
->shader
;
138 assert(nir
->stage
== stage
);
139 nir_validate_shader(nir
);
143 /* We have to lower away local constant initializers right before we
144 * inline functions. That way they get properly initialized at the top
145 * of the function and not at the top of its caller.
147 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_local
);
148 NIR_PASS_V(nir
, nir_lower_returns
);
149 NIR_PASS_V(nir
, nir_inline_functions
);
151 /* Pick off the single entrypoint that we want */
152 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
153 if (func
!= entry_point
)
154 exec_node_remove(&func
->node
);
156 assert(exec_list_length(&nir
->functions
) == 1);
157 entry_point
->name
= ralloc_strdup(entry_point
, "main");
159 NIR_PASS_V(nir
, nir_remove_dead_variables
,
160 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
162 if (stage
== MESA_SHADER_FRAGMENT
)
163 NIR_PASS_V(nir
, nir_lower_wpos_center
, pipeline
->sample_shading_enable
);
165 /* Now that we've deleted all but the main function, we can go ahead and
166 * lower the rest of the constant initializers.
168 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
169 NIR_PASS_V(nir
, nir_propagate_invariant
);
170 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
171 entry_point
->impl
, true, false);
172 NIR_PASS_V(nir
, nir_lower_system_values
);
174 /* Vulkan uses the separate-shader linking model */
175 nir
->info
->separate_shader
= true;
177 nir
= brw_preprocess_nir(compiler
, nir
);
179 NIR_PASS_V(nir
, nir_lower_clip_cull_distance_arrays
);
181 if (stage
== MESA_SHADER_FRAGMENT
)
182 NIR_PASS_V(nir
, anv_nir_lower_input_attachments
);
187 void anv_DestroyPipeline(
189 VkPipeline _pipeline
,
190 const VkAllocationCallbacks
* pAllocator
)
192 ANV_FROM_HANDLE(anv_device
, device
, _device
);
193 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
198 anv_reloc_list_finish(&pipeline
->batch_relocs
,
199 pAllocator
? pAllocator
: &device
->alloc
);
200 if (pipeline
->blend_state
.map
)
201 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
203 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
204 if (pipeline
->shaders
[s
])
205 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
208 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
211 static const uint32_t vk_to_gen_primitive_type
[] = {
212 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
213 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
214 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
215 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
216 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
217 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
218 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
219 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
220 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
221 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
225 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
226 struct brw_sampler_prog_key_data
*key
)
228 /* Almost all multisampled textures are compressed. The only time when we
229 * don't compress a multisampled texture is for 16x MSAA with a surface
230 * width greater than 8k which is a bit of an edge case. Since the sampler
231 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
232 * to tell the compiler to always assume compression.
234 key
->compressed_multisample_layout_mask
= ~0;
236 /* SkyLake added support for 16x MSAA. With this came a new message for
237 * reading from a 16x MSAA surface with compression. The new message was
238 * needed because now the MCS data is 64 bits instead of 32 or lower as is
239 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
240 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
241 * so we can just use it unconditionally. This may not be quite as
242 * efficient but it saves us from recompiling.
244 if (devinfo
->gen
>= 9)
247 /* XXX: Handle texture swizzle on HSW- */
248 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
249 /* Assume color sampler, no swizzling. (Works for BDW+) */
250 key
->swizzles
[i
] = SWIZZLE_XYZW
;
255 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
256 struct brw_vs_prog_key
*key
)
258 memset(key
, 0, sizeof(*key
));
260 populate_sampler_prog_key(devinfo
, &key
->tex
);
262 /* XXX: Handle vertex input work-arounds */
264 /* XXX: Handle sampler_prog_key */
268 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
269 struct brw_gs_prog_key
*key
)
271 memset(key
, 0, sizeof(*key
));
273 populate_sampler_prog_key(devinfo
, &key
->tex
);
277 populate_wm_prog_key(const struct anv_pipeline
*pipeline
,
278 const VkGraphicsPipelineCreateInfo
*info
,
279 struct brw_wm_prog_key
*key
)
281 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
282 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, info
->renderPass
);
284 memset(key
, 0, sizeof(*key
));
286 populate_sampler_prog_key(devinfo
, &key
->tex
);
288 /* TODO: we could set this to 0 based on the information in nir_shader, but
289 * this function is called before spirv_to_nir. */
290 const struct brw_vue_map
*vue_map
=
291 &anv_pipeline_get_last_vue_prog_data(pipeline
)->vue_map
;
292 key
->input_slots_valid
= vue_map
->slots_valid
;
294 /* Vulkan doesn't specify a default */
295 key
->high_quality_derivatives
= false;
297 /* XXX Vulkan doesn't appear to specify */
298 key
->clamp_fragment_color
= false;
300 key
->nr_color_regions
=
301 render_pass
->subpasses
[info
->subpass
].color_count
;
303 key
->replicate_alpha
= key
->nr_color_regions
> 1 &&
304 info
->pMultisampleState
&&
305 info
->pMultisampleState
->alphaToCoverageEnable
;
307 if (info
->pMultisampleState
) {
308 /* We should probably pull this out of the shader, but it's fairly
309 * harmless to compute it and then let dead-code take care of it.
311 if (info
->pMultisampleState
->rasterizationSamples
> 1) {
312 key
->persample_interp
=
313 (info
->pMultisampleState
->minSampleShading
*
314 info
->pMultisampleState
->rasterizationSamples
) > 1;
315 key
->multisample_fbo
= true;
318 key
->frag_coord_adds_sample_pos
=
319 info
->pMultisampleState
->sampleShadingEnable
;
324 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
325 struct brw_cs_prog_key
*key
)
327 memset(key
, 0, sizeof(*key
));
329 populate_sampler_prog_key(devinfo
, &key
->tex
);
333 anv_pipeline_hash_shader(struct anv_pipeline
*pipeline
,
334 struct anv_shader_module
*module
,
335 const char *entrypoint
,
336 gl_shader_stage stage
,
337 const VkSpecializationInfo
*spec_info
,
338 const void *key
, size_t key_size
,
339 unsigned char *sha1_out
)
341 struct mesa_sha1 ctx
;
343 _mesa_sha1_init(&ctx
);
344 if (pipeline
->layout
) {
345 _mesa_sha1_update(&ctx
, pipeline
->layout
->sha1
,
346 sizeof(pipeline
->layout
->sha1
));
348 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
349 _mesa_sha1_update(&ctx
, entrypoint
, strlen(entrypoint
));
350 _mesa_sha1_update(&ctx
, &stage
, sizeof(stage
));
352 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
353 spec_info
->mapEntryCount
* sizeof(*spec_info
->pMapEntries
));
354 _mesa_sha1_update(&ctx
, spec_info
->pData
, spec_info
->dataSize
);
356 _mesa_sha1_update(&ctx
, key
, key_size
);
357 _mesa_sha1_final(&ctx
, sha1_out
);
361 anv_pipeline_compile(struct anv_pipeline
*pipeline
,
362 struct anv_shader_module
*module
,
363 const char *entrypoint
,
364 gl_shader_stage stage
,
365 const VkSpecializationInfo
*spec_info
,
366 struct brw_stage_prog_data
*prog_data
,
367 struct anv_pipeline_bind_map
*map
)
369 nir_shader
*nir
= anv_shader_compile_to_nir(pipeline
,
370 module
, entrypoint
, stage
,
375 NIR_PASS_V(nir
, anv_nir_lower_push_constants
);
377 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
379 /* Figure out the number of parameters */
380 prog_data
->nr_params
= 0;
382 if (nir
->num_uniforms
> 0) {
383 /* If the shader uses any push constants at all, we'll just give
384 * them the maximum possible number
386 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
387 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
390 if (nir
->info
->num_images
> 0) {
391 prog_data
->nr_params
+= nir
->info
->num_images
* BRW_IMAGE_PARAM_SIZE
;
392 pipeline
->needs_data_cache
= true;
395 if (stage
== MESA_SHADER_COMPUTE
)
396 ((struct brw_cs_prog_data
*)prog_data
)->thread_local_id_index
=
397 prog_data
->nr_params
++; /* The CS Thread ID uniform */
399 if (nir
->info
->num_ssbos
> 0)
400 pipeline
->needs_data_cache
= true;
402 if (prog_data
->nr_params
> 0) {
403 /* XXX: I think we're leaking this */
404 prog_data
->param
= (const union gl_constant_value
**)
405 malloc(prog_data
->nr_params
* sizeof(union gl_constant_value
*));
407 /* We now set the param values to be offsets into a
408 * anv_push_constant_data structure. Since the compiler doesn't
409 * actually dereference any of the gl_constant_value pointers in the
410 * params array, it doesn't really matter what we put here.
412 struct anv_push_constants
*null_data
= NULL
;
413 if (nir
->num_uniforms
> 0) {
414 /* Fill out the push constants section of the param array */
415 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++)
416 prog_data
->param
[i
] = (const union gl_constant_value
*)
417 &null_data
->client_data
[i
* sizeof(float)];
421 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
422 if (pipeline
->layout
)
423 anv_nir_apply_pipeline_layout(pipeline
, nir
, prog_data
, map
);
425 /* nir_lower_io will only handle the push constants; we need to set this
426 * to the full number of possible uniforms.
428 nir
->num_uniforms
= prog_data
->nr_params
* 4;
434 anv_fill_binding_table(struct brw_stage_prog_data
*prog_data
, unsigned bias
)
436 prog_data
->binding_table
.size_bytes
= 0;
437 prog_data
->binding_table
.texture_start
= bias
;
438 prog_data
->binding_table
.gather_texture_start
= bias
;
439 prog_data
->binding_table
.ubo_start
= bias
;
440 prog_data
->binding_table
.ssbo_start
= bias
;
441 prog_data
->binding_table
.image_start
= bias
;
444 static struct anv_shader_bin
*
445 anv_pipeline_upload_kernel(struct anv_pipeline
*pipeline
,
446 struct anv_pipeline_cache
*cache
,
447 const void *key_data
, uint32_t key_size
,
448 const void *kernel_data
, uint32_t kernel_size
,
449 const struct brw_stage_prog_data
*prog_data
,
450 uint32_t prog_data_size
,
451 const struct anv_pipeline_bind_map
*bind_map
)
454 return anv_pipeline_cache_upload_kernel(cache
, key_data
, key_size
,
455 kernel_data
, kernel_size
,
456 prog_data
, prog_data_size
,
459 return anv_shader_bin_create(pipeline
->device
, key_data
, key_size
,
460 kernel_data
, kernel_size
,
461 prog_data
, prog_data_size
,
462 prog_data
->param
, bind_map
);
468 anv_pipeline_add_compiled_stage(struct anv_pipeline
*pipeline
,
469 gl_shader_stage stage
,
470 struct anv_shader_bin
*shader
)
472 pipeline
->shaders
[stage
] = shader
;
473 pipeline
->active_stages
|= mesa_to_vk_shader_stage(stage
);
477 anv_pipeline_compile_vs(struct anv_pipeline
*pipeline
,
478 struct anv_pipeline_cache
*cache
,
479 const VkGraphicsPipelineCreateInfo
*info
,
480 struct anv_shader_module
*module
,
481 const char *entrypoint
,
482 const VkSpecializationInfo
*spec_info
)
484 const struct brw_compiler
*compiler
=
485 pipeline
->device
->instance
->physicalDevice
.compiler
;
486 struct anv_pipeline_bind_map map
;
487 struct brw_vs_prog_key key
;
488 struct anv_shader_bin
*bin
= NULL
;
489 unsigned char sha1
[20];
491 populate_vs_prog_key(&pipeline
->device
->info
, &key
);
494 anv_pipeline_hash_shader(pipeline
, module
, entrypoint
,
495 MESA_SHADER_VERTEX
, spec_info
,
496 &key
, sizeof(key
), sha1
);
497 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
501 struct brw_vs_prog_data prog_data
= { 0, };
502 struct anv_pipeline_binding surface_to_descriptor
[256];
503 struct anv_pipeline_binding sampler_to_descriptor
[256];
505 map
= (struct anv_pipeline_bind_map
) {
506 .surface_to_descriptor
= surface_to_descriptor
,
507 .sampler_to_descriptor
= sampler_to_descriptor
510 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
511 MESA_SHADER_VERTEX
, spec_info
,
512 &prog_data
.base
.base
, &map
);
514 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
516 anv_fill_binding_table(&prog_data
.base
.base
, 0);
518 void *mem_ctx
= ralloc_context(NULL
);
520 ralloc_steal(mem_ctx
, nir
);
522 prog_data
.inputs_read
= nir
->info
->inputs_read
;
523 prog_data
.double_inputs_read
= nir
->info
->double_inputs_read
;
525 brw_compute_vue_map(&pipeline
->device
->info
,
526 &prog_data
.base
.vue_map
,
527 nir
->info
->outputs_written
,
528 nir
->info
->separate_shader
);
531 const unsigned *shader_code
=
532 brw_compile_vs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
533 NULL
, false, -1, &code_size
, NULL
);
534 if (shader_code
== NULL
) {
535 ralloc_free(mem_ctx
);
536 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
539 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
540 shader_code
, code_size
,
541 &prog_data
.base
.base
, sizeof(prog_data
),
544 ralloc_free(mem_ctx
);
545 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
548 ralloc_free(mem_ctx
);
551 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_VERTEX
, bin
);
557 merge_tess_info(struct shader_info
*tes_info
,
558 const struct shader_info
*tcs_info
)
560 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
562 * "PointMode. Controls generation of points rather than triangles
563 * or lines. This functionality defaults to disabled, and is
564 * enabled if either shader stage includes the execution mode.
566 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
567 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
568 * and OutputVertices, it says:
570 * "One mode must be set in at least one of the tessellation
573 * So, the fields can be set in either the TCS or TES, but they must
574 * agree if set in both. Our backend looks at TES, so bitwise-or in
575 * the values from the TCS.
577 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
578 tes_info
->tess
.tcs_vertices_out
== 0 ||
579 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
580 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
582 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
583 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
584 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
585 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
587 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
588 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
592 anv_pipeline_compile_tcs_tes(struct anv_pipeline
*pipeline
,
593 struct anv_pipeline_cache
*cache
,
594 const VkGraphicsPipelineCreateInfo
*info
,
595 struct anv_shader_module
*tcs_module
,
596 const char *tcs_entrypoint
,
597 const VkSpecializationInfo
*tcs_spec_info
,
598 struct anv_shader_module
*tes_module
,
599 const char *tes_entrypoint
,
600 const VkSpecializationInfo
*tes_spec_info
)
602 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
603 const struct brw_compiler
*compiler
=
604 pipeline
->device
->instance
->physicalDevice
.compiler
;
605 struct anv_pipeline_bind_map tcs_map
;
606 struct anv_pipeline_bind_map tes_map
;
607 struct brw_tcs_prog_key tcs_key
= { 0, };
608 struct brw_tes_prog_key tes_key
= { 0, };
609 struct anv_shader_bin
*tcs_bin
= NULL
;
610 struct anv_shader_bin
*tes_bin
= NULL
;
611 unsigned char tcs_sha1
[40];
612 unsigned char tes_sha1
[40];
614 populate_sampler_prog_key(&pipeline
->device
->info
, &tcs_key
.tex
);
615 populate_sampler_prog_key(&pipeline
->device
->info
, &tes_key
.tex
);
616 tcs_key
.input_vertices
= info
->pTessellationState
->patchControlPoints
;
619 anv_pipeline_hash_shader(pipeline
, tcs_module
, tcs_entrypoint
,
620 MESA_SHADER_TESS_CTRL
, tcs_spec_info
,
621 &tcs_key
, sizeof(tcs_key
), tcs_sha1
);
622 anv_pipeline_hash_shader(pipeline
, tes_module
, tes_entrypoint
,
623 MESA_SHADER_TESS_EVAL
, tes_spec_info
,
624 &tes_key
, sizeof(tes_key
), tes_sha1
);
625 memcpy(&tcs_sha1
[20], tes_sha1
, 20);
626 memcpy(&tes_sha1
[20], tcs_sha1
, 20);
627 tcs_bin
= anv_pipeline_cache_search(cache
, tcs_sha1
, sizeof(tcs_sha1
));
628 tes_bin
= anv_pipeline_cache_search(cache
, tes_sha1
, sizeof(tes_sha1
));
631 if (tcs_bin
== NULL
|| tes_bin
== NULL
) {
632 struct brw_tcs_prog_data tcs_prog_data
= { 0, };
633 struct brw_tes_prog_data tes_prog_data
= { 0, };
634 struct anv_pipeline_binding tcs_surface_to_descriptor
[256];
635 struct anv_pipeline_binding tcs_sampler_to_descriptor
[256];
636 struct anv_pipeline_binding tes_surface_to_descriptor
[256];
637 struct anv_pipeline_binding tes_sampler_to_descriptor
[256];
639 tcs_map
= (struct anv_pipeline_bind_map
) {
640 .surface_to_descriptor
= tcs_surface_to_descriptor
,
641 .sampler_to_descriptor
= tcs_sampler_to_descriptor
643 tes_map
= (struct anv_pipeline_bind_map
) {
644 .surface_to_descriptor
= tes_surface_to_descriptor
,
645 .sampler_to_descriptor
= tes_sampler_to_descriptor
648 nir_shader
*tcs_nir
=
649 anv_pipeline_compile(pipeline
, tcs_module
, tcs_entrypoint
,
650 MESA_SHADER_TESS_CTRL
, tcs_spec_info
,
651 &tcs_prog_data
.base
.base
, &tcs_map
);
652 nir_shader
*tes_nir
=
653 anv_pipeline_compile(pipeline
, tes_module
, tes_entrypoint
,
654 MESA_SHADER_TESS_EVAL
, tes_spec_info
,
655 &tes_prog_data
.base
.base
, &tes_map
);
656 if (tcs_nir
== NULL
|| tes_nir
== NULL
)
657 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
659 nir_lower_tes_patch_vertices(tes_nir
,
660 tcs_nir
->info
->tess
.tcs_vertices_out
);
662 /* Copy TCS info into the TES info */
663 merge_tess_info(tes_nir
->info
, tcs_nir
->info
);
665 anv_fill_binding_table(&tcs_prog_data
.base
.base
, 0);
666 anv_fill_binding_table(&tes_prog_data
.base
.base
, 0);
668 void *mem_ctx
= ralloc_context(NULL
);
670 ralloc_steal(mem_ctx
, tcs_nir
);
671 ralloc_steal(mem_ctx
, tes_nir
);
673 /* Whacking the key after cache lookup is a bit sketchy, but all of
674 * this comes from the SPIR-V, which is part of the hash used for the
675 * pipeline cache. So it should be safe.
677 tcs_key
.tes_primitive_mode
= tes_nir
->info
->tess
.primitive_mode
;
678 tcs_key
.outputs_written
= tcs_nir
->info
->outputs_written
;
679 tcs_key
.patch_outputs_written
= tcs_nir
->info
->patch_outputs_written
;
680 tcs_key
.quads_workaround
=
682 tes_nir
->info
->tess
.primitive_mode
== 7 /* GL_QUADS */ &&
683 tes_nir
->info
->tess
.spacing
== TESS_SPACING_EQUAL
;
685 tes_key
.inputs_read
= tcs_key
.outputs_written
;
686 tes_key
.patch_inputs_read
= tcs_key
.patch_outputs_written
;
689 const int shader_time_index
= -1;
690 const unsigned *shader_code
;
693 brw_compile_tcs(compiler
, NULL
, mem_ctx
, &tcs_key
, &tcs_prog_data
,
694 tcs_nir
, shader_time_index
, &code_size
, NULL
);
695 if (shader_code
== NULL
) {
696 ralloc_free(mem_ctx
);
697 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
700 tcs_bin
= anv_pipeline_upload_kernel(pipeline
, cache
,
701 tcs_sha1
, sizeof(tcs_sha1
),
702 shader_code
, code_size
,
703 &tcs_prog_data
.base
.base
,
704 sizeof(tcs_prog_data
),
707 ralloc_free(mem_ctx
);
708 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
712 brw_compile_tes(compiler
, NULL
, mem_ctx
, &tes_key
,
713 &tcs_prog_data
.base
.vue_map
, &tes_prog_data
, tes_nir
,
714 NULL
, shader_time_index
, &code_size
, NULL
);
715 if (shader_code
== NULL
) {
716 ralloc_free(mem_ctx
);
717 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
720 tes_bin
= anv_pipeline_upload_kernel(pipeline
, cache
,
721 tes_sha1
, sizeof(tes_sha1
),
722 shader_code
, code_size
,
723 &tes_prog_data
.base
.base
,
724 sizeof(tes_prog_data
),
727 ralloc_free(mem_ctx
);
728 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
731 ralloc_free(mem_ctx
);
734 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_TESS_CTRL
, tcs_bin
);
735 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_TESS_EVAL
, tes_bin
);
741 anv_pipeline_compile_gs(struct anv_pipeline
*pipeline
,
742 struct anv_pipeline_cache
*cache
,
743 const VkGraphicsPipelineCreateInfo
*info
,
744 struct anv_shader_module
*module
,
745 const char *entrypoint
,
746 const VkSpecializationInfo
*spec_info
)
748 const struct brw_compiler
*compiler
=
749 pipeline
->device
->instance
->physicalDevice
.compiler
;
750 struct anv_pipeline_bind_map map
;
751 struct brw_gs_prog_key key
;
752 struct anv_shader_bin
*bin
= NULL
;
753 unsigned char sha1
[20];
755 populate_gs_prog_key(&pipeline
->device
->info
, &key
);
758 anv_pipeline_hash_shader(pipeline
, module
, entrypoint
,
759 MESA_SHADER_GEOMETRY
, spec_info
,
760 &key
, sizeof(key
), sha1
);
761 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
765 struct brw_gs_prog_data prog_data
= { 0, };
766 struct anv_pipeline_binding surface_to_descriptor
[256];
767 struct anv_pipeline_binding sampler_to_descriptor
[256];
769 map
= (struct anv_pipeline_bind_map
) {
770 .surface_to_descriptor
= surface_to_descriptor
,
771 .sampler_to_descriptor
= sampler_to_descriptor
774 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
775 MESA_SHADER_GEOMETRY
, spec_info
,
776 &prog_data
.base
.base
, &map
);
778 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
780 anv_fill_binding_table(&prog_data
.base
.base
, 0);
782 void *mem_ctx
= ralloc_context(NULL
);
784 ralloc_steal(mem_ctx
, nir
);
786 brw_compute_vue_map(&pipeline
->device
->info
,
787 &prog_data
.base
.vue_map
,
788 nir
->info
->outputs_written
,
789 nir
->info
->separate_shader
);
792 const unsigned *shader_code
=
793 brw_compile_gs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
794 NULL
, -1, &code_size
, NULL
);
795 if (shader_code
== NULL
) {
796 ralloc_free(mem_ctx
);
797 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
801 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
802 shader_code
, code_size
,
803 &prog_data
.base
.base
, sizeof(prog_data
),
806 ralloc_free(mem_ctx
);
807 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
810 ralloc_free(mem_ctx
);
813 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_GEOMETRY
, bin
);
819 anv_pipeline_compile_fs(struct anv_pipeline
*pipeline
,
820 struct anv_pipeline_cache
*cache
,
821 const VkGraphicsPipelineCreateInfo
*info
,
822 struct anv_shader_module
*module
,
823 const char *entrypoint
,
824 const VkSpecializationInfo
*spec_info
)
826 const struct brw_compiler
*compiler
=
827 pipeline
->device
->instance
->physicalDevice
.compiler
;
828 struct anv_pipeline_bind_map map
;
829 struct brw_wm_prog_key key
;
830 struct anv_shader_bin
*bin
= NULL
;
831 unsigned char sha1
[20];
833 populate_wm_prog_key(pipeline
, info
, &key
);
836 anv_pipeline_hash_shader(pipeline
, module
, entrypoint
,
837 MESA_SHADER_FRAGMENT
, spec_info
,
838 &key
, sizeof(key
), sha1
);
839 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
843 struct brw_wm_prog_data prog_data
= { 0, };
844 struct anv_pipeline_binding surface_to_descriptor
[256];
845 struct anv_pipeline_binding sampler_to_descriptor
[256];
847 map
= (struct anv_pipeline_bind_map
) {
848 .surface_to_descriptor
= surface_to_descriptor
+ 8,
849 .sampler_to_descriptor
= sampler_to_descriptor
852 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
853 MESA_SHADER_FRAGMENT
, spec_info
,
854 &prog_data
.base
, &map
);
856 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
858 unsigned num_rts
= 0;
859 struct anv_pipeline_binding rt_bindings
[8];
860 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
861 nir_foreach_variable_safe(var
, &nir
->outputs
) {
862 if (var
->data
.location
< FRAG_RESULT_DATA0
)
865 unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
866 if (rt
>= key
.nr_color_regions
) {
867 /* Out-of-bounds, throw it away */
868 var
->data
.mode
= nir_var_local
;
869 exec_node_remove(&var
->node
);
870 exec_list_push_tail(&impl
->locals
, &var
->node
);
874 /* Give it a new, compacted, location */
875 var
->data
.location
= FRAG_RESULT_DATA0
+ num_rts
;
878 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
879 assert(num_rts
+ array_len
<= 8);
881 for (unsigned i
= 0; i
< array_len
; i
++) {
882 rt_bindings
[num_rts
+ i
] = (struct anv_pipeline_binding
) {
883 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
889 num_rts
+= array_len
;
893 /* If we have no render targets, we need a null render target */
894 rt_bindings
[0] = (struct anv_pipeline_binding
) {
895 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
902 assert(num_rts
<= 8);
903 map
.surface_to_descriptor
-= num_rts
;
904 map
.surface_count
+= num_rts
;
905 assert(map
.surface_count
<= 256);
906 memcpy(map
.surface_to_descriptor
, rt_bindings
,
907 num_rts
* sizeof(*rt_bindings
));
909 anv_fill_binding_table(&prog_data
.base
, num_rts
);
911 void *mem_ctx
= ralloc_context(NULL
);
913 ralloc_steal(mem_ctx
, nir
);
916 const unsigned *shader_code
=
917 brw_compile_fs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
918 NULL
, -1, -1, true, false, NULL
, &code_size
, NULL
);
919 if (shader_code
== NULL
) {
920 ralloc_free(mem_ctx
);
921 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
924 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
925 shader_code
, code_size
,
926 &prog_data
.base
, sizeof(prog_data
),
929 ralloc_free(mem_ctx
);
930 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
933 ralloc_free(mem_ctx
);
936 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_FRAGMENT
, bin
);
942 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
943 struct anv_pipeline_cache
*cache
,
944 const VkComputePipelineCreateInfo
*info
,
945 struct anv_shader_module
*module
,
946 const char *entrypoint
,
947 const VkSpecializationInfo
*spec_info
)
949 const struct brw_compiler
*compiler
=
950 pipeline
->device
->instance
->physicalDevice
.compiler
;
951 struct anv_pipeline_bind_map map
;
952 struct brw_cs_prog_key key
;
953 struct anv_shader_bin
*bin
= NULL
;
954 unsigned char sha1
[20];
956 populate_cs_prog_key(&pipeline
->device
->info
, &key
);
959 anv_pipeline_hash_shader(pipeline
, module
, entrypoint
,
960 MESA_SHADER_COMPUTE
, spec_info
,
961 &key
, sizeof(key
), sha1
);
962 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
966 struct brw_cs_prog_data prog_data
= { 0, };
967 struct anv_pipeline_binding surface_to_descriptor
[256];
968 struct anv_pipeline_binding sampler_to_descriptor
[256];
970 map
= (struct anv_pipeline_bind_map
) {
971 .surface_to_descriptor
= surface_to_descriptor
,
972 .sampler_to_descriptor
= sampler_to_descriptor
975 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
976 MESA_SHADER_COMPUTE
, spec_info
,
977 &prog_data
.base
, &map
);
979 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
981 anv_fill_binding_table(&prog_data
.base
, 1);
983 void *mem_ctx
= ralloc_context(NULL
);
985 ralloc_steal(mem_ctx
, nir
);
988 const unsigned *shader_code
=
989 brw_compile_cs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
990 -1, &code_size
, NULL
);
991 if (shader_code
== NULL
) {
992 ralloc_free(mem_ctx
);
993 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
996 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
997 shader_code
, code_size
,
998 &prog_data
.base
, sizeof(prog_data
),
1001 ralloc_free(mem_ctx
);
1002 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1005 ralloc_free(mem_ctx
);
1008 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_COMPUTE
, bin
);
1014 * Copy pipeline state not marked as dynamic.
1015 * Dynamic state is pipeline state which hasn't been provided at pipeline
1016 * creation time, but is dynamically provided afterwards using various
1017 * vkCmdSet* functions.
1019 * The set of state considered "non_dynamic" is determined by the pieces of
1020 * state that have their corresponding VkDynamicState enums omitted from
1021 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1023 * @param[out] pipeline Destination non_dynamic state.
1024 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1027 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
1028 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1030 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
1031 ANV_FROM_HANDLE(anv_render_pass
, pass
, pCreateInfo
->renderPass
);
1032 struct anv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1034 pipeline
->dynamic_state
= default_dynamic_state
;
1036 if (pCreateInfo
->pDynamicState
) {
1037 /* Remove all of the states that are marked as dynamic */
1038 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1039 for (uint32_t s
= 0; s
< count
; s
++)
1040 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1043 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1045 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1047 * pViewportState is [...] NULL if the pipeline
1048 * has rasterization disabled.
1050 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1051 assert(pCreateInfo
->pViewportState
);
1053 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1054 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
1055 typed_memcpy(dynamic
->viewport
.viewports
,
1056 pCreateInfo
->pViewportState
->pViewports
,
1057 pCreateInfo
->pViewportState
->viewportCount
);
1060 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1061 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
1062 typed_memcpy(dynamic
->scissor
.scissors
,
1063 pCreateInfo
->pViewportState
->pScissors
,
1064 pCreateInfo
->pViewportState
->scissorCount
);
1068 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1069 assert(pCreateInfo
->pRasterizationState
);
1070 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1073 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1074 assert(pCreateInfo
->pRasterizationState
);
1075 dynamic
->depth_bias
.bias
=
1076 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1077 dynamic
->depth_bias
.clamp
=
1078 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1079 dynamic
->depth_bias
.slope
=
1080 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1083 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1085 * pColorBlendState is [...] NULL if the pipeline has rasterization
1086 * disabled or if the subpass of the render pass the pipeline is
1087 * created against does not use any color attachments.
1089 bool uses_color_att
= false;
1090 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1091 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1092 uses_color_att
= true;
1097 if (uses_color_att
&&
1098 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1099 assert(pCreateInfo
->pColorBlendState
);
1101 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
1102 typed_memcpy(dynamic
->blend_constants
,
1103 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1106 /* If there is no depthstencil attachment, then don't read
1107 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1108 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1109 * no need to override the depthstencil defaults in
1110 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1112 * Section 9.2 of the Vulkan 1.0.15 spec says:
1114 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1115 * disabled or if the subpass of the render pass the pipeline is created
1116 * against does not use a depth/stencil attachment.
1118 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1119 subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1120 assert(pCreateInfo
->pDepthStencilState
);
1122 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1123 dynamic
->depth_bounds
.min
=
1124 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1125 dynamic
->depth_bounds
.max
=
1126 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1129 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1130 dynamic
->stencil_compare_mask
.front
=
1131 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1132 dynamic
->stencil_compare_mask
.back
=
1133 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1136 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1137 dynamic
->stencil_write_mask
.front
=
1138 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1139 dynamic
->stencil_write_mask
.back
=
1140 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1143 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1144 dynamic
->stencil_reference
.front
=
1145 pCreateInfo
->pDepthStencilState
->front
.reference
;
1146 dynamic
->stencil_reference
.back
=
1147 pCreateInfo
->pDepthStencilState
->back
.reference
;
1151 pipeline
->dynamic_state_mask
= states
;
1155 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1158 struct anv_render_pass
*renderpass
= NULL
;
1159 struct anv_subpass
*subpass
= NULL
;
1161 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1162 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1164 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1166 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1169 assert(info
->subpass
< renderpass
->subpass_count
);
1170 subpass
= &renderpass
->subpasses
[info
->subpass
];
1172 assert(info
->stageCount
>= 1);
1173 assert(info
->pVertexInputState
);
1174 assert(info
->pInputAssemblyState
);
1175 assert(info
->pRasterizationState
);
1176 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1177 assert(info
->pViewportState
);
1178 assert(info
->pMultisampleState
);
1180 if (subpass
&& subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
)
1181 assert(info
->pDepthStencilState
);
1183 if (subpass
&& subpass
->color_count
> 0)
1184 assert(info
->pColorBlendState
);
1187 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1188 switch (info
->pStages
[i
].stage
) {
1189 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1190 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1191 assert(info
->pTessellationState
);
1201 * Calculate the desired L3 partitioning based on the current state of the
1202 * pipeline. For now this simply returns the conservative defaults calculated
1203 * by get_default_l3_weights(), but we could probably do better by gathering
1204 * more statistics from the pipeline state (e.g. guess of expected URB usage
1205 * and bound surfaces), or by using feed-back from performance counters.
1208 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1210 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1212 const struct gen_l3_weights w
=
1213 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
1215 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
1216 pipeline
->urb
.total_size
=
1217 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
1221 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1222 struct anv_device
*device
,
1223 struct anv_pipeline_cache
*cache
,
1224 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1225 const VkAllocationCallbacks
*alloc
)
1229 anv_pipeline_validate_create_info(pCreateInfo
);
1232 alloc
= &device
->alloc
;
1234 pipeline
->device
= device
;
1235 pipeline
->layout
= anv_pipeline_layout_from_handle(pCreateInfo
->layout
);
1237 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1238 if (result
!= VK_SUCCESS
)
1241 pipeline
->batch
.alloc
= alloc
;
1242 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1243 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1244 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1245 pipeline
->batch
.status
= VK_SUCCESS
;
1247 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1248 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1249 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1251 pipeline
->sample_shading_enable
= pCreateInfo
->pMultisampleState
&&
1252 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
1254 pipeline
->needs_data_cache
= false;
1256 /* When we free the pipeline, we detect stages based on the NULL status
1257 * of various prog_data pointers. Make them NULL by default.
1259 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1261 pipeline
->active_stages
= 0;
1263 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
1264 struct anv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
1265 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
1266 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
1267 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
1268 modules
[stage
] = anv_shader_module_from_handle(pStages
[stage
]->module
);
1271 if (modules
[MESA_SHADER_VERTEX
]) {
1272 result
= anv_pipeline_compile_vs(pipeline
, cache
, pCreateInfo
,
1273 modules
[MESA_SHADER_VERTEX
],
1274 pStages
[MESA_SHADER_VERTEX
]->pName
,
1275 pStages
[MESA_SHADER_VERTEX
]->pSpecializationInfo
);
1276 if (result
!= VK_SUCCESS
)
1280 if (modules
[MESA_SHADER_TESS_EVAL
]) {
1281 anv_pipeline_compile_tcs_tes(pipeline
, cache
, pCreateInfo
,
1282 modules
[MESA_SHADER_TESS_CTRL
],
1283 pStages
[MESA_SHADER_TESS_CTRL
]->pName
,
1284 pStages
[MESA_SHADER_TESS_CTRL
]->pSpecializationInfo
,
1285 modules
[MESA_SHADER_TESS_EVAL
],
1286 pStages
[MESA_SHADER_TESS_EVAL
]->pName
,
1287 pStages
[MESA_SHADER_TESS_EVAL
]->pSpecializationInfo
);
1290 if (modules
[MESA_SHADER_GEOMETRY
]) {
1291 result
= anv_pipeline_compile_gs(pipeline
, cache
, pCreateInfo
,
1292 modules
[MESA_SHADER_GEOMETRY
],
1293 pStages
[MESA_SHADER_GEOMETRY
]->pName
,
1294 pStages
[MESA_SHADER_GEOMETRY
]->pSpecializationInfo
);
1295 if (result
!= VK_SUCCESS
)
1299 if (modules
[MESA_SHADER_FRAGMENT
]) {
1300 result
= anv_pipeline_compile_fs(pipeline
, cache
, pCreateInfo
,
1301 modules
[MESA_SHADER_FRAGMENT
],
1302 pStages
[MESA_SHADER_FRAGMENT
]->pName
,
1303 pStages
[MESA_SHADER_FRAGMENT
]->pSpecializationInfo
);
1304 if (result
!= VK_SUCCESS
)
1308 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1310 anv_pipeline_setup_l3_config(pipeline
, false);
1312 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1313 pCreateInfo
->pVertexInputState
;
1315 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1317 pipeline
->vb_used
= 0;
1318 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1319 const VkVertexInputAttributeDescription
*desc
=
1320 &vi_info
->pVertexAttributeDescriptions
[i
];
1322 if (inputs_read
& (1 << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1323 pipeline
->vb_used
|= 1 << desc
->binding
;
1326 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1327 const VkVertexInputBindingDescription
*desc
=
1328 &vi_info
->pVertexBindingDescriptions
[i
];
1330 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
1332 /* Step rate is programmed per vertex element (attribute), not
1333 * binding. Set up a map of which bindings step per instance, for
1334 * reference by vertex element setup. */
1335 switch (desc
->inputRate
) {
1337 case VK_VERTEX_INPUT_RATE_VERTEX
:
1338 pipeline
->instancing_enable
[desc
->binding
] = false;
1340 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1341 pipeline
->instancing_enable
[desc
->binding
] = true;
1346 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1347 pCreateInfo
->pInputAssemblyState
;
1348 const VkPipelineTessellationStateCreateInfo
*tess_info
=
1349 pCreateInfo
->pTessellationState
;
1350 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1352 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1353 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
1355 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];
1360 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1361 if (pipeline
->shaders
[s
])
1362 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
1365 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);