2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "common/gen_l3_config.h"
32 #include "anv_private.h"
33 #include "compiler/brw_nir.h"
35 #include "spirv/nir_spirv.h"
37 /* Needed for SWIZZLE macros */
38 #include "program/prog_instruction.h"
42 VkResult
anv_CreateShaderModule(
44 const VkShaderModuleCreateInfo
* pCreateInfo
,
45 const VkAllocationCallbacks
* pAllocator
,
46 VkShaderModule
* pShaderModule
)
48 ANV_FROM_HANDLE(anv_device
, device
, _device
);
49 struct anv_shader_module
*module
;
51 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
52 assert(pCreateInfo
->flags
== 0);
54 module
= vk_alloc2(&device
->alloc
, pAllocator
,
55 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
56 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
58 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
60 module
->size
= pCreateInfo
->codeSize
;
61 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
63 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
65 *pShaderModule
= anv_shader_module_to_handle(module
);
70 void anv_DestroyShaderModule(
72 VkShaderModule _module
,
73 const VkAllocationCallbacks
* pAllocator
)
75 ANV_FROM_HANDLE(anv_device
, device
, _device
);
76 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
81 vk_free2(&device
->alloc
, pAllocator
, module
);
84 #define SPIR_V_MAGIC_NUMBER 0x07230203
86 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
87 * we can't do that yet because we don't have the ability to copy nir.
90 anv_shader_compile_to_nir(struct anv_pipeline
*pipeline
,
91 struct anv_shader_module
*module
,
92 const char *entrypoint_name
,
93 gl_shader_stage stage
,
94 const VkSpecializationInfo
*spec_info
)
96 const struct anv_device
*device
= pipeline
->device
;
98 const struct brw_compiler
*compiler
=
99 device
->instance
->physicalDevice
.compiler
;
100 const nir_shader_compiler_options
*nir_options
=
101 compiler
->glsl_compiler_options
[stage
].NirOptions
;
103 uint32_t *spirv
= (uint32_t *) module
->data
;
104 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
105 assert(module
->size
% 4 == 0);
107 uint32_t num_spec_entries
= 0;
108 struct nir_spirv_specialization
*spec_entries
= NULL
;
109 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
110 num_spec_entries
= spec_info
->mapEntryCount
;
111 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
112 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
113 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
114 const void *data
= spec_info
->pData
+ entry
.offset
;
115 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
117 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
118 if (spec_info
->dataSize
== 8)
119 spec_entries
[i
].data64
= *(const uint64_t *)data
;
121 spec_entries
[i
].data32
= *(const uint32_t *)data
;
125 const struct nir_spirv_supported_extensions supported_ext
= {
126 .float64
= device
->instance
->physicalDevice
.info
.gen
>= 8,
127 .int64
= device
->instance
->physicalDevice
.info
.gen
>= 8,
128 .tessellation
= true,
129 .draw_parameters
= true,
130 .image_write_without_format
= true,
133 nir_function
*entry_point
=
134 spirv_to_nir(spirv
, module
->size
/ 4,
135 spec_entries
, num_spec_entries
,
136 stage
, entrypoint_name
, &supported_ext
, nir_options
);
137 nir_shader
*nir
= entry_point
->shader
;
138 assert(nir
->stage
== stage
);
139 nir_validate_shader(nir
);
143 /* We have to lower away local constant initializers right before we
144 * inline functions. That way they get properly initialized at the top
145 * of the function and not at the top of its caller.
147 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_local
);
148 NIR_PASS_V(nir
, nir_lower_returns
);
149 NIR_PASS_V(nir
, nir_inline_functions
);
151 /* Pick off the single entrypoint that we want */
152 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
153 if (func
!= entry_point
)
154 exec_node_remove(&func
->node
);
156 assert(exec_list_length(&nir
->functions
) == 1);
157 entry_point
->name
= ralloc_strdup(entry_point
, "main");
159 NIR_PASS_V(nir
, nir_remove_dead_variables
,
160 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
162 if (stage
== MESA_SHADER_FRAGMENT
)
163 NIR_PASS_V(nir
, nir_lower_wpos_center
, pipeline
->sample_shading_enable
);
165 /* Now that we've deleted all but the main function, we can go ahead and
166 * lower the rest of the constant initializers.
168 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
169 NIR_PASS_V(nir
, nir_propagate_invariant
);
170 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
171 entry_point
->impl
, true, false);
172 NIR_PASS_V(nir
, nir_lower_system_values
);
174 /* Vulkan uses the separate-shader linking model */
175 nir
->info
->separate_shader
= true;
177 nir
= brw_preprocess_nir(compiler
, nir
);
179 NIR_PASS_V(nir
, nir_lower_clip_cull_distance_arrays
);
181 if (stage
== MESA_SHADER_FRAGMENT
)
182 NIR_PASS_V(nir
, anv_nir_lower_input_attachments
);
187 void anv_DestroyPipeline(
189 VkPipeline _pipeline
,
190 const VkAllocationCallbacks
* pAllocator
)
192 ANV_FROM_HANDLE(anv_device
, device
, _device
);
193 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
198 anv_reloc_list_finish(&pipeline
->batch_relocs
,
199 pAllocator
? pAllocator
: &device
->alloc
);
200 if (pipeline
->blend_state
.map
)
201 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
203 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
204 if (pipeline
->shaders
[s
])
205 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
208 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
211 static const uint32_t vk_to_gen_primitive_type
[] = {
212 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
213 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
214 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
215 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
216 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
217 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
218 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
219 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
220 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
221 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
225 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
226 struct brw_sampler_prog_key_data
*key
)
228 /* Almost all multisampled textures are compressed. The only time when we
229 * don't compress a multisampled texture is for 16x MSAA with a surface
230 * width greater than 8k which is a bit of an edge case. Since the sampler
231 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
232 * to tell the compiler to always assume compression.
234 key
->compressed_multisample_layout_mask
= ~0;
236 /* SkyLake added support for 16x MSAA. With this came a new message for
237 * reading from a 16x MSAA surface with compression. The new message was
238 * needed because now the MCS data is 64 bits instead of 32 or lower as is
239 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
240 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
241 * so we can just use it unconditionally. This may not be quite as
242 * efficient but it saves us from recompiling.
244 if (devinfo
->gen
>= 9)
247 /* XXX: Handle texture swizzle on HSW- */
248 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
249 /* Assume color sampler, no swizzling. (Works for BDW+) */
250 key
->swizzles
[i
] = SWIZZLE_XYZW
;
255 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
256 struct brw_vs_prog_key
*key
)
258 memset(key
, 0, sizeof(*key
));
260 populate_sampler_prog_key(devinfo
, &key
->tex
);
262 /* XXX: Handle vertex input work-arounds */
264 /* XXX: Handle sampler_prog_key */
268 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
269 struct brw_gs_prog_key
*key
)
271 memset(key
, 0, sizeof(*key
));
273 populate_sampler_prog_key(devinfo
, &key
->tex
);
277 populate_wm_prog_key(const struct anv_pipeline
*pipeline
,
278 const VkGraphicsPipelineCreateInfo
*info
,
279 struct brw_wm_prog_key
*key
)
281 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
283 memset(key
, 0, sizeof(*key
));
285 populate_sampler_prog_key(devinfo
, &key
->tex
);
287 /* TODO: we could set this to 0 based on the information in nir_shader, but
288 * this function is called before spirv_to_nir. */
289 const struct brw_vue_map
*vue_map
=
290 &anv_pipeline_get_last_vue_prog_data(pipeline
)->vue_map
;
291 key
->input_slots_valid
= vue_map
->slots_valid
;
293 /* Vulkan doesn't specify a default */
294 key
->high_quality_derivatives
= false;
296 /* XXX Vulkan doesn't appear to specify */
297 key
->clamp_fragment_color
= false;
299 key
->nr_color_regions
= pipeline
->subpass
->color_count
;
301 key
->replicate_alpha
= key
->nr_color_regions
> 1 &&
302 info
->pMultisampleState
&&
303 info
->pMultisampleState
->alphaToCoverageEnable
;
305 if (info
->pMultisampleState
) {
306 /* We should probably pull this out of the shader, but it's fairly
307 * harmless to compute it and then let dead-code take care of it.
309 if (info
->pMultisampleState
->rasterizationSamples
> 1) {
310 key
->persample_interp
=
311 (info
->pMultisampleState
->minSampleShading
*
312 info
->pMultisampleState
->rasterizationSamples
) > 1;
313 key
->multisample_fbo
= true;
316 key
->frag_coord_adds_sample_pos
=
317 info
->pMultisampleState
->sampleShadingEnable
;
322 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
323 struct brw_cs_prog_key
*key
)
325 memset(key
, 0, sizeof(*key
));
327 populate_sampler_prog_key(devinfo
, &key
->tex
);
331 anv_pipeline_hash_shader(struct anv_pipeline
*pipeline
,
332 struct anv_shader_module
*module
,
333 const char *entrypoint
,
334 gl_shader_stage stage
,
335 const VkSpecializationInfo
*spec_info
,
336 const void *key
, size_t key_size
,
337 unsigned char *sha1_out
)
339 struct mesa_sha1 ctx
;
341 _mesa_sha1_init(&ctx
);
342 if (stage
!= MESA_SHADER_COMPUTE
) {
343 _mesa_sha1_update(&ctx
, &pipeline
->subpass
->view_mask
,
344 sizeof(pipeline
->subpass
->view_mask
));
346 if (pipeline
->layout
) {
347 _mesa_sha1_update(&ctx
, pipeline
->layout
->sha1
,
348 sizeof(pipeline
->layout
->sha1
));
350 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
351 _mesa_sha1_update(&ctx
, entrypoint
, strlen(entrypoint
));
352 _mesa_sha1_update(&ctx
, &stage
, sizeof(stage
));
354 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
355 spec_info
->mapEntryCount
* sizeof(*spec_info
->pMapEntries
));
356 _mesa_sha1_update(&ctx
, spec_info
->pData
, spec_info
->dataSize
);
358 _mesa_sha1_update(&ctx
, key
, key_size
);
359 _mesa_sha1_final(&ctx
, sha1_out
);
363 anv_pipeline_compile(struct anv_pipeline
*pipeline
,
364 struct anv_shader_module
*module
,
365 const char *entrypoint
,
366 gl_shader_stage stage
,
367 const VkSpecializationInfo
*spec_info
,
368 struct brw_stage_prog_data
*prog_data
,
369 struct anv_pipeline_bind_map
*map
)
371 nir_shader
*nir
= anv_shader_compile_to_nir(pipeline
,
372 module
, entrypoint
, stage
,
377 NIR_PASS_V(nir
, anv_nir_lower_push_constants
);
379 if (stage
!= MESA_SHADER_COMPUTE
)
380 NIR_PASS_V(nir
, anv_nir_lower_multiview
, pipeline
->subpass
->view_mask
);
382 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
384 /* Figure out the number of parameters */
385 prog_data
->nr_params
= 0;
387 if (nir
->num_uniforms
> 0) {
388 /* If the shader uses any push constants at all, we'll just give
389 * them the maximum possible number
391 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
392 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
395 if (nir
->info
->num_images
> 0) {
396 prog_data
->nr_params
+= nir
->info
->num_images
* BRW_IMAGE_PARAM_SIZE
;
397 pipeline
->needs_data_cache
= true;
400 if (stage
== MESA_SHADER_COMPUTE
)
401 ((struct brw_cs_prog_data
*)prog_data
)->thread_local_id_index
=
402 prog_data
->nr_params
++; /* The CS Thread ID uniform */
404 if (nir
->info
->num_ssbos
> 0)
405 pipeline
->needs_data_cache
= true;
407 if (prog_data
->nr_params
> 0) {
408 /* XXX: I think we're leaking this */
409 prog_data
->param
= (const union gl_constant_value
**)
410 malloc(prog_data
->nr_params
* sizeof(union gl_constant_value
*));
412 /* We now set the param values to be offsets into a
413 * anv_push_constant_data structure. Since the compiler doesn't
414 * actually dereference any of the gl_constant_value pointers in the
415 * params array, it doesn't really matter what we put here.
417 struct anv_push_constants
*null_data
= NULL
;
418 if (nir
->num_uniforms
> 0) {
419 /* Fill out the push constants section of the param array */
420 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++)
421 prog_data
->param
[i
] = (const union gl_constant_value
*)
422 &null_data
->client_data
[i
* sizeof(float)];
426 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
427 if (pipeline
->layout
)
428 anv_nir_apply_pipeline_layout(pipeline
, nir
, prog_data
, map
);
430 /* nir_lower_io will only handle the push constants; we need to set this
431 * to the full number of possible uniforms.
433 nir
->num_uniforms
= prog_data
->nr_params
* 4;
439 anv_fill_binding_table(struct brw_stage_prog_data
*prog_data
, unsigned bias
)
441 prog_data
->binding_table
.size_bytes
= 0;
442 prog_data
->binding_table
.texture_start
= bias
;
443 prog_data
->binding_table
.gather_texture_start
= bias
;
444 prog_data
->binding_table
.ubo_start
= bias
;
445 prog_data
->binding_table
.ssbo_start
= bias
;
446 prog_data
->binding_table
.image_start
= bias
;
449 static struct anv_shader_bin
*
450 anv_pipeline_upload_kernel(struct anv_pipeline
*pipeline
,
451 struct anv_pipeline_cache
*cache
,
452 const void *key_data
, uint32_t key_size
,
453 const void *kernel_data
, uint32_t kernel_size
,
454 const struct brw_stage_prog_data
*prog_data
,
455 uint32_t prog_data_size
,
456 const struct anv_pipeline_bind_map
*bind_map
)
459 return anv_pipeline_cache_upload_kernel(cache
, key_data
, key_size
,
460 kernel_data
, kernel_size
,
461 prog_data
, prog_data_size
,
464 return anv_shader_bin_create(pipeline
->device
, key_data
, key_size
,
465 kernel_data
, kernel_size
,
466 prog_data
, prog_data_size
,
467 prog_data
->param
, bind_map
);
473 anv_pipeline_add_compiled_stage(struct anv_pipeline
*pipeline
,
474 gl_shader_stage stage
,
475 struct anv_shader_bin
*shader
)
477 pipeline
->shaders
[stage
] = shader
;
478 pipeline
->active_stages
|= mesa_to_vk_shader_stage(stage
);
482 anv_pipeline_compile_vs(struct anv_pipeline
*pipeline
,
483 struct anv_pipeline_cache
*cache
,
484 const VkGraphicsPipelineCreateInfo
*info
,
485 struct anv_shader_module
*module
,
486 const char *entrypoint
,
487 const VkSpecializationInfo
*spec_info
)
489 const struct brw_compiler
*compiler
=
490 pipeline
->device
->instance
->physicalDevice
.compiler
;
491 struct anv_pipeline_bind_map map
;
492 struct brw_vs_prog_key key
;
493 struct anv_shader_bin
*bin
= NULL
;
494 unsigned char sha1
[20];
496 populate_vs_prog_key(&pipeline
->device
->info
, &key
);
499 anv_pipeline_hash_shader(pipeline
, module
, entrypoint
,
500 MESA_SHADER_VERTEX
, spec_info
,
501 &key
, sizeof(key
), sha1
);
502 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
506 struct brw_vs_prog_data prog_data
= { 0, };
507 struct anv_pipeline_binding surface_to_descriptor
[256];
508 struct anv_pipeline_binding sampler_to_descriptor
[256];
510 map
= (struct anv_pipeline_bind_map
) {
511 .surface_to_descriptor
= surface_to_descriptor
,
512 .sampler_to_descriptor
= sampler_to_descriptor
515 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
516 MESA_SHADER_VERTEX
, spec_info
,
517 &prog_data
.base
.base
, &map
);
519 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
521 anv_fill_binding_table(&prog_data
.base
.base
, 0);
523 void *mem_ctx
= ralloc_context(NULL
);
525 ralloc_steal(mem_ctx
, nir
);
527 prog_data
.inputs_read
= nir
->info
->inputs_read
;
528 prog_data
.double_inputs_read
= nir
->info
->double_inputs_read
;
530 brw_compute_vue_map(&pipeline
->device
->info
,
531 &prog_data
.base
.vue_map
,
532 nir
->info
->outputs_written
,
533 nir
->info
->separate_shader
);
536 const unsigned *shader_code
=
537 brw_compile_vs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
538 NULL
, false, -1, &code_size
, NULL
);
539 if (shader_code
== NULL
) {
540 ralloc_free(mem_ctx
);
541 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
544 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
545 shader_code
, code_size
,
546 &prog_data
.base
.base
, sizeof(prog_data
),
549 ralloc_free(mem_ctx
);
550 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
553 ralloc_free(mem_ctx
);
556 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_VERTEX
, bin
);
562 merge_tess_info(struct shader_info
*tes_info
,
563 const struct shader_info
*tcs_info
)
565 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
567 * "PointMode. Controls generation of points rather than triangles
568 * or lines. This functionality defaults to disabled, and is
569 * enabled if either shader stage includes the execution mode.
571 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
572 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
573 * and OutputVertices, it says:
575 * "One mode must be set in at least one of the tessellation
578 * So, the fields can be set in either the TCS or TES, but they must
579 * agree if set in both. Our backend looks at TES, so bitwise-or in
580 * the values from the TCS.
582 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
583 tes_info
->tess
.tcs_vertices_out
== 0 ||
584 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
585 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
587 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
588 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
589 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
590 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
592 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
593 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
597 anv_pipeline_compile_tcs_tes(struct anv_pipeline
*pipeline
,
598 struct anv_pipeline_cache
*cache
,
599 const VkGraphicsPipelineCreateInfo
*info
,
600 struct anv_shader_module
*tcs_module
,
601 const char *tcs_entrypoint
,
602 const VkSpecializationInfo
*tcs_spec_info
,
603 struct anv_shader_module
*tes_module
,
604 const char *tes_entrypoint
,
605 const VkSpecializationInfo
*tes_spec_info
)
607 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
608 const struct brw_compiler
*compiler
=
609 pipeline
->device
->instance
->physicalDevice
.compiler
;
610 struct anv_pipeline_bind_map tcs_map
;
611 struct anv_pipeline_bind_map tes_map
;
612 struct brw_tcs_prog_key tcs_key
= { 0, };
613 struct brw_tes_prog_key tes_key
= { 0, };
614 struct anv_shader_bin
*tcs_bin
= NULL
;
615 struct anv_shader_bin
*tes_bin
= NULL
;
616 unsigned char tcs_sha1
[40];
617 unsigned char tes_sha1
[40];
619 populate_sampler_prog_key(&pipeline
->device
->info
, &tcs_key
.tex
);
620 populate_sampler_prog_key(&pipeline
->device
->info
, &tes_key
.tex
);
621 tcs_key
.input_vertices
= info
->pTessellationState
->patchControlPoints
;
624 anv_pipeline_hash_shader(pipeline
, tcs_module
, tcs_entrypoint
,
625 MESA_SHADER_TESS_CTRL
, tcs_spec_info
,
626 &tcs_key
, sizeof(tcs_key
), tcs_sha1
);
627 anv_pipeline_hash_shader(pipeline
, tes_module
, tes_entrypoint
,
628 MESA_SHADER_TESS_EVAL
, tes_spec_info
,
629 &tes_key
, sizeof(tes_key
), tes_sha1
);
630 memcpy(&tcs_sha1
[20], tes_sha1
, 20);
631 memcpy(&tes_sha1
[20], tcs_sha1
, 20);
632 tcs_bin
= anv_pipeline_cache_search(cache
, tcs_sha1
, sizeof(tcs_sha1
));
633 tes_bin
= anv_pipeline_cache_search(cache
, tes_sha1
, sizeof(tes_sha1
));
636 if (tcs_bin
== NULL
|| tes_bin
== NULL
) {
637 struct brw_tcs_prog_data tcs_prog_data
= { 0, };
638 struct brw_tes_prog_data tes_prog_data
= { 0, };
639 struct anv_pipeline_binding tcs_surface_to_descriptor
[256];
640 struct anv_pipeline_binding tcs_sampler_to_descriptor
[256];
641 struct anv_pipeline_binding tes_surface_to_descriptor
[256];
642 struct anv_pipeline_binding tes_sampler_to_descriptor
[256];
644 tcs_map
= (struct anv_pipeline_bind_map
) {
645 .surface_to_descriptor
= tcs_surface_to_descriptor
,
646 .sampler_to_descriptor
= tcs_sampler_to_descriptor
648 tes_map
= (struct anv_pipeline_bind_map
) {
649 .surface_to_descriptor
= tes_surface_to_descriptor
,
650 .sampler_to_descriptor
= tes_sampler_to_descriptor
653 nir_shader
*tcs_nir
=
654 anv_pipeline_compile(pipeline
, tcs_module
, tcs_entrypoint
,
655 MESA_SHADER_TESS_CTRL
, tcs_spec_info
,
656 &tcs_prog_data
.base
.base
, &tcs_map
);
657 nir_shader
*tes_nir
=
658 anv_pipeline_compile(pipeline
, tes_module
, tes_entrypoint
,
659 MESA_SHADER_TESS_EVAL
, tes_spec_info
,
660 &tes_prog_data
.base
.base
, &tes_map
);
661 if (tcs_nir
== NULL
|| tes_nir
== NULL
)
662 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
664 nir_lower_tes_patch_vertices(tes_nir
,
665 tcs_nir
->info
->tess
.tcs_vertices_out
);
667 /* Copy TCS info into the TES info */
668 merge_tess_info(tes_nir
->info
, tcs_nir
->info
);
670 anv_fill_binding_table(&tcs_prog_data
.base
.base
, 0);
671 anv_fill_binding_table(&tes_prog_data
.base
.base
, 0);
673 void *mem_ctx
= ralloc_context(NULL
);
675 ralloc_steal(mem_ctx
, tcs_nir
);
676 ralloc_steal(mem_ctx
, tes_nir
);
678 /* Whacking the key after cache lookup is a bit sketchy, but all of
679 * this comes from the SPIR-V, which is part of the hash used for the
680 * pipeline cache. So it should be safe.
682 tcs_key
.tes_primitive_mode
= tes_nir
->info
->tess
.primitive_mode
;
683 tcs_key
.outputs_written
= tcs_nir
->info
->outputs_written
;
684 tcs_key
.patch_outputs_written
= tcs_nir
->info
->patch_outputs_written
;
685 tcs_key
.quads_workaround
=
687 tes_nir
->info
->tess
.primitive_mode
== 7 /* GL_QUADS */ &&
688 tes_nir
->info
->tess
.spacing
== TESS_SPACING_EQUAL
;
690 tes_key
.inputs_read
= tcs_key
.outputs_written
;
691 tes_key
.patch_inputs_read
= tcs_key
.patch_outputs_written
;
694 const int shader_time_index
= -1;
695 const unsigned *shader_code
;
698 brw_compile_tcs(compiler
, NULL
, mem_ctx
, &tcs_key
, &tcs_prog_data
,
699 tcs_nir
, shader_time_index
, &code_size
, NULL
);
700 if (shader_code
== NULL
) {
701 ralloc_free(mem_ctx
);
702 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
705 tcs_bin
= anv_pipeline_upload_kernel(pipeline
, cache
,
706 tcs_sha1
, sizeof(tcs_sha1
),
707 shader_code
, code_size
,
708 &tcs_prog_data
.base
.base
,
709 sizeof(tcs_prog_data
),
712 ralloc_free(mem_ctx
);
713 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
717 brw_compile_tes(compiler
, NULL
, mem_ctx
, &tes_key
,
718 &tcs_prog_data
.base
.vue_map
, &tes_prog_data
, tes_nir
,
719 NULL
, shader_time_index
, &code_size
, NULL
);
720 if (shader_code
== NULL
) {
721 ralloc_free(mem_ctx
);
722 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
725 tes_bin
= anv_pipeline_upload_kernel(pipeline
, cache
,
726 tes_sha1
, sizeof(tes_sha1
),
727 shader_code
, code_size
,
728 &tes_prog_data
.base
.base
,
729 sizeof(tes_prog_data
),
732 ralloc_free(mem_ctx
);
733 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
736 ralloc_free(mem_ctx
);
739 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_TESS_CTRL
, tcs_bin
);
740 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_TESS_EVAL
, tes_bin
);
746 anv_pipeline_compile_gs(struct anv_pipeline
*pipeline
,
747 struct anv_pipeline_cache
*cache
,
748 const VkGraphicsPipelineCreateInfo
*info
,
749 struct anv_shader_module
*module
,
750 const char *entrypoint
,
751 const VkSpecializationInfo
*spec_info
)
753 const struct brw_compiler
*compiler
=
754 pipeline
->device
->instance
->physicalDevice
.compiler
;
755 struct anv_pipeline_bind_map map
;
756 struct brw_gs_prog_key key
;
757 struct anv_shader_bin
*bin
= NULL
;
758 unsigned char sha1
[20];
760 populate_gs_prog_key(&pipeline
->device
->info
, &key
);
763 anv_pipeline_hash_shader(pipeline
, module
, entrypoint
,
764 MESA_SHADER_GEOMETRY
, spec_info
,
765 &key
, sizeof(key
), sha1
);
766 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
770 struct brw_gs_prog_data prog_data
= { 0, };
771 struct anv_pipeline_binding surface_to_descriptor
[256];
772 struct anv_pipeline_binding sampler_to_descriptor
[256];
774 map
= (struct anv_pipeline_bind_map
) {
775 .surface_to_descriptor
= surface_to_descriptor
,
776 .sampler_to_descriptor
= sampler_to_descriptor
779 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
780 MESA_SHADER_GEOMETRY
, spec_info
,
781 &prog_data
.base
.base
, &map
);
783 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
785 anv_fill_binding_table(&prog_data
.base
.base
, 0);
787 void *mem_ctx
= ralloc_context(NULL
);
789 ralloc_steal(mem_ctx
, nir
);
791 brw_compute_vue_map(&pipeline
->device
->info
,
792 &prog_data
.base
.vue_map
,
793 nir
->info
->outputs_written
,
794 nir
->info
->separate_shader
);
797 const unsigned *shader_code
=
798 brw_compile_gs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
799 NULL
, -1, &code_size
, NULL
);
800 if (shader_code
== NULL
) {
801 ralloc_free(mem_ctx
);
802 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
806 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
807 shader_code
, code_size
,
808 &prog_data
.base
.base
, sizeof(prog_data
),
811 ralloc_free(mem_ctx
);
812 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
815 ralloc_free(mem_ctx
);
818 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_GEOMETRY
, bin
);
824 anv_pipeline_compile_fs(struct anv_pipeline
*pipeline
,
825 struct anv_pipeline_cache
*cache
,
826 const VkGraphicsPipelineCreateInfo
*info
,
827 struct anv_shader_module
*module
,
828 const char *entrypoint
,
829 const VkSpecializationInfo
*spec_info
)
831 const struct brw_compiler
*compiler
=
832 pipeline
->device
->instance
->physicalDevice
.compiler
;
833 struct anv_pipeline_bind_map map
;
834 struct brw_wm_prog_key key
;
835 struct anv_shader_bin
*bin
= NULL
;
836 unsigned char sha1
[20];
838 populate_wm_prog_key(pipeline
, info
, &key
);
841 anv_pipeline_hash_shader(pipeline
, module
, entrypoint
,
842 MESA_SHADER_FRAGMENT
, spec_info
,
843 &key
, sizeof(key
), sha1
);
844 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
848 struct brw_wm_prog_data prog_data
= { 0, };
849 struct anv_pipeline_binding surface_to_descriptor
[256];
850 struct anv_pipeline_binding sampler_to_descriptor
[256];
852 map
= (struct anv_pipeline_bind_map
) {
853 .surface_to_descriptor
= surface_to_descriptor
+ 8,
854 .sampler_to_descriptor
= sampler_to_descriptor
857 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
858 MESA_SHADER_FRAGMENT
, spec_info
,
859 &prog_data
.base
, &map
);
861 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
863 unsigned num_rts
= 0;
864 struct anv_pipeline_binding rt_bindings
[8];
865 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
866 nir_foreach_variable_safe(var
, &nir
->outputs
) {
867 if (var
->data
.location
< FRAG_RESULT_DATA0
)
870 unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
871 if (rt
>= key
.nr_color_regions
) {
872 /* Out-of-bounds, throw it away */
873 var
->data
.mode
= nir_var_local
;
874 exec_node_remove(&var
->node
);
875 exec_list_push_tail(&impl
->locals
, &var
->node
);
879 /* Give it a new, compacted, location */
880 var
->data
.location
= FRAG_RESULT_DATA0
+ num_rts
;
883 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
884 assert(num_rts
+ array_len
<= 8);
886 for (unsigned i
= 0; i
< array_len
; i
++) {
887 rt_bindings
[num_rts
+ i
] = (struct anv_pipeline_binding
) {
888 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
894 num_rts
+= array_len
;
898 /* If we have no render targets, we need a null render target */
899 rt_bindings
[0] = (struct anv_pipeline_binding
) {
900 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
907 assert(num_rts
<= 8);
908 map
.surface_to_descriptor
-= num_rts
;
909 map
.surface_count
+= num_rts
;
910 assert(map
.surface_count
<= 256);
911 memcpy(map
.surface_to_descriptor
, rt_bindings
,
912 num_rts
* sizeof(*rt_bindings
));
914 anv_fill_binding_table(&prog_data
.base
, num_rts
);
916 void *mem_ctx
= ralloc_context(NULL
);
918 ralloc_steal(mem_ctx
, nir
);
921 const unsigned *shader_code
=
922 brw_compile_fs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
923 NULL
, -1, -1, true, false, NULL
, &code_size
, NULL
);
924 if (shader_code
== NULL
) {
925 ralloc_free(mem_ctx
);
926 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
929 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
930 shader_code
, code_size
,
931 &prog_data
.base
, sizeof(prog_data
),
934 ralloc_free(mem_ctx
);
935 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
938 ralloc_free(mem_ctx
);
941 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_FRAGMENT
, bin
);
947 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
948 struct anv_pipeline_cache
*cache
,
949 const VkComputePipelineCreateInfo
*info
,
950 struct anv_shader_module
*module
,
951 const char *entrypoint
,
952 const VkSpecializationInfo
*spec_info
)
954 const struct brw_compiler
*compiler
=
955 pipeline
->device
->instance
->physicalDevice
.compiler
;
956 struct anv_pipeline_bind_map map
;
957 struct brw_cs_prog_key key
;
958 struct anv_shader_bin
*bin
= NULL
;
959 unsigned char sha1
[20];
961 populate_cs_prog_key(&pipeline
->device
->info
, &key
);
964 anv_pipeline_hash_shader(pipeline
, module
, entrypoint
,
965 MESA_SHADER_COMPUTE
, spec_info
,
966 &key
, sizeof(key
), sha1
);
967 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
971 struct brw_cs_prog_data prog_data
= { 0, };
972 struct anv_pipeline_binding surface_to_descriptor
[256];
973 struct anv_pipeline_binding sampler_to_descriptor
[256];
975 map
= (struct anv_pipeline_bind_map
) {
976 .surface_to_descriptor
= surface_to_descriptor
,
977 .sampler_to_descriptor
= sampler_to_descriptor
980 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
981 MESA_SHADER_COMPUTE
, spec_info
,
982 &prog_data
.base
, &map
);
984 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
986 anv_fill_binding_table(&prog_data
.base
, 1);
988 void *mem_ctx
= ralloc_context(NULL
);
990 ralloc_steal(mem_ctx
, nir
);
993 const unsigned *shader_code
=
994 brw_compile_cs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
995 -1, &code_size
, NULL
);
996 if (shader_code
== NULL
) {
997 ralloc_free(mem_ctx
);
998 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1001 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
1002 shader_code
, code_size
,
1003 &prog_data
.base
, sizeof(prog_data
),
1006 ralloc_free(mem_ctx
);
1007 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1010 ralloc_free(mem_ctx
);
1013 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_COMPUTE
, bin
);
1019 * Copy pipeline state not marked as dynamic.
1020 * Dynamic state is pipeline state which hasn't been provided at pipeline
1021 * creation time, but is dynamically provided afterwards using various
1022 * vkCmdSet* functions.
1024 * The set of state considered "non_dynamic" is determined by the pieces of
1025 * state that have their corresponding VkDynamicState enums omitted from
1026 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1028 * @param[out] pipeline Destination non_dynamic state.
1029 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1032 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
1033 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1035 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
1036 struct anv_subpass
*subpass
= pipeline
->subpass
;
1038 pipeline
->dynamic_state
= default_dynamic_state
;
1040 if (pCreateInfo
->pDynamicState
) {
1041 /* Remove all of the states that are marked as dynamic */
1042 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1043 for (uint32_t s
= 0; s
< count
; s
++)
1044 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1047 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1049 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1051 * pViewportState is [...] NULL if the pipeline
1052 * has rasterization disabled.
1054 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1055 assert(pCreateInfo
->pViewportState
);
1057 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1058 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
1059 typed_memcpy(dynamic
->viewport
.viewports
,
1060 pCreateInfo
->pViewportState
->pViewports
,
1061 pCreateInfo
->pViewportState
->viewportCount
);
1064 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1065 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
1066 typed_memcpy(dynamic
->scissor
.scissors
,
1067 pCreateInfo
->pViewportState
->pScissors
,
1068 pCreateInfo
->pViewportState
->scissorCount
);
1072 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1073 assert(pCreateInfo
->pRasterizationState
);
1074 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1077 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1078 assert(pCreateInfo
->pRasterizationState
);
1079 dynamic
->depth_bias
.bias
=
1080 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1081 dynamic
->depth_bias
.clamp
=
1082 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1083 dynamic
->depth_bias
.slope
=
1084 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1087 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1089 * pColorBlendState is [...] NULL if the pipeline has rasterization
1090 * disabled or if the subpass of the render pass the pipeline is
1091 * created against does not use any color attachments.
1093 bool uses_color_att
= false;
1094 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1095 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1096 uses_color_att
= true;
1101 if (uses_color_att
&&
1102 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1103 assert(pCreateInfo
->pColorBlendState
);
1105 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
1106 typed_memcpy(dynamic
->blend_constants
,
1107 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1110 /* If there is no depthstencil attachment, then don't read
1111 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1112 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1113 * no need to override the depthstencil defaults in
1114 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1116 * Section 9.2 of the Vulkan 1.0.15 spec says:
1118 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1119 * disabled or if the subpass of the render pass the pipeline is created
1120 * against does not use a depth/stencil attachment.
1122 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1123 subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1124 assert(pCreateInfo
->pDepthStencilState
);
1126 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1127 dynamic
->depth_bounds
.min
=
1128 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1129 dynamic
->depth_bounds
.max
=
1130 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1133 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1134 dynamic
->stencil_compare_mask
.front
=
1135 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1136 dynamic
->stencil_compare_mask
.back
=
1137 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1140 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1141 dynamic
->stencil_write_mask
.front
=
1142 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1143 dynamic
->stencil_write_mask
.back
=
1144 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1147 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1148 dynamic
->stencil_reference
.front
=
1149 pCreateInfo
->pDepthStencilState
->front
.reference
;
1150 dynamic
->stencil_reference
.back
=
1151 pCreateInfo
->pDepthStencilState
->back
.reference
;
1155 pipeline
->dynamic_state_mask
= states
;
1159 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1162 struct anv_render_pass
*renderpass
= NULL
;
1163 struct anv_subpass
*subpass
= NULL
;
1165 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1166 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1168 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1170 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1173 assert(info
->subpass
< renderpass
->subpass_count
);
1174 subpass
= &renderpass
->subpasses
[info
->subpass
];
1176 assert(info
->stageCount
>= 1);
1177 assert(info
->pVertexInputState
);
1178 assert(info
->pInputAssemblyState
);
1179 assert(info
->pRasterizationState
);
1180 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1181 assert(info
->pViewportState
);
1182 assert(info
->pMultisampleState
);
1184 if (subpass
&& subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
)
1185 assert(info
->pDepthStencilState
);
1187 if (subpass
&& subpass
->color_count
> 0)
1188 assert(info
->pColorBlendState
);
1191 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1192 switch (info
->pStages
[i
].stage
) {
1193 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1194 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1195 assert(info
->pTessellationState
);
1205 * Calculate the desired L3 partitioning based on the current state of the
1206 * pipeline. For now this simply returns the conservative defaults calculated
1207 * by get_default_l3_weights(), but we could probably do better by gathering
1208 * more statistics from the pipeline state (e.g. guess of expected URB usage
1209 * and bound surfaces), or by using feed-back from performance counters.
1212 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1214 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1216 const struct gen_l3_weights w
=
1217 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
1219 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
1220 pipeline
->urb
.total_size
=
1221 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
1225 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1226 struct anv_device
*device
,
1227 struct anv_pipeline_cache
*cache
,
1228 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1229 const VkAllocationCallbacks
*alloc
)
1233 anv_pipeline_validate_create_info(pCreateInfo
);
1236 alloc
= &device
->alloc
;
1238 pipeline
->device
= device
;
1240 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, pCreateInfo
->renderPass
);
1241 assert(pCreateInfo
->subpass
< render_pass
->subpass_count
);
1242 pipeline
->subpass
= &render_pass
->subpasses
[pCreateInfo
->subpass
];
1244 pipeline
->layout
= anv_pipeline_layout_from_handle(pCreateInfo
->layout
);
1246 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1247 if (result
!= VK_SUCCESS
)
1250 pipeline
->batch
.alloc
= alloc
;
1251 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1252 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1253 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1254 pipeline
->batch
.status
= VK_SUCCESS
;
1256 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1257 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1258 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1260 pipeline
->sample_shading_enable
= pCreateInfo
->pMultisampleState
&&
1261 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
1263 pipeline
->needs_data_cache
= false;
1265 /* When we free the pipeline, we detect stages based on the NULL status
1266 * of various prog_data pointers. Make them NULL by default.
1268 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1270 pipeline
->active_stages
= 0;
1272 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
1273 struct anv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
1274 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
1275 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
1276 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
1277 modules
[stage
] = anv_shader_module_from_handle(pStages
[stage
]->module
);
1280 if (modules
[MESA_SHADER_VERTEX
]) {
1281 result
= anv_pipeline_compile_vs(pipeline
, cache
, pCreateInfo
,
1282 modules
[MESA_SHADER_VERTEX
],
1283 pStages
[MESA_SHADER_VERTEX
]->pName
,
1284 pStages
[MESA_SHADER_VERTEX
]->pSpecializationInfo
);
1285 if (result
!= VK_SUCCESS
)
1289 if (modules
[MESA_SHADER_TESS_EVAL
]) {
1290 anv_pipeline_compile_tcs_tes(pipeline
, cache
, pCreateInfo
,
1291 modules
[MESA_SHADER_TESS_CTRL
],
1292 pStages
[MESA_SHADER_TESS_CTRL
]->pName
,
1293 pStages
[MESA_SHADER_TESS_CTRL
]->pSpecializationInfo
,
1294 modules
[MESA_SHADER_TESS_EVAL
],
1295 pStages
[MESA_SHADER_TESS_EVAL
]->pName
,
1296 pStages
[MESA_SHADER_TESS_EVAL
]->pSpecializationInfo
);
1299 if (modules
[MESA_SHADER_GEOMETRY
]) {
1300 result
= anv_pipeline_compile_gs(pipeline
, cache
, pCreateInfo
,
1301 modules
[MESA_SHADER_GEOMETRY
],
1302 pStages
[MESA_SHADER_GEOMETRY
]->pName
,
1303 pStages
[MESA_SHADER_GEOMETRY
]->pSpecializationInfo
);
1304 if (result
!= VK_SUCCESS
)
1308 if (modules
[MESA_SHADER_FRAGMENT
]) {
1309 result
= anv_pipeline_compile_fs(pipeline
, cache
, pCreateInfo
,
1310 modules
[MESA_SHADER_FRAGMENT
],
1311 pStages
[MESA_SHADER_FRAGMENT
]->pName
,
1312 pStages
[MESA_SHADER_FRAGMENT
]->pSpecializationInfo
);
1313 if (result
!= VK_SUCCESS
)
1317 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1319 anv_pipeline_setup_l3_config(pipeline
, false);
1321 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1322 pCreateInfo
->pVertexInputState
;
1324 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1326 pipeline
->vb_used
= 0;
1327 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1328 const VkVertexInputAttributeDescription
*desc
=
1329 &vi_info
->pVertexAttributeDescriptions
[i
];
1331 if (inputs_read
& (1 << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1332 pipeline
->vb_used
|= 1 << desc
->binding
;
1335 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1336 const VkVertexInputBindingDescription
*desc
=
1337 &vi_info
->pVertexBindingDescriptions
[i
];
1339 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
1341 /* Step rate is programmed per vertex element (attribute), not
1342 * binding. Set up a map of which bindings step per instance, for
1343 * reference by vertex element setup. */
1344 switch (desc
->inputRate
) {
1346 case VK_VERTEX_INPUT_RATE_VERTEX
:
1347 pipeline
->instancing_enable
[desc
->binding
] = false;
1349 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1350 pipeline
->instancing_enable
[desc
->binding
] = true;
1355 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1356 pCreateInfo
->pInputAssemblyState
;
1357 const VkPipelineTessellationStateCreateInfo
*tess_info
=
1358 pCreateInfo
->pTessellationState
;
1359 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1361 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1362 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
1364 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];
1369 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1370 if (pipeline
->shaders
[s
])
1371 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
1374 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);