2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "util/os_time.h"
32 #include "common/gen_l3_config.h"
33 #include "anv_private.h"
34 #include "compiler/brw_nir.h"
36 #include "nir/nir_xfb_info.h"
37 #include "spirv/nir_spirv.h"
40 /* Needed for SWIZZLE macros */
41 #include "program/prog_instruction.h"
45 VkResult
anv_CreateShaderModule(
47 const VkShaderModuleCreateInfo
* pCreateInfo
,
48 const VkAllocationCallbacks
* pAllocator
,
49 VkShaderModule
* pShaderModule
)
51 ANV_FROM_HANDLE(anv_device
, device
, _device
);
52 struct anv_shader_module
*module
;
54 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
55 assert(pCreateInfo
->flags
== 0);
57 module
= vk_alloc2(&device
->alloc
, pAllocator
,
58 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
59 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
61 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
63 module
->size
= pCreateInfo
->codeSize
;
64 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
66 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
68 *pShaderModule
= anv_shader_module_to_handle(module
);
73 void anv_DestroyShaderModule(
75 VkShaderModule _module
,
76 const VkAllocationCallbacks
* pAllocator
)
78 ANV_FROM_HANDLE(anv_device
, device
, _device
);
79 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
84 vk_free2(&device
->alloc
, pAllocator
, module
);
87 #define SPIR_V_MAGIC_NUMBER 0x07230203
89 static const uint64_t stage_to_debug
[] = {
90 [MESA_SHADER_VERTEX
] = DEBUG_VS
,
91 [MESA_SHADER_TESS_CTRL
] = DEBUG_TCS
,
92 [MESA_SHADER_TESS_EVAL
] = DEBUG_TES
,
93 [MESA_SHADER_GEOMETRY
] = DEBUG_GS
,
94 [MESA_SHADER_FRAGMENT
] = DEBUG_WM
,
95 [MESA_SHADER_COMPUTE
] = DEBUG_CS
,
98 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
99 * we can't do that yet because we don't have the ability to copy nir.
102 anv_shader_compile_to_nir(struct anv_device
*device
,
104 const struct anv_shader_module
*module
,
105 const char *entrypoint_name
,
106 gl_shader_stage stage
,
107 const VkSpecializationInfo
*spec_info
)
109 const struct anv_physical_device
*pdevice
=
110 &device
->instance
->physicalDevice
;
111 const struct brw_compiler
*compiler
= pdevice
->compiler
;
112 const nir_shader_compiler_options
*nir_options
=
113 compiler
->glsl_compiler_options
[stage
].NirOptions
;
115 uint32_t *spirv
= (uint32_t *) module
->data
;
116 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
117 assert(module
->size
% 4 == 0);
119 uint32_t num_spec_entries
= 0;
120 struct nir_spirv_specialization
*spec_entries
= NULL
;
121 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
122 num_spec_entries
= spec_info
->mapEntryCount
;
123 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
124 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
125 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
126 const void *data
= spec_info
->pData
+ entry
.offset
;
127 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
129 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
130 if (spec_info
->dataSize
== 8)
131 spec_entries
[i
].data64
= *(const uint64_t *)data
;
133 spec_entries
[i
].data32
= *(const uint32_t *)data
;
137 struct spirv_to_nir_options spirv_options
= {
138 .lower_workgroup_access_to_offsets
= true,
140 .derivative_group
= true,
141 .descriptor_array_dynamic_indexing
= true,
142 .device_group
= true,
143 .draw_parameters
= true,
144 .float16
= pdevice
->info
.gen
>= 8,
145 .float64
= pdevice
->info
.gen
>= 8,
146 .geometry_streams
= true,
147 .image_write_without_format
= true,
148 .int8
= pdevice
->info
.gen
>= 8,
149 .int16
= pdevice
->info
.gen
>= 8,
150 .int64
= pdevice
->info
.gen
>= 8,
151 .int64_atomics
= pdevice
->info
.gen
>= 9 && pdevice
->use_softpin
,
154 .physical_storage_buffer_address
= pdevice
->has_a64_buffer_access
,
155 .post_depth_coverage
= pdevice
->info
.gen
>= 9,
156 .runtime_descriptor_array
= true,
157 .shader_viewport_index_layer
= true,
158 .stencil_export
= pdevice
->info
.gen
>= 9,
159 .storage_8bit
= pdevice
->info
.gen
>= 8,
160 .storage_16bit
= pdevice
->info
.gen
>= 8,
161 .subgroup_arithmetic
= true,
162 .subgroup_basic
= true,
163 .subgroup_ballot
= true,
164 .subgroup_quad
= true,
165 .subgroup_shuffle
= true,
166 .subgroup_vote
= true,
167 .tessellation
= true,
168 .transform_feedback
= pdevice
->info
.gen
>= 8,
169 .variable_pointers
= true,
171 .ubo_ptr_type
= glsl_vector_type(GLSL_TYPE_UINT
, 2),
172 .phys_ssbo_ptr_type
= glsl_vector_type(GLSL_TYPE_UINT64
, 1),
173 .push_const_ptr_type
= glsl_uint_type(),
174 .shared_ptr_type
= glsl_uint_type(),
177 if (pdevice
->has_a64_buffer_access
) {
178 if (device
->robust_buffer_access
)
179 spirv_options
.ssbo_ptr_type
= glsl_vector_type(GLSL_TYPE_UINT
, 4);
181 spirv_options
.ssbo_ptr_type
= glsl_vector_type(GLSL_TYPE_UINT64
, 1);
183 spirv_options
.ssbo_ptr_type
= glsl_vector_type(GLSL_TYPE_UINT
, 2);
186 nir_function
*entry_point
=
187 spirv_to_nir(spirv
, module
->size
/ 4,
188 spec_entries
, num_spec_entries
,
189 stage
, entrypoint_name
, &spirv_options
, nir_options
);
190 nir_shader
*nir
= entry_point
->shader
;
191 assert(nir
->info
.stage
== stage
);
192 nir_validate_shader(nir
, "after spirv_to_nir");
193 ralloc_steal(mem_ctx
, nir
);
197 if (unlikely(INTEL_DEBUG
& stage_to_debug
[stage
])) {
198 fprintf(stderr
, "NIR (from SPIR-V) for %s shader:\n",
199 gl_shader_stage_name(stage
));
200 nir_print_shader(nir
, stderr
);
203 /* We have to lower away local constant initializers right before we
204 * inline functions. That way they get properly initialized at the top
205 * of the function and not at the top of its caller.
207 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_function_temp
);
208 NIR_PASS_V(nir
, nir_lower_returns
);
209 NIR_PASS_V(nir
, nir_inline_functions
);
210 NIR_PASS_V(nir
, nir_opt_deref
);
212 /* Pick off the single entrypoint that we want */
213 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
214 if (func
!= entry_point
)
215 exec_node_remove(&func
->node
);
217 assert(exec_list_length(&nir
->functions
) == 1);
219 /* Now that we've deleted all but the main function, we can go ahead and
220 * lower the rest of the constant initializers. We do this here so that
221 * nir_remove_dead_variables and split_per_member_structs below see the
222 * corresponding stores.
224 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
226 /* Split member structs. We do this before lower_io_to_temporaries so that
227 * it doesn't lower system values to temporaries by accident.
229 NIR_PASS_V(nir
, nir_split_var_copies
);
230 NIR_PASS_V(nir
, nir_split_per_member_structs
);
232 NIR_PASS_V(nir
, nir_remove_dead_variables
,
233 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
235 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_global
,
236 nir_address_format_64bit_global
);
238 NIR_PASS_V(nir
, nir_propagate_invariant
);
239 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
240 entry_point
->impl
, true, false);
242 NIR_PASS_V(nir
, nir_lower_frexp
);
244 /* Vulkan uses the separate-shader linking model */
245 nir
->info
.separate_shader
= true;
247 nir
= brw_preprocess_nir(compiler
, nir
, NULL
);
252 void anv_DestroyPipeline(
254 VkPipeline _pipeline
,
255 const VkAllocationCallbacks
* pAllocator
)
257 ANV_FROM_HANDLE(anv_device
, device
, _device
);
258 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
263 anv_reloc_list_finish(&pipeline
->batch_relocs
,
264 pAllocator
? pAllocator
: &device
->alloc
);
265 if (pipeline
->blend_state
.map
)
266 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
268 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
269 if (pipeline
->shaders
[s
])
270 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
273 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
276 static const uint32_t vk_to_gen_primitive_type
[] = {
277 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
278 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
279 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
280 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
281 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
282 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
283 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
284 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
285 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
286 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
290 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
291 struct brw_sampler_prog_key_data
*key
)
293 /* Almost all multisampled textures are compressed. The only time when we
294 * don't compress a multisampled texture is for 16x MSAA with a surface
295 * width greater than 8k which is a bit of an edge case. Since the sampler
296 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
297 * to tell the compiler to always assume compression.
299 key
->compressed_multisample_layout_mask
= ~0;
301 /* SkyLake added support for 16x MSAA. With this came a new message for
302 * reading from a 16x MSAA surface with compression. The new message was
303 * needed because now the MCS data is 64 bits instead of 32 or lower as is
304 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
305 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
306 * so we can just use it unconditionally. This may not be quite as
307 * efficient but it saves us from recompiling.
309 if (devinfo
->gen
>= 9)
312 /* XXX: Handle texture swizzle on HSW- */
313 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
314 /* Assume color sampler, no swizzling. (Works for BDW+) */
315 key
->swizzles
[i
] = SWIZZLE_XYZW
;
320 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
321 struct brw_vs_prog_key
*key
)
323 memset(key
, 0, sizeof(*key
));
325 populate_sampler_prog_key(devinfo
, &key
->tex
);
327 /* XXX: Handle vertex input work-arounds */
329 /* XXX: Handle sampler_prog_key */
333 populate_tcs_prog_key(const struct gen_device_info
*devinfo
,
334 unsigned input_vertices
,
335 struct brw_tcs_prog_key
*key
)
337 memset(key
, 0, sizeof(*key
));
339 populate_sampler_prog_key(devinfo
, &key
->tex
);
341 key
->input_vertices
= input_vertices
;
345 populate_tes_prog_key(const struct gen_device_info
*devinfo
,
346 struct brw_tes_prog_key
*key
)
348 memset(key
, 0, sizeof(*key
));
350 populate_sampler_prog_key(devinfo
, &key
->tex
);
354 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
355 struct brw_gs_prog_key
*key
)
357 memset(key
, 0, sizeof(*key
));
359 populate_sampler_prog_key(devinfo
, &key
->tex
);
363 populate_wm_prog_key(const struct gen_device_info
*devinfo
,
364 const struct anv_subpass
*subpass
,
365 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
366 struct brw_wm_prog_key
*key
)
368 memset(key
, 0, sizeof(*key
));
370 populate_sampler_prog_key(devinfo
, &key
->tex
);
372 /* We set this to 0 here and set to the actual value before we call
375 key
->input_slots_valid
= 0;
377 /* Vulkan doesn't specify a default */
378 key
->high_quality_derivatives
= false;
380 /* XXX Vulkan doesn't appear to specify */
381 key
->clamp_fragment_color
= false;
383 assert(subpass
->color_count
<= MAX_RTS
);
384 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
385 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
386 key
->color_outputs_valid
|= (1 << i
);
389 key
->nr_color_regions
= util_bitcount(key
->color_outputs_valid
);
391 /* To reduce possible shader recompilations we would need to know if
392 * there is a SampleMask output variable to compute if we should emit
393 * code to workaround the issue that hardware disables alpha to coverage
394 * when there is SampleMask output.
396 key
->alpha_to_coverage
= ms_info
&& ms_info
->alphaToCoverageEnable
;
398 /* Vulkan doesn't support fixed-function alpha test */
399 key
->alpha_test_replicate_alpha
= false;
402 /* We should probably pull this out of the shader, but it's fairly
403 * harmless to compute it and then let dead-code take care of it.
405 if (ms_info
->rasterizationSamples
> 1) {
406 key
->persample_interp
=
407 (ms_info
->minSampleShading
* ms_info
->rasterizationSamples
) > 1;
408 key
->multisample_fbo
= true;
411 key
->frag_coord_adds_sample_pos
= ms_info
->sampleShadingEnable
;
416 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
417 struct brw_cs_prog_key
*key
)
419 memset(key
, 0, sizeof(*key
));
421 populate_sampler_prog_key(devinfo
, &key
->tex
);
424 struct anv_pipeline_stage
{
425 gl_shader_stage stage
;
427 const struct anv_shader_module
*module
;
428 const char *entrypoint
;
429 const VkSpecializationInfo
*spec_info
;
431 unsigned char shader_sha1
[20];
433 union brw_any_prog_key key
;
436 gl_shader_stage stage
;
437 unsigned char sha1
[20];
442 struct anv_pipeline_binding surface_to_descriptor
[256];
443 struct anv_pipeline_binding sampler_to_descriptor
[256];
444 struct anv_pipeline_bind_map bind_map
;
446 union brw_any_prog_data prog_data
;
448 VkPipelineCreationFeedbackEXT feedback
;
452 anv_pipeline_hash_shader(const struct anv_shader_module
*module
,
453 const char *entrypoint
,
454 gl_shader_stage stage
,
455 const VkSpecializationInfo
*spec_info
,
456 unsigned char *sha1_out
)
458 struct mesa_sha1 ctx
;
459 _mesa_sha1_init(&ctx
);
461 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
462 _mesa_sha1_update(&ctx
, entrypoint
, strlen(entrypoint
));
463 _mesa_sha1_update(&ctx
, &stage
, sizeof(stage
));
465 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
466 spec_info
->mapEntryCount
*
467 sizeof(*spec_info
->pMapEntries
));
468 _mesa_sha1_update(&ctx
, spec_info
->pData
,
469 spec_info
->dataSize
);
472 _mesa_sha1_final(&ctx
, sha1_out
);
476 anv_pipeline_hash_graphics(struct anv_pipeline
*pipeline
,
477 struct anv_pipeline_layout
*layout
,
478 struct anv_pipeline_stage
*stages
,
479 unsigned char *sha1_out
)
481 struct mesa_sha1 ctx
;
482 _mesa_sha1_init(&ctx
);
484 _mesa_sha1_update(&ctx
, &pipeline
->subpass
->view_mask
,
485 sizeof(pipeline
->subpass
->view_mask
));
488 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
490 const bool rba
= pipeline
->device
->robust_buffer_access
;
491 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
493 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
494 if (stages
[s
].entrypoint
) {
495 _mesa_sha1_update(&ctx
, stages
[s
].shader_sha1
,
496 sizeof(stages
[s
].shader_sha1
));
497 _mesa_sha1_update(&ctx
, &stages
[s
].key
, brw_prog_key_size(s
));
501 _mesa_sha1_final(&ctx
, sha1_out
);
505 anv_pipeline_hash_compute(struct anv_pipeline
*pipeline
,
506 struct anv_pipeline_layout
*layout
,
507 struct anv_pipeline_stage
*stage
,
508 unsigned char *sha1_out
)
510 struct mesa_sha1 ctx
;
511 _mesa_sha1_init(&ctx
);
514 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
516 const bool rba
= pipeline
->device
->robust_buffer_access
;
517 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
519 _mesa_sha1_update(&ctx
, stage
->shader_sha1
,
520 sizeof(stage
->shader_sha1
));
521 _mesa_sha1_update(&ctx
, &stage
->key
.cs
, sizeof(stage
->key
.cs
));
523 _mesa_sha1_final(&ctx
, sha1_out
);
527 anv_pipeline_stage_get_nir(struct anv_pipeline
*pipeline
,
528 struct anv_pipeline_cache
*cache
,
530 struct anv_pipeline_stage
*stage
)
532 const struct brw_compiler
*compiler
=
533 pipeline
->device
->instance
->physicalDevice
.compiler
;
534 const nir_shader_compiler_options
*nir_options
=
535 compiler
->glsl_compiler_options
[stage
->stage
].NirOptions
;
538 nir
= anv_device_search_for_nir(pipeline
->device
, cache
,
543 assert(nir
->info
.stage
== stage
->stage
);
547 nir
= anv_shader_compile_to_nir(pipeline
->device
,
554 anv_device_upload_nir(pipeline
->device
, cache
, nir
, stage
->shader_sha1
);
562 anv_pipeline_lower_nir(struct anv_pipeline
*pipeline
,
564 struct anv_pipeline_stage
*stage
,
565 struct anv_pipeline_layout
*layout
)
567 const struct anv_physical_device
*pdevice
=
568 &pipeline
->device
->instance
->physicalDevice
;
569 const struct brw_compiler
*compiler
= pdevice
->compiler
;
571 struct brw_stage_prog_data
*prog_data
= &stage
->prog_data
.base
;
572 nir_shader
*nir
= stage
->nir
;
574 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
575 NIR_PASS_V(nir
, nir_lower_wpos_center
, pipeline
->sample_shading_enable
);
576 NIR_PASS_V(nir
, anv_nir_lower_input_attachments
);
579 NIR_PASS_V(nir
, anv_nir_lower_ycbcr_textures
, layout
);
581 NIR_PASS_V(nir
, anv_nir_lower_push_constants
);
583 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
584 NIR_PASS_V(nir
, anv_nir_lower_multiview
, pipeline
->subpass
->view_mask
);
586 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
587 prog_data
->total_shared
= nir
->num_shared
;
589 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
591 if (nir
->num_uniforms
> 0) {
592 assert(prog_data
->nr_params
== 0);
594 /* If the shader uses any push constants at all, we'll just give
595 * them the maximum possible number
597 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
598 nir
->num_uniforms
= MAX_PUSH_CONSTANTS_SIZE
;
599 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
600 prog_data
->param
= ralloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
602 /* We now set the param values to be offsets into a
603 * anv_push_constant_data structure. Since the compiler doesn't
604 * actually dereference any of the gl_constant_value pointers in the
605 * params array, it doesn't really matter what we put here.
607 struct anv_push_constants
*null_data
= NULL
;
608 /* Fill out the push constants section of the param array */
609 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++) {
610 prog_data
->param
[i
] = ANV_PARAM_PUSH(
611 (uintptr_t)&null_data
->client_data
[i
* sizeof(float)]);
615 if (nir
->info
.num_ssbos
> 0 || nir
->info
.num_images
> 0)
616 pipeline
->needs_data_cache
= true;
618 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, compiler
->devinfo
);
620 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
622 anv_nir_apply_pipeline_layout(pdevice
,
623 pipeline
->device
->robust_buffer_access
,
624 layout
, nir
, prog_data
,
627 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ubo
,
628 nir_address_format_32bit_index_offset
);
630 nir_address_format ssbo_address_format
;
631 if (pdevice
->has_a64_buffer_access
) {
632 if (pipeline
->device
->robust_buffer_access
)
633 ssbo_address_format
= nir_address_format_64bit_bounded_global
;
635 ssbo_address_format
= nir_address_format_64bit_global
;
637 ssbo_address_format
= nir_address_format_32bit_index_offset
;
639 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ssbo
,
640 ssbo_address_format
);
642 NIR_PASS_V(nir
, nir_opt_constant_folding
);
644 /* We don't support non-uniform UBOs and non-uniform SSBO access is
645 * handled naturally by falling back to A64 messages.
647 NIR_PASS_V(nir
, nir_lower_non_uniform_access
,
648 nir_lower_non_uniform_texture_access
|
649 nir_lower_non_uniform_image_access
);
652 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
653 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
655 assert(nir
->num_uniforms
== prog_data
->nr_params
* 4);
661 anv_pipeline_link_vs(const struct brw_compiler
*compiler
,
662 struct anv_pipeline_stage
*vs_stage
,
663 struct anv_pipeline_stage
*next_stage
)
666 brw_nir_link_shaders(compiler
, &vs_stage
->nir
, &next_stage
->nir
);
669 static const unsigned *
670 anv_pipeline_compile_vs(const struct brw_compiler
*compiler
,
672 struct anv_device
*device
,
673 struct anv_pipeline_stage
*vs_stage
)
675 brw_compute_vue_map(compiler
->devinfo
,
676 &vs_stage
->prog_data
.vs
.base
.vue_map
,
677 vs_stage
->nir
->info
.outputs_written
,
678 vs_stage
->nir
->info
.separate_shader
);
680 return brw_compile_vs(compiler
, device
, mem_ctx
, &vs_stage
->key
.vs
,
681 &vs_stage
->prog_data
.vs
, vs_stage
->nir
, -1, NULL
);
685 merge_tess_info(struct shader_info
*tes_info
,
686 const struct shader_info
*tcs_info
)
688 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
690 * "PointMode. Controls generation of points rather than triangles
691 * or lines. This functionality defaults to disabled, and is
692 * enabled if either shader stage includes the execution mode.
694 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
695 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
696 * and OutputVertices, it says:
698 * "One mode must be set in at least one of the tessellation
701 * So, the fields can be set in either the TCS or TES, but they must
702 * agree if set in both. Our backend looks at TES, so bitwise-or in
703 * the values from the TCS.
705 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
706 tes_info
->tess
.tcs_vertices_out
== 0 ||
707 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
708 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
710 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
711 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
712 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
713 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
715 assert(tcs_info
->tess
.primitive_mode
== 0 ||
716 tes_info
->tess
.primitive_mode
== 0 ||
717 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
718 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
719 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
720 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
724 anv_pipeline_link_tcs(const struct brw_compiler
*compiler
,
725 struct anv_pipeline_stage
*tcs_stage
,
726 struct anv_pipeline_stage
*tes_stage
)
728 assert(tes_stage
&& tes_stage
->stage
== MESA_SHADER_TESS_EVAL
);
730 brw_nir_link_shaders(compiler
, &tcs_stage
->nir
, &tes_stage
->nir
);
732 nir_lower_patch_vertices(tes_stage
->nir
,
733 tcs_stage
->nir
->info
.tess
.tcs_vertices_out
,
736 /* Copy TCS info into the TES info */
737 merge_tess_info(&tes_stage
->nir
->info
, &tcs_stage
->nir
->info
);
739 /* Whacking the key after cache lookup is a bit sketchy, but all of
740 * this comes from the SPIR-V, which is part of the hash used for the
741 * pipeline cache. So it should be safe.
743 tcs_stage
->key
.tcs
.tes_primitive_mode
=
744 tes_stage
->nir
->info
.tess
.primitive_mode
;
745 tcs_stage
->key
.tcs
.quads_workaround
=
746 compiler
->devinfo
->gen
< 9 &&
747 tes_stage
->nir
->info
.tess
.primitive_mode
== 7 /* GL_QUADS */ &&
748 tes_stage
->nir
->info
.tess
.spacing
== TESS_SPACING_EQUAL
;
751 static const unsigned *
752 anv_pipeline_compile_tcs(const struct brw_compiler
*compiler
,
754 struct anv_device
*device
,
755 struct anv_pipeline_stage
*tcs_stage
,
756 struct anv_pipeline_stage
*prev_stage
)
758 tcs_stage
->key
.tcs
.outputs_written
=
759 tcs_stage
->nir
->info
.outputs_written
;
760 tcs_stage
->key
.tcs
.patch_outputs_written
=
761 tcs_stage
->nir
->info
.patch_outputs_written
;
763 return brw_compile_tcs(compiler
, device
, mem_ctx
, &tcs_stage
->key
.tcs
,
764 &tcs_stage
->prog_data
.tcs
, tcs_stage
->nir
,
769 anv_pipeline_link_tes(const struct brw_compiler
*compiler
,
770 struct anv_pipeline_stage
*tes_stage
,
771 struct anv_pipeline_stage
*next_stage
)
774 brw_nir_link_shaders(compiler
, &tes_stage
->nir
, &next_stage
->nir
);
777 static const unsigned *
778 anv_pipeline_compile_tes(const struct brw_compiler
*compiler
,
780 struct anv_device
*device
,
781 struct anv_pipeline_stage
*tes_stage
,
782 struct anv_pipeline_stage
*tcs_stage
)
784 tes_stage
->key
.tes
.inputs_read
=
785 tcs_stage
->nir
->info
.outputs_written
;
786 tes_stage
->key
.tes
.patch_inputs_read
=
787 tcs_stage
->nir
->info
.patch_outputs_written
;
789 return brw_compile_tes(compiler
, device
, mem_ctx
, &tes_stage
->key
.tes
,
790 &tcs_stage
->prog_data
.tcs
.base
.vue_map
,
791 &tes_stage
->prog_data
.tes
, tes_stage
->nir
,
796 anv_pipeline_link_gs(const struct brw_compiler
*compiler
,
797 struct anv_pipeline_stage
*gs_stage
,
798 struct anv_pipeline_stage
*next_stage
)
801 brw_nir_link_shaders(compiler
, &gs_stage
->nir
, &next_stage
->nir
);
804 static const unsigned *
805 anv_pipeline_compile_gs(const struct brw_compiler
*compiler
,
807 struct anv_device
*device
,
808 struct anv_pipeline_stage
*gs_stage
,
809 struct anv_pipeline_stage
*prev_stage
)
811 brw_compute_vue_map(compiler
->devinfo
,
812 &gs_stage
->prog_data
.gs
.base
.vue_map
,
813 gs_stage
->nir
->info
.outputs_written
,
814 gs_stage
->nir
->info
.separate_shader
);
816 return brw_compile_gs(compiler
, device
, mem_ctx
, &gs_stage
->key
.gs
,
817 &gs_stage
->prog_data
.gs
, gs_stage
->nir
,
822 anv_pipeline_link_fs(const struct brw_compiler
*compiler
,
823 struct anv_pipeline_stage
*stage
)
825 unsigned num_rts
= 0;
826 const int max_rt
= FRAG_RESULT_DATA7
- FRAG_RESULT_DATA0
+ 1;
827 struct anv_pipeline_binding rt_bindings
[max_rt
];
828 nir_function_impl
*impl
= nir_shader_get_entrypoint(stage
->nir
);
829 int rt_to_bindings
[max_rt
];
830 memset(rt_to_bindings
, -1, sizeof(rt_to_bindings
));
831 bool rt_used
[max_rt
];
832 memset(rt_used
, 0, sizeof(rt_used
));
834 /* Flag used render targets */
835 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
836 if (var
->data
.location
< FRAG_RESULT_DATA0
)
839 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
840 /* Unused or out-of-bounds */
841 if (rt
>= MAX_RTS
|| !(stage
->key
.wm
.color_outputs_valid
& (1 << rt
)))
844 const unsigned array_len
=
845 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
846 assert(rt
+ array_len
<= max_rt
);
848 for (unsigned i
= 0; i
< array_len
; i
++)
849 rt_used
[rt
+ i
] = true;
852 /* Set new, compacted, location */
853 for (unsigned i
= 0; i
< max_rt
; i
++) {
857 rt_to_bindings
[i
] = num_rts
;
858 rt_bindings
[rt_to_bindings
[i
]] = (struct anv_pipeline_binding
) {
859 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
866 bool deleted_output
= false;
867 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
868 if (var
->data
.location
< FRAG_RESULT_DATA0
)
871 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
873 !(stage
->key
.wm
.color_outputs_valid
& (1 << rt
))) {
874 /* Unused or out-of-bounds, throw it away */
875 deleted_output
= true;
876 var
->data
.mode
= nir_var_function_temp
;
877 exec_node_remove(&var
->node
);
878 exec_list_push_tail(&impl
->locals
, &var
->node
);
882 /* Give it the new location */
883 assert(rt_to_bindings
[rt
] != -1);
884 var
->data
.location
= rt_to_bindings
[rt
] + FRAG_RESULT_DATA0
;
888 nir_fixup_deref_modes(stage
->nir
);
891 /* If we have no render targets, we need a null render target */
892 rt_bindings
[0] = (struct anv_pipeline_binding
) {
893 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
900 /* Now that we've determined the actual number of render targets, adjust
901 * the key accordingly.
903 stage
->key
.wm
.nr_color_regions
= num_rts
;
904 stage
->key
.wm
.color_outputs_valid
= (1 << num_rts
) - 1;
906 assert(num_rts
<= max_rt
);
907 assert(stage
->bind_map
.surface_count
== 0);
908 typed_memcpy(stage
->bind_map
.surface_to_descriptor
,
909 rt_bindings
, num_rts
);
910 stage
->bind_map
.surface_count
+= num_rts
;
913 static const unsigned *
914 anv_pipeline_compile_fs(const struct brw_compiler
*compiler
,
916 struct anv_device
*device
,
917 struct anv_pipeline_stage
*fs_stage
,
918 struct anv_pipeline_stage
*prev_stage
)
920 /* TODO: we could set this to 0 based on the information in nir_shader, but
921 * we need this before we call spirv_to_nir.
924 fs_stage
->key
.wm
.input_slots_valid
=
925 prev_stage
->prog_data
.vue
.vue_map
.slots_valid
;
927 const unsigned *code
=
928 brw_compile_fs(compiler
, device
, mem_ctx
, &fs_stage
->key
.wm
,
929 &fs_stage
->prog_data
.wm
, fs_stage
->nir
,
930 NULL
, -1, -1, -1, true, false, NULL
, NULL
);
932 if (fs_stage
->key
.wm
.nr_color_regions
== 0 &&
933 !fs_stage
->prog_data
.wm
.has_side_effects
&&
934 !fs_stage
->prog_data
.wm
.uses_kill
&&
935 fs_stage
->prog_data
.wm
.computed_depth_mode
== BRW_PSCDEPTH_OFF
&&
936 !fs_stage
->prog_data
.wm
.computed_stencil
) {
937 /* This fragment shader has no outputs and no side effects. Go ahead
938 * and return the code pointer so we don't accidentally think the
939 * compile failed but zero out prog_data which will set program_size to
940 * zero and disable the stage.
942 memset(&fs_stage
->prog_data
, 0, sizeof(fs_stage
->prog_data
));
949 anv_pipeline_compile_graphics(struct anv_pipeline
*pipeline
,
950 struct anv_pipeline_cache
*cache
,
951 const VkGraphicsPipelineCreateInfo
*info
)
953 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
954 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
956 int64_t pipeline_start
= os_time_get_nano();
958 const struct brw_compiler
*compiler
=
959 pipeline
->device
->instance
->physicalDevice
.compiler
;
960 struct anv_pipeline_stage stages
[MESA_SHADER_STAGES
] = {};
962 pipeline
->active_stages
= 0;
965 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
966 const VkPipelineShaderStageCreateInfo
*sinfo
= &info
->pStages
[i
];
967 gl_shader_stage stage
= vk_to_mesa_shader_stage(sinfo
->stage
);
969 pipeline
->active_stages
|= sinfo
->stage
;
971 int64_t stage_start
= os_time_get_nano();
973 stages
[stage
].stage
= stage
;
974 stages
[stage
].module
= anv_shader_module_from_handle(sinfo
->module
);
975 stages
[stage
].entrypoint
= sinfo
->pName
;
976 stages
[stage
].spec_info
= sinfo
->pSpecializationInfo
;
977 anv_pipeline_hash_shader(stages
[stage
].module
,
978 stages
[stage
].entrypoint
,
980 stages
[stage
].spec_info
,
981 stages
[stage
].shader_sha1
);
983 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
985 case MESA_SHADER_VERTEX
:
986 populate_vs_prog_key(devinfo
, &stages
[stage
].key
.vs
);
988 case MESA_SHADER_TESS_CTRL
:
989 populate_tcs_prog_key(devinfo
,
990 info
->pTessellationState
->patchControlPoints
,
991 &stages
[stage
].key
.tcs
);
993 case MESA_SHADER_TESS_EVAL
:
994 populate_tes_prog_key(devinfo
, &stages
[stage
].key
.tes
);
996 case MESA_SHADER_GEOMETRY
:
997 populate_gs_prog_key(devinfo
, &stages
[stage
].key
.gs
);
999 case MESA_SHADER_FRAGMENT
:
1000 populate_wm_prog_key(devinfo
, pipeline
->subpass
,
1001 info
->pMultisampleState
,
1002 &stages
[stage
].key
.wm
);
1005 unreachable("Invalid graphics shader stage");
1008 stages
[stage
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1009 stages
[stage
].feedback
.flags
|= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
1012 if (pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
)
1013 pipeline
->active_stages
|= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
1015 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1017 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1019 unsigned char sha1
[20];
1020 anv_pipeline_hash_graphics(pipeline
, layout
, stages
, sha1
);
1023 unsigned cache_hits
= 0;
1024 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1025 if (!stages
[s
].entrypoint
)
1028 int64_t stage_start
= os_time_get_nano();
1030 stages
[s
].cache_key
.stage
= s
;
1031 memcpy(stages
[s
].cache_key
.sha1
, sha1
, sizeof(sha1
));
1034 struct anv_shader_bin
*bin
=
1035 anv_device_search_for_kernel(pipeline
->device
, cache
,
1036 &stages
[s
].cache_key
,
1037 sizeof(stages
[s
].cache_key
), &cache_hit
);
1040 pipeline
->shaders
[s
] = bin
;
1045 stages
[s
].feedback
.flags
|=
1046 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1048 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1051 if (found
== __builtin_popcount(pipeline
->active_stages
)) {
1052 if (cache_hits
== found
) {
1053 pipeline_feedback
.flags
|=
1054 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1056 /* We found all our shaders in the cache. We're done. */
1058 } else if (found
> 0) {
1059 /* We found some but not all of our shaders. This shouldn't happen
1060 * most of the time but it can if we have a partially populated
1063 assert(found
< __builtin_popcount(pipeline
->active_stages
));
1065 vk_debug_report(&pipeline
->device
->instance
->debug_report_callbacks
,
1066 VK_DEBUG_REPORT_WARNING_BIT_EXT
|
1067 VK_DEBUG_REPORT_PERFORMANCE_WARNING_BIT_EXT
,
1068 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT
,
1069 (uint64_t)(uintptr_t)cache
,
1071 "Found a partial pipeline in the cache. This is "
1072 "most likely caused by an incomplete pipeline cache "
1073 "import or export");
1075 /* We're going to have to recompile anyway, so just throw away our
1076 * references to the shaders in the cache. We'll get them out of the
1077 * cache again as part of the compilation process.
1079 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1080 stages
[s
].feedback
.flags
= 0;
1081 if (pipeline
->shaders
[s
]) {
1082 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1083 pipeline
->shaders
[s
] = NULL
;
1088 void *pipeline_ctx
= ralloc_context(NULL
);
1090 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1091 if (!stages
[s
].entrypoint
)
1094 int64_t stage_start
= os_time_get_nano();
1096 assert(stages
[s
].stage
== s
);
1097 assert(pipeline
->shaders
[s
] == NULL
);
1099 stages
[s
].bind_map
= (struct anv_pipeline_bind_map
) {
1100 .surface_to_descriptor
= stages
[s
].surface_to_descriptor
,
1101 .sampler_to_descriptor
= stages
[s
].sampler_to_descriptor
1104 stages
[s
].nir
= anv_pipeline_stage_get_nir(pipeline
, cache
,
1107 if (stages
[s
].nir
== NULL
) {
1108 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1112 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1115 /* Walk backwards to link */
1116 struct anv_pipeline_stage
*next_stage
= NULL
;
1117 for (int s
= MESA_SHADER_STAGES
- 1; s
>= 0; s
--) {
1118 if (!stages
[s
].entrypoint
)
1122 case MESA_SHADER_VERTEX
:
1123 anv_pipeline_link_vs(compiler
, &stages
[s
], next_stage
);
1125 case MESA_SHADER_TESS_CTRL
:
1126 anv_pipeline_link_tcs(compiler
, &stages
[s
], next_stage
);
1128 case MESA_SHADER_TESS_EVAL
:
1129 anv_pipeline_link_tes(compiler
, &stages
[s
], next_stage
);
1131 case MESA_SHADER_GEOMETRY
:
1132 anv_pipeline_link_gs(compiler
, &stages
[s
], next_stage
);
1134 case MESA_SHADER_FRAGMENT
:
1135 anv_pipeline_link_fs(compiler
, &stages
[s
]);
1138 unreachable("Invalid graphics shader stage");
1141 next_stage
= &stages
[s
];
1144 struct anv_pipeline_stage
*prev_stage
= NULL
;
1145 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1146 if (!stages
[s
].entrypoint
)
1149 int64_t stage_start
= os_time_get_nano();
1151 void *stage_ctx
= ralloc_context(NULL
);
1153 nir_xfb_info
*xfb_info
= NULL
;
1154 if (s
== MESA_SHADER_VERTEX
||
1155 s
== MESA_SHADER_TESS_EVAL
||
1156 s
== MESA_SHADER_GEOMETRY
)
1157 xfb_info
= nir_gather_xfb_info(stages
[s
].nir
, stage_ctx
);
1159 anv_pipeline_lower_nir(pipeline
, stage_ctx
, &stages
[s
], layout
);
1161 const unsigned *code
;
1163 case MESA_SHADER_VERTEX
:
1164 code
= anv_pipeline_compile_vs(compiler
, stage_ctx
, pipeline
->device
,
1167 case MESA_SHADER_TESS_CTRL
:
1168 code
= anv_pipeline_compile_tcs(compiler
, stage_ctx
, pipeline
->device
,
1169 &stages
[s
], prev_stage
);
1171 case MESA_SHADER_TESS_EVAL
:
1172 code
= anv_pipeline_compile_tes(compiler
, stage_ctx
, pipeline
->device
,
1173 &stages
[s
], prev_stage
);
1175 case MESA_SHADER_GEOMETRY
:
1176 code
= anv_pipeline_compile_gs(compiler
, stage_ctx
, pipeline
->device
,
1177 &stages
[s
], prev_stage
);
1179 case MESA_SHADER_FRAGMENT
:
1180 code
= anv_pipeline_compile_fs(compiler
, stage_ctx
, pipeline
->device
,
1181 &stages
[s
], prev_stage
);
1184 unreachable("Invalid graphics shader stage");
1187 ralloc_free(stage_ctx
);
1188 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1192 struct anv_shader_bin
*bin
=
1193 anv_device_upload_kernel(pipeline
->device
, cache
,
1194 &stages
[s
].cache_key
,
1195 sizeof(stages
[s
].cache_key
),
1196 code
, stages
[s
].prog_data
.base
.program_size
,
1197 stages
[s
].nir
->constant_data
,
1198 stages
[s
].nir
->constant_data_size
,
1199 &stages
[s
].prog_data
.base
,
1200 brw_prog_data_size(s
),
1201 xfb_info
, &stages
[s
].bind_map
);
1203 ralloc_free(stage_ctx
);
1204 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1208 pipeline
->shaders
[s
] = bin
;
1209 ralloc_free(stage_ctx
);
1211 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1213 prev_stage
= &stages
[s
];
1216 ralloc_free(pipeline_ctx
);
1220 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
] &&
1221 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->prog_data
->program_size
== 0) {
1222 /* This can happen if we decided to implicitly disable the fragment
1223 * shader. See anv_pipeline_compile_fs().
1225 anv_shader_bin_unref(pipeline
->device
,
1226 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
1227 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] = NULL
;
1228 pipeline
->active_stages
&= ~VK_SHADER_STAGE_FRAGMENT_BIT
;
1231 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1233 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1234 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1235 if (create_feedback
) {
1236 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1238 assert(info
->stageCount
== create_feedback
->pipelineStageCreationFeedbackCount
);
1239 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1240 gl_shader_stage s
= vk_to_mesa_shader_stage(info
->pStages
[i
].stage
);
1241 create_feedback
->pPipelineStageCreationFeedbacks
[i
] = stages
[s
].feedback
;
1248 ralloc_free(pipeline_ctx
);
1250 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1251 if (pipeline
->shaders
[s
])
1252 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1259 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1260 struct anv_pipeline_cache
*cache
,
1261 const VkComputePipelineCreateInfo
*info
,
1262 const struct anv_shader_module
*module
,
1263 const char *entrypoint
,
1264 const VkSpecializationInfo
*spec_info
)
1266 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1267 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1269 int64_t pipeline_start
= os_time_get_nano();
1271 const struct brw_compiler
*compiler
=
1272 pipeline
->device
->instance
->physicalDevice
.compiler
;
1274 struct anv_pipeline_stage stage
= {
1275 .stage
= MESA_SHADER_COMPUTE
,
1277 .entrypoint
= entrypoint
,
1278 .spec_info
= spec_info
,
1280 .stage
= MESA_SHADER_COMPUTE
,
1283 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1286 anv_pipeline_hash_shader(stage
.module
,
1288 MESA_SHADER_COMPUTE
,
1292 struct anv_shader_bin
*bin
= NULL
;
1294 populate_cs_prog_key(&pipeline
->device
->info
, &stage
.key
.cs
);
1296 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1298 anv_pipeline_hash_compute(pipeline
, layout
, &stage
, stage
.cache_key
.sha1
);
1300 bin
= anv_device_search_for_kernel(pipeline
->device
, cache
, &stage
.cache_key
,
1301 sizeof(stage
.cache_key
), &cache_hit
);
1304 int64_t stage_start
= os_time_get_nano();
1306 stage
.bind_map
= (struct anv_pipeline_bind_map
) {
1307 .surface_to_descriptor
= stage
.surface_to_descriptor
,
1308 .sampler_to_descriptor
= stage
.sampler_to_descriptor
1311 /* Set up a binding for the gl_NumWorkGroups */
1312 stage
.bind_map
.surface_count
= 1;
1313 stage
.bind_map
.surface_to_descriptor
[0] = (struct anv_pipeline_binding
) {
1314 .set
= ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
,
1317 void *mem_ctx
= ralloc_context(NULL
);
1319 stage
.nir
= anv_pipeline_stage_get_nir(pipeline
, cache
, mem_ctx
, &stage
);
1320 if (stage
.nir
== NULL
) {
1321 ralloc_free(mem_ctx
);
1322 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1325 anv_pipeline_lower_nir(pipeline
, mem_ctx
, &stage
, layout
);
1327 NIR_PASS_V(stage
.nir
, anv_nir_add_base_work_group_id
,
1328 &stage
.prog_data
.cs
);
1330 const unsigned *shader_code
=
1331 brw_compile_cs(compiler
, pipeline
->device
, mem_ctx
, &stage
.key
.cs
,
1332 &stage
.prog_data
.cs
, stage
.nir
, -1, NULL
);
1333 if (shader_code
== NULL
) {
1334 ralloc_free(mem_ctx
);
1335 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1338 const unsigned code_size
= stage
.prog_data
.base
.program_size
;
1339 bin
= anv_device_upload_kernel(pipeline
->device
, cache
,
1340 &stage
.cache_key
, sizeof(stage
.cache_key
),
1341 shader_code
, code_size
,
1342 stage
.nir
->constant_data
,
1343 stage
.nir
->constant_data_size
,
1344 &stage
.prog_data
.base
,
1345 sizeof(stage
.prog_data
.cs
),
1346 NULL
, &stage
.bind_map
);
1348 ralloc_free(mem_ctx
);
1349 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1352 ralloc_free(mem_ctx
);
1354 stage
.feedback
.duration
= os_time_get_nano() - stage_start
;
1358 stage
.feedback
.flags
|=
1359 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1360 pipeline_feedback
.flags
|=
1361 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1363 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1365 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1366 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1367 if (create_feedback
) {
1368 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1370 assert(create_feedback
->pipelineStageCreationFeedbackCount
== 1);
1371 create_feedback
->pPipelineStageCreationFeedbacks
[0] = stage
.feedback
;
1374 pipeline
->active_stages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1375 pipeline
->shaders
[MESA_SHADER_COMPUTE
] = bin
;
1381 * Copy pipeline state not marked as dynamic.
1382 * Dynamic state is pipeline state which hasn't been provided at pipeline
1383 * creation time, but is dynamically provided afterwards using various
1384 * vkCmdSet* functions.
1386 * The set of state considered "non_dynamic" is determined by the pieces of
1387 * state that have their corresponding VkDynamicState enums omitted from
1388 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1390 * @param[out] pipeline Destination non_dynamic state.
1391 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1394 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
1395 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1397 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
1398 struct anv_subpass
*subpass
= pipeline
->subpass
;
1400 pipeline
->dynamic_state
= default_dynamic_state
;
1402 if (pCreateInfo
->pDynamicState
) {
1403 /* Remove all of the states that are marked as dynamic */
1404 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1405 for (uint32_t s
= 0; s
< count
; s
++)
1406 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1409 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1411 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1413 * pViewportState is [...] NULL if the pipeline
1414 * has rasterization disabled.
1416 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1417 assert(pCreateInfo
->pViewportState
);
1419 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1420 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
1421 typed_memcpy(dynamic
->viewport
.viewports
,
1422 pCreateInfo
->pViewportState
->pViewports
,
1423 pCreateInfo
->pViewportState
->viewportCount
);
1426 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1427 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
1428 typed_memcpy(dynamic
->scissor
.scissors
,
1429 pCreateInfo
->pViewportState
->pScissors
,
1430 pCreateInfo
->pViewportState
->scissorCount
);
1434 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1435 assert(pCreateInfo
->pRasterizationState
);
1436 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1439 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1440 assert(pCreateInfo
->pRasterizationState
);
1441 dynamic
->depth_bias
.bias
=
1442 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1443 dynamic
->depth_bias
.clamp
=
1444 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1445 dynamic
->depth_bias
.slope
=
1446 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1449 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1451 * pColorBlendState is [...] NULL if the pipeline has rasterization
1452 * disabled or if the subpass of the render pass the pipeline is
1453 * created against does not use any color attachments.
1455 bool uses_color_att
= false;
1456 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1457 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1458 uses_color_att
= true;
1463 if (uses_color_att
&&
1464 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1465 assert(pCreateInfo
->pColorBlendState
);
1467 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
1468 typed_memcpy(dynamic
->blend_constants
,
1469 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1472 /* If there is no depthstencil attachment, then don't read
1473 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1474 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1475 * no need to override the depthstencil defaults in
1476 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1478 * Section 9.2 of the Vulkan 1.0.15 spec says:
1480 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1481 * disabled or if the subpass of the render pass the pipeline is created
1482 * against does not use a depth/stencil attachment.
1484 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1485 subpass
->depth_stencil_attachment
) {
1486 assert(pCreateInfo
->pDepthStencilState
);
1488 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1489 dynamic
->depth_bounds
.min
=
1490 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1491 dynamic
->depth_bounds
.max
=
1492 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1495 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1496 dynamic
->stencil_compare_mask
.front
=
1497 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1498 dynamic
->stencil_compare_mask
.back
=
1499 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1502 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1503 dynamic
->stencil_write_mask
.front
=
1504 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1505 dynamic
->stencil_write_mask
.back
=
1506 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1509 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1510 dynamic
->stencil_reference
.front
=
1511 pCreateInfo
->pDepthStencilState
->front
.reference
;
1512 dynamic
->stencil_reference
.back
=
1513 pCreateInfo
->pDepthStencilState
->back
.reference
;
1517 pipeline
->dynamic_state_mask
= states
;
1521 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1524 struct anv_render_pass
*renderpass
= NULL
;
1525 struct anv_subpass
*subpass
= NULL
;
1527 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1528 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1530 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1532 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1535 assert(info
->subpass
< renderpass
->subpass_count
);
1536 subpass
= &renderpass
->subpasses
[info
->subpass
];
1538 assert(info
->stageCount
>= 1);
1539 assert(info
->pVertexInputState
);
1540 assert(info
->pInputAssemblyState
);
1541 assert(info
->pRasterizationState
);
1542 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1543 assert(info
->pViewportState
);
1544 assert(info
->pMultisampleState
);
1546 if (subpass
&& subpass
->depth_stencil_attachment
)
1547 assert(info
->pDepthStencilState
);
1549 if (subpass
&& subpass
->color_count
> 0) {
1550 bool all_color_unused
= true;
1551 for (int i
= 0; i
< subpass
->color_count
; i
++) {
1552 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
1553 all_color_unused
= false;
1555 /* pColorBlendState is ignored if the pipeline has rasterization
1556 * disabled or if the subpass of the render pass the pipeline is
1557 * created against does not use any color attachments.
1559 assert(info
->pColorBlendState
|| all_color_unused
);
1563 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1564 switch (info
->pStages
[i
].stage
) {
1565 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1566 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1567 assert(info
->pTessellationState
);
1577 * Calculate the desired L3 partitioning based on the current state of the
1578 * pipeline. For now this simply returns the conservative defaults calculated
1579 * by get_default_l3_weights(), but we could probably do better by gathering
1580 * more statistics from the pipeline state (e.g. guess of expected URB usage
1581 * and bound surfaces), or by using feed-back from performance counters.
1584 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1586 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1588 const struct gen_l3_weights w
=
1589 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
1591 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
1592 pipeline
->urb
.total_size
=
1593 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
1597 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1598 struct anv_device
*device
,
1599 struct anv_pipeline_cache
*cache
,
1600 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1601 const VkAllocationCallbacks
*alloc
)
1605 anv_pipeline_validate_create_info(pCreateInfo
);
1608 alloc
= &device
->alloc
;
1610 pipeline
->device
= device
;
1612 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, pCreateInfo
->renderPass
);
1613 assert(pCreateInfo
->subpass
< render_pass
->subpass_count
);
1614 pipeline
->subpass
= &render_pass
->subpasses
[pCreateInfo
->subpass
];
1616 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1617 if (result
!= VK_SUCCESS
)
1620 pipeline
->batch
.alloc
= alloc
;
1621 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1622 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1623 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1624 pipeline
->batch
.status
= VK_SUCCESS
;
1626 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1627 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1628 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1630 /* Previously we enabled depth clipping when !depthClampEnable.
1631 * DepthClipStateCreateInfo now makes depth clipping explicit so if the
1632 * clipping info is available, use its enable value to determine clipping,
1633 * otherwise fallback to the previous !depthClampEnable logic.
1635 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*clip_info
=
1636 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1637 PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
1638 pipeline
->depth_clip_enable
= clip_info
? clip_info
->depthClipEnable
: !pipeline
->depth_clamp_enable
;
1640 pipeline
->sample_shading_enable
= pCreateInfo
->pMultisampleState
&&
1641 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
1643 pipeline
->needs_data_cache
= false;
1645 /* When we free the pipeline, we detect stages based on the NULL status
1646 * of various prog_data pointers. Make them NULL by default.
1648 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1650 result
= anv_pipeline_compile_graphics(pipeline
, cache
, pCreateInfo
);
1651 if (result
!= VK_SUCCESS
) {
1652 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);
1656 assert(pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1658 anv_pipeline_setup_l3_config(pipeline
, false);
1660 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1661 pCreateInfo
->pVertexInputState
;
1663 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1665 pipeline
->vb_used
= 0;
1666 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1667 const VkVertexInputAttributeDescription
*desc
=
1668 &vi_info
->pVertexAttributeDescriptions
[i
];
1670 if (inputs_read
& (1ull << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1671 pipeline
->vb_used
|= 1 << desc
->binding
;
1674 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1675 const VkVertexInputBindingDescription
*desc
=
1676 &vi_info
->pVertexBindingDescriptions
[i
];
1678 pipeline
->vb
[desc
->binding
].stride
= desc
->stride
;
1680 /* Step rate is programmed per vertex element (attribute), not
1681 * binding. Set up a map of which bindings step per instance, for
1682 * reference by vertex element setup. */
1683 switch (desc
->inputRate
) {
1685 case VK_VERTEX_INPUT_RATE_VERTEX
:
1686 pipeline
->vb
[desc
->binding
].instanced
= false;
1688 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1689 pipeline
->vb
[desc
->binding
].instanced
= true;
1693 pipeline
->vb
[desc
->binding
].instance_divisor
= 1;
1696 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*vi_div_state
=
1697 vk_find_struct_const(vi_info
->pNext
,
1698 PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
1700 for (uint32_t i
= 0; i
< vi_div_state
->vertexBindingDivisorCount
; i
++) {
1701 const VkVertexInputBindingDivisorDescriptionEXT
*desc
=
1702 &vi_div_state
->pVertexBindingDivisors
[i
];
1704 pipeline
->vb
[desc
->binding
].instance_divisor
= desc
->divisor
;
1708 /* Our implementation of VK_KHR_multiview uses instancing to draw the
1709 * different views. If the client asks for instancing, we need to multiply
1710 * the instance divisor by the number of views ensure that we repeat the
1711 * client's per-instance data once for each view.
1713 if (pipeline
->subpass
->view_mask
) {
1714 const uint32_t view_count
= anv_subpass_view_count(pipeline
->subpass
);
1715 for (uint32_t vb
= 0; vb
< MAX_VBS
; vb
++) {
1716 if (pipeline
->vb
[vb
].instanced
)
1717 pipeline
->vb
[vb
].instance_divisor
*= view_count
;
1721 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1722 pCreateInfo
->pInputAssemblyState
;
1723 const VkPipelineTessellationStateCreateInfo
*tess_info
=
1724 pCreateInfo
->pTessellationState
;
1725 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1727 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1728 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
1730 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];