2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "common/gen_l3_config.h"
32 #include "anv_private.h"
33 #include "compiler/brw_nir.h"
35 #include "spirv/nir_spirv.h"
37 /* Needed for SWIZZLE macros */
38 #include "program/prog_instruction.h"
42 VkResult
anv_CreateShaderModule(
44 const VkShaderModuleCreateInfo
* pCreateInfo
,
45 const VkAllocationCallbacks
* pAllocator
,
46 VkShaderModule
* pShaderModule
)
48 ANV_FROM_HANDLE(anv_device
, device
, _device
);
49 struct anv_shader_module
*module
;
51 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
52 assert(pCreateInfo
->flags
== 0);
54 module
= vk_alloc2(&device
->alloc
, pAllocator
,
55 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
56 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
58 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
60 module
->size
= pCreateInfo
->codeSize
;
61 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
63 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
65 *pShaderModule
= anv_shader_module_to_handle(module
);
70 void anv_DestroyShaderModule(
72 VkShaderModule _module
,
73 const VkAllocationCallbacks
* pAllocator
)
75 ANV_FROM_HANDLE(anv_device
, device
, _device
);
76 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
81 vk_free2(&device
->alloc
, pAllocator
, module
);
84 #define SPIR_V_MAGIC_NUMBER 0x07230203
86 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
87 * we can't do that yet because we don't have the ability to copy nir.
90 anv_shader_compile_to_nir(struct anv_pipeline
*pipeline
,
92 struct anv_shader_module
*module
,
93 const char *entrypoint_name
,
94 gl_shader_stage stage
,
95 const VkSpecializationInfo
*spec_info
)
97 const struct anv_device
*device
= pipeline
->device
;
99 const struct brw_compiler
*compiler
=
100 device
->instance
->physicalDevice
.compiler
;
101 const nir_shader_compiler_options
*nir_options
=
102 compiler
->glsl_compiler_options
[stage
].NirOptions
;
104 uint32_t *spirv
= (uint32_t *) module
->data
;
105 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
106 assert(module
->size
% 4 == 0);
108 uint32_t num_spec_entries
= 0;
109 struct nir_spirv_specialization
*spec_entries
= NULL
;
110 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
111 num_spec_entries
= spec_info
->mapEntryCount
;
112 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
113 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
114 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
115 const void *data
= spec_info
->pData
+ entry
.offset
;
116 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
118 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
119 if (spec_info
->dataSize
== 8)
120 spec_entries
[i
].data64
= *(const uint64_t *)data
;
122 spec_entries
[i
].data32
= *(const uint32_t *)data
;
126 const struct nir_spirv_supported_extensions supported_ext
= {
127 .float64
= device
->instance
->physicalDevice
.info
.gen
>= 8,
128 .int64
= device
->instance
->physicalDevice
.info
.gen
>= 8,
129 .tessellation
= true,
130 .draw_parameters
= true,
131 .image_write_without_format
= true,
133 .variable_pointers
= true,
136 nir_function
*entry_point
=
137 spirv_to_nir(spirv
, module
->size
/ 4,
138 spec_entries
, num_spec_entries
,
139 stage
, entrypoint_name
, &supported_ext
, nir_options
);
140 nir_shader
*nir
= entry_point
->shader
;
141 assert(nir
->stage
== stage
);
142 nir_validate_shader(nir
);
143 ralloc_steal(mem_ctx
, nir
);
147 /* We have to lower away local constant initializers right before we
148 * inline functions. That way they get properly initialized at the top
149 * of the function and not at the top of its caller.
151 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_local
);
152 NIR_PASS_V(nir
, nir_lower_returns
);
153 NIR_PASS_V(nir
, nir_inline_functions
);
155 /* Pick off the single entrypoint that we want */
156 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
157 if (func
!= entry_point
)
158 exec_node_remove(&func
->node
);
160 assert(exec_list_length(&nir
->functions
) == 1);
161 entry_point
->name
= ralloc_strdup(entry_point
, "main");
163 NIR_PASS_V(nir
, nir_remove_dead_variables
,
164 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
166 if (stage
== MESA_SHADER_FRAGMENT
)
167 NIR_PASS_V(nir
, nir_lower_wpos_center
, pipeline
->sample_shading_enable
);
169 /* Now that we've deleted all but the main function, we can go ahead and
170 * lower the rest of the constant initializers.
172 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
173 NIR_PASS_V(nir
, nir_propagate_invariant
);
174 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
175 entry_point
->impl
, true, false);
176 NIR_PASS_V(nir
, nir_lower_system_values
);
178 /* Vulkan uses the separate-shader linking model */
179 nir
->info
.separate_shader
= true;
181 nir
= brw_preprocess_nir(compiler
, nir
);
183 NIR_PASS_V(nir
, nir_lower_clip_cull_distance_arrays
);
185 if (stage
== MESA_SHADER_FRAGMENT
)
186 NIR_PASS_V(nir
, anv_nir_lower_input_attachments
);
191 void anv_DestroyPipeline(
193 VkPipeline _pipeline
,
194 const VkAllocationCallbacks
* pAllocator
)
196 ANV_FROM_HANDLE(anv_device
, device
, _device
);
197 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
202 anv_reloc_list_finish(&pipeline
->batch_relocs
,
203 pAllocator
? pAllocator
: &device
->alloc
);
204 if (pipeline
->blend_state
.map
)
205 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
207 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
208 if (pipeline
->shaders
[s
])
209 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
212 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
215 static const uint32_t vk_to_gen_primitive_type
[] = {
216 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
217 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
218 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
219 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
220 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
221 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
222 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
223 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
224 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
225 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
229 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
230 struct brw_sampler_prog_key_data
*key
)
232 /* Almost all multisampled textures are compressed. The only time when we
233 * don't compress a multisampled texture is for 16x MSAA with a surface
234 * width greater than 8k which is a bit of an edge case. Since the sampler
235 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
236 * to tell the compiler to always assume compression.
238 key
->compressed_multisample_layout_mask
= ~0;
240 /* SkyLake added support for 16x MSAA. With this came a new message for
241 * reading from a 16x MSAA surface with compression. The new message was
242 * needed because now the MCS data is 64 bits instead of 32 or lower as is
243 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
244 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
245 * so we can just use it unconditionally. This may not be quite as
246 * efficient but it saves us from recompiling.
248 if (devinfo
->gen
>= 9)
251 /* XXX: Handle texture swizzle on HSW- */
252 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
253 /* Assume color sampler, no swizzling. (Works for BDW+) */
254 key
->swizzles
[i
] = SWIZZLE_XYZW
;
259 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
260 struct brw_vs_prog_key
*key
)
262 memset(key
, 0, sizeof(*key
));
264 populate_sampler_prog_key(devinfo
, &key
->tex
);
266 /* XXX: Handle vertex input work-arounds */
268 /* XXX: Handle sampler_prog_key */
272 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
273 struct brw_gs_prog_key
*key
)
275 memset(key
, 0, sizeof(*key
));
277 populate_sampler_prog_key(devinfo
, &key
->tex
);
281 populate_wm_prog_key(const struct anv_pipeline
*pipeline
,
282 const VkGraphicsPipelineCreateInfo
*info
,
283 struct brw_wm_prog_key
*key
)
285 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
287 memset(key
, 0, sizeof(*key
));
289 populate_sampler_prog_key(devinfo
, &key
->tex
);
291 /* TODO: we could set this to 0 based on the information in nir_shader, but
292 * this function is called before spirv_to_nir. */
293 const struct brw_vue_map
*vue_map
=
294 &anv_pipeline_get_last_vue_prog_data(pipeline
)->vue_map
;
295 key
->input_slots_valid
= vue_map
->slots_valid
;
297 /* Vulkan doesn't specify a default */
298 key
->high_quality_derivatives
= false;
300 /* XXX Vulkan doesn't appear to specify */
301 key
->clamp_fragment_color
= false;
303 key
->nr_color_regions
= pipeline
->subpass
->color_count
;
305 key
->replicate_alpha
= key
->nr_color_regions
> 1 &&
306 info
->pMultisampleState
&&
307 info
->pMultisampleState
->alphaToCoverageEnable
;
309 if (info
->pMultisampleState
) {
310 /* We should probably pull this out of the shader, but it's fairly
311 * harmless to compute it and then let dead-code take care of it.
313 if (info
->pMultisampleState
->rasterizationSamples
> 1) {
314 key
->persample_interp
=
315 (info
->pMultisampleState
->minSampleShading
*
316 info
->pMultisampleState
->rasterizationSamples
) > 1;
317 key
->multisample_fbo
= true;
320 key
->frag_coord_adds_sample_pos
=
321 info
->pMultisampleState
->sampleShadingEnable
;
326 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
327 struct brw_cs_prog_key
*key
)
329 memset(key
, 0, sizeof(*key
));
331 populate_sampler_prog_key(devinfo
, &key
->tex
);
335 anv_pipeline_hash_shader(struct anv_pipeline
*pipeline
,
336 struct anv_shader_module
*module
,
337 const char *entrypoint
,
338 gl_shader_stage stage
,
339 const VkSpecializationInfo
*spec_info
,
340 const void *key
, size_t key_size
,
341 unsigned char *sha1_out
)
343 struct mesa_sha1 ctx
;
345 _mesa_sha1_init(&ctx
);
346 if (stage
!= MESA_SHADER_COMPUTE
) {
347 _mesa_sha1_update(&ctx
, &pipeline
->subpass
->view_mask
,
348 sizeof(pipeline
->subpass
->view_mask
));
350 if (pipeline
->layout
) {
351 _mesa_sha1_update(&ctx
, pipeline
->layout
->sha1
,
352 sizeof(pipeline
->layout
->sha1
));
354 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
355 _mesa_sha1_update(&ctx
, entrypoint
, strlen(entrypoint
));
356 _mesa_sha1_update(&ctx
, &stage
, sizeof(stage
));
358 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
359 spec_info
->mapEntryCount
* sizeof(*spec_info
->pMapEntries
));
360 _mesa_sha1_update(&ctx
, spec_info
->pData
, spec_info
->dataSize
);
362 _mesa_sha1_update(&ctx
, key
, key_size
);
363 _mesa_sha1_final(&ctx
, sha1_out
);
367 anv_pipeline_compile(struct anv_pipeline
*pipeline
,
369 struct anv_shader_module
*module
,
370 const char *entrypoint
,
371 gl_shader_stage stage
,
372 const VkSpecializationInfo
*spec_info
,
373 struct brw_stage_prog_data
*prog_data
,
374 struct anv_pipeline_bind_map
*map
)
376 nir_shader
*nir
= anv_shader_compile_to_nir(pipeline
, mem_ctx
,
377 module
, entrypoint
, stage
,
382 NIR_PASS_V(nir
, anv_nir_lower_ycbcr_textures
, pipeline
);
384 NIR_PASS_V(nir
, anv_nir_lower_push_constants
);
386 if (stage
!= MESA_SHADER_COMPUTE
)
387 NIR_PASS_V(nir
, anv_nir_lower_multiview
, pipeline
->subpass
->view_mask
);
389 if (stage
== MESA_SHADER_COMPUTE
) {
390 NIR_PASS_V(nir
, brw_nir_lower_cs_shared
);
391 prog_data
->total_shared
= nir
->num_shared
;
394 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
396 if (nir
->num_uniforms
> 0) {
397 assert(prog_data
->nr_params
== 0);
399 /* If the shader uses any push constants at all, we'll just give
400 * them the maximum possible number
402 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
403 nir
->num_uniforms
= MAX_PUSH_CONSTANTS_SIZE
;
404 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
405 prog_data
->param
= ralloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
407 /* We now set the param values to be offsets into a
408 * anv_push_constant_data structure. Since the compiler doesn't
409 * actually dereference any of the gl_constant_value pointers in the
410 * params array, it doesn't really matter what we put here.
412 struct anv_push_constants
*null_data
= NULL
;
413 /* Fill out the push constants section of the param array */
414 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++) {
415 prog_data
->param
[i
] = ANV_PARAM_PUSH(
416 (uintptr_t)&null_data
->client_data
[i
* sizeof(float)]);
420 if (nir
->info
.num_ssbos
> 0 || nir
->info
.num_images
> 0)
421 pipeline
->needs_data_cache
= true;
423 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
424 if (pipeline
->layout
)
425 anv_nir_apply_pipeline_layout(pipeline
, nir
, prog_data
, map
);
427 assert(nir
->num_uniforms
== prog_data
->nr_params
* 4);
433 anv_fill_binding_table(struct brw_stage_prog_data
*prog_data
, unsigned bias
)
435 prog_data
->binding_table
.size_bytes
= 0;
436 prog_data
->binding_table
.texture_start
= bias
;
437 prog_data
->binding_table
.gather_texture_start
= bias
;
438 prog_data
->binding_table
.ubo_start
= bias
;
439 prog_data
->binding_table
.ssbo_start
= bias
;
440 prog_data
->binding_table
.image_start
= bias
;
443 static struct anv_shader_bin
*
444 anv_pipeline_upload_kernel(struct anv_pipeline
*pipeline
,
445 struct anv_pipeline_cache
*cache
,
446 const void *key_data
, uint32_t key_size
,
447 const void *kernel_data
, uint32_t kernel_size
,
448 const struct brw_stage_prog_data
*prog_data
,
449 uint32_t prog_data_size
,
450 const struct anv_pipeline_bind_map
*bind_map
)
453 return anv_pipeline_cache_upload_kernel(cache
, key_data
, key_size
,
454 kernel_data
, kernel_size
,
455 prog_data
, prog_data_size
,
458 return anv_shader_bin_create(pipeline
->device
, key_data
, key_size
,
459 kernel_data
, kernel_size
,
460 prog_data
, prog_data_size
,
461 prog_data
->param
, bind_map
);
467 anv_pipeline_add_compiled_stage(struct anv_pipeline
*pipeline
,
468 gl_shader_stage stage
,
469 struct anv_shader_bin
*shader
)
471 pipeline
->shaders
[stage
] = shader
;
472 pipeline
->active_stages
|= mesa_to_vk_shader_stage(stage
);
476 anv_pipeline_compile_vs(struct anv_pipeline
*pipeline
,
477 struct anv_pipeline_cache
*cache
,
478 const VkGraphicsPipelineCreateInfo
*info
,
479 struct anv_shader_module
*module
,
480 const char *entrypoint
,
481 const VkSpecializationInfo
*spec_info
)
483 const struct brw_compiler
*compiler
=
484 pipeline
->device
->instance
->physicalDevice
.compiler
;
485 struct brw_vs_prog_key key
;
486 struct anv_shader_bin
*bin
= NULL
;
487 unsigned char sha1
[20];
489 populate_vs_prog_key(&pipeline
->device
->info
, &key
);
492 anv_pipeline_hash_shader(pipeline
, module
, entrypoint
,
493 MESA_SHADER_VERTEX
, spec_info
,
494 &key
, sizeof(key
), sha1
);
495 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
499 struct brw_vs_prog_data prog_data
= {};
500 struct anv_pipeline_binding surface_to_descriptor
[256];
501 struct anv_pipeline_binding sampler_to_descriptor
[256];
503 struct anv_pipeline_bind_map map
= {
504 .surface_to_descriptor
= surface_to_descriptor
,
505 .sampler_to_descriptor
= sampler_to_descriptor
508 void *mem_ctx
= ralloc_context(NULL
);
510 nir_shader
*nir
= anv_pipeline_compile(pipeline
, mem_ctx
,
512 MESA_SHADER_VERTEX
, spec_info
,
513 &prog_data
.base
.base
, &map
);
515 ralloc_free(mem_ctx
);
516 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
519 anv_fill_binding_table(&prog_data
.base
.base
, 0);
521 brw_compute_vue_map(&pipeline
->device
->info
,
522 &prog_data
.base
.vue_map
,
523 nir
->info
.outputs_written
,
524 nir
->info
.separate_shader
);
527 const unsigned *shader_code
=
528 brw_compile_vs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
529 false, -1, &code_size
, NULL
);
530 if (shader_code
== NULL
) {
531 ralloc_free(mem_ctx
);
532 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
535 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
536 shader_code
, code_size
,
537 &prog_data
.base
.base
, sizeof(prog_data
),
540 ralloc_free(mem_ctx
);
541 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
544 ralloc_free(mem_ctx
);
547 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_VERTEX
, bin
);
553 merge_tess_info(struct shader_info
*tes_info
,
554 const struct shader_info
*tcs_info
)
556 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
558 * "PointMode. Controls generation of points rather than triangles
559 * or lines. This functionality defaults to disabled, and is
560 * enabled if either shader stage includes the execution mode.
562 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
563 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
564 * and OutputVertices, it says:
566 * "One mode must be set in at least one of the tessellation
569 * So, the fields can be set in either the TCS or TES, but they must
570 * agree if set in both. Our backend looks at TES, so bitwise-or in
571 * the values from the TCS.
573 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
574 tes_info
->tess
.tcs_vertices_out
== 0 ||
575 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
576 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
578 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
579 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
580 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
581 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
583 assert(tcs_info
->tess
.primitive_mode
== 0 ||
584 tes_info
->tess
.primitive_mode
== 0 ||
585 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
586 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
587 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
588 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
592 anv_pipeline_compile_tcs_tes(struct anv_pipeline
*pipeline
,
593 struct anv_pipeline_cache
*cache
,
594 const VkGraphicsPipelineCreateInfo
*info
,
595 struct anv_shader_module
*tcs_module
,
596 const char *tcs_entrypoint
,
597 const VkSpecializationInfo
*tcs_spec_info
,
598 struct anv_shader_module
*tes_module
,
599 const char *tes_entrypoint
,
600 const VkSpecializationInfo
*tes_spec_info
)
602 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
603 const struct brw_compiler
*compiler
=
604 pipeline
->device
->instance
->physicalDevice
.compiler
;
605 struct brw_tcs_prog_key tcs_key
= {};
606 struct brw_tes_prog_key tes_key
= {};
607 struct anv_shader_bin
*tcs_bin
= NULL
;
608 struct anv_shader_bin
*tes_bin
= NULL
;
609 unsigned char tcs_sha1
[40];
610 unsigned char tes_sha1
[40];
612 populate_sampler_prog_key(&pipeline
->device
->info
, &tcs_key
.tex
);
613 populate_sampler_prog_key(&pipeline
->device
->info
, &tes_key
.tex
);
614 tcs_key
.input_vertices
= info
->pTessellationState
->patchControlPoints
;
617 anv_pipeline_hash_shader(pipeline
, tcs_module
, tcs_entrypoint
,
618 MESA_SHADER_TESS_CTRL
, tcs_spec_info
,
619 &tcs_key
, sizeof(tcs_key
), tcs_sha1
);
620 anv_pipeline_hash_shader(pipeline
, tes_module
, tes_entrypoint
,
621 MESA_SHADER_TESS_EVAL
, tes_spec_info
,
622 &tes_key
, sizeof(tes_key
), tes_sha1
);
623 memcpy(&tcs_sha1
[20], tes_sha1
, 20);
624 memcpy(&tes_sha1
[20], tcs_sha1
, 20);
625 tcs_bin
= anv_pipeline_cache_search(cache
, tcs_sha1
, sizeof(tcs_sha1
));
626 tes_bin
= anv_pipeline_cache_search(cache
, tes_sha1
, sizeof(tes_sha1
));
629 if (tcs_bin
== NULL
|| tes_bin
== NULL
) {
630 struct brw_tcs_prog_data tcs_prog_data
= {};
631 struct brw_tes_prog_data tes_prog_data
= {};
632 struct anv_pipeline_binding tcs_surface_to_descriptor
[256];
633 struct anv_pipeline_binding tcs_sampler_to_descriptor
[256];
634 struct anv_pipeline_binding tes_surface_to_descriptor
[256];
635 struct anv_pipeline_binding tes_sampler_to_descriptor
[256];
637 struct anv_pipeline_bind_map tcs_map
= {
638 .surface_to_descriptor
= tcs_surface_to_descriptor
,
639 .sampler_to_descriptor
= tcs_sampler_to_descriptor
641 struct anv_pipeline_bind_map tes_map
= {
642 .surface_to_descriptor
= tes_surface_to_descriptor
,
643 .sampler_to_descriptor
= tes_sampler_to_descriptor
646 void *mem_ctx
= ralloc_context(NULL
);
648 nir_shader
*tcs_nir
=
649 anv_pipeline_compile(pipeline
, mem_ctx
, tcs_module
, tcs_entrypoint
,
650 MESA_SHADER_TESS_CTRL
, tcs_spec_info
,
651 &tcs_prog_data
.base
.base
, &tcs_map
);
652 nir_shader
*tes_nir
=
653 anv_pipeline_compile(pipeline
, mem_ctx
, tes_module
, tes_entrypoint
,
654 MESA_SHADER_TESS_EVAL
, tes_spec_info
,
655 &tes_prog_data
.base
.base
, &tes_map
);
656 if (tcs_nir
== NULL
|| tes_nir
== NULL
) {
657 ralloc_free(mem_ctx
);
658 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
661 nir_lower_tes_patch_vertices(tes_nir
,
662 tcs_nir
->info
.tess
.tcs_vertices_out
);
664 /* Copy TCS info into the TES info */
665 merge_tess_info(&tes_nir
->info
, &tcs_nir
->info
);
667 anv_fill_binding_table(&tcs_prog_data
.base
.base
, 0);
668 anv_fill_binding_table(&tes_prog_data
.base
.base
, 0);
670 /* Whacking the key after cache lookup is a bit sketchy, but all of
671 * this comes from the SPIR-V, which is part of the hash used for the
672 * pipeline cache. So it should be safe.
674 tcs_key
.tes_primitive_mode
= tes_nir
->info
.tess
.primitive_mode
;
675 tcs_key
.outputs_written
= tcs_nir
->info
.outputs_written
;
676 tcs_key
.patch_outputs_written
= tcs_nir
->info
.patch_outputs_written
;
677 tcs_key
.quads_workaround
=
679 tes_nir
->info
.tess
.primitive_mode
== 7 /* GL_QUADS */ &&
680 tes_nir
->info
.tess
.spacing
== TESS_SPACING_EQUAL
;
682 tes_key
.inputs_read
= tcs_key
.outputs_written
;
683 tes_key
.patch_inputs_read
= tcs_key
.patch_outputs_written
;
686 const int shader_time_index
= -1;
687 const unsigned *shader_code
;
690 brw_compile_tcs(compiler
, NULL
, mem_ctx
, &tcs_key
, &tcs_prog_data
,
691 tcs_nir
, shader_time_index
, &code_size
, NULL
);
692 if (shader_code
== NULL
) {
693 ralloc_free(mem_ctx
);
694 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
697 tcs_bin
= anv_pipeline_upload_kernel(pipeline
, cache
,
698 tcs_sha1
, sizeof(tcs_sha1
),
699 shader_code
, code_size
,
700 &tcs_prog_data
.base
.base
,
701 sizeof(tcs_prog_data
),
704 ralloc_free(mem_ctx
);
705 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
709 brw_compile_tes(compiler
, NULL
, mem_ctx
, &tes_key
,
710 &tcs_prog_data
.base
.vue_map
, &tes_prog_data
, tes_nir
,
711 NULL
, shader_time_index
, &code_size
, NULL
);
712 if (shader_code
== NULL
) {
713 ralloc_free(mem_ctx
);
714 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
717 tes_bin
= anv_pipeline_upload_kernel(pipeline
, cache
,
718 tes_sha1
, sizeof(tes_sha1
),
719 shader_code
, code_size
,
720 &tes_prog_data
.base
.base
,
721 sizeof(tes_prog_data
),
724 ralloc_free(mem_ctx
);
725 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
728 ralloc_free(mem_ctx
);
731 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_TESS_CTRL
, tcs_bin
);
732 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_TESS_EVAL
, tes_bin
);
738 anv_pipeline_compile_gs(struct anv_pipeline
*pipeline
,
739 struct anv_pipeline_cache
*cache
,
740 const VkGraphicsPipelineCreateInfo
*info
,
741 struct anv_shader_module
*module
,
742 const char *entrypoint
,
743 const VkSpecializationInfo
*spec_info
)
745 const struct brw_compiler
*compiler
=
746 pipeline
->device
->instance
->physicalDevice
.compiler
;
747 struct brw_gs_prog_key key
;
748 struct anv_shader_bin
*bin
= NULL
;
749 unsigned char sha1
[20];
751 populate_gs_prog_key(&pipeline
->device
->info
, &key
);
754 anv_pipeline_hash_shader(pipeline
, module
, entrypoint
,
755 MESA_SHADER_GEOMETRY
, spec_info
,
756 &key
, sizeof(key
), sha1
);
757 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
761 struct brw_gs_prog_data prog_data
= {};
762 struct anv_pipeline_binding surface_to_descriptor
[256];
763 struct anv_pipeline_binding sampler_to_descriptor
[256];
765 struct anv_pipeline_bind_map map
= {
766 .surface_to_descriptor
= surface_to_descriptor
,
767 .sampler_to_descriptor
= sampler_to_descriptor
770 void *mem_ctx
= ralloc_context(NULL
);
772 nir_shader
*nir
= anv_pipeline_compile(pipeline
, mem_ctx
,
774 MESA_SHADER_GEOMETRY
, spec_info
,
775 &prog_data
.base
.base
, &map
);
777 ralloc_free(mem_ctx
);
778 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
781 anv_fill_binding_table(&prog_data
.base
.base
, 0);
783 brw_compute_vue_map(&pipeline
->device
->info
,
784 &prog_data
.base
.vue_map
,
785 nir
->info
.outputs_written
,
786 nir
->info
.separate_shader
);
789 const unsigned *shader_code
=
790 brw_compile_gs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
791 NULL
, -1, &code_size
, NULL
);
792 if (shader_code
== NULL
) {
793 ralloc_free(mem_ctx
);
794 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
798 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
799 shader_code
, code_size
,
800 &prog_data
.base
.base
, sizeof(prog_data
),
803 ralloc_free(mem_ctx
);
804 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
807 ralloc_free(mem_ctx
);
810 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_GEOMETRY
, bin
);
816 anv_pipeline_compile_fs(struct anv_pipeline
*pipeline
,
817 struct anv_pipeline_cache
*cache
,
818 const VkGraphicsPipelineCreateInfo
*info
,
819 struct anv_shader_module
*module
,
820 const char *entrypoint
,
821 const VkSpecializationInfo
*spec_info
)
823 const struct brw_compiler
*compiler
=
824 pipeline
->device
->instance
->physicalDevice
.compiler
;
825 struct brw_wm_prog_key key
;
826 struct anv_shader_bin
*bin
= NULL
;
827 unsigned char sha1
[20];
829 populate_wm_prog_key(pipeline
, info
, &key
);
832 anv_pipeline_hash_shader(pipeline
, module
, entrypoint
,
833 MESA_SHADER_FRAGMENT
, spec_info
,
834 &key
, sizeof(key
), sha1
);
835 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
839 struct brw_wm_prog_data prog_data
= {};
840 struct anv_pipeline_binding surface_to_descriptor
[256];
841 struct anv_pipeline_binding sampler_to_descriptor
[256];
843 struct anv_pipeline_bind_map map
= {
844 .surface_to_descriptor
= surface_to_descriptor
+ 8,
845 .sampler_to_descriptor
= sampler_to_descriptor
848 void *mem_ctx
= ralloc_context(NULL
);
850 nir_shader
*nir
= anv_pipeline_compile(pipeline
, mem_ctx
,
852 MESA_SHADER_FRAGMENT
, spec_info
,
853 &prog_data
.base
, &map
);
855 ralloc_free(mem_ctx
);
856 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
859 unsigned num_rts
= 0;
860 struct anv_pipeline_binding rt_bindings
[8];
861 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
862 nir_foreach_variable_safe(var
, &nir
->outputs
) {
863 if (var
->data
.location
< FRAG_RESULT_DATA0
)
866 unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
867 if (rt
>= key
.nr_color_regions
) {
868 /* Out-of-bounds, throw it away */
869 var
->data
.mode
= nir_var_local
;
870 exec_node_remove(&var
->node
);
871 exec_list_push_tail(&impl
->locals
, &var
->node
);
875 /* Give it a new, compacted, location */
876 var
->data
.location
= FRAG_RESULT_DATA0
+ num_rts
;
879 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
880 assert(num_rts
+ array_len
<= 8);
882 for (unsigned i
= 0; i
< array_len
; i
++) {
883 rt_bindings
[num_rts
+ i
] = (struct anv_pipeline_binding
) {
884 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
890 num_rts
+= array_len
;
894 /* If we have no render targets, we need a null render target */
895 rt_bindings
[0] = (struct anv_pipeline_binding
) {
896 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
903 assert(num_rts
<= 8);
904 map
.surface_to_descriptor
-= num_rts
;
905 map
.surface_count
+= num_rts
;
906 assert(map
.surface_count
<= 256);
907 memcpy(map
.surface_to_descriptor
, rt_bindings
,
908 num_rts
* sizeof(*rt_bindings
));
910 anv_fill_binding_table(&prog_data
.base
, num_rts
);
913 const unsigned *shader_code
=
914 brw_compile_fs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
915 NULL
, -1, -1, true, false, NULL
, &code_size
, NULL
);
916 if (shader_code
== NULL
) {
917 ralloc_free(mem_ctx
);
918 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
921 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
922 shader_code
, code_size
,
923 &prog_data
.base
, sizeof(prog_data
),
926 ralloc_free(mem_ctx
);
927 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
930 ralloc_free(mem_ctx
);
933 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_FRAGMENT
, bin
);
939 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
940 struct anv_pipeline_cache
*cache
,
941 const VkComputePipelineCreateInfo
*info
,
942 struct anv_shader_module
*module
,
943 const char *entrypoint
,
944 const VkSpecializationInfo
*spec_info
)
946 const struct brw_compiler
*compiler
=
947 pipeline
->device
->instance
->physicalDevice
.compiler
;
948 struct brw_cs_prog_key key
;
949 struct anv_shader_bin
*bin
= NULL
;
950 unsigned char sha1
[20];
952 populate_cs_prog_key(&pipeline
->device
->info
, &key
);
955 anv_pipeline_hash_shader(pipeline
, module
, entrypoint
,
956 MESA_SHADER_COMPUTE
, spec_info
,
957 &key
, sizeof(key
), sha1
);
958 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
962 struct brw_cs_prog_data prog_data
= {};
963 struct anv_pipeline_binding surface_to_descriptor
[256];
964 struct anv_pipeline_binding sampler_to_descriptor
[256];
966 struct anv_pipeline_bind_map map
= {
967 .surface_to_descriptor
= surface_to_descriptor
,
968 .sampler_to_descriptor
= sampler_to_descriptor
971 void *mem_ctx
= ralloc_context(NULL
);
973 nir_shader
*nir
= anv_pipeline_compile(pipeline
, mem_ctx
,
975 MESA_SHADER_COMPUTE
, spec_info
,
976 &prog_data
.base
, &map
);
978 ralloc_free(mem_ctx
);
979 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
982 anv_fill_binding_table(&prog_data
.base
, 1);
985 const unsigned *shader_code
=
986 brw_compile_cs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
987 -1, &code_size
, NULL
);
988 if (shader_code
== NULL
) {
989 ralloc_free(mem_ctx
);
990 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
993 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
994 shader_code
, code_size
,
995 &prog_data
.base
, sizeof(prog_data
),
998 ralloc_free(mem_ctx
);
999 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1002 ralloc_free(mem_ctx
);
1005 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_COMPUTE
, bin
);
1011 * Copy pipeline state not marked as dynamic.
1012 * Dynamic state is pipeline state which hasn't been provided at pipeline
1013 * creation time, but is dynamically provided afterwards using various
1014 * vkCmdSet* functions.
1016 * The set of state considered "non_dynamic" is determined by the pieces of
1017 * state that have their corresponding VkDynamicState enums omitted from
1018 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1020 * @param[out] pipeline Destination non_dynamic state.
1021 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1024 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
1025 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1027 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
1028 struct anv_subpass
*subpass
= pipeline
->subpass
;
1030 pipeline
->dynamic_state
= default_dynamic_state
;
1032 if (pCreateInfo
->pDynamicState
) {
1033 /* Remove all of the states that are marked as dynamic */
1034 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1035 for (uint32_t s
= 0; s
< count
; s
++)
1036 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1039 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1041 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1043 * pViewportState is [...] NULL if the pipeline
1044 * has rasterization disabled.
1046 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1047 assert(pCreateInfo
->pViewportState
);
1049 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1050 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
1051 typed_memcpy(dynamic
->viewport
.viewports
,
1052 pCreateInfo
->pViewportState
->pViewports
,
1053 pCreateInfo
->pViewportState
->viewportCount
);
1056 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1057 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
1058 typed_memcpy(dynamic
->scissor
.scissors
,
1059 pCreateInfo
->pViewportState
->pScissors
,
1060 pCreateInfo
->pViewportState
->scissorCount
);
1064 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1065 assert(pCreateInfo
->pRasterizationState
);
1066 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1069 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1070 assert(pCreateInfo
->pRasterizationState
);
1071 dynamic
->depth_bias
.bias
=
1072 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1073 dynamic
->depth_bias
.clamp
=
1074 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1075 dynamic
->depth_bias
.slope
=
1076 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1079 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1081 * pColorBlendState is [...] NULL if the pipeline has rasterization
1082 * disabled or if the subpass of the render pass the pipeline is
1083 * created against does not use any color attachments.
1085 bool uses_color_att
= false;
1086 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1087 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1088 uses_color_att
= true;
1093 if (uses_color_att
&&
1094 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1095 assert(pCreateInfo
->pColorBlendState
);
1097 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
1098 typed_memcpy(dynamic
->blend_constants
,
1099 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1102 /* If there is no depthstencil attachment, then don't read
1103 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1104 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1105 * no need to override the depthstencil defaults in
1106 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1108 * Section 9.2 of the Vulkan 1.0.15 spec says:
1110 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1111 * disabled or if the subpass of the render pass the pipeline is created
1112 * against does not use a depth/stencil attachment.
1114 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1115 subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1116 assert(pCreateInfo
->pDepthStencilState
);
1118 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1119 dynamic
->depth_bounds
.min
=
1120 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1121 dynamic
->depth_bounds
.max
=
1122 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1125 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1126 dynamic
->stencil_compare_mask
.front
=
1127 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1128 dynamic
->stencil_compare_mask
.back
=
1129 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1132 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1133 dynamic
->stencil_write_mask
.front
=
1134 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1135 dynamic
->stencil_write_mask
.back
=
1136 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1139 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1140 dynamic
->stencil_reference
.front
=
1141 pCreateInfo
->pDepthStencilState
->front
.reference
;
1142 dynamic
->stencil_reference
.back
=
1143 pCreateInfo
->pDepthStencilState
->back
.reference
;
1147 pipeline
->dynamic_state_mask
= states
;
1151 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1154 struct anv_render_pass
*renderpass
= NULL
;
1155 struct anv_subpass
*subpass
= NULL
;
1157 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1158 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1160 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1162 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1165 assert(info
->subpass
< renderpass
->subpass_count
);
1166 subpass
= &renderpass
->subpasses
[info
->subpass
];
1168 assert(info
->stageCount
>= 1);
1169 assert(info
->pVertexInputState
);
1170 assert(info
->pInputAssemblyState
);
1171 assert(info
->pRasterizationState
);
1172 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1173 assert(info
->pViewportState
);
1174 assert(info
->pMultisampleState
);
1176 if (subpass
&& subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
)
1177 assert(info
->pDepthStencilState
);
1179 if (subpass
&& subpass
->color_count
> 0)
1180 assert(info
->pColorBlendState
);
1183 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1184 switch (info
->pStages
[i
].stage
) {
1185 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1186 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1187 assert(info
->pTessellationState
);
1197 * Calculate the desired L3 partitioning based on the current state of the
1198 * pipeline. For now this simply returns the conservative defaults calculated
1199 * by get_default_l3_weights(), but we could probably do better by gathering
1200 * more statistics from the pipeline state (e.g. guess of expected URB usage
1201 * and bound surfaces), or by using feed-back from performance counters.
1204 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1206 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1208 const struct gen_l3_weights w
=
1209 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
1211 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
1212 pipeline
->urb
.total_size
=
1213 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
1217 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1218 struct anv_device
*device
,
1219 struct anv_pipeline_cache
*cache
,
1220 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1221 const VkAllocationCallbacks
*alloc
)
1225 anv_pipeline_validate_create_info(pCreateInfo
);
1228 alloc
= &device
->alloc
;
1230 pipeline
->device
= device
;
1232 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, pCreateInfo
->renderPass
);
1233 assert(pCreateInfo
->subpass
< render_pass
->subpass_count
);
1234 pipeline
->subpass
= &render_pass
->subpasses
[pCreateInfo
->subpass
];
1236 pipeline
->layout
= anv_pipeline_layout_from_handle(pCreateInfo
->layout
);
1238 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1239 if (result
!= VK_SUCCESS
)
1242 pipeline
->batch
.alloc
= alloc
;
1243 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1244 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1245 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1246 pipeline
->batch
.status
= VK_SUCCESS
;
1248 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1249 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1250 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1252 pipeline
->sample_shading_enable
= pCreateInfo
->pMultisampleState
&&
1253 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
1255 pipeline
->needs_data_cache
= false;
1257 /* When we free the pipeline, we detect stages based on the NULL status
1258 * of various prog_data pointers. Make them NULL by default.
1260 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1262 pipeline
->active_stages
= 0;
1264 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = {};
1265 struct anv_shader_module
*modules
[MESA_SHADER_STAGES
] = {};
1266 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
1267 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
1268 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
1269 modules
[stage
] = anv_shader_module_from_handle(pStages
[stage
]->module
);
1272 if (modules
[MESA_SHADER_VERTEX
]) {
1273 result
= anv_pipeline_compile_vs(pipeline
, cache
, pCreateInfo
,
1274 modules
[MESA_SHADER_VERTEX
],
1275 pStages
[MESA_SHADER_VERTEX
]->pName
,
1276 pStages
[MESA_SHADER_VERTEX
]->pSpecializationInfo
);
1277 if (result
!= VK_SUCCESS
)
1281 if (modules
[MESA_SHADER_TESS_EVAL
]) {
1282 anv_pipeline_compile_tcs_tes(pipeline
, cache
, pCreateInfo
,
1283 modules
[MESA_SHADER_TESS_CTRL
],
1284 pStages
[MESA_SHADER_TESS_CTRL
]->pName
,
1285 pStages
[MESA_SHADER_TESS_CTRL
]->pSpecializationInfo
,
1286 modules
[MESA_SHADER_TESS_EVAL
],
1287 pStages
[MESA_SHADER_TESS_EVAL
]->pName
,
1288 pStages
[MESA_SHADER_TESS_EVAL
]->pSpecializationInfo
);
1291 if (modules
[MESA_SHADER_GEOMETRY
]) {
1292 result
= anv_pipeline_compile_gs(pipeline
, cache
, pCreateInfo
,
1293 modules
[MESA_SHADER_GEOMETRY
],
1294 pStages
[MESA_SHADER_GEOMETRY
]->pName
,
1295 pStages
[MESA_SHADER_GEOMETRY
]->pSpecializationInfo
);
1296 if (result
!= VK_SUCCESS
)
1300 if (modules
[MESA_SHADER_FRAGMENT
]) {
1301 result
= anv_pipeline_compile_fs(pipeline
, cache
, pCreateInfo
,
1302 modules
[MESA_SHADER_FRAGMENT
],
1303 pStages
[MESA_SHADER_FRAGMENT
]->pName
,
1304 pStages
[MESA_SHADER_FRAGMENT
]->pSpecializationInfo
);
1305 if (result
!= VK_SUCCESS
)
1309 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1311 anv_pipeline_setup_l3_config(pipeline
, false);
1313 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1314 pCreateInfo
->pVertexInputState
;
1316 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1318 pipeline
->vb_used
= 0;
1319 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1320 const VkVertexInputAttributeDescription
*desc
=
1321 &vi_info
->pVertexAttributeDescriptions
[i
];
1323 if (inputs_read
& (1ull << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1324 pipeline
->vb_used
|= 1 << desc
->binding
;
1327 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1328 const VkVertexInputBindingDescription
*desc
=
1329 &vi_info
->pVertexBindingDescriptions
[i
];
1331 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
1333 /* Step rate is programmed per vertex element (attribute), not
1334 * binding. Set up a map of which bindings step per instance, for
1335 * reference by vertex element setup. */
1336 switch (desc
->inputRate
) {
1338 case VK_VERTEX_INPUT_RATE_VERTEX
:
1339 pipeline
->instancing_enable
[desc
->binding
] = false;
1341 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1342 pipeline
->instancing_enable
[desc
->binding
] = true;
1347 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1348 pCreateInfo
->pInputAssemblyState
;
1349 const VkPipelineTessellationStateCreateInfo
*tess_info
=
1350 pCreateInfo
->pTessellationState
;
1351 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1353 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1354 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
1356 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];
1361 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1362 if (pipeline
->shaders
[s
])
1363 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
1366 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);