2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "common/gen_l3_config.h"
32 #include "anv_private.h"
35 #include "spirv/nir_spirv.h"
37 /* Needed for SWIZZLE macros */
38 #include "program/prog_instruction.h"
42 VkResult
anv_CreateShaderModule(
44 const VkShaderModuleCreateInfo
* pCreateInfo
,
45 const VkAllocationCallbacks
* pAllocator
,
46 VkShaderModule
* pShaderModule
)
48 ANV_FROM_HANDLE(anv_device
, device
, _device
);
49 struct anv_shader_module
*module
;
51 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
52 assert(pCreateInfo
->flags
== 0);
54 module
= anv_alloc2(&device
->alloc
, pAllocator
,
55 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
56 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
58 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
61 module
->size
= pCreateInfo
->codeSize
;
62 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
64 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
66 *pShaderModule
= anv_shader_module_to_handle(module
);
71 void anv_DestroyShaderModule(
73 VkShaderModule _module
,
74 const VkAllocationCallbacks
* pAllocator
)
76 ANV_FROM_HANDLE(anv_device
, device
, _device
);
77 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
79 anv_free2(&device
->alloc
, pAllocator
, module
);
82 #define SPIR_V_MAGIC_NUMBER 0x07230203
84 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
85 * we can't do that yet because we don't have the ability to copy nir.
88 anv_shader_compile_to_nir(struct anv_device
*device
,
89 struct anv_shader_module
*module
,
90 const char *entrypoint_name
,
91 gl_shader_stage stage
,
92 const VkSpecializationInfo
*spec_info
)
94 if (strcmp(entrypoint_name
, "main") != 0) {
95 anv_finishme("Multiple shaders per module not really supported");
98 const struct brw_compiler
*compiler
=
99 device
->instance
->physicalDevice
.compiler
;
100 const nir_shader_compiler_options
*nir_options
=
101 compiler
->glsl_compiler_options
[stage
].NirOptions
;
104 nir_function
*entry_point
;
106 /* Some things such as our meta clear/blit code will give us a NIR
107 * shader directly. In that case, we just ignore the SPIR-V entirely
108 * and just use the NIR shader */
110 nir
->options
= nir_options
;
111 nir_validate_shader(nir
);
113 assert(exec_list_length(&nir
->functions
) == 1);
114 struct exec_node
*node
= exec_list_get_head(&nir
->functions
);
115 entry_point
= exec_node_data(nir_function
, node
, node
);
117 uint32_t *spirv
= (uint32_t *) module
->data
;
118 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
119 assert(module
->size
% 4 == 0);
121 uint32_t num_spec_entries
= 0;
122 struct nir_spirv_specialization
*spec_entries
= NULL
;
123 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
124 num_spec_entries
= spec_info
->mapEntryCount
;
125 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
126 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
127 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
128 const void *data
= spec_info
->pData
+ entry
.offset
;
129 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
131 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
132 spec_entries
[i
].data
= *(const uint32_t *)data
;
136 entry_point
= spirv_to_nir(spirv
, module
->size
/ 4,
137 spec_entries
, num_spec_entries
,
138 stage
, entrypoint_name
, nir_options
);
139 nir
= entry_point
->shader
;
140 assert(nir
->stage
== stage
);
141 nir_validate_shader(nir
);
145 if (stage
== MESA_SHADER_FRAGMENT
) {
146 nir_lower_wpos_center(nir
);
147 nir_validate_shader(nir
);
150 nir_lower_returns(nir
);
151 nir_validate_shader(nir
);
153 nir_inline_functions(nir
);
154 nir_validate_shader(nir
);
156 /* Pick off the single entrypoint that we want */
157 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
158 if (func
!= entry_point
)
159 exec_node_remove(&func
->node
);
161 assert(exec_list_length(&nir
->functions
) == 1);
162 entry_point
->name
= ralloc_strdup(entry_point
, "main");
164 nir_remove_dead_variables(nir
, nir_var_shader_in
);
165 nir_remove_dead_variables(nir
, nir_var_shader_out
);
166 nir_remove_dead_variables(nir
, nir_var_system_value
);
167 nir_validate_shader(nir
);
169 nir_propagate_invariant(nir
);
170 nir_validate_shader(nir
);
172 nir_lower_io_to_temporaries(entry_point
->shader
, entry_point
->impl
,
175 nir_lower_system_values(nir
);
176 nir_validate_shader(nir
);
179 /* Vulkan uses the separate-shader linking model */
180 nir
->info
.separate_shader
= true;
182 nir
= brw_preprocess_nir(compiler
, nir
);
184 nir_shader_gather_info(nir
, entry_point
->impl
);
186 nir_variable_mode indirect_mask
= 0;
187 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectInput
)
188 indirect_mask
|= nir_var_shader_in
;
189 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectOutput
)
190 indirect_mask
|= nir_var_shader_out
;
191 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectTemp
)
192 indirect_mask
|= nir_var_local
;
194 nir_lower_indirect_derefs(nir
, indirect_mask
);
199 void anv_DestroyPipeline(
201 VkPipeline _pipeline
,
202 const VkAllocationCallbacks
* pAllocator
)
204 ANV_FROM_HANDLE(anv_device
, device
, _device
);
205 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
207 anv_reloc_list_finish(&pipeline
->batch_relocs
,
208 pAllocator
? pAllocator
: &device
->alloc
);
209 if (pipeline
->blend_state
.map
)
210 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
212 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
213 if (pipeline
->shaders
[s
])
214 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
217 anv_free2(&device
->alloc
, pAllocator
, pipeline
);
220 static const uint32_t vk_to_gen_primitive_type
[] = {
221 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
222 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
223 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
224 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
225 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
226 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
227 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
228 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
229 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
230 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
231 /* [VK_PRIMITIVE_TOPOLOGY_PATCH_LIST] = _3DPRIM_PATCHLIST_1 */
235 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
236 struct brw_sampler_prog_key_data
*key
)
238 /* XXX: Handle texture swizzle on HSW- */
239 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
240 /* Assume color sampler, no swizzling. (Works for BDW+) */
241 key
->swizzles
[i
] = SWIZZLE_XYZW
;
246 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
247 struct brw_vs_prog_key
*key
)
249 memset(key
, 0, sizeof(*key
));
251 populate_sampler_prog_key(devinfo
, &key
->tex
);
253 /* XXX: Handle vertex input work-arounds */
255 /* XXX: Handle sampler_prog_key */
259 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
260 struct brw_gs_prog_key
*key
)
262 memset(key
, 0, sizeof(*key
));
264 populate_sampler_prog_key(devinfo
, &key
->tex
);
268 populate_wm_prog_key(const struct gen_device_info
*devinfo
,
269 const VkGraphicsPipelineCreateInfo
*info
,
270 const struct anv_graphics_pipeline_create_info
*extra
,
271 struct brw_wm_prog_key
*key
)
273 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, info
->renderPass
);
275 memset(key
, 0, sizeof(*key
));
277 populate_sampler_prog_key(devinfo
, &key
->tex
);
279 /* TODO: Fill out key->input_slots_valid */
281 /* Vulkan doesn't specify a default */
282 key
->high_quality_derivatives
= false;
284 /* XXX Vulkan doesn't appear to specify */
285 key
->clamp_fragment_color
= false;
287 if (extra
&& extra
->color_attachment_count
>= 0) {
288 key
->nr_color_regions
= extra
->color_attachment_count
;
290 key
->nr_color_regions
=
291 render_pass
->subpasses
[info
->subpass
].color_count
;
294 key
->replicate_alpha
= key
->nr_color_regions
> 1 &&
295 info
->pMultisampleState
&&
296 info
->pMultisampleState
->alphaToCoverageEnable
;
298 if (info
->pMultisampleState
&& info
->pMultisampleState
->rasterizationSamples
> 1) {
299 /* We should probably pull this out of the shader, but it's fairly
300 * harmless to compute it and then let dead-code take care of it.
302 key
->persample_interp
=
303 (info
->pMultisampleState
->minSampleShading
*
304 info
->pMultisampleState
->rasterizationSamples
) > 1;
305 key
->multisample_fbo
= true;
310 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
311 struct brw_cs_prog_key
*key
)
313 memset(key
, 0, sizeof(*key
));
315 populate_sampler_prog_key(devinfo
, &key
->tex
);
319 anv_pipeline_compile(struct anv_pipeline
*pipeline
,
320 struct anv_shader_module
*module
,
321 const char *entrypoint
,
322 gl_shader_stage stage
,
323 const VkSpecializationInfo
*spec_info
,
324 struct brw_stage_prog_data
*prog_data
,
325 struct anv_pipeline_bind_map
*map
)
327 nir_shader
*nir
= anv_shader_compile_to_nir(pipeline
->device
,
328 module
, entrypoint
, stage
,
333 anv_nir_lower_push_constants(nir
);
335 /* Figure out the number of parameters */
336 prog_data
->nr_params
= 0;
338 if (nir
->num_uniforms
> 0) {
339 /* If the shader uses any push constants at all, we'll just give
340 * them the maximum possible number
342 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
343 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
346 if (pipeline
->layout
&& pipeline
->layout
->stage
[stage
].has_dynamic_offsets
)
347 prog_data
->nr_params
+= MAX_DYNAMIC_BUFFERS
* 2;
349 if (nir
->info
.num_images
> 0) {
350 prog_data
->nr_params
+= nir
->info
.num_images
* BRW_IMAGE_PARAM_SIZE
;
351 pipeline
->needs_data_cache
= true;
354 if (stage
== MESA_SHADER_COMPUTE
)
355 ((struct brw_cs_prog_data
*)prog_data
)->thread_local_id_index
=
356 prog_data
->nr_params
++; /* The CS Thread ID uniform */
358 if (nir
->info
.num_ssbos
> 0)
359 pipeline
->needs_data_cache
= true;
361 if (prog_data
->nr_params
> 0) {
362 /* XXX: I think we're leaking this */
363 prog_data
->param
= (const union gl_constant_value
**)
364 malloc(prog_data
->nr_params
* sizeof(union gl_constant_value
*));
366 /* We now set the param values to be offsets into a
367 * anv_push_constant_data structure. Since the compiler doesn't
368 * actually dereference any of the gl_constant_value pointers in the
369 * params array, it doesn't really matter what we put here.
371 struct anv_push_constants
*null_data
= NULL
;
372 if (nir
->num_uniforms
> 0) {
373 /* Fill out the push constants section of the param array */
374 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++)
375 prog_data
->param
[i
] = (const union gl_constant_value
*)
376 &null_data
->client_data
[i
* sizeof(float)];
380 /* Set up dynamic offsets */
381 anv_nir_apply_dynamic_offsets(pipeline
, nir
, prog_data
);
383 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
384 if (pipeline
->layout
)
385 anv_nir_apply_pipeline_layout(pipeline
, nir
, prog_data
, map
);
387 /* nir_lower_io will only handle the push constants; we need to set this
388 * to the full number of possible uniforms.
390 nir
->num_uniforms
= prog_data
->nr_params
* 4;
396 anv_fill_binding_table(struct brw_stage_prog_data
*prog_data
, unsigned bias
)
398 prog_data
->binding_table
.size_bytes
= 0;
399 prog_data
->binding_table
.texture_start
= bias
;
400 prog_data
->binding_table
.gather_texture_start
= bias
;
401 prog_data
->binding_table
.ubo_start
= bias
;
402 prog_data
->binding_table
.ssbo_start
= bias
;
403 prog_data
->binding_table
.image_start
= bias
;
406 static struct anv_shader_bin
*
407 anv_pipeline_upload_kernel(struct anv_pipeline
*pipeline
,
408 struct anv_pipeline_cache
*cache
,
409 const void *key_data
, uint32_t key_size
,
410 const void *kernel_data
, uint32_t kernel_size
,
411 const void *prog_data
, uint32_t prog_data_size
,
412 const struct anv_pipeline_bind_map
*bind_map
)
415 return anv_pipeline_cache_upload_kernel(cache
, key_data
, key_size
,
416 kernel_data
, kernel_size
,
417 prog_data
, prog_data_size
,
420 return anv_shader_bin_create(pipeline
->device
, key_data
, key_size
,
421 kernel_data
, kernel_size
,
422 prog_data
, prog_data_size
, bind_map
);
428 anv_pipeline_add_compiled_stage(struct anv_pipeline
*pipeline
,
429 gl_shader_stage stage
,
430 struct anv_shader_bin
*shader
)
432 pipeline
->shaders
[stage
] = shader
;
433 pipeline
->active_stages
|= mesa_to_vk_shader_stage(stage
);
437 anv_pipeline_compile_vs(struct anv_pipeline
*pipeline
,
438 struct anv_pipeline_cache
*cache
,
439 const VkGraphicsPipelineCreateInfo
*info
,
440 struct anv_shader_module
*module
,
441 const char *entrypoint
,
442 const VkSpecializationInfo
*spec_info
)
444 const struct brw_compiler
*compiler
=
445 pipeline
->device
->instance
->physicalDevice
.compiler
;
446 struct anv_pipeline_bind_map map
;
447 struct brw_vs_prog_key key
;
448 struct anv_shader_bin
*bin
= NULL
;
449 unsigned char sha1
[20];
451 populate_vs_prog_key(&pipeline
->device
->info
, &key
);
454 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
,
455 pipeline
->layout
, spec_info
);
456 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
460 struct brw_vs_prog_data prog_data
= { 0, };
461 struct anv_pipeline_binding surface_to_descriptor
[256];
462 struct anv_pipeline_binding sampler_to_descriptor
[256];
464 map
= (struct anv_pipeline_bind_map
) {
465 .surface_to_descriptor
= surface_to_descriptor
,
466 .sampler_to_descriptor
= sampler_to_descriptor
469 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
470 MESA_SHADER_VERTEX
, spec_info
,
471 &prog_data
.base
.base
, &map
);
473 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
475 anv_fill_binding_table(&prog_data
.base
.base
, 0);
477 void *mem_ctx
= ralloc_context(NULL
);
479 if (module
->nir
== NULL
)
480 ralloc_steal(mem_ctx
, nir
);
482 prog_data
.inputs_read
= nir
->info
.inputs_read
;
484 brw_compute_vue_map(&pipeline
->device
->info
,
485 &prog_data
.base
.vue_map
,
486 nir
->info
.outputs_written
,
487 nir
->info
.separate_shader
);
490 const unsigned *shader_code
=
491 brw_compile_vs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
492 NULL
, false, -1, &code_size
, NULL
);
493 if (shader_code
== NULL
) {
494 ralloc_free(mem_ctx
);
495 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
498 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
499 shader_code
, code_size
,
500 &prog_data
, sizeof(prog_data
), &map
);
502 ralloc_free(mem_ctx
);
503 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
506 ralloc_free(mem_ctx
);
509 const struct brw_vs_prog_data
*vs_prog_data
=
510 (const struct brw_vs_prog_data
*)anv_shader_bin_get_prog_data(bin
);
512 if (vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
) {
513 pipeline
->vs_simd8
= bin
->kernel
.offset
;
514 pipeline
->vs_vec4
= NO_KERNEL
;
516 pipeline
->vs_simd8
= NO_KERNEL
;
517 pipeline
->vs_vec4
= bin
->kernel
.offset
;
520 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_VERTEX
, bin
);
526 anv_pipeline_compile_gs(struct anv_pipeline
*pipeline
,
527 struct anv_pipeline_cache
*cache
,
528 const VkGraphicsPipelineCreateInfo
*info
,
529 struct anv_shader_module
*module
,
530 const char *entrypoint
,
531 const VkSpecializationInfo
*spec_info
)
533 const struct brw_compiler
*compiler
=
534 pipeline
->device
->instance
->physicalDevice
.compiler
;
535 struct anv_pipeline_bind_map map
;
536 struct brw_gs_prog_key key
;
537 struct anv_shader_bin
*bin
= NULL
;
538 unsigned char sha1
[20];
540 populate_gs_prog_key(&pipeline
->device
->info
, &key
);
543 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
,
544 pipeline
->layout
, spec_info
);
545 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
549 struct brw_gs_prog_data prog_data
= { 0, };
550 struct anv_pipeline_binding surface_to_descriptor
[256];
551 struct anv_pipeline_binding sampler_to_descriptor
[256];
553 map
= (struct anv_pipeline_bind_map
) {
554 .surface_to_descriptor
= surface_to_descriptor
,
555 .sampler_to_descriptor
= sampler_to_descriptor
558 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
559 MESA_SHADER_GEOMETRY
, spec_info
,
560 &prog_data
.base
.base
, &map
);
562 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
564 anv_fill_binding_table(&prog_data
.base
.base
, 0);
566 void *mem_ctx
= ralloc_context(NULL
);
568 if (module
->nir
== NULL
)
569 ralloc_steal(mem_ctx
, nir
);
571 brw_compute_vue_map(&pipeline
->device
->info
,
572 &prog_data
.base
.vue_map
,
573 nir
->info
.outputs_written
,
574 nir
->info
.separate_shader
);
577 const unsigned *shader_code
=
578 brw_compile_gs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
579 NULL
, -1, &code_size
, NULL
);
580 if (shader_code
== NULL
) {
581 ralloc_free(mem_ctx
);
582 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
586 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
587 shader_code
, code_size
,
588 &prog_data
, sizeof(prog_data
), &map
);
590 ralloc_free(mem_ctx
);
591 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
594 ralloc_free(mem_ctx
);
597 pipeline
->gs_kernel
= bin
->kernel
.offset
;
599 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_GEOMETRY
, bin
);
605 anv_pipeline_compile_fs(struct anv_pipeline
*pipeline
,
606 struct anv_pipeline_cache
*cache
,
607 const VkGraphicsPipelineCreateInfo
*info
,
608 const struct anv_graphics_pipeline_create_info
*extra
,
609 struct anv_shader_module
*module
,
610 const char *entrypoint
,
611 const VkSpecializationInfo
*spec_info
)
613 const struct brw_compiler
*compiler
=
614 pipeline
->device
->instance
->physicalDevice
.compiler
;
615 struct anv_pipeline_bind_map map
;
616 struct brw_wm_prog_key key
;
617 struct anv_shader_bin
*bin
= NULL
;
618 unsigned char sha1
[20];
620 populate_wm_prog_key(&pipeline
->device
->info
, info
, extra
, &key
);
623 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
,
624 pipeline
->layout
, spec_info
);
625 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
629 struct brw_wm_prog_data prog_data
= { 0, };
630 struct anv_pipeline_binding surface_to_descriptor
[256];
631 struct anv_pipeline_binding sampler_to_descriptor
[256];
633 map
= (struct anv_pipeline_bind_map
) {
634 .surface_to_descriptor
= surface_to_descriptor
+ 8,
635 .sampler_to_descriptor
= sampler_to_descriptor
638 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
639 MESA_SHADER_FRAGMENT
, spec_info
,
640 &prog_data
.base
, &map
);
642 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
644 unsigned num_rts
= 0;
645 struct anv_pipeline_binding rt_bindings
[8];
646 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
647 nir_foreach_variable_safe(var
, &nir
->outputs
) {
648 if (var
->data
.location
< FRAG_RESULT_DATA0
)
651 unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
652 if (rt
>= key
.nr_color_regions
) {
653 /* Out-of-bounds, throw it away */
654 var
->data
.mode
= nir_var_local
;
655 exec_node_remove(&var
->node
);
656 exec_list_push_tail(&impl
->locals
, &var
->node
);
660 /* Give it a new, compacted, location */
661 var
->data
.location
= FRAG_RESULT_DATA0
+ num_rts
;
664 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
665 assert(num_rts
+ array_len
<= 8);
667 for (unsigned i
= 0; i
< array_len
; i
++) {
668 rt_bindings
[num_rts
+ i
] = (struct anv_pipeline_binding
) {
669 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
675 num_rts
+= array_len
;
678 if (pipeline
->use_repclear
) {
679 assert(num_rts
== 1);
680 key
.nr_color_regions
= 1;
684 /* If we have no render targets, we need a null render target */
685 rt_bindings
[0] = (struct anv_pipeline_binding
) {
686 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
693 assert(num_rts
<= 8);
694 map
.surface_to_descriptor
-= num_rts
;
695 map
.surface_count
+= num_rts
;
696 assert(map
.surface_count
<= 256);
697 memcpy(map
.surface_to_descriptor
, rt_bindings
,
698 num_rts
* sizeof(*rt_bindings
));
700 anv_fill_binding_table(&prog_data
.base
, num_rts
);
702 void *mem_ctx
= ralloc_context(NULL
);
704 if (module
->nir
== NULL
)
705 ralloc_steal(mem_ctx
, nir
);
708 const unsigned *shader_code
=
709 brw_compile_fs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
710 NULL
, -1, -1, true, pipeline
->use_repclear
,
712 if (shader_code
== NULL
) {
713 ralloc_free(mem_ctx
);
714 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
717 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
718 shader_code
, code_size
,
719 &prog_data
, sizeof(prog_data
), &map
);
721 ralloc_free(mem_ctx
);
722 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
725 ralloc_free(mem_ctx
);
728 pipeline
->ps_ksp0
= bin
->kernel
.offset
;
730 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_FRAGMENT
, bin
);
736 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
737 struct anv_pipeline_cache
*cache
,
738 const VkComputePipelineCreateInfo
*info
,
739 struct anv_shader_module
*module
,
740 const char *entrypoint
,
741 const VkSpecializationInfo
*spec_info
)
743 const struct brw_compiler
*compiler
=
744 pipeline
->device
->instance
->physicalDevice
.compiler
;
745 struct anv_pipeline_bind_map map
;
746 struct brw_cs_prog_key key
;
747 struct anv_shader_bin
*bin
= NULL
;
748 unsigned char sha1
[20];
750 populate_cs_prog_key(&pipeline
->device
->info
, &key
);
753 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
,
754 pipeline
->layout
, spec_info
);
755 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
759 struct brw_cs_prog_data prog_data
= { 0, };
760 struct anv_pipeline_binding surface_to_descriptor
[256];
761 struct anv_pipeline_binding sampler_to_descriptor
[256];
763 map
= (struct anv_pipeline_bind_map
) {
764 .surface_to_descriptor
= surface_to_descriptor
,
765 .sampler_to_descriptor
= sampler_to_descriptor
768 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
769 MESA_SHADER_COMPUTE
, spec_info
,
770 &prog_data
.base
, &map
);
772 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
774 anv_fill_binding_table(&prog_data
.base
, 1);
776 void *mem_ctx
= ralloc_context(NULL
);
778 if (module
->nir
== NULL
)
779 ralloc_steal(mem_ctx
, nir
);
782 const unsigned *shader_code
=
783 brw_compile_cs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
784 -1, &code_size
, NULL
);
785 if (shader_code
== NULL
) {
786 ralloc_free(mem_ctx
);
787 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
790 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
791 shader_code
, code_size
,
792 &prog_data
, sizeof(prog_data
), &map
);
794 ralloc_free(mem_ctx
);
795 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
798 ralloc_free(mem_ctx
);
801 pipeline
->cs_simd
= bin
->kernel
.offset
;
803 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_COMPUTE
, bin
);
809 anv_compute_urb_partition(struct anv_pipeline
*pipeline
)
811 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
813 bool vs_present
= pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
;
814 unsigned vs_size
= vs_present
?
815 get_vs_prog_data(pipeline
)->base
.urb_entry_size
: 1;
816 unsigned vs_entry_size_bytes
= vs_size
* 64;
817 bool gs_present
= pipeline
->active_stages
& VK_SHADER_STAGE_GEOMETRY_BIT
;
818 unsigned gs_size
= gs_present
?
819 get_gs_prog_data(pipeline
)->base
.urb_entry_size
: 1;
820 unsigned gs_entry_size_bytes
= gs_size
* 64;
822 /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
824 * VS Number of URB Entries must be divisible by 8 if the VS URB Entry
825 * Allocation Size is less than 9 512-bit URB entries.
827 * Similar text exists for GS.
829 unsigned vs_granularity
= (vs_size
< 9) ? 8 : 1;
830 unsigned gs_granularity
= (gs_size
< 9) ? 8 : 1;
832 /* URB allocations must be done in 8k chunks. */
833 unsigned chunk_size_bytes
= 8192;
835 /* Determine the size of the URB in chunks. */
836 unsigned urb_chunks
= pipeline
->urb
.total_size
* 1024 / chunk_size_bytes
;
838 /* Reserve space for push constants */
839 unsigned push_constant_kb
;
840 if (pipeline
->device
->info
.gen
>= 8)
841 push_constant_kb
= 32;
842 else if (pipeline
->device
->info
.is_haswell
)
843 push_constant_kb
= pipeline
->device
->info
.gt
== 3 ? 32 : 16;
845 push_constant_kb
= 16;
847 unsigned push_constant_bytes
= push_constant_kb
* 1024;
848 unsigned push_constant_chunks
=
849 push_constant_bytes
/ chunk_size_bytes
;
851 /* Initially, assign each stage the minimum amount of URB space it needs,
852 * and make a note of how much additional space it "wants" (the amount of
853 * additional space it could actually make use of).
856 /* VS has a lower limit on the number of URB entries */
858 ALIGN(devinfo
->urb
.min_vs_entries
* vs_entry_size_bytes
,
859 chunk_size_bytes
) / chunk_size_bytes
;
861 ALIGN(devinfo
->urb
.max_vs_entries
* vs_entry_size_bytes
,
862 chunk_size_bytes
) / chunk_size_bytes
- vs_chunks
;
864 unsigned gs_chunks
= 0;
865 unsigned gs_wants
= 0;
867 /* There are two constraints on the minimum amount of URB space we can
870 * (1) We need room for at least 2 URB entries, since we always operate
871 * the GS in DUAL_OBJECT mode.
873 * (2) We can't allocate less than nr_gs_entries_granularity.
875 gs_chunks
= ALIGN(MAX2(gs_granularity
, 2) * gs_entry_size_bytes
,
876 chunk_size_bytes
) / chunk_size_bytes
;
878 ALIGN(devinfo
->urb
.max_gs_entries
* gs_entry_size_bytes
,
879 chunk_size_bytes
) / chunk_size_bytes
- gs_chunks
;
882 /* There should always be enough URB space to satisfy the minimum
883 * requirements of each stage.
885 unsigned total_needs
= push_constant_chunks
+ vs_chunks
+ gs_chunks
;
886 assert(total_needs
<= urb_chunks
);
888 /* Mete out remaining space (if any) in proportion to "wants". */
889 unsigned total_wants
= vs_wants
+ gs_wants
;
890 unsigned remaining_space
= urb_chunks
- total_needs
;
891 if (remaining_space
> total_wants
)
892 remaining_space
= total_wants
;
893 if (remaining_space
> 0) {
894 unsigned vs_additional
= (unsigned)
895 round(vs_wants
* (((double) remaining_space
) / total_wants
));
896 vs_chunks
+= vs_additional
;
897 remaining_space
-= vs_additional
;
898 gs_chunks
+= remaining_space
;
901 /* Sanity check that we haven't over-allocated. */
902 assert(push_constant_chunks
+ vs_chunks
+ gs_chunks
<= urb_chunks
);
904 /* Finally, compute the number of entries that can fit in the space
905 * allocated to each stage.
907 unsigned nr_vs_entries
= vs_chunks
* chunk_size_bytes
/ vs_entry_size_bytes
;
908 unsigned nr_gs_entries
= gs_chunks
* chunk_size_bytes
/ gs_entry_size_bytes
;
910 /* Since we rounded up when computing *_wants, this may be slightly more
911 * than the maximum allowed amount, so correct for that.
913 nr_vs_entries
= MIN2(nr_vs_entries
, devinfo
->urb
.max_vs_entries
);
914 nr_gs_entries
= MIN2(nr_gs_entries
, devinfo
->urb
.max_gs_entries
);
916 /* Ensure that we program a multiple of the granularity. */
917 nr_vs_entries
= ROUND_DOWN_TO(nr_vs_entries
, vs_granularity
);
918 nr_gs_entries
= ROUND_DOWN_TO(nr_gs_entries
, gs_granularity
);
920 /* Finally, sanity check to make sure we have at least the minimum number
921 * of entries needed for each stage.
923 assert(nr_vs_entries
>= devinfo
->urb
.min_vs_entries
);
925 assert(nr_gs_entries
>= 2);
927 /* Lay out the URB in the following order:
932 pipeline
->urb
.start
[MESA_SHADER_VERTEX
] = push_constant_chunks
;
933 pipeline
->urb
.size
[MESA_SHADER_VERTEX
] = vs_size
;
934 pipeline
->urb
.entries
[MESA_SHADER_VERTEX
] = nr_vs_entries
;
936 pipeline
->urb
.start
[MESA_SHADER_GEOMETRY
] = push_constant_chunks
+ vs_chunks
;
937 pipeline
->urb
.size
[MESA_SHADER_GEOMETRY
] = gs_size
;
938 pipeline
->urb
.entries
[MESA_SHADER_GEOMETRY
] = nr_gs_entries
;
940 pipeline
->urb
.start
[MESA_SHADER_TESS_CTRL
] = push_constant_chunks
;
941 pipeline
->urb
.size
[MESA_SHADER_TESS_CTRL
] = 1;
942 pipeline
->urb
.entries
[MESA_SHADER_TESS_CTRL
] = 0;
944 pipeline
->urb
.start
[MESA_SHADER_TESS_EVAL
] = push_constant_chunks
;
945 pipeline
->urb
.size
[MESA_SHADER_TESS_EVAL
] = 1;
946 pipeline
->urb
.entries
[MESA_SHADER_TESS_EVAL
] = 0;
950 * Copy pipeline state not marked as dynamic.
951 * Dynamic state is pipeline state which hasn't been provided at pipeline
952 * creation time, but is dynamically provided afterwards using various
953 * vkCmdSet* functions.
955 * The set of state considered "non_dynamic" is determined by the pieces of
956 * state that have their corresponding VkDynamicState enums omitted from
957 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
959 * @param[out] pipeline Destination non_dynamic state.
960 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
963 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
964 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
966 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
967 ANV_FROM_HANDLE(anv_render_pass
, pass
, pCreateInfo
->renderPass
);
968 struct anv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
970 pipeline
->dynamic_state
= default_dynamic_state
;
972 if (pCreateInfo
->pDynamicState
) {
973 /* Remove all of the states that are marked as dynamic */
974 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
975 for (uint32_t s
= 0; s
< count
; s
++)
976 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
979 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
981 /* Section 9.2 of the Vulkan 1.0.15 spec says:
983 * pViewportState is [...] NULL if the pipeline
984 * has rasterization disabled.
986 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
987 assert(pCreateInfo
->pViewportState
);
989 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
990 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
991 typed_memcpy(dynamic
->viewport
.viewports
,
992 pCreateInfo
->pViewportState
->pViewports
,
993 pCreateInfo
->pViewportState
->viewportCount
);
996 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
997 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
998 typed_memcpy(dynamic
->scissor
.scissors
,
999 pCreateInfo
->pViewportState
->pScissors
,
1000 pCreateInfo
->pViewportState
->scissorCount
);
1004 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1005 assert(pCreateInfo
->pRasterizationState
);
1006 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1009 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1010 assert(pCreateInfo
->pRasterizationState
);
1011 dynamic
->depth_bias
.bias
=
1012 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1013 dynamic
->depth_bias
.clamp
=
1014 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1015 dynamic
->depth_bias
.slope
=
1016 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1019 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1021 * pColorBlendState is [...] NULL if the pipeline has rasterization
1022 * disabled or if the subpass of the render pass the pipeline is
1023 * created against does not use any color attachments.
1025 bool uses_color_att
= false;
1026 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1027 if (subpass
->color_attachments
[i
] != VK_ATTACHMENT_UNUSED
) {
1028 uses_color_att
= true;
1033 if (uses_color_att
&&
1034 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1035 assert(pCreateInfo
->pColorBlendState
);
1037 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
1038 typed_memcpy(dynamic
->blend_constants
,
1039 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1042 /* If there is no depthstencil attachment, then don't read
1043 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1044 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1045 * no need to override the depthstencil defaults in
1046 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1048 * Section 9.2 of the Vulkan 1.0.15 spec says:
1050 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1051 * disabled or if the subpass of the render pass the pipeline is created
1052 * against does not use a depth/stencil attachment.
1054 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1055 subpass
->depth_stencil_attachment
!= VK_ATTACHMENT_UNUSED
) {
1056 assert(pCreateInfo
->pDepthStencilState
);
1058 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1059 dynamic
->depth_bounds
.min
=
1060 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1061 dynamic
->depth_bounds
.max
=
1062 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1065 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1066 dynamic
->stencil_compare_mask
.front
=
1067 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1068 dynamic
->stencil_compare_mask
.back
=
1069 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1072 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1073 dynamic
->stencil_write_mask
.front
=
1074 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1075 dynamic
->stencil_write_mask
.back
=
1076 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1079 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1080 dynamic
->stencil_reference
.front
=
1081 pCreateInfo
->pDepthStencilState
->front
.reference
;
1082 dynamic
->stencil_reference
.back
=
1083 pCreateInfo
->pDepthStencilState
->back
.reference
;
1087 pipeline
->dynamic_state_mask
= states
;
1091 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1093 struct anv_render_pass
*renderpass
= NULL
;
1094 struct anv_subpass
*subpass
= NULL
;
1096 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1097 * present, as explained by the Vulkan (20 Oct 2015, git-aa308cb), Section
1098 * 4.2 Graphics Pipeline.
1100 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1102 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1105 if (renderpass
!= &anv_meta_dummy_renderpass
) {
1106 assert(info
->subpass
< renderpass
->subpass_count
);
1107 subpass
= &renderpass
->subpasses
[info
->subpass
];
1110 assert(info
->stageCount
>= 1);
1111 assert(info
->pVertexInputState
);
1112 assert(info
->pInputAssemblyState
);
1113 assert(info
->pViewportState
);
1114 assert(info
->pRasterizationState
);
1116 if (subpass
&& subpass
->depth_stencil_attachment
!= VK_ATTACHMENT_UNUSED
)
1117 assert(info
->pDepthStencilState
);
1119 if (subpass
&& subpass
->color_count
> 0)
1120 assert(info
->pColorBlendState
);
1122 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1123 switch (info
->pStages
[i
].stage
) {
1124 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1125 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1126 assert(info
->pTessellationState
);
1135 * Calculate the desired L3 partitioning based on the current state of the
1136 * pipeline. For now this simply returns the conservative defaults calculated
1137 * by get_default_l3_weights(), but we could probably do better by gathering
1138 * more statistics from the pipeline state (e.g. guess of expected URB usage
1139 * and bound surfaces), or by using feed-back from performance counters.
1142 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1144 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1146 const struct gen_l3_weights w
=
1147 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
1149 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
1150 pipeline
->urb
.total_size
=
1151 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
1155 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1156 struct anv_device
*device
,
1157 struct anv_pipeline_cache
*cache
,
1158 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1159 const struct anv_graphics_pipeline_create_info
*extra
,
1160 const VkAllocationCallbacks
*alloc
)
1165 anv_pipeline_validate_create_info(pCreateInfo
);
1169 alloc
= &device
->alloc
;
1171 pipeline
->device
= device
;
1172 pipeline
->layout
= anv_pipeline_layout_from_handle(pCreateInfo
->layout
);
1174 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1175 if (result
!= VK_SUCCESS
)
1178 pipeline
->batch
.alloc
= alloc
;
1179 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1180 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1181 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1183 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1184 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1185 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1187 pipeline
->use_repclear
= extra
&& extra
->use_repclear
;
1189 pipeline
->needs_data_cache
= false;
1191 /* When we free the pipeline, we detect stages based on the NULL status
1192 * of various prog_data pointers. Make them NULL by default.
1194 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1196 pipeline
->vs_simd8
= NO_KERNEL
;
1197 pipeline
->vs_vec4
= NO_KERNEL
;
1198 pipeline
->gs_kernel
= NO_KERNEL
;
1199 pipeline
->ps_ksp0
= NO_KERNEL
;
1201 pipeline
->active_stages
= 0;
1203 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
1204 struct anv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
1205 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
1206 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
1207 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
1208 modules
[stage
] = anv_shader_module_from_handle(pStages
[stage
]->module
);
1211 if (modules
[MESA_SHADER_VERTEX
]) {
1212 result
= anv_pipeline_compile_vs(pipeline
, cache
, pCreateInfo
,
1213 modules
[MESA_SHADER_VERTEX
],
1214 pStages
[MESA_SHADER_VERTEX
]->pName
,
1215 pStages
[MESA_SHADER_VERTEX
]->pSpecializationInfo
);
1216 if (result
!= VK_SUCCESS
)
1220 if (modules
[MESA_SHADER_TESS_CTRL
] || modules
[MESA_SHADER_TESS_EVAL
])
1221 anv_finishme("no tessellation support");
1223 if (modules
[MESA_SHADER_GEOMETRY
]) {
1224 result
= anv_pipeline_compile_gs(pipeline
, cache
, pCreateInfo
,
1225 modules
[MESA_SHADER_GEOMETRY
],
1226 pStages
[MESA_SHADER_GEOMETRY
]->pName
,
1227 pStages
[MESA_SHADER_GEOMETRY
]->pSpecializationInfo
);
1228 if (result
!= VK_SUCCESS
)
1232 if (modules
[MESA_SHADER_FRAGMENT
]) {
1233 result
= anv_pipeline_compile_fs(pipeline
, cache
, pCreateInfo
, extra
,
1234 modules
[MESA_SHADER_FRAGMENT
],
1235 pStages
[MESA_SHADER_FRAGMENT
]->pName
,
1236 pStages
[MESA_SHADER_FRAGMENT
]->pSpecializationInfo
);
1237 if (result
!= VK_SUCCESS
)
1241 if (!(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
)) {
1242 /* Vertex is only optional if disable_vs is set */
1243 assert(extra
->disable_vs
);
1246 anv_pipeline_setup_l3_config(pipeline
, false);
1247 anv_compute_urb_partition(pipeline
);
1249 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1250 pCreateInfo
->pVertexInputState
;
1252 uint64_t inputs_read
;
1253 if (extra
&& extra
->disable_vs
) {
1254 /* If the VS is disabled, just assume the user knows what they're
1255 * doing and apply the layout blindly. This can only come from
1256 * meta, so this *should* be safe.
1258 inputs_read
= ~0ull;
1260 inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1263 pipeline
->vb_used
= 0;
1264 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1265 const VkVertexInputAttributeDescription
*desc
=
1266 &vi_info
->pVertexAttributeDescriptions
[i
];
1268 if (inputs_read
& (1 << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1269 pipeline
->vb_used
|= 1 << desc
->binding
;
1272 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1273 const VkVertexInputBindingDescription
*desc
=
1274 &vi_info
->pVertexBindingDescriptions
[i
];
1276 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
1278 /* Step rate is programmed per vertex element (attribute), not
1279 * binding. Set up a map of which bindings step per instance, for
1280 * reference by vertex element setup. */
1281 switch (desc
->inputRate
) {
1283 case VK_VERTEX_INPUT_RATE_VERTEX
:
1284 pipeline
->instancing_enable
[desc
->binding
] = false;
1286 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1287 pipeline
->instancing_enable
[desc
->binding
] = true;
1292 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1293 pCreateInfo
->pInputAssemblyState
;
1294 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1295 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];
1297 if (extra
&& extra
->use_rectlist
)
1298 pipeline
->topology
= _3DPRIM_RECTLIST
;
1303 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1304 if (pipeline
->shaders
[s
])
1305 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
1308 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);
1314 anv_graphics_pipeline_create(
1316 VkPipelineCache _cache
,
1317 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1318 const struct anv_graphics_pipeline_create_info
*extra
,
1319 const VkAllocationCallbacks
*pAllocator
,
1320 VkPipeline
*pPipeline
)
1322 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1323 ANV_FROM_HANDLE(anv_pipeline_cache
, cache
, _cache
);
1325 switch (device
->info
.gen
) {
1327 if (device
->info
.is_haswell
)
1328 return gen75_graphics_pipeline_create(_device
, cache
, pCreateInfo
, extra
, pAllocator
, pPipeline
);
1330 return gen7_graphics_pipeline_create(_device
, cache
, pCreateInfo
, extra
, pAllocator
, pPipeline
);
1332 return gen8_graphics_pipeline_create(_device
, cache
, pCreateInfo
, extra
, pAllocator
, pPipeline
);
1334 return gen9_graphics_pipeline_create(_device
, cache
, pCreateInfo
, extra
, pAllocator
, pPipeline
);
1336 unreachable("unsupported gen\n");
1340 VkResult
anv_CreateGraphicsPipelines(
1342 VkPipelineCache pipelineCache
,
1344 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
1345 const VkAllocationCallbacks
* pAllocator
,
1346 VkPipeline
* pPipelines
)
1348 VkResult result
= VK_SUCCESS
;
1351 for (; i
< count
; i
++) {
1352 result
= anv_graphics_pipeline_create(_device
,
1355 NULL
, pAllocator
, &pPipelines
[i
]);
1356 if (result
!= VK_SUCCESS
) {
1357 for (unsigned j
= 0; j
< i
; j
++) {
1358 anv_DestroyPipeline(_device
, pPipelines
[j
], pAllocator
);
1368 static VkResult
anv_compute_pipeline_create(
1370 VkPipelineCache _cache
,
1371 const VkComputePipelineCreateInfo
* pCreateInfo
,
1372 const VkAllocationCallbacks
* pAllocator
,
1373 VkPipeline
* pPipeline
)
1375 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1376 ANV_FROM_HANDLE(anv_pipeline_cache
, cache
, _cache
);
1378 switch (device
->info
.gen
) {
1380 if (device
->info
.is_haswell
)
1381 return gen75_compute_pipeline_create(_device
, cache
, pCreateInfo
, pAllocator
, pPipeline
);
1383 return gen7_compute_pipeline_create(_device
, cache
, pCreateInfo
, pAllocator
, pPipeline
);
1385 return gen8_compute_pipeline_create(_device
, cache
, pCreateInfo
, pAllocator
, pPipeline
);
1387 return gen9_compute_pipeline_create(_device
, cache
, pCreateInfo
, pAllocator
, pPipeline
);
1389 unreachable("unsupported gen\n");
1393 VkResult
anv_CreateComputePipelines(
1395 VkPipelineCache pipelineCache
,
1397 const VkComputePipelineCreateInfo
* pCreateInfos
,
1398 const VkAllocationCallbacks
* pAllocator
,
1399 VkPipeline
* pPipelines
)
1401 VkResult result
= VK_SUCCESS
;
1404 for (; i
< count
; i
++) {
1405 result
= anv_compute_pipeline_create(_device
, pipelineCache
,
1407 pAllocator
, &pPipelines
[i
]);
1408 if (result
!= VK_SUCCESS
) {
1409 for (unsigned j
= 0; j
< i
; j
++) {
1410 anv_DestroyPipeline(_device
, pPipelines
[j
], pAllocator
);