2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "util/os_time.h"
32 #include "common/gen_l3_config.h"
33 #include "common/gen_disasm.h"
34 #include "anv_private.h"
35 #include "compiler/brw_nir.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
41 /* Needed for SWIZZLE macros */
42 #include "program/prog_instruction.h"
46 VkResult
anv_CreateShaderModule(
48 const VkShaderModuleCreateInfo
* pCreateInfo
,
49 const VkAllocationCallbacks
* pAllocator
,
50 VkShaderModule
* pShaderModule
)
52 ANV_FROM_HANDLE(anv_device
, device
, _device
);
53 struct anv_shader_module
*module
;
55 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
56 assert(pCreateInfo
->flags
== 0);
58 module
= vk_alloc2(&device
->alloc
, pAllocator
,
59 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
60 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
62 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
64 module
->size
= pCreateInfo
->codeSize
;
65 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
67 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
69 *pShaderModule
= anv_shader_module_to_handle(module
);
74 void anv_DestroyShaderModule(
76 VkShaderModule _module
,
77 const VkAllocationCallbacks
* pAllocator
)
79 ANV_FROM_HANDLE(anv_device
, device
, _device
);
80 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
85 vk_free2(&device
->alloc
, pAllocator
, module
);
88 #define SPIR_V_MAGIC_NUMBER 0x07230203
90 struct anv_spirv_debug_data
{
91 struct anv_device
*device
;
92 const struct anv_shader_module
*module
;
95 static void anv_spirv_nir_debug(void *private_data
,
96 enum nir_spirv_debug_level level
,
100 struct anv_spirv_debug_data
*debug_data
= private_data
;
101 struct anv_instance
*instance
= debug_data
->device
->physical
->instance
;
103 static const VkDebugReportFlagsEXT vk_flags
[] = {
104 [NIR_SPIRV_DEBUG_LEVEL_INFO
] = VK_DEBUG_REPORT_INFORMATION_BIT_EXT
,
105 [NIR_SPIRV_DEBUG_LEVEL_WARNING
] = VK_DEBUG_REPORT_WARNING_BIT_EXT
,
106 [NIR_SPIRV_DEBUG_LEVEL_ERROR
] = VK_DEBUG_REPORT_ERROR_BIT_EXT
,
110 snprintf(buffer
, sizeof(buffer
), "SPIR-V offset %lu: %s", (unsigned long) spirv_offset
, message
);
112 vk_debug_report(&instance
->debug_report_callbacks
,
114 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT
,
115 (uint64_t) (uintptr_t) debug_data
->module
,
116 0, 0, "anv", buffer
);
119 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
120 * we can't do that yet because we don't have the ability to copy nir.
123 anv_shader_compile_to_nir(struct anv_device
*device
,
125 const struct anv_shader_module
*module
,
126 const char *entrypoint_name
,
127 gl_shader_stage stage
,
128 const VkSpecializationInfo
*spec_info
)
130 const struct anv_physical_device
*pdevice
= device
->physical
;
131 const struct brw_compiler
*compiler
= pdevice
->compiler
;
132 const nir_shader_compiler_options
*nir_options
=
133 compiler
->glsl_compiler_options
[stage
].NirOptions
;
135 uint32_t *spirv
= (uint32_t *) module
->data
;
136 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
137 assert(module
->size
% 4 == 0);
139 uint32_t num_spec_entries
= 0;
140 struct nir_spirv_specialization
*spec_entries
= NULL
;
141 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
142 num_spec_entries
= spec_info
->mapEntryCount
;
143 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
144 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
145 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
146 const void *data
= spec_info
->pData
+ entry
.offset
;
147 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
149 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
150 if (spec_info
->dataSize
== 8)
151 spec_entries
[i
].data64
= *(const uint64_t *)data
;
153 spec_entries
[i
].data32
= *(const uint32_t *)data
;
157 struct anv_spirv_debug_data spirv_debug_data
= {
161 struct spirv_to_nir_options spirv_options
= {
162 .frag_coord_is_sysval
= true,
164 .demote_to_helper_invocation
= true,
165 .derivative_group
= true,
166 .descriptor_array_dynamic_indexing
= true,
167 .descriptor_array_non_uniform_indexing
= true,
168 .descriptor_indexing
= true,
169 .device_group
= true,
170 .draw_parameters
= true,
171 .float16
= pdevice
->info
.gen
>= 8,
172 .float64
= pdevice
->info
.gen
>= 8,
173 .fragment_shader_sample_interlock
= pdevice
->info
.gen
>= 9,
174 .fragment_shader_pixel_interlock
= pdevice
->info
.gen
>= 9,
175 .geometry_streams
= true,
176 .image_write_without_format
= true,
177 .int8
= pdevice
->info
.gen
>= 8,
178 .int16
= pdevice
->info
.gen
>= 8,
179 .int64
= pdevice
->info
.gen
>= 8,
180 .int64_atomics
= pdevice
->info
.gen
>= 9 && pdevice
->use_softpin
,
181 .integer_functions2
= pdevice
->info
.gen
>= 8,
184 .physical_storage_buffer_address
= pdevice
->has_a64_buffer_access
,
185 .post_depth_coverage
= pdevice
->info
.gen
>= 9,
186 .runtime_descriptor_array
= true,
187 .float_controls
= pdevice
->info
.gen
>= 8,
188 .shader_clock
= true,
189 .shader_viewport_index_layer
= true,
190 .stencil_export
= pdevice
->info
.gen
>= 9,
191 .storage_8bit
= pdevice
->info
.gen
>= 8,
192 .storage_16bit
= pdevice
->info
.gen
>= 8,
193 .subgroup_arithmetic
= true,
194 .subgroup_basic
= true,
195 .subgroup_ballot
= true,
196 .subgroup_quad
= true,
197 .subgroup_shuffle
= true,
198 .subgroup_vote
= true,
199 .tessellation
= true,
200 .transform_feedback
= pdevice
->info
.gen
>= 8,
201 .variable_pointers
= true,
202 .vk_memory_model
= true,
203 .vk_memory_model_device_scope
= true,
205 .ubo_addr_format
= nir_address_format_32bit_index_offset
,
207 anv_nir_ssbo_addr_format(pdevice
, device
->robust_buffer_access
),
208 .phys_ssbo_addr_format
= nir_address_format_64bit_global
,
209 .push_const_addr_format
= nir_address_format_logical
,
211 /* TODO: Consider changing this to an address format that has the NULL
212 * pointer equals to 0. That might be a better format to play nice
213 * with certain code / code generators.
215 .shared_addr_format
= nir_address_format_32bit_offset
,
217 .func
= anv_spirv_nir_debug
,
218 .private_data
= &spirv_debug_data
,
224 spirv_to_nir(spirv
, module
->size
/ 4,
225 spec_entries
, num_spec_entries
,
226 stage
, entrypoint_name
, &spirv_options
, nir_options
);
227 assert(nir
->info
.stage
== stage
);
228 nir_validate_shader(nir
, "after spirv_to_nir");
229 ralloc_steal(mem_ctx
, nir
);
233 if (unlikely(INTEL_DEBUG
& intel_debug_flag_for_shader_stage(stage
))) {
234 fprintf(stderr
, "NIR (from SPIR-V) for %s shader:\n",
235 gl_shader_stage_name(stage
));
236 nir_print_shader(nir
, stderr
);
239 /* We have to lower away local constant initializers right before we
240 * inline functions. That way they get properly initialized at the top
241 * of the function and not at the top of its caller.
243 NIR_PASS_V(nir
, nir_lower_variable_initializers
, nir_var_function_temp
);
244 NIR_PASS_V(nir
, nir_lower_returns
);
245 NIR_PASS_V(nir
, nir_inline_functions
);
246 NIR_PASS_V(nir
, nir_opt_deref
);
248 /* Pick off the single entrypoint that we want */
249 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
250 if (!func
->is_entrypoint
)
251 exec_node_remove(&func
->node
);
253 assert(exec_list_length(&nir
->functions
) == 1);
255 /* Now that we've deleted all but the main function, we can go ahead and
256 * lower the rest of the constant initializers. We do this here so that
257 * nir_remove_dead_variables and split_per_member_structs below see the
258 * corresponding stores.
260 NIR_PASS_V(nir
, nir_lower_variable_initializers
, ~0);
262 /* Split member structs. We do this before lower_io_to_temporaries so that
263 * it doesn't lower system values to temporaries by accident.
265 NIR_PASS_V(nir
, nir_split_var_copies
);
266 NIR_PASS_V(nir
, nir_split_per_member_structs
);
268 NIR_PASS_V(nir
, nir_remove_dead_variables
,
269 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
271 NIR_PASS_V(nir
, nir_propagate_invariant
);
272 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
273 nir_shader_get_entrypoint(nir
), true, false);
275 NIR_PASS_V(nir
, nir_lower_frexp
);
277 /* Vulkan uses the separate-shader linking model */
278 nir
->info
.separate_shader
= true;
280 brw_preprocess_nir(compiler
, nir
, NULL
);
285 void anv_DestroyPipeline(
287 VkPipeline _pipeline
,
288 const VkAllocationCallbacks
* pAllocator
)
290 ANV_FROM_HANDLE(anv_device
, device
, _device
);
291 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
296 anv_reloc_list_finish(&pipeline
->batch_relocs
,
297 pAllocator
? pAllocator
: &device
->alloc
);
299 ralloc_free(pipeline
->mem_ctx
);
301 if (pipeline
->blend_state
.map
)
302 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
304 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
305 if (pipeline
->shaders
[s
])
306 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
309 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
312 static const uint32_t vk_to_gen_primitive_type
[] = {
313 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
314 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
315 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
316 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
317 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
318 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
319 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
320 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
321 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
322 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
326 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
327 struct brw_sampler_prog_key_data
*key
)
329 /* Almost all multisampled textures are compressed. The only time when we
330 * don't compress a multisampled texture is for 16x MSAA with a surface
331 * width greater than 8k which is a bit of an edge case. Since the sampler
332 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
333 * to tell the compiler to always assume compression.
335 key
->compressed_multisample_layout_mask
= ~0;
337 /* SkyLake added support for 16x MSAA. With this came a new message for
338 * reading from a 16x MSAA surface with compression. The new message was
339 * needed because now the MCS data is 64 bits instead of 32 or lower as is
340 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
341 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
342 * so we can just use it unconditionally. This may not be quite as
343 * efficient but it saves us from recompiling.
345 if (devinfo
->gen
>= 9)
348 /* XXX: Handle texture swizzle on HSW- */
349 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
350 /* Assume color sampler, no swizzling. (Works for BDW+) */
351 key
->swizzles
[i
] = SWIZZLE_XYZW
;
356 populate_base_prog_key(const struct gen_device_info
*devinfo
,
357 VkPipelineShaderStageCreateFlags flags
,
358 struct brw_base_prog_key
*key
)
360 if (flags
& VK_PIPELINE_SHADER_STAGE_CREATE_ALLOW_VARYING_SUBGROUP_SIZE_BIT_EXT
)
361 key
->subgroup_size_type
= BRW_SUBGROUP_SIZE_VARYING
;
363 key
->subgroup_size_type
= BRW_SUBGROUP_SIZE_API_CONSTANT
;
365 populate_sampler_prog_key(devinfo
, &key
->tex
);
369 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
370 VkPipelineShaderStageCreateFlags flags
,
371 struct brw_vs_prog_key
*key
)
373 memset(key
, 0, sizeof(*key
));
375 populate_base_prog_key(devinfo
, flags
, &key
->base
);
377 /* XXX: Handle vertex input work-arounds */
379 /* XXX: Handle sampler_prog_key */
383 populate_tcs_prog_key(const struct gen_device_info
*devinfo
,
384 VkPipelineShaderStageCreateFlags flags
,
385 unsigned input_vertices
,
386 struct brw_tcs_prog_key
*key
)
388 memset(key
, 0, sizeof(*key
));
390 populate_base_prog_key(devinfo
, flags
, &key
->base
);
392 key
->input_vertices
= input_vertices
;
396 populate_tes_prog_key(const struct gen_device_info
*devinfo
,
397 VkPipelineShaderStageCreateFlags flags
,
398 struct brw_tes_prog_key
*key
)
400 memset(key
, 0, sizeof(*key
));
402 populate_base_prog_key(devinfo
, flags
, &key
->base
);
406 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
407 VkPipelineShaderStageCreateFlags flags
,
408 struct brw_gs_prog_key
*key
)
410 memset(key
, 0, sizeof(*key
));
412 populate_base_prog_key(devinfo
, flags
, &key
->base
);
416 populate_wm_prog_key(const struct gen_device_info
*devinfo
,
417 VkPipelineShaderStageCreateFlags flags
,
418 const struct anv_subpass
*subpass
,
419 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
420 struct brw_wm_prog_key
*key
)
422 memset(key
, 0, sizeof(*key
));
424 populate_base_prog_key(devinfo
, flags
, &key
->base
);
426 /* We set this to 0 here and set to the actual value before we call
429 key
->input_slots_valid
= 0;
431 /* Vulkan doesn't specify a default */
432 key
->high_quality_derivatives
= false;
434 /* XXX Vulkan doesn't appear to specify */
435 key
->clamp_fragment_color
= false;
437 assert(subpass
->color_count
<= MAX_RTS
);
438 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
439 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
440 key
->color_outputs_valid
|= (1 << i
);
443 key
->nr_color_regions
= subpass
->color_count
;
445 /* To reduce possible shader recompilations we would need to know if
446 * there is a SampleMask output variable to compute if we should emit
447 * code to workaround the issue that hardware disables alpha to coverage
448 * when there is SampleMask output.
450 key
->alpha_to_coverage
= ms_info
&& ms_info
->alphaToCoverageEnable
;
452 /* Vulkan doesn't support fixed-function alpha test */
453 key
->alpha_test_replicate_alpha
= false;
456 /* We should probably pull this out of the shader, but it's fairly
457 * harmless to compute it and then let dead-code take care of it.
459 if (ms_info
->rasterizationSamples
> 1) {
460 key
->persample_interp
= ms_info
->sampleShadingEnable
&&
461 (ms_info
->minSampleShading
* ms_info
->rasterizationSamples
) > 1;
462 key
->multisample_fbo
= true;
465 key
->frag_coord_adds_sample_pos
= key
->persample_interp
;
470 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
471 VkPipelineShaderStageCreateFlags flags
,
472 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*rss_info
,
473 struct brw_cs_prog_key
*key
)
475 memset(key
, 0, sizeof(*key
));
477 populate_base_prog_key(devinfo
, flags
, &key
->base
);
480 assert(key
->base
.subgroup_size_type
!= BRW_SUBGROUP_SIZE_VARYING
);
482 /* These enum values are expressly chosen to be equal to the subgroup
483 * size that they require.
485 assert(rss_info
->requiredSubgroupSize
== 8 ||
486 rss_info
->requiredSubgroupSize
== 16 ||
487 rss_info
->requiredSubgroupSize
== 32);
488 key
->base
.subgroup_size_type
= rss_info
->requiredSubgroupSize
;
489 } else if (flags
& VK_PIPELINE_SHADER_STAGE_CREATE_REQUIRE_FULL_SUBGROUPS_BIT_EXT
) {
490 /* If the client expressly requests full subgroups and they don't
491 * specify a subgroup size, we need to pick one. If they're requested
492 * varying subgroup sizes, we set it to UNIFORM and let the back-end
493 * compiler pick. Otherwise, we specify the API value of 32.
494 * Performance will likely be terrible in this case but there's nothing
495 * we can do about that. The client should have chosen a size.
497 if (flags
& VK_PIPELINE_SHADER_STAGE_CREATE_ALLOW_VARYING_SUBGROUP_SIZE_BIT_EXT
)
498 key
->base
.subgroup_size_type
= BRW_SUBGROUP_SIZE_UNIFORM
;
500 key
->base
.subgroup_size_type
= BRW_SUBGROUP_SIZE_REQUIRE_32
;
504 struct anv_pipeline_stage
{
505 gl_shader_stage stage
;
507 const struct anv_shader_module
*module
;
508 const char *entrypoint
;
509 const VkSpecializationInfo
*spec_info
;
511 unsigned char shader_sha1
[20];
513 union brw_any_prog_key key
;
516 gl_shader_stage stage
;
517 unsigned char sha1
[20];
522 struct anv_pipeline_binding surface_to_descriptor
[256];
523 struct anv_pipeline_binding sampler_to_descriptor
[256];
524 struct anv_pipeline_bind_map bind_map
;
526 union brw_any_prog_data prog_data
;
529 struct brw_compile_stats stats
[3];
532 VkPipelineCreationFeedbackEXT feedback
;
534 const unsigned *code
;
538 anv_pipeline_hash_shader(const struct anv_shader_module
*module
,
539 const char *entrypoint
,
540 gl_shader_stage stage
,
541 const VkSpecializationInfo
*spec_info
,
542 unsigned char *sha1_out
)
544 struct mesa_sha1 ctx
;
545 _mesa_sha1_init(&ctx
);
547 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
548 _mesa_sha1_update(&ctx
, entrypoint
, strlen(entrypoint
));
549 _mesa_sha1_update(&ctx
, &stage
, sizeof(stage
));
551 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
552 spec_info
->mapEntryCount
*
553 sizeof(*spec_info
->pMapEntries
));
554 _mesa_sha1_update(&ctx
, spec_info
->pData
,
555 spec_info
->dataSize
);
558 _mesa_sha1_final(&ctx
, sha1_out
);
562 anv_pipeline_hash_graphics(struct anv_pipeline
*pipeline
,
563 struct anv_pipeline_layout
*layout
,
564 struct anv_pipeline_stage
*stages
,
565 unsigned char *sha1_out
)
567 struct mesa_sha1 ctx
;
568 _mesa_sha1_init(&ctx
);
570 _mesa_sha1_update(&ctx
, &pipeline
->subpass
->view_mask
,
571 sizeof(pipeline
->subpass
->view_mask
));
574 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
576 const bool rba
= pipeline
->device
->robust_buffer_access
;
577 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
579 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
580 if (stages
[s
].entrypoint
) {
581 _mesa_sha1_update(&ctx
, stages
[s
].shader_sha1
,
582 sizeof(stages
[s
].shader_sha1
));
583 _mesa_sha1_update(&ctx
, &stages
[s
].key
, brw_prog_key_size(s
));
587 _mesa_sha1_final(&ctx
, sha1_out
);
591 anv_pipeline_hash_compute(struct anv_pipeline
*pipeline
,
592 struct anv_pipeline_layout
*layout
,
593 struct anv_pipeline_stage
*stage
,
594 unsigned char *sha1_out
)
596 struct mesa_sha1 ctx
;
597 _mesa_sha1_init(&ctx
);
600 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
602 const bool rba
= pipeline
->device
->robust_buffer_access
;
603 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
605 _mesa_sha1_update(&ctx
, stage
->shader_sha1
,
606 sizeof(stage
->shader_sha1
));
607 _mesa_sha1_update(&ctx
, &stage
->key
.cs
, sizeof(stage
->key
.cs
));
609 _mesa_sha1_final(&ctx
, sha1_out
);
613 anv_pipeline_stage_get_nir(struct anv_pipeline
*pipeline
,
614 struct anv_pipeline_cache
*cache
,
616 struct anv_pipeline_stage
*stage
)
618 const struct brw_compiler
*compiler
=
619 pipeline
->device
->physical
->compiler
;
620 const nir_shader_compiler_options
*nir_options
=
621 compiler
->glsl_compiler_options
[stage
->stage
].NirOptions
;
624 nir
= anv_device_search_for_nir(pipeline
->device
, cache
,
629 assert(nir
->info
.stage
== stage
->stage
);
633 nir
= anv_shader_compile_to_nir(pipeline
->device
,
640 anv_device_upload_nir(pipeline
->device
, cache
, nir
, stage
->shader_sha1
);
648 anv_pipeline_lower_nir(struct anv_pipeline
*pipeline
,
650 struct anv_pipeline_stage
*stage
,
651 struct anv_pipeline_layout
*layout
)
653 const struct anv_physical_device
*pdevice
= pipeline
->device
->physical
;
654 const struct brw_compiler
*compiler
= pdevice
->compiler
;
656 struct brw_stage_prog_data
*prog_data
= &stage
->prog_data
.base
;
657 nir_shader
*nir
= stage
->nir
;
659 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
660 NIR_PASS_V(nir
, nir_lower_wpos_center
, pipeline
->sample_shading_enable
);
661 NIR_PASS_V(nir
, nir_lower_input_attachments
, true);
664 NIR_PASS_V(nir
, anv_nir_lower_ycbcr_textures
, layout
);
666 if (pipeline
->type
== ANV_PIPELINE_GRAPHICS
)
667 NIR_PASS_V(nir
, anv_nir_lower_multiview
, pipeline
->subpass
->view_mask
);
669 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
671 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, compiler
->devinfo
);
673 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_global
,
674 nir_address_format_64bit_global
);
676 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
677 anv_nir_apply_pipeline_layout(pdevice
,
678 pipeline
->device
->robust_buffer_access
,
679 layout
, nir
, &stage
->bind_map
);
681 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ubo
,
682 nir_address_format_32bit_index_offset
);
683 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ssbo
,
684 anv_nir_ssbo_addr_format(pdevice
,
685 pipeline
->device
->robust_buffer_access
));
687 NIR_PASS_V(nir
, nir_opt_constant_folding
);
689 /* We don't support non-uniform UBOs and non-uniform SSBO access is
690 * handled naturally by falling back to A64 messages.
692 NIR_PASS_V(nir
, nir_lower_non_uniform_access
,
693 nir_lower_non_uniform_texture_access
|
694 nir_lower_non_uniform_image_access
);
696 anv_nir_compute_push_layout(pdevice
, pipeline
->device
->robust_buffer_access
,
697 nir
, prog_data
, &stage
->bind_map
, mem_ctx
);
703 anv_pipeline_link_vs(const struct brw_compiler
*compiler
,
704 struct anv_pipeline_stage
*vs_stage
,
705 struct anv_pipeline_stage
*next_stage
)
708 brw_nir_link_shaders(compiler
, vs_stage
->nir
, next_stage
->nir
);
712 anv_pipeline_compile_vs(const struct brw_compiler
*compiler
,
714 struct anv_device
*device
,
715 struct anv_pipeline_stage
*vs_stage
)
717 brw_compute_vue_map(compiler
->devinfo
,
718 &vs_stage
->prog_data
.vs
.base
.vue_map
,
719 vs_stage
->nir
->info
.outputs_written
,
720 vs_stage
->nir
->info
.separate_shader
);
722 vs_stage
->num_stats
= 1;
723 vs_stage
->code
= brw_compile_vs(compiler
, device
, mem_ctx
,
725 &vs_stage
->prog_data
.vs
,
727 vs_stage
->stats
, NULL
);
731 merge_tess_info(struct shader_info
*tes_info
,
732 const struct shader_info
*tcs_info
)
734 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
736 * "PointMode. Controls generation of points rather than triangles
737 * or lines. This functionality defaults to disabled, and is
738 * enabled if either shader stage includes the execution mode.
740 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
741 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
742 * and OutputVertices, it says:
744 * "One mode must be set in at least one of the tessellation
747 * So, the fields can be set in either the TCS or TES, but they must
748 * agree if set in both. Our backend looks at TES, so bitwise-or in
749 * the values from the TCS.
751 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
752 tes_info
->tess
.tcs_vertices_out
== 0 ||
753 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
754 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
756 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
757 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
758 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
759 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
761 assert(tcs_info
->tess
.primitive_mode
== 0 ||
762 tes_info
->tess
.primitive_mode
== 0 ||
763 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
764 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
765 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
766 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
770 anv_pipeline_link_tcs(const struct brw_compiler
*compiler
,
771 struct anv_pipeline_stage
*tcs_stage
,
772 struct anv_pipeline_stage
*tes_stage
)
774 assert(tes_stage
&& tes_stage
->stage
== MESA_SHADER_TESS_EVAL
);
776 brw_nir_link_shaders(compiler
, tcs_stage
->nir
, tes_stage
->nir
);
778 nir_lower_patch_vertices(tes_stage
->nir
,
779 tcs_stage
->nir
->info
.tess
.tcs_vertices_out
,
782 /* Copy TCS info into the TES info */
783 merge_tess_info(&tes_stage
->nir
->info
, &tcs_stage
->nir
->info
);
785 /* Whacking the key after cache lookup is a bit sketchy, but all of
786 * this comes from the SPIR-V, which is part of the hash used for the
787 * pipeline cache. So it should be safe.
789 tcs_stage
->key
.tcs
.tes_primitive_mode
=
790 tes_stage
->nir
->info
.tess
.primitive_mode
;
791 tcs_stage
->key
.tcs
.quads_workaround
=
792 compiler
->devinfo
->gen
< 9 &&
793 tes_stage
->nir
->info
.tess
.primitive_mode
== 7 /* GL_QUADS */ &&
794 tes_stage
->nir
->info
.tess
.spacing
== TESS_SPACING_EQUAL
;
798 anv_pipeline_compile_tcs(const struct brw_compiler
*compiler
,
800 struct anv_device
*device
,
801 struct anv_pipeline_stage
*tcs_stage
,
802 struct anv_pipeline_stage
*prev_stage
)
804 tcs_stage
->key
.tcs
.outputs_written
=
805 tcs_stage
->nir
->info
.outputs_written
;
806 tcs_stage
->key
.tcs
.patch_outputs_written
=
807 tcs_stage
->nir
->info
.patch_outputs_written
;
809 tcs_stage
->num_stats
= 1;
810 tcs_stage
->code
= brw_compile_tcs(compiler
, device
, mem_ctx
,
812 &tcs_stage
->prog_data
.tcs
,
814 tcs_stage
->stats
, NULL
);
818 anv_pipeline_link_tes(const struct brw_compiler
*compiler
,
819 struct anv_pipeline_stage
*tes_stage
,
820 struct anv_pipeline_stage
*next_stage
)
823 brw_nir_link_shaders(compiler
, tes_stage
->nir
, next_stage
->nir
);
827 anv_pipeline_compile_tes(const struct brw_compiler
*compiler
,
829 struct anv_device
*device
,
830 struct anv_pipeline_stage
*tes_stage
,
831 struct anv_pipeline_stage
*tcs_stage
)
833 tes_stage
->key
.tes
.inputs_read
=
834 tcs_stage
->nir
->info
.outputs_written
;
835 tes_stage
->key
.tes
.patch_inputs_read
=
836 tcs_stage
->nir
->info
.patch_outputs_written
;
838 tes_stage
->num_stats
= 1;
839 tes_stage
->code
= brw_compile_tes(compiler
, device
, mem_ctx
,
841 &tcs_stage
->prog_data
.tcs
.base
.vue_map
,
842 &tes_stage
->prog_data
.tes
,
844 tes_stage
->stats
, NULL
);
848 anv_pipeline_link_gs(const struct brw_compiler
*compiler
,
849 struct anv_pipeline_stage
*gs_stage
,
850 struct anv_pipeline_stage
*next_stage
)
853 brw_nir_link_shaders(compiler
, gs_stage
->nir
, next_stage
->nir
);
857 anv_pipeline_compile_gs(const struct brw_compiler
*compiler
,
859 struct anv_device
*device
,
860 struct anv_pipeline_stage
*gs_stage
,
861 struct anv_pipeline_stage
*prev_stage
)
863 brw_compute_vue_map(compiler
->devinfo
,
864 &gs_stage
->prog_data
.gs
.base
.vue_map
,
865 gs_stage
->nir
->info
.outputs_written
,
866 gs_stage
->nir
->info
.separate_shader
);
868 gs_stage
->num_stats
= 1;
869 gs_stage
->code
= brw_compile_gs(compiler
, device
, mem_ctx
,
871 &gs_stage
->prog_data
.gs
,
872 gs_stage
->nir
, NULL
, -1,
873 gs_stage
->stats
, NULL
);
877 anv_pipeline_link_fs(const struct brw_compiler
*compiler
,
878 struct anv_pipeline_stage
*stage
)
880 unsigned num_rt_bindings
;
881 struct anv_pipeline_binding rt_bindings
[MAX_RTS
];
882 if (stage
->key
.wm
.nr_color_regions
> 0) {
883 assert(stage
->key
.wm
.nr_color_regions
<= MAX_RTS
);
884 for (unsigned rt
= 0; rt
< stage
->key
.wm
.nr_color_regions
; rt
++) {
885 if (stage
->key
.wm
.color_outputs_valid
& BITFIELD_BIT(rt
)) {
886 rt_bindings
[rt
] = (struct anv_pipeline_binding
) {
887 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
891 /* Setup a null render target */
892 rt_bindings
[rt
] = (struct anv_pipeline_binding
) {
893 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
898 num_rt_bindings
= stage
->key
.wm
.nr_color_regions
;
900 /* Setup a null render target */
901 rt_bindings
[0] = (struct anv_pipeline_binding
) {
902 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
908 assert(num_rt_bindings
<= MAX_RTS
);
909 assert(stage
->bind_map
.surface_count
== 0);
910 typed_memcpy(stage
->bind_map
.surface_to_descriptor
,
911 rt_bindings
, num_rt_bindings
);
912 stage
->bind_map
.surface_count
+= num_rt_bindings
;
914 /* Now that we've set up the color attachments, we can go through and
915 * eliminate any shader outputs that map to VK_ATTACHMENT_UNUSED in the
916 * hopes that dead code can clean them up in this and any earlier shader
919 nir_function_impl
*impl
= nir_shader_get_entrypoint(stage
->nir
);
920 bool deleted_output
= false;
921 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
922 /* TODO: We don't delete depth/stencil writes. We probably could if the
923 * subpass doesn't have a depth/stencil attachment.
925 if (var
->data
.location
< FRAG_RESULT_DATA0
)
928 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
930 /* If this is the RT at location 0 and we have alpha to coverage
931 * enabled we still need that write because it will affect the coverage
932 * mask even if it's never written to a color target.
934 if (rt
== 0 && stage
->key
.wm
.alpha_to_coverage
)
937 const unsigned array_len
=
938 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
939 assert(rt
+ array_len
<= MAX_RTS
);
941 if (rt
>= MAX_RTS
|| !(stage
->key
.wm
.color_outputs_valid
&
942 BITFIELD_RANGE(rt
, array_len
))) {
943 deleted_output
= true;
944 var
->data
.mode
= nir_var_function_temp
;
945 exec_node_remove(&var
->node
);
946 exec_list_push_tail(&impl
->locals
, &var
->node
);
951 nir_fixup_deref_modes(stage
->nir
);
953 /* We stored the number of subpass color attachments in nr_color_regions
954 * when calculating the key for caching. Now that we've computed the bind
955 * map, we can reduce this to the actual max before we go into the back-end
958 stage
->key
.wm
.nr_color_regions
=
959 util_last_bit(stage
->key
.wm
.color_outputs_valid
);
963 anv_pipeline_compile_fs(const struct brw_compiler
*compiler
,
965 struct anv_device
*device
,
966 struct anv_pipeline_stage
*fs_stage
,
967 struct anv_pipeline_stage
*prev_stage
)
969 /* TODO: we could set this to 0 based on the information in nir_shader, but
970 * we need this before we call spirv_to_nir.
973 fs_stage
->key
.wm
.input_slots_valid
=
974 prev_stage
->prog_data
.vue
.vue_map
.slots_valid
;
976 fs_stage
->code
= brw_compile_fs(compiler
, device
, mem_ctx
,
978 &fs_stage
->prog_data
.wm
,
979 fs_stage
->nir
, -1, -1, -1,
981 fs_stage
->stats
, NULL
);
983 fs_stage
->num_stats
= (uint32_t)fs_stage
->prog_data
.wm
.dispatch_8
+
984 (uint32_t)fs_stage
->prog_data
.wm
.dispatch_16
+
985 (uint32_t)fs_stage
->prog_data
.wm
.dispatch_32
;
987 if (fs_stage
->key
.wm
.color_outputs_valid
== 0 &&
988 !fs_stage
->prog_data
.wm
.has_side_effects
&&
989 !fs_stage
->prog_data
.wm
.uses_omask
&&
990 !fs_stage
->key
.wm
.alpha_to_coverage
&&
991 !fs_stage
->prog_data
.wm
.uses_kill
&&
992 fs_stage
->prog_data
.wm
.computed_depth_mode
== BRW_PSCDEPTH_OFF
&&
993 !fs_stage
->prog_data
.wm
.computed_stencil
) {
994 /* This fragment shader has no outputs and no side effects. Go ahead
995 * and return the code pointer so we don't accidentally think the
996 * compile failed but zero out prog_data which will set program_size to
997 * zero and disable the stage.
999 memset(&fs_stage
->prog_data
, 0, sizeof(fs_stage
->prog_data
));
1004 anv_pipeline_add_executable(struct anv_pipeline
*pipeline
,
1005 struct anv_pipeline_stage
*stage
,
1006 struct brw_compile_stats
*stats
,
1007 uint32_t code_offset
)
1012 VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
)) {
1013 char *stream_data
= NULL
;
1014 size_t stream_size
= 0;
1015 FILE *stream
= open_memstream(&stream_data
, &stream_size
);
1017 nir_print_shader(stage
->nir
, stream
);
1021 /* Copy it to a ralloc'd thing */
1022 nir
= ralloc_size(pipeline
->mem_ctx
, stream_size
+ 1);
1023 memcpy(nir
, stream_data
, stream_size
);
1024 nir
[stream_size
] = 0;
1029 char *disasm
= NULL
;
1032 VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
)) {
1033 char *stream_data
= NULL
;
1034 size_t stream_size
= 0;
1035 FILE *stream
= open_memstream(&stream_data
, &stream_size
);
1037 /* Creating this is far cheaper than it looks. It's perfectly fine to
1038 * do it for every binary.
1040 struct gen_disasm
*d
= gen_disasm_create(&pipeline
->device
->info
);
1041 gen_disasm_disassemble(d
, stage
->code
, code_offset
, stream
);
1042 gen_disasm_destroy(d
);
1046 /* Copy it to a ralloc'd thing */
1047 disasm
= ralloc_size(pipeline
->mem_ctx
, stream_size
+ 1);
1048 memcpy(disasm
, stream_data
, stream_size
);
1049 disasm
[stream_size
] = 0;
1054 const struct anv_pipeline_executable exe
= {
1055 .stage
= stage
->stage
,
1060 util_dynarray_append(&pipeline
->executables
,
1061 struct anv_pipeline_executable
, exe
);
1065 anv_pipeline_add_executables(struct anv_pipeline
*pipeline
,
1066 struct anv_pipeline_stage
*stage
,
1067 struct anv_shader_bin
*bin
)
1069 if (stage
->stage
== MESA_SHADER_FRAGMENT
) {
1070 /* We pull the prog data and stats out of the anv_shader_bin because
1071 * the anv_pipeline_stage may not be fully populated if we successfully
1072 * looked up the shader in a cache.
1074 const struct brw_wm_prog_data
*wm_prog_data
=
1075 (const struct brw_wm_prog_data
*)bin
->prog_data
;
1076 struct brw_compile_stats
*stats
= bin
->stats
;
1078 if (wm_prog_data
->dispatch_8
) {
1079 anv_pipeline_add_executable(pipeline
, stage
, stats
++, 0);
1082 if (wm_prog_data
->dispatch_16
) {
1083 anv_pipeline_add_executable(pipeline
, stage
, stats
++,
1084 wm_prog_data
->prog_offset_16
);
1087 if (wm_prog_data
->dispatch_32
) {
1088 anv_pipeline_add_executable(pipeline
, stage
, stats
++,
1089 wm_prog_data
->prog_offset_32
);
1092 anv_pipeline_add_executable(pipeline
, stage
, bin
->stats
, 0);
1097 anv_pipeline_compile_graphics(struct anv_pipeline
*pipeline
,
1098 struct anv_pipeline_cache
*cache
,
1099 const VkGraphicsPipelineCreateInfo
*info
)
1101 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1102 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1104 int64_t pipeline_start
= os_time_get_nano();
1106 const struct brw_compiler
*compiler
= pipeline
->device
->physical
->compiler
;
1107 struct anv_pipeline_stage stages
[MESA_SHADER_STAGES
] = {};
1109 pipeline
->active_stages
= 0;
1112 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1113 const VkPipelineShaderStageCreateInfo
*sinfo
= &info
->pStages
[i
];
1114 gl_shader_stage stage
= vk_to_mesa_shader_stage(sinfo
->stage
);
1116 pipeline
->active_stages
|= sinfo
->stage
;
1118 int64_t stage_start
= os_time_get_nano();
1120 stages
[stage
].stage
= stage
;
1121 stages
[stage
].module
= anv_shader_module_from_handle(sinfo
->module
);
1122 stages
[stage
].entrypoint
= sinfo
->pName
;
1123 stages
[stage
].spec_info
= sinfo
->pSpecializationInfo
;
1124 anv_pipeline_hash_shader(stages
[stage
].module
,
1125 stages
[stage
].entrypoint
,
1127 stages
[stage
].spec_info
,
1128 stages
[stage
].shader_sha1
);
1130 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1132 case MESA_SHADER_VERTEX
:
1133 populate_vs_prog_key(devinfo
, sinfo
->flags
, &stages
[stage
].key
.vs
);
1135 case MESA_SHADER_TESS_CTRL
:
1136 populate_tcs_prog_key(devinfo
, sinfo
->flags
,
1137 info
->pTessellationState
->patchControlPoints
,
1138 &stages
[stage
].key
.tcs
);
1140 case MESA_SHADER_TESS_EVAL
:
1141 populate_tes_prog_key(devinfo
, sinfo
->flags
, &stages
[stage
].key
.tes
);
1143 case MESA_SHADER_GEOMETRY
:
1144 populate_gs_prog_key(devinfo
, sinfo
->flags
, &stages
[stage
].key
.gs
);
1146 case MESA_SHADER_FRAGMENT
: {
1147 const bool raster_enabled
=
1148 !info
->pRasterizationState
->rasterizerDiscardEnable
;
1149 populate_wm_prog_key(devinfo
, sinfo
->flags
,
1151 raster_enabled
? info
->pMultisampleState
: NULL
,
1152 &stages
[stage
].key
.wm
);
1156 unreachable("Invalid graphics shader stage");
1159 stages
[stage
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1160 stages
[stage
].feedback
.flags
|= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
1163 if (pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
)
1164 pipeline
->active_stages
|= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
1166 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1168 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1170 unsigned char sha1
[20];
1171 anv_pipeline_hash_graphics(pipeline
, layout
, stages
, sha1
);
1173 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1174 if (!stages
[s
].entrypoint
)
1177 stages
[s
].cache_key
.stage
= s
;
1178 memcpy(stages
[s
].cache_key
.sha1
, sha1
, sizeof(sha1
));
1181 const bool skip_cache_lookup
=
1182 (pipeline
->flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
);
1184 if (!skip_cache_lookup
) {
1186 unsigned cache_hits
= 0;
1187 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1188 if (!stages
[s
].entrypoint
)
1191 int64_t stage_start
= os_time_get_nano();
1194 struct anv_shader_bin
*bin
=
1195 anv_device_search_for_kernel(pipeline
->device
, cache
,
1196 &stages
[s
].cache_key
,
1197 sizeof(stages
[s
].cache_key
), &cache_hit
);
1200 pipeline
->shaders
[s
] = bin
;
1205 stages
[s
].feedback
.flags
|=
1206 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1208 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1211 if (found
== __builtin_popcount(pipeline
->active_stages
)) {
1212 if (cache_hits
== found
) {
1213 pipeline_feedback
.flags
|=
1214 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1216 /* We found all our shaders in the cache. We're done. */
1217 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1218 if (!stages
[s
].entrypoint
)
1221 anv_pipeline_add_executables(pipeline
, &stages
[s
],
1222 pipeline
->shaders
[s
]);
1225 } else if (found
> 0) {
1226 /* We found some but not all of our shaders. This shouldn't happen
1227 * most of the time but it can if we have a partially populated
1230 assert(found
< __builtin_popcount(pipeline
->active_stages
));
1232 vk_debug_report(&pipeline
->device
->physical
->instance
->debug_report_callbacks
,
1233 VK_DEBUG_REPORT_WARNING_BIT_EXT
|
1234 VK_DEBUG_REPORT_PERFORMANCE_WARNING_BIT_EXT
,
1235 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT
,
1236 (uint64_t)(uintptr_t)cache
,
1238 "Found a partial pipeline in the cache. This is "
1239 "most likely caused by an incomplete pipeline cache "
1240 "import or export");
1242 /* We're going to have to recompile anyway, so just throw away our
1243 * references to the shaders in the cache. We'll get them out of the
1244 * cache again as part of the compilation process.
1246 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1247 stages
[s
].feedback
.flags
= 0;
1248 if (pipeline
->shaders
[s
]) {
1249 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1250 pipeline
->shaders
[s
] = NULL
;
1256 void *pipeline_ctx
= ralloc_context(NULL
);
1258 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1259 if (!stages
[s
].entrypoint
)
1262 int64_t stage_start
= os_time_get_nano();
1264 assert(stages
[s
].stage
== s
);
1265 assert(pipeline
->shaders
[s
] == NULL
);
1267 stages
[s
].bind_map
= (struct anv_pipeline_bind_map
) {
1268 .surface_to_descriptor
= stages
[s
].surface_to_descriptor
,
1269 .sampler_to_descriptor
= stages
[s
].sampler_to_descriptor
1272 stages
[s
].nir
= anv_pipeline_stage_get_nir(pipeline
, cache
,
1275 if (stages
[s
].nir
== NULL
) {
1276 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1280 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1283 /* Walk backwards to link */
1284 struct anv_pipeline_stage
*next_stage
= NULL
;
1285 for (int s
= MESA_SHADER_STAGES
- 1; s
>= 0; s
--) {
1286 if (!stages
[s
].entrypoint
)
1290 case MESA_SHADER_VERTEX
:
1291 anv_pipeline_link_vs(compiler
, &stages
[s
], next_stage
);
1293 case MESA_SHADER_TESS_CTRL
:
1294 anv_pipeline_link_tcs(compiler
, &stages
[s
], next_stage
);
1296 case MESA_SHADER_TESS_EVAL
:
1297 anv_pipeline_link_tes(compiler
, &stages
[s
], next_stage
);
1299 case MESA_SHADER_GEOMETRY
:
1300 anv_pipeline_link_gs(compiler
, &stages
[s
], next_stage
);
1302 case MESA_SHADER_FRAGMENT
:
1303 anv_pipeline_link_fs(compiler
, &stages
[s
]);
1306 unreachable("Invalid graphics shader stage");
1309 next_stage
= &stages
[s
];
1312 struct anv_pipeline_stage
*prev_stage
= NULL
;
1313 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1314 if (!stages
[s
].entrypoint
)
1317 int64_t stage_start
= os_time_get_nano();
1319 void *stage_ctx
= ralloc_context(NULL
);
1321 nir_xfb_info
*xfb_info
= NULL
;
1322 if (s
== MESA_SHADER_VERTEX
||
1323 s
== MESA_SHADER_TESS_EVAL
||
1324 s
== MESA_SHADER_GEOMETRY
)
1325 xfb_info
= nir_gather_xfb_info(stages
[s
].nir
, stage_ctx
);
1327 anv_pipeline_lower_nir(pipeline
, stage_ctx
, &stages
[s
], layout
);
1330 case MESA_SHADER_VERTEX
:
1331 anv_pipeline_compile_vs(compiler
, stage_ctx
, pipeline
->device
,
1334 case MESA_SHADER_TESS_CTRL
:
1335 anv_pipeline_compile_tcs(compiler
, stage_ctx
, pipeline
->device
,
1336 &stages
[s
], prev_stage
);
1338 case MESA_SHADER_TESS_EVAL
:
1339 anv_pipeline_compile_tes(compiler
, stage_ctx
, pipeline
->device
,
1340 &stages
[s
], prev_stage
);
1342 case MESA_SHADER_GEOMETRY
:
1343 anv_pipeline_compile_gs(compiler
, stage_ctx
, pipeline
->device
,
1344 &stages
[s
], prev_stage
);
1346 case MESA_SHADER_FRAGMENT
:
1347 anv_pipeline_compile_fs(compiler
, stage_ctx
, pipeline
->device
,
1348 &stages
[s
], prev_stage
);
1351 unreachable("Invalid graphics shader stage");
1353 if (stages
[s
].code
== NULL
) {
1354 ralloc_free(stage_ctx
);
1355 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1359 anv_nir_validate_push_layout(&stages
[s
].prog_data
.base
,
1360 &stages
[s
].bind_map
);
1362 struct anv_shader_bin
*bin
=
1363 anv_device_upload_kernel(pipeline
->device
, cache
,
1364 &stages
[s
].cache_key
,
1365 sizeof(stages
[s
].cache_key
),
1367 stages
[s
].prog_data
.base
.program_size
,
1368 stages
[s
].nir
->constant_data
,
1369 stages
[s
].nir
->constant_data_size
,
1370 &stages
[s
].prog_data
.base
,
1371 brw_prog_data_size(s
),
1372 stages
[s
].stats
, stages
[s
].num_stats
,
1373 xfb_info
, &stages
[s
].bind_map
);
1375 ralloc_free(stage_ctx
);
1376 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1380 anv_pipeline_add_executables(pipeline
, &stages
[s
], bin
);
1382 pipeline
->shaders
[s
] = bin
;
1383 ralloc_free(stage_ctx
);
1385 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1387 prev_stage
= &stages
[s
];
1390 ralloc_free(pipeline_ctx
);
1394 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
] &&
1395 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->prog_data
->program_size
== 0) {
1396 /* This can happen if we decided to implicitly disable the fragment
1397 * shader. See anv_pipeline_compile_fs().
1399 anv_shader_bin_unref(pipeline
->device
,
1400 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
1401 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] = NULL
;
1402 pipeline
->active_stages
&= ~VK_SHADER_STAGE_FRAGMENT_BIT
;
1405 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1407 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1408 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1409 if (create_feedback
) {
1410 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1412 assert(info
->stageCount
== create_feedback
->pipelineStageCreationFeedbackCount
);
1413 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1414 gl_shader_stage s
= vk_to_mesa_shader_stage(info
->pStages
[i
].stage
);
1415 create_feedback
->pPipelineStageCreationFeedbacks
[i
] = stages
[s
].feedback
;
1422 ralloc_free(pipeline_ctx
);
1424 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1425 if (pipeline
->shaders
[s
])
1426 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1433 shared_type_info(const struct glsl_type
*type
, unsigned *size
, unsigned *align
)
1435 assert(glsl_type_is_vector_or_scalar(type
));
1437 uint32_t comp_size
= glsl_type_is_boolean(type
)
1438 ? 4 : glsl_get_bit_size(type
) / 8;
1439 unsigned length
= glsl_get_vector_elements(type
);
1440 *size
= comp_size
* length
,
1441 *align
= comp_size
* (length
== 3 ? 4 : length
);
1445 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1446 struct anv_pipeline_cache
*cache
,
1447 const VkComputePipelineCreateInfo
*info
,
1448 const struct anv_shader_module
*module
,
1449 const char *entrypoint
,
1450 const VkSpecializationInfo
*spec_info
)
1452 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1453 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1455 int64_t pipeline_start
= os_time_get_nano();
1457 const struct brw_compiler
*compiler
= pipeline
->device
->physical
->compiler
;
1459 struct anv_pipeline_stage stage
= {
1460 .stage
= MESA_SHADER_COMPUTE
,
1462 .entrypoint
= entrypoint
,
1463 .spec_info
= spec_info
,
1465 .stage
= MESA_SHADER_COMPUTE
,
1468 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1471 anv_pipeline_hash_shader(stage
.module
,
1473 MESA_SHADER_COMPUTE
,
1477 struct anv_shader_bin
*bin
= NULL
;
1479 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*rss_info
=
1480 vk_find_struct_const(info
->stage
.pNext
,
1481 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
1483 populate_cs_prog_key(&pipeline
->device
->info
, info
->stage
.flags
,
1484 rss_info
, &stage
.key
.cs
);
1486 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1488 const bool skip_cache_lookup
=
1489 (pipeline
->flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
);
1491 anv_pipeline_hash_compute(pipeline
, layout
, &stage
, stage
.cache_key
.sha1
);
1493 bool cache_hit
= false;
1494 if (!skip_cache_lookup
) {
1495 bin
= anv_device_search_for_kernel(pipeline
->device
, cache
,
1497 sizeof(stage
.cache_key
),
1501 void *mem_ctx
= ralloc_context(NULL
);
1503 int64_t stage_start
= os_time_get_nano();
1505 stage
.bind_map
= (struct anv_pipeline_bind_map
) {
1506 .surface_to_descriptor
= stage
.surface_to_descriptor
,
1507 .sampler_to_descriptor
= stage
.sampler_to_descriptor
1510 /* Set up a binding for the gl_NumWorkGroups */
1511 stage
.bind_map
.surface_count
= 1;
1512 stage
.bind_map
.surface_to_descriptor
[0] = (struct anv_pipeline_binding
) {
1513 .set
= ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
,
1516 stage
.nir
= anv_pipeline_stage_get_nir(pipeline
, cache
, mem_ctx
, &stage
);
1517 if (stage
.nir
== NULL
) {
1518 ralloc_free(mem_ctx
);
1519 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1522 NIR_PASS_V(stage
.nir
, anv_nir_add_base_work_group_id
);
1524 anv_pipeline_lower_nir(pipeline
, mem_ctx
, &stage
, layout
);
1526 NIR_PASS_V(stage
.nir
, nir_lower_vars_to_explicit_types
,
1527 nir_var_mem_shared
, shared_type_info
);
1528 NIR_PASS_V(stage
.nir
, nir_lower_explicit_io
,
1529 nir_var_mem_shared
, nir_address_format_32bit_offset
);
1531 stage
.num_stats
= 1;
1532 stage
.code
= brw_compile_cs(compiler
, pipeline
->device
, mem_ctx
,
1533 &stage
.key
.cs
, &stage
.prog_data
.cs
,
1534 stage
.nir
, -1, stage
.stats
, NULL
);
1535 if (stage
.code
== NULL
) {
1536 ralloc_free(mem_ctx
);
1537 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1540 anv_nir_validate_push_layout(&stage
.prog_data
.base
, &stage
.bind_map
);
1542 if (!stage
.prog_data
.cs
.uses_num_work_groups
) {
1543 assert(stage
.bind_map
.surface_to_descriptor
[0].set
==
1544 ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
);
1545 stage
.bind_map
.surface_to_descriptor
[0].set
= ANV_DESCRIPTOR_SET_NULL
;
1548 const unsigned code_size
= stage
.prog_data
.base
.program_size
;
1549 bin
= anv_device_upload_kernel(pipeline
->device
, cache
,
1550 &stage
.cache_key
, sizeof(stage
.cache_key
),
1551 stage
.code
, code_size
,
1552 stage
.nir
->constant_data
,
1553 stage
.nir
->constant_data_size
,
1554 &stage
.prog_data
.base
,
1555 sizeof(stage
.prog_data
.cs
),
1556 stage
.stats
, stage
.num_stats
,
1557 NULL
, &stage
.bind_map
);
1559 ralloc_free(mem_ctx
);
1560 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1563 stage
.feedback
.duration
= os_time_get_nano() - stage_start
;
1566 anv_pipeline_add_executables(pipeline
, &stage
, bin
);
1568 ralloc_free(mem_ctx
);
1571 stage
.feedback
.flags
|=
1572 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1573 pipeline_feedback
.flags
|=
1574 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1576 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1578 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1579 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1580 if (create_feedback
) {
1581 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1583 assert(create_feedback
->pipelineStageCreationFeedbackCount
== 1);
1584 create_feedback
->pPipelineStageCreationFeedbacks
[0] = stage
.feedback
;
1587 pipeline
->active_stages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1588 pipeline
->shaders
[MESA_SHADER_COMPUTE
] = bin
;
1594 * Copy pipeline state not marked as dynamic.
1595 * Dynamic state is pipeline state which hasn't been provided at pipeline
1596 * creation time, but is dynamically provided afterwards using various
1597 * vkCmdSet* functions.
1599 * The set of state considered "non_dynamic" is determined by the pieces of
1600 * state that have their corresponding VkDynamicState enums omitted from
1601 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1603 * @param[out] pipeline Destination non_dynamic state.
1604 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1607 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
1608 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1610 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
1611 struct anv_subpass
*subpass
= pipeline
->subpass
;
1613 pipeline
->dynamic_state
= default_dynamic_state
;
1615 if (pCreateInfo
->pDynamicState
) {
1616 /* Remove all of the states that are marked as dynamic */
1617 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1618 for (uint32_t s
= 0; s
< count
; s
++) {
1619 states
&= ~anv_cmd_dirty_bit_for_vk_dynamic_state(
1620 pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1624 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1626 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1628 * pViewportState is [...] NULL if the pipeline
1629 * has rasterization disabled.
1631 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1632 assert(pCreateInfo
->pViewportState
);
1634 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1635 if (states
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
) {
1636 typed_memcpy(dynamic
->viewport
.viewports
,
1637 pCreateInfo
->pViewportState
->pViewports
,
1638 pCreateInfo
->pViewportState
->viewportCount
);
1641 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1642 if (states
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
) {
1643 typed_memcpy(dynamic
->scissor
.scissors
,
1644 pCreateInfo
->pViewportState
->pScissors
,
1645 pCreateInfo
->pViewportState
->scissorCount
);
1649 if (states
& ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
) {
1650 assert(pCreateInfo
->pRasterizationState
);
1651 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1654 if (states
& ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
) {
1655 assert(pCreateInfo
->pRasterizationState
);
1656 dynamic
->depth_bias
.bias
=
1657 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1658 dynamic
->depth_bias
.clamp
=
1659 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1660 dynamic
->depth_bias
.slope
=
1661 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1664 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1666 * pColorBlendState is [...] NULL if the pipeline has rasterization
1667 * disabled or if the subpass of the render pass the pipeline is
1668 * created against does not use any color attachments.
1670 bool uses_color_att
= false;
1671 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1672 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1673 uses_color_att
= true;
1678 if (uses_color_att
&&
1679 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1680 assert(pCreateInfo
->pColorBlendState
);
1682 if (states
& ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
1683 typed_memcpy(dynamic
->blend_constants
,
1684 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1687 /* If there is no depthstencil attachment, then don't read
1688 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1689 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1690 * no need to override the depthstencil defaults in
1691 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1693 * Section 9.2 of the Vulkan 1.0.15 spec says:
1695 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1696 * disabled or if the subpass of the render pass the pipeline is created
1697 * against does not use a depth/stencil attachment.
1699 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1700 subpass
->depth_stencil_attachment
) {
1701 assert(pCreateInfo
->pDepthStencilState
);
1703 if (states
& ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
) {
1704 dynamic
->depth_bounds
.min
=
1705 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1706 dynamic
->depth_bounds
.max
=
1707 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1710 if (states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
) {
1711 dynamic
->stencil_compare_mask
.front
=
1712 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1713 dynamic
->stencil_compare_mask
.back
=
1714 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1717 if (states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
) {
1718 dynamic
->stencil_write_mask
.front
=
1719 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1720 dynamic
->stencil_write_mask
.back
=
1721 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1724 if (states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
) {
1725 dynamic
->stencil_reference
.front
=
1726 pCreateInfo
->pDepthStencilState
->front
.reference
;
1727 dynamic
->stencil_reference
.back
=
1728 pCreateInfo
->pDepthStencilState
->back
.reference
;
1732 const VkPipelineRasterizationLineStateCreateInfoEXT
*line_state
=
1733 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1734 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1736 if (states
& ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
) {
1737 dynamic
->line_stipple
.factor
= line_state
->lineStippleFactor
;
1738 dynamic
->line_stipple
.pattern
= line_state
->lineStipplePattern
;
1742 pipeline
->dynamic_state_mask
= states
;
1746 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1749 struct anv_render_pass
*renderpass
= NULL
;
1750 struct anv_subpass
*subpass
= NULL
;
1752 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1753 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1755 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1757 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1760 assert(info
->subpass
< renderpass
->subpass_count
);
1761 subpass
= &renderpass
->subpasses
[info
->subpass
];
1763 assert(info
->stageCount
>= 1);
1764 assert(info
->pVertexInputState
);
1765 assert(info
->pInputAssemblyState
);
1766 assert(info
->pRasterizationState
);
1767 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1768 assert(info
->pViewportState
);
1769 assert(info
->pMultisampleState
);
1771 if (subpass
&& subpass
->depth_stencil_attachment
)
1772 assert(info
->pDepthStencilState
);
1774 if (subpass
&& subpass
->color_count
> 0) {
1775 bool all_color_unused
= true;
1776 for (int i
= 0; i
< subpass
->color_count
; i
++) {
1777 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
1778 all_color_unused
= false;
1780 /* pColorBlendState is ignored if the pipeline has rasterization
1781 * disabled or if the subpass of the render pass the pipeline is
1782 * created against does not use any color attachments.
1784 assert(info
->pColorBlendState
|| all_color_unused
);
1788 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1789 switch (info
->pStages
[i
].stage
) {
1790 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1791 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1792 assert(info
->pTessellationState
);
1802 * Calculate the desired L3 partitioning based on the current state of the
1803 * pipeline. For now this simply returns the conservative defaults calculated
1804 * by get_default_l3_weights(), but we could probably do better by gathering
1805 * more statistics from the pipeline state (e.g. guess of expected URB usage
1806 * and bound surfaces), or by using feed-back from performance counters.
1809 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1811 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1813 const struct gen_l3_weights w
=
1814 gen_get_default_l3_weights(devinfo
, true, needs_slm
);
1816 pipeline
->l3_config
= gen_get_l3_config(devinfo
, w
);
1820 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1821 struct anv_device
*device
,
1822 struct anv_pipeline_cache
*cache
,
1823 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1824 const VkAllocationCallbacks
*alloc
)
1828 anv_pipeline_validate_create_info(pCreateInfo
);
1831 alloc
= &device
->alloc
;
1833 pipeline
->device
= device
;
1834 pipeline
->type
= ANV_PIPELINE_GRAPHICS
;
1836 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, pCreateInfo
->renderPass
);
1837 assert(pCreateInfo
->subpass
< render_pass
->subpass_count
);
1838 pipeline
->subpass
= &render_pass
->subpasses
[pCreateInfo
->subpass
];
1840 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1841 if (result
!= VK_SUCCESS
)
1844 pipeline
->batch
.alloc
= alloc
;
1845 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1846 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1847 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1848 pipeline
->batch
.status
= VK_SUCCESS
;
1850 pipeline
->mem_ctx
= ralloc_context(NULL
);
1851 pipeline
->flags
= pCreateInfo
->flags
;
1853 assert(pCreateInfo
->pRasterizationState
);
1855 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1856 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
->depthClampEnable
;
1858 /* Previously we enabled depth clipping when !depthClampEnable.
1859 * DepthClipStateCreateInfo now makes depth clipping explicit so if the
1860 * clipping info is available, use its enable value to determine clipping,
1861 * otherwise fallback to the previous !depthClampEnable logic.
1863 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*clip_info
=
1864 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1865 PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
1866 pipeline
->depth_clip_enable
= clip_info
? clip_info
->depthClipEnable
: !pipeline
->depth_clamp_enable
;
1868 pipeline
->sample_shading_enable
=
1869 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1870 pCreateInfo
->pMultisampleState
&&
1871 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
1873 /* When we free the pipeline, we detect stages based on the NULL status
1874 * of various prog_data pointers. Make them NULL by default.
1876 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1878 util_dynarray_init(&pipeline
->executables
, pipeline
->mem_ctx
);
1880 result
= anv_pipeline_compile_graphics(pipeline
, cache
, pCreateInfo
);
1881 if (result
!= VK_SUCCESS
) {
1882 ralloc_free(pipeline
->mem_ctx
);
1883 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);
1887 assert(pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1889 anv_pipeline_setup_l3_config(pipeline
, false);
1891 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1892 pCreateInfo
->pVertexInputState
;
1894 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1896 pipeline
->vb_used
= 0;
1897 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1898 const VkVertexInputAttributeDescription
*desc
=
1899 &vi_info
->pVertexAttributeDescriptions
[i
];
1901 if (inputs_read
& (1ull << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1902 pipeline
->vb_used
|= 1 << desc
->binding
;
1905 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1906 const VkVertexInputBindingDescription
*desc
=
1907 &vi_info
->pVertexBindingDescriptions
[i
];
1909 pipeline
->vb
[desc
->binding
].stride
= desc
->stride
;
1911 /* Step rate is programmed per vertex element (attribute), not
1912 * binding. Set up a map of which bindings step per instance, for
1913 * reference by vertex element setup. */
1914 switch (desc
->inputRate
) {
1916 case VK_VERTEX_INPUT_RATE_VERTEX
:
1917 pipeline
->vb
[desc
->binding
].instanced
= false;
1919 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1920 pipeline
->vb
[desc
->binding
].instanced
= true;
1924 pipeline
->vb
[desc
->binding
].instance_divisor
= 1;
1927 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*vi_div_state
=
1928 vk_find_struct_const(vi_info
->pNext
,
1929 PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
1931 for (uint32_t i
= 0; i
< vi_div_state
->vertexBindingDivisorCount
; i
++) {
1932 const VkVertexInputBindingDivisorDescriptionEXT
*desc
=
1933 &vi_div_state
->pVertexBindingDivisors
[i
];
1935 pipeline
->vb
[desc
->binding
].instance_divisor
= desc
->divisor
;
1939 /* Our implementation of VK_KHR_multiview uses instancing to draw the
1940 * different views. If the client asks for instancing, we need to multiply
1941 * the instance divisor by the number of views ensure that we repeat the
1942 * client's per-instance data once for each view.
1944 if (pipeline
->subpass
->view_mask
) {
1945 const uint32_t view_count
= anv_subpass_view_count(pipeline
->subpass
);
1946 for (uint32_t vb
= 0; vb
< MAX_VBS
; vb
++) {
1947 if (pipeline
->vb
[vb
].instanced
)
1948 pipeline
->vb
[vb
].instance_divisor
*= view_count
;
1952 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1953 pCreateInfo
->pInputAssemblyState
;
1954 const VkPipelineTessellationStateCreateInfo
*tess_info
=
1955 pCreateInfo
->pTessellationState
;
1956 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1958 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1959 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
1961 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];
1966 #define WRITE_STR(field, ...) ({ \
1967 memset(field, 0, sizeof(field)); \
1968 UNUSED int i = snprintf(field, sizeof(field), __VA_ARGS__); \
1969 assert(i > 0 && i < sizeof(field)); \
1972 VkResult
anv_GetPipelineExecutablePropertiesKHR(
1974 const VkPipelineInfoKHR
* pPipelineInfo
,
1975 uint32_t* pExecutableCount
,
1976 VkPipelineExecutablePropertiesKHR
* pProperties
)
1978 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
1979 VK_OUTARRAY_MAKE(out
, pProperties
, pExecutableCount
);
1981 util_dynarray_foreach (&pipeline
->executables
, struct anv_pipeline_executable
, exe
) {
1982 vk_outarray_append(&out
, props
) {
1983 gl_shader_stage stage
= exe
->stage
;
1984 props
->stages
= mesa_to_vk_shader_stage(stage
);
1986 unsigned simd_width
= exe
->stats
.dispatch_width
;
1987 if (stage
== MESA_SHADER_FRAGMENT
) {
1988 WRITE_STR(props
->name
, "%s%d %s",
1989 simd_width
? "SIMD" : "vec",
1990 simd_width
? simd_width
: 4,
1991 _mesa_shader_stage_to_string(stage
));
1993 WRITE_STR(props
->name
, "%s", _mesa_shader_stage_to_string(stage
));
1995 WRITE_STR(props
->description
, "%s%d %s shader",
1996 simd_width
? "SIMD" : "vec",
1997 simd_width
? simd_width
: 4,
1998 _mesa_shader_stage_to_string(stage
));
2000 /* The compiler gives us a dispatch width of 0 for vec4 but Vulkan
2001 * wants a subgroup size of 1.
2003 props
->subgroupSize
= MAX2(simd_width
, 1);
2007 return vk_outarray_status(&out
);
2010 static const struct anv_pipeline_executable
*
2011 anv_pipeline_get_executable(struct anv_pipeline
*pipeline
, uint32_t index
)
2013 assert(index
< util_dynarray_num_elements(&pipeline
->executables
,
2014 struct anv_pipeline_executable
));
2015 return util_dynarray_element(
2016 &pipeline
->executables
, struct anv_pipeline_executable
, index
);
2019 VkResult
anv_GetPipelineExecutableStatisticsKHR(
2021 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
2022 uint32_t* pStatisticCount
,
2023 VkPipelineExecutableStatisticKHR
* pStatistics
)
2025 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
2026 VK_OUTARRAY_MAKE(out
, pStatistics
, pStatisticCount
);
2028 const struct anv_pipeline_executable
*exe
=
2029 anv_pipeline_get_executable(pipeline
, pExecutableInfo
->executableIndex
);
2030 const struct brw_stage_prog_data
*prog_data
=
2031 pipeline
->shaders
[exe
->stage
]->prog_data
;
2033 vk_outarray_append(&out
, stat
) {
2034 WRITE_STR(stat
->name
, "Instruction Count");
2035 WRITE_STR(stat
->description
,
2036 "Number of GEN instructions in the final generated "
2037 "shader executable.");
2038 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2039 stat
->value
.u64
= exe
->stats
.instructions
;
2042 vk_outarray_append(&out
, stat
) {
2043 WRITE_STR(stat
->name
, "Loop Count");
2044 WRITE_STR(stat
->description
,
2045 "Number of loops (not unrolled) in the final generated "
2046 "shader executable.");
2047 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2048 stat
->value
.u64
= exe
->stats
.loops
;
2051 vk_outarray_append(&out
, stat
) {
2052 WRITE_STR(stat
->name
, "Cycle Count");
2053 WRITE_STR(stat
->description
,
2054 "Estimate of the number of EU cycles required to execute "
2055 "the final generated executable. This is an estimate only "
2056 "and may vary greatly from actual run-time performance.");
2057 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2058 stat
->value
.u64
= exe
->stats
.cycles
;
2061 vk_outarray_append(&out
, stat
) {
2062 WRITE_STR(stat
->name
, "Spill Count");
2063 WRITE_STR(stat
->description
,
2064 "Number of scratch spill operations. This gives a rough "
2065 "estimate of the cost incurred due to spilling temporary "
2066 "values to memory. If this is non-zero, you may want to "
2067 "adjust your shader to reduce register pressure.");
2068 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2069 stat
->value
.u64
= exe
->stats
.spills
;
2072 vk_outarray_append(&out
, stat
) {
2073 WRITE_STR(stat
->name
, "Fill Count");
2074 WRITE_STR(stat
->description
,
2075 "Number of scratch fill operations. This gives a rough "
2076 "estimate of the cost incurred due to spilling temporary "
2077 "values to memory. If this is non-zero, you may want to "
2078 "adjust your shader to reduce register pressure.");
2079 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2080 stat
->value
.u64
= exe
->stats
.fills
;
2083 vk_outarray_append(&out
, stat
) {
2084 WRITE_STR(stat
->name
, "Scratch Memory Size");
2085 WRITE_STR(stat
->description
,
2086 "Number of bytes of scratch memory required by the "
2087 "generated shader executable. If this is non-zero, you "
2088 "may want to adjust your shader to reduce register "
2090 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2091 stat
->value
.u64
= prog_data
->total_scratch
;
2094 if (exe
->stage
== MESA_SHADER_COMPUTE
) {
2095 vk_outarray_append(&out
, stat
) {
2096 WRITE_STR(stat
->name
, "Workgroup Memory Size");
2097 WRITE_STR(stat
->description
,
2098 "Number of bytes of workgroup shared memory used by this "
2099 "compute shader including any padding.");
2100 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2101 stat
->value
.u64
= prog_data
->total_scratch
;
2105 return vk_outarray_status(&out
);
2109 write_ir_text(VkPipelineExecutableInternalRepresentationKHR
* ir
,
2112 ir
->isText
= VK_TRUE
;
2114 size_t data_len
= strlen(data
) + 1;
2116 if (ir
->pData
== NULL
) {
2117 ir
->dataSize
= data_len
;
2121 strncpy(ir
->pData
, data
, ir
->dataSize
);
2122 if (ir
->dataSize
< data_len
)
2125 ir
->dataSize
= data_len
;
2129 VkResult
anv_GetPipelineExecutableInternalRepresentationsKHR(
2131 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
2132 uint32_t* pInternalRepresentationCount
,
2133 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
2135 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
2136 VK_OUTARRAY_MAKE(out
, pInternalRepresentations
,
2137 pInternalRepresentationCount
);
2138 bool incomplete_text
= false;
2140 const struct anv_pipeline_executable
*exe
=
2141 anv_pipeline_get_executable(pipeline
, pExecutableInfo
->executableIndex
);
2144 vk_outarray_append(&out
, ir
) {
2145 WRITE_STR(ir
->name
, "Final NIR");
2146 WRITE_STR(ir
->description
,
2147 "Final NIR before going into the back-end compiler");
2149 if (!write_ir_text(ir
, exe
->nir
))
2150 incomplete_text
= true;
2155 vk_outarray_append(&out
, ir
) {
2156 WRITE_STR(ir
->name
, "GEN Assembly");
2157 WRITE_STR(ir
->description
,
2158 "Final GEN assembly for the generated shader binary");
2160 if (!write_ir_text(ir
, exe
->disasm
))
2161 incomplete_text
= true;
2165 return incomplete_text
? VK_INCOMPLETE
: vk_outarray_status(&out
);