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anv: Rework fences
[mesa.git] / src / intel / vulkan / anv_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "util/mesa-sha1.h"
31 #include "common/gen_l3_config.h"
32 #include "anv_private.h"
33 #include "brw_nir.h"
34 #include "anv_nir.h"
35 #include "spirv/nir_spirv.h"
36
37 /* Needed for SWIZZLE macros */
38 #include "program/prog_instruction.h"
39
40 // Shader functions
41
42 VkResult anv_CreateShaderModule(
43 VkDevice _device,
44 const VkShaderModuleCreateInfo* pCreateInfo,
45 const VkAllocationCallbacks* pAllocator,
46 VkShaderModule* pShaderModule)
47 {
48 ANV_FROM_HANDLE(anv_device, device, _device);
49 struct anv_shader_module *module;
50
51 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
52 assert(pCreateInfo->flags == 0);
53
54 module = vk_alloc2(&device->alloc, pAllocator,
55 sizeof(*module) + pCreateInfo->codeSize, 8,
56 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
57 if (module == NULL)
58 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
59
60 module->size = pCreateInfo->codeSize;
61 memcpy(module->data, pCreateInfo->pCode, module->size);
62
63 _mesa_sha1_compute(module->data, module->size, module->sha1);
64
65 *pShaderModule = anv_shader_module_to_handle(module);
66
67 return VK_SUCCESS;
68 }
69
70 void anv_DestroyShaderModule(
71 VkDevice _device,
72 VkShaderModule _module,
73 const VkAllocationCallbacks* pAllocator)
74 {
75 ANV_FROM_HANDLE(anv_device, device, _device);
76 ANV_FROM_HANDLE(anv_shader_module, module, _module);
77
78 vk_free2(&device->alloc, pAllocator, module);
79 }
80
81 #define SPIR_V_MAGIC_NUMBER 0x07230203
82
83 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
84 * we can't do that yet because we don't have the ability to copy nir.
85 */
86 static nir_shader *
87 anv_shader_compile_to_nir(struct anv_device *device,
88 struct anv_shader_module *module,
89 const char *entrypoint_name,
90 gl_shader_stage stage,
91 const VkSpecializationInfo *spec_info)
92 {
93 if (strcmp(entrypoint_name, "main") != 0) {
94 anv_finishme("Multiple shaders per module not really supported");
95 }
96
97 const struct brw_compiler *compiler =
98 device->instance->physicalDevice.compiler;
99 const nir_shader_compiler_options *nir_options =
100 compiler->glsl_compiler_options[stage].NirOptions;
101
102 uint32_t *spirv = (uint32_t *) module->data;
103 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
104 assert(module->size % 4 == 0);
105
106 uint32_t num_spec_entries = 0;
107 struct nir_spirv_specialization *spec_entries = NULL;
108 if (spec_info && spec_info->mapEntryCount > 0) {
109 num_spec_entries = spec_info->mapEntryCount;
110 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
111 for (uint32_t i = 0; i < num_spec_entries; i++) {
112 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
113 const void *data = spec_info->pData + entry.offset;
114 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
115
116 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
117 spec_entries[i].data = *(const uint32_t *)data;
118 }
119 }
120
121 nir_function *entry_point =
122 spirv_to_nir(spirv, module->size / 4,
123 spec_entries, num_spec_entries,
124 stage, entrypoint_name, nir_options);
125 nir_shader *nir = entry_point->shader;
126 assert(nir->stage == stage);
127 nir_validate_shader(nir);
128
129 free(spec_entries);
130
131 if (stage == MESA_SHADER_FRAGMENT) {
132 nir_lower_wpos_center(nir);
133 nir_validate_shader(nir);
134 }
135
136 nir_lower_returns(nir);
137 nir_validate_shader(nir);
138
139 nir_inline_functions(nir);
140 nir_validate_shader(nir);
141
142 /* Pick off the single entrypoint that we want */
143 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
144 if (func != entry_point)
145 exec_node_remove(&func->node);
146 }
147 assert(exec_list_length(&nir->functions) == 1);
148 entry_point->name = ralloc_strdup(entry_point, "main");
149
150 nir_remove_dead_variables(nir, nir_var_shader_in);
151 nir_remove_dead_variables(nir, nir_var_shader_out);
152 nir_remove_dead_variables(nir, nir_var_system_value);
153 nir_validate_shader(nir);
154
155 nir_propagate_invariant(nir);
156 nir_validate_shader(nir);
157
158 nir_lower_io_to_temporaries(entry_point->shader, entry_point->impl,
159 true, false);
160
161 nir_lower_system_values(nir);
162 nir_validate_shader(nir);
163
164 /* Vulkan uses the separate-shader linking model */
165 nir->info->separate_shader = true;
166
167 nir = brw_preprocess_nir(compiler, nir);
168
169 nir_shader_gather_info(nir, entry_point->impl);
170
171 nir_variable_mode indirect_mask = 0;
172 if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput)
173 indirect_mask |= nir_var_shader_in;
174 if (compiler->glsl_compiler_options[stage].EmitNoIndirectOutput)
175 indirect_mask |= nir_var_shader_out;
176 if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
177 indirect_mask |= nir_var_local;
178
179 nir_lower_indirect_derefs(nir, indirect_mask);
180
181 return nir;
182 }
183
184 void anv_DestroyPipeline(
185 VkDevice _device,
186 VkPipeline _pipeline,
187 const VkAllocationCallbacks* pAllocator)
188 {
189 ANV_FROM_HANDLE(anv_device, device, _device);
190 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
191
192 anv_reloc_list_finish(&pipeline->batch_relocs,
193 pAllocator ? pAllocator : &device->alloc);
194 if (pipeline->blend_state.map)
195 anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
196
197 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
198 if (pipeline->shaders[s])
199 anv_shader_bin_unref(device, pipeline->shaders[s]);
200 }
201
202 vk_free2(&device->alloc, pAllocator, pipeline);
203 }
204
205 static const uint32_t vk_to_gen_primitive_type[] = {
206 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
207 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
208 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
209 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
210 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
211 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
212 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
213 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
214 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
215 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
216 /* [VK_PRIMITIVE_TOPOLOGY_PATCH_LIST] = _3DPRIM_PATCHLIST_1 */
217 };
218
219 static void
220 populate_sampler_prog_key(const struct gen_device_info *devinfo,
221 struct brw_sampler_prog_key_data *key)
222 {
223 /* XXX: Handle texture swizzle on HSW- */
224 for (int i = 0; i < MAX_SAMPLERS; i++) {
225 /* Assume color sampler, no swizzling. (Works for BDW+) */
226 key->swizzles[i] = SWIZZLE_XYZW;
227 }
228 }
229
230 static void
231 populate_vs_prog_key(const struct gen_device_info *devinfo,
232 struct brw_vs_prog_key *key)
233 {
234 memset(key, 0, sizeof(*key));
235
236 populate_sampler_prog_key(devinfo, &key->tex);
237
238 /* XXX: Handle vertex input work-arounds */
239
240 /* XXX: Handle sampler_prog_key */
241 }
242
243 static void
244 populate_gs_prog_key(const struct gen_device_info *devinfo,
245 struct brw_gs_prog_key *key)
246 {
247 memset(key, 0, sizeof(*key));
248
249 populate_sampler_prog_key(devinfo, &key->tex);
250 }
251
252 static void
253 populate_wm_prog_key(const struct gen_device_info *devinfo,
254 const VkGraphicsPipelineCreateInfo *info,
255 struct brw_wm_prog_key *key)
256 {
257 ANV_FROM_HANDLE(anv_render_pass, render_pass, info->renderPass);
258
259 memset(key, 0, sizeof(*key));
260
261 populate_sampler_prog_key(devinfo, &key->tex);
262
263 /* TODO: Fill out key->input_slots_valid */
264
265 /* Vulkan doesn't specify a default */
266 key->high_quality_derivatives = false;
267
268 /* XXX Vulkan doesn't appear to specify */
269 key->clamp_fragment_color = false;
270
271 key->nr_color_regions =
272 render_pass->subpasses[info->subpass].color_count;
273
274 key->replicate_alpha = key->nr_color_regions > 1 &&
275 info->pMultisampleState &&
276 info->pMultisampleState->alphaToCoverageEnable;
277
278 if (info->pMultisampleState && info->pMultisampleState->rasterizationSamples > 1) {
279 /* We should probably pull this out of the shader, but it's fairly
280 * harmless to compute it and then let dead-code take care of it.
281 */
282 key->persample_interp =
283 (info->pMultisampleState->minSampleShading *
284 info->pMultisampleState->rasterizationSamples) > 1;
285 key->multisample_fbo = true;
286 }
287 }
288
289 static void
290 populate_cs_prog_key(const struct gen_device_info *devinfo,
291 struct brw_cs_prog_key *key)
292 {
293 memset(key, 0, sizeof(*key));
294
295 populate_sampler_prog_key(devinfo, &key->tex);
296 }
297
298 static nir_shader *
299 anv_pipeline_compile(struct anv_pipeline *pipeline,
300 struct anv_shader_module *module,
301 const char *entrypoint,
302 gl_shader_stage stage,
303 const VkSpecializationInfo *spec_info,
304 struct brw_stage_prog_data *prog_data,
305 struct anv_pipeline_bind_map *map)
306 {
307 nir_shader *nir = anv_shader_compile_to_nir(pipeline->device,
308 module, entrypoint, stage,
309 spec_info);
310 if (nir == NULL)
311 return NULL;
312
313 anv_nir_lower_push_constants(nir);
314
315 /* Figure out the number of parameters */
316 prog_data->nr_params = 0;
317
318 if (nir->num_uniforms > 0) {
319 /* If the shader uses any push constants at all, we'll just give
320 * them the maximum possible number
321 */
322 assert(nir->num_uniforms <= MAX_PUSH_CONSTANTS_SIZE);
323 prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
324 }
325
326 if (pipeline->layout && pipeline->layout->stage[stage].has_dynamic_offsets)
327 prog_data->nr_params += MAX_DYNAMIC_BUFFERS * 2;
328
329 if (nir->info->num_images > 0) {
330 prog_data->nr_params += nir->info->num_images * BRW_IMAGE_PARAM_SIZE;
331 pipeline->needs_data_cache = true;
332 }
333
334 if (stage == MESA_SHADER_COMPUTE)
335 ((struct brw_cs_prog_data *)prog_data)->thread_local_id_index =
336 prog_data->nr_params++; /* The CS Thread ID uniform */
337
338 if (nir->info->num_ssbos > 0)
339 pipeline->needs_data_cache = true;
340
341 if (prog_data->nr_params > 0) {
342 /* XXX: I think we're leaking this */
343 prog_data->param = (const union gl_constant_value **)
344 malloc(prog_data->nr_params * sizeof(union gl_constant_value *));
345
346 /* We now set the param values to be offsets into a
347 * anv_push_constant_data structure. Since the compiler doesn't
348 * actually dereference any of the gl_constant_value pointers in the
349 * params array, it doesn't really matter what we put here.
350 */
351 struct anv_push_constants *null_data = NULL;
352 if (nir->num_uniforms > 0) {
353 /* Fill out the push constants section of the param array */
354 for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++)
355 prog_data->param[i] = (const union gl_constant_value *)
356 &null_data->client_data[i * sizeof(float)];
357 }
358 }
359
360 /* Set up dynamic offsets */
361 anv_nir_apply_dynamic_offsets(pipeline, nir, prog_data);
362
363 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
364 if (pipeline->layout)
365 anv_nir_apply_pipeline_layout(pipeline, nir, prog_data, map);
366
367 /* nir_lower_io will only handle the push constants; we need to set this
368 * to the full number of possible uniforms.
369 */
370 nir->num_uniforms = prog_data->nr_params * 4;
371
372 return nir;
373 }
374
375 static void
376 anv_fill_binding_table(struct brw_stage_prog_data *prog_data, unsigned bias)
377 {
378 prog_data->binding_table.size_bytes = 0;
379 prog_data->binding_table.texture_start = bias;
380 prog_data->binding_table.gather_texture_start = bias;
381 prog_data->binding_table.ubo_start = bias;
382 prog_data->binding_table.ssbo_start = bias;
383 prog_data->binding_table.image_start = bias;
384 }
385
386 static struct anv_shader_bin *
387 anv_pipeline_upload_kernel(struct anv_pipeline *pipeline,
388 struct anv_pipeline_cache *cache,
389 const void *key_data, uint32_t key_size,
390 const void *kernel_data, uint32_t kernel_size,
391 const struct brw_stage_prog_data *prog_data,
392 uint32_t prog_data_size,
393 const struct anv_pipeline_bind_map *bind_map)
394 {
395 if (cache) {
396 return anv_pipeline_cache_upload_kernel(cache, key_data, key_size,
397 kernel_data, kernel_size,
398 prog_data, prog_data_size,
399 bind_map);
400 } else {
401 return anv_shader_bin_create(pipeline->device, key_data, key_size,
402 kernel_data, kernel_size,
403 prog_data, prog_data_size,
404 prog_data->param, bind_map);
405 }
406 }
407
408
409 static void
410 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
411 gl_shader_stage stage,
412 struct anv_shader_bin *shader)
413 {
414 pipeline->shaders[stage] = shader;
415 pipeline->active_stages |= mesa_to_vk_shader_stage(stage);
416 }
417
418 static VkResult
419 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
420 struct anv_pipeline_cache *cache,
421 const VkGraphicsPipelineCreateInfo *info,
422 struct anv_shader_module *module,
423 const char *entrypoint,
424 const VkSpecializationInfo *spec_info)
425 {
426 const struct brw_compiler *compiler =
427 pipeline->device->instance->physicalDevice.compiler;
428 struct anv_pipeline_bind_map map;
429 struct brw_vs_prog_key key;
430 struct anv_shader_bin *bin = NULL;
431 unsigned char sha1[20];
432
433 populate_vs_prog_key(&pipeline->device->info, &key);
434
435 if (cache) {
436 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint,
437 pipeline->layout, spec_info);
438 bin = anv_pipeline_cache_search(cache, sha1, 20);
439 }
440
441 if (bin == NULL) {
442 struct brw_vs_prog_data prog_data = { 0, };
443 struct anv_pipeline_binding surface_to_descriptor[256];
444 struct anv_pipeline_binding sampler_to_descriptor[256];
445
446 map = (struct anv_pipeline_bind_map) {
447 .surface_to_descriptor = surface_to_descriptor,
448 .sampler_to_descriptor = sampler_to_descriptor
449 };
450
451 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
452 MESA_SHADER_VERTEX, spec_info,
453 &prog_data.base.base, &map);
454 if (nir == NULL)
455 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
456
457 anv_fill_binding_table(&prog_data.base.base, 0);
458
459 void *mem_ctx = ralloc_context(NULL);
460
461 ralloc_steal(mem_ctx, nir);
462
463 prog_data.inputs_read = nir->info->inputs_read;
464
465 brw_compute_vue_map(&pipeline->device->info,
466 &prog_data.base.vue_map,
467 nir->info->outputs_written,
468 nir->info->separate_shader);
469
470 unsigned code_size;
471 const unsigned *shader_code =
472 brw_compile_vs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
473 NULL, false, -1, &code_size, NULL);
474 if (shader_code == NULL) {
475 ralloc_free(mem_ctx);
476 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
477 }
478
479 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
480 shader_code, code_size,
481 &prog_data.base.base, sizeof(prog_data),
482 &map);
483 if (!bin) {
484 ralloc_free(mem_ctx);
485 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
486 }
487
488 ralloc_free(mem_ctx);
489 }
490
491 const struct brw_vs_prog_data *vs_prog_data =
492 (const struct brw_vs_prog_data *)bin->prog_data;
493
494 if (vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8) {
495 pipeline->vs_simd8 = bin->kernel.offset;
496 pipeline->vs_vec4 = NO_KERNEL;
497 } else {
498 pipeline->vs_simd8 = NO_KERNEL;
499 pipeline->vs_vec4 = bin->kernel.offset;
500 }
501
502 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX, bin);
503
504 return VK_SUCCESS;
505 }
506
507 static VkResult
508 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
509 struct anv_pipeline_cache *cache,
510 const VkGraphicsPipelineCreateInfo *info,
511 struct anv_shader_module *module,
512 const char *entrypoint,
513 const VkSpecializationInfo *spec_info)
514 {
515 const struct brw_compiler *compiler =
516 pipeline->device->instance->physicalDevice.compiler;
517 struct anv_pipeline_bind_map map;
518 struct brw_gs_prog_key key;
519 struct anv_shader_bin *bin = NULL;
520 unsigned char sha1[20];
521
522 populate_gs_prog_key(&pipeline->device->info, &key);
523
524 if (cache) {
525 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint,
526 pipeline->layout, spec_info);
527 bin = anv_pipeline_cache_search(cache, sha1, 20);
528 }
529
530 if (bin == NULL) {
531 struct brw_gs_prog_data prog_data = { 0, };
532 struct anv_pipeline_binding surface_to_descriptor[256];
533 struct anv_pipeline_binding sampler_to_descriptor[256];
534
535 map = (struct anv_pipeline_bind_map) {
536 .surface_to_descriptor = surface_to_descriptor,
537 .sampler_to_descriptor = sampler_to_descriptor
538 };
539
540 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
541 MESA_SHADER_GEOMETRY, spec_info,
542 &prog_data.base.base, &map);
543 if (nir == NULL)
544 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
545
546 anv_fill_binding_table(&prog_data.base.base, 0);
547
548 void *mem_ctx = ralloc_context(NULL);
549
550 ralloc_steal(mem_ctx, nir);
551
552 brw_compute_vue_map(&pipeline->device->info,
553 &prog_data.base.vue_map,
554 nir->info->outputs_written,
555 nir->info->separate_shader);
556
557 unsigned code_size;
558 const unsigned *shader_code =
559 brw_compile_gs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
560 NULL, -1, &code_size, NULL);
561 if (shader_code == NULL) {
562 ralloc_free(mem_ctx);
563 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
564 }
565
566 /* TODO: SIMD8 GS */
567 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
568 shader_code, code_size,
569 &prog_data.base.base, sizeof(prog_data),
570 &map);
571 if (!bin) {
572 ralloc_free(mem_ctx);
573 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
574 }
575
576 ralloc_free(mem_ctx);
577 }
578
579 pipeline->gs_kernel = bin->kernel.offset;
580
581 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY, bin);
582
583 return VK_SUCCESS;
584 }
585
586 static VkResult
587 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
588 struct anv_pipeline_cache *cache,
589 const VkGraphicsPipelineCreateInfo *info,
590 struct anv_shader_module *module,
591 const char *entrypoint,
592 const VkSpecializationInfo *spec_info)
593 {
594 const struct brw_compiler *compiler =
595 pipeline->device->instance->physicalDevice.compiler;
596 struct anv_pipeline_bind_map map;
597 struct brw_wm_prog_key key;
598 struct anv_shader_bin *bin = NULL;
599 unsigned char sha1[20];
600
601 populate_wm_prog_key(&pipeline->device->info, info, &key);
602
603 if (cache) {
604 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint,
605 pipeline->layout, spec_info);
606 bin = anv_pipeline_cache_search(cache, sha1, 20);
607 }
608
609 if (bin == NULL) {
610 struct brw_wm_prog_data prog_data = { 0, };
611 struct anv_pipeline_binding surface_to_descriptor[256];
612 struct anv_pipeline_binding sampler_to_descriptor[256];
613
614 map = (struct anv_pipeline_bind_map) {
615 .surface_to_descriptor = surface_to_descriptor + 8,
616 .sampler_to_descriptor = sampler_to_descriptor
617 };
618
619 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
620 MESA_SHADER_FRAGMENT, spec_info,
621 &prog_data.base, &map);
622 if (nir == NULL)
623 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
624
625 unsigned num_rts = 0;
626 struct anv_pipeline_binding rt_bindings[8];
627 nir_function_impl *impl = nir_shader_get_entrypoint(nir);
628 nir_foreach_variable_safe(var, &nir->outputs) {
629 if (var->data.location < FRAG_RESULT_DATA0)
630 continue;
631
632 unsigned rt = var->data.location - FRAG_RESULT_DATA0;
633 if (rt >= key.nr_color_regions) {
634 /* Out-of-bounds, throw it away */
635 var->data.mode = nir_var_local;
636 exec_node_remove(&var->node);
637 exec_list_push_tail(&impl->locals, &var->node);
638 continue;
639 }
640
641 /* Give it a new, compacted, location */
642 var->data.location = FRAG_RESULT_DATA0 + num_rts;
643
644 unsigned array_len =
645 glsl_type_is_array(var->type) ? glsl_get_length(var->type) : 1;
646 assert(num_rts + array_len <= 8);
647
648 for (unsigned i = 0; i < array_len; i++) {
649 rt_bindings[num_rts + i] = (struct anv_pipeline_binding) {
650 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
651 .binding = 0,
652 .index = rt + i,
653 };
654 }
655
656 num_rts += array_len;
657 }
658
659 if (num_rts == 0) {
660 /* If we have no render targets, we need a null render target */
661 rt_bindings[0] = (struct anv_pipeline_binding) {
662 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
663 .binding = 0,
664 .index = UINT8_MAX,
665 };
666 num_rts = 1;
667 }
668
669 assert(num_rts <= 8);
670 map.surface_to_descriptor -= num_rts;
671 map.surface_count += num_rts;
672 assert(map.surface_count <= 256);
673 memcpy(map.surface_to_descriptor, rt_bindings,
674 num_rts * sizeof(*rt_bindings));
675
676 anv_fill_binding_table(&prog_data.base, num_rts);
677
678 void *mem_ctx = ralloc_context(NULL);
679
680 ralloc_steal(mem_ctx, nir);
681
682 unsigned code_size;
683 const unsigned *shader_code =
684 brw_compile_fs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
685 NULL, -1, -1, true, false, NULL, &code_size, NULL);
686 if (shader_code == NULL) {
687 ralloc_free(mem_ctx);
688 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
689 }
690
691 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
692 shader_code, code_size,
693 &prog_data.base, sizeof(prog_data),
694 &map);
695 if (!bin) {
696 ralloc_free(mem_ctx);
697 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
698 }
699
700 ralloc_free(mem_ctx);
701 }
702
703 pipeline->ps_ksp0 = bin->kernel.offset;
704
705 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT, bin);
706
707 return VK_SUCCESS;
708 }
709
710 VkResult
711 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
712 struct anv_pipeline_cache *cache,
713 const VkComputePipelineCreateInfo *info,
714 struct anv_shader_module *module,
715 const char *entrypoint,
716 const VkSpecializationInfo *spec_info)
717 {
718 const struct brw_compiler *compiler =
719 pipeline->device->instance->physicalDevice.compiler;
720 struct anv_pipeline_bind_map map;
721 struct brw_cs_prog_key key;
722 struct anv_shader_bin *bin = NULL;
723 unsigned char sha1[20];
724
725 populate_cs_prog_key(&pipeline->device->info, &key);
726
727 if (cache) {
728 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint,
729 pipeline->layout, spec_info);
730 bin = anv_pipeline_cache_search(cache, sha1, 20);
731 }
732
733 if (bin == NULL) {
734 struct brw_cs_prog_data prog_data = { 0, };
735 struct anv_pipeline_binding surface_to_descriptor[256];
736 struct anv_pipeline_binding sampler_to_descriptor[256];
737
738 map = (struct anv_pipeline_bind_map) {
739 .surface_to_descriptor = surface_to_descriptor,
740 .sampler_to_descriptor = sampler_to_descriptor
741 };
742
743 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
744 MESA_SHADER_COMPUTE, spec_info,
745 &prog_data.base, &map);
746 if (nir == NULL)
747 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
748
749 anv_fill_binding_table(&prog_data.base, 1);
750
751 void *mem_ctx = ralloc_context(NULL);
752
753 ralloc_steal(mem_ctx, nir);
754
755 unsigned code_size;
756 const unsigned *shader_code =
757 brw_compile_cs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
758 -1, &code_size, NULL);
759 if (shader_code == NULL) {
760 ralloc_free(mem_ctx);
761 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
762 }
763
764 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
765 shader_code, code_size,
766 &prog_data.base, sizeof(prog_data),
767 &map);
768 if (!bin) {
769 ralloc_free(mem_ctx);
770 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
771 }
772
773 ralloc_free(mem_ctx);
774 }
775
776 pipeline->cs_simd = bin->kernel.offset;
777
778 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE, bin);
779
780 return VK_SUCCESS;
781 }
782
783 /**
784 * Copy pipeline state not marked as dynamic.
785 * Dynamic state is pipeline state which hasn't been provided at pipeline
786 * creation time, but is dynamically provided afterwards using various
787 * vkCmdSet* functions.
788 *
789 * The set of state considered "non_dynamic" is determined by the pieces of
790 * state that have their corresponding VkDynamicState enums omitted from
791 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
792 *
793 * @param[out] pipeline Destination non_dynamic state.
794 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
795 */
796 static void
797 copy_non_dynamic_state(struct anv_pipeline *pipeline,
798 const VkGraphicsPipelineCreateInfo *pCreateInfo)
799 {
800 anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
801 ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
802 struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
803
804 pipeline->dynamic_state = default_dynamic_state;
805
806 if (pCreateInfo->pDynamicState) {
807 /* Remove all of the states that are marked as dynamic */
808 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
809 for (uint32_t s = 0; s < count; s++)
810 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
811 }
812
813 struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
814
815 /* Section 9.2 of the Vulkan 1.0.15 spec says:
816 *
817 * pViewportState is [...] NULL if the pipeline
818 * has rasterization disabled.
819 */
820 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
821 assert(pCreateInfo->pViewportState);
822
823 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
824 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
825 typed_memcpy(dynamic->viewport.viewports,
826 pCreateInfo->pViewportState->pViewports,
827 pCreateInfo->pViewportState->viewportCount);
828 }
829
830 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
831 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
832 typed_memcpy(dynamic->scissor.scissors,
833 pCreateInfo->pViewportState->pScissors,
834 pCreateInfo->pViewportState->scissorCount);
835 }
836 }
837
838 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
839 assert(pCreateInfo->pRasterizationState);
840 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
841 }
842
843 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
844 assert(pCreateInfo->pRasterizationState);
845 dynamic->depth_bias.bias =
846 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
847 dynamic->depth_bias.clamp =
848 pCreateInfo->pRasterizationState->depthBiasClamp;
849 dynamic->depth_bias.slope =
850 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
851 }
852
853 /* Section 9.2 of the Vulkan 1.0.15 spec says:
854 *
855 * pColorBlendState is [...] NULL if the pipeline has rasterization
856 * disabled or if the subpass of the render pass the pipeline is
857 * created against does not use any color attachments.
858 */
859 bool uses_color_att = false;
860 for (unsigned i = 0; i < subpass->color_count; ++i) {
861 if (subpass->color_attachments[i] != VK_ATTACHMENT_UNUSED) {
862 uses_color_att = true;
863 break;
864 }
865 }
866
867 if (uses_color_att &&
868 !pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
869 assert(pCreateInfo->pColorBlendState);
870
871 if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
872 typed_memcpy(dynamic->blend_constants,
873 pCreateInfo->pColorBlendState->blendConstants, 4);
874 }
875
876 /* If there is no depthstencil attachment, then don't read
877 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
878 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
879 * no need to override the depthstencil defaults in
880 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
881 *
882 * Section 9.2 of the Vulkan 1.0.15 spec says:
883 *
884 * pDepthStencilState is [...] NULL if the pipeline has rasterization
885 * disabled or if the subpass of the render pass the pipeline is created
886 * against does not use a depth/stencil attachment.
887 */
888 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
889 subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
890 assert(pCreateInfo->pDepthStencilState);
891
892 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
893 dynamic->depth_bounds.min =
894 pCreateInfo->pDepthStencilState->minDepthBounds;
895 dynamic->depth_bounds.max =
896 pCreateInfo->pDepthStencilState->maxDepthBounds;
897 }
898
899 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
900 dynamic->stencil_compare_mask.front =
901 pCreateInfo->pDepthStencilState->front.compareMask;
902 dynamic->stencil_compare_mask.back =
903 pCreateInfo->pDepthStencilState->back.compareMask;
904 }
905
906 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
907 dynamic->stencil_write_mask.front =
908 pCreateInfo->pDepthStencilState->front.writeMask;
909 dynamic->stencil_write_mask.back =
910 pCreateInfo->pDepthStencilState->back.writeMask;
911 }
912
913 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
914 dynamic->stencil_reference.front =
915 pCreateInfo->pDepthStencilState->front.reference;
916 dynamic->stencil_reference.back =
917 pCreateInfo->pDepthStencilState->back.reference;
918 }
919 }
920
921 pipeline->dynamic_state_mask = states;
922 }
923
924 static void
925 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
926 {
927 struct anv_render_pass *renderpass = NULL;
928 struct anv_subpass *subpass = NULL;
929
930 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
931 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
932 */
933 assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
934
935 renderpass = anv_render_pass_from_handle(info->renderPass);
936 assert(renderpass);
937
938 assert(info->subpass < renderpass->subpass_count);
939 subpass = &renderpass->subpasses[info->subpass];
940
941 assert(info->stageCount >= 1);
942 assert(info->pVertexInputState);
943 assert(info->pInputAssemblyState);
944 assert(info->pRasterizationState);
945 if (!info->pRasterizationState->rasterizerDiscardEnable) {
946 assert(info->pViewportState);
947 assert(info->pMultisampleState);
948
949 if (subpass && subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED)
950 assert(info->pDepthStencilState);
951
952 if (subpass && subpass->color_count > 0)
953 assert(info->pColorBlendState);
954 }
955
956 for (uint32_t i = 0; i < info->stageCount; ++i) {
957 switch (info->pStages[i].stage) {
958 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
959 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
960 assert(info->pTessellationState);
961 break;
962 default:
963 break;
964 }
965 }
966 }
967
968 /**
969 * Calculate the desired L3 partitioning based on the current state of the
970 * pipeline. For now this simply returns the conservative defaults calculated
971 * by get_default_l3_weights(), but we could probably do better by gathering
972 * more statistics from the pipeline state (e.g. guess of expected URB usage
973 * and bound surfaces), or by using feed-back from performance counters.
974 */
975 void
976 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm)
977 {
978 const struct gen_device_info *devinfo = &pipeline->device->info;
979
980 const struct gen_l3_weights w =
981 gen_get_default_l3_weights(devinfo, pipeline->needs_data_cache, needs_slm);
982
983 pipeline->urb.l3_config = gen_get_l3_config(devinfo, w);
984 pipeline->urb.total_size =
985 gen_get_l3_config_urb_size(devinfo, pipeline->urb.l3_config);
986 }
987
988 VkResult
989 anv_pipeline_init(struct anv_pipeline *pipeline,
990 struct anv_device *device,
991 struct anv_pipeline_cache *cache,
992 const VkGraphicsPipelineCreateInfo *pCreateInfo,
993 const VkAllocationCallbacks *alloc)
994 {
995 VkResult result;
996
997 anv_validate {
998 anv_pipeline_validate_create_info(pCreateInfo);
999 }
1000
1001 if (alloc == NULL)
1002 alloc = &device->alloc;
1003
1004 pipeline->device = device;
1005 pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
1006
1007 result = anv_reloc_list_init(&pipeline->batch_relocs, alloc);
1008 if (result != VK_SUCCESS)
1009 return result;
1010
1011 pipeline->batch.alloc = alloc;
1012 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
1013 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
1014 pipeline->batch.relocs = &pipeline->batch_relocs;
1015
1016 copy_non_dynamic_state(pipeline, pCreateInfo);
1017 pipeline->depth_clamp_enable = pCreateInfo->pRasterizationState &&
1018 pCreateInfo->pRasterizationState->depthClampEnable;
1019
1020 pipeline->needs_data_cache = false;
1021
1022 /* When we free the pipeline, we detect stages based on the NULL status
1023 * of various prog_data pointers. Make them NULL by default.
1024 */
1025 memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
1026
1027 pipeline->vs_simd8 = NO_KERNEL;
1028 pipeline->vs_vec4 = NO_KERNEL;
1029 pipeline->gs_kernel = NO_KERNEL;
1030 pipeline->ps_ksp0 = NO_KERNEL;
1031
1032 pipeline->active_stages = 0;
1033
1034 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1035 struct anv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1036 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1037 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1038 pStages[stage] = &pCreateInfo->pStages[i];
1039 modules[stage] = anv_shader_module_from_handle(pStages[stage]->module);
1040 }
1041
1042 if (modules[MESA_SHADER_VERTEX]) {
1043 result = anv_pipeline_compile_vs(pipeline, cache, pCreateInfo,
1044 modules[MESA_SHADER_VERTEX],
1045 pStages[MESA_SHADER_VERTEX]->pName,
1046 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo);
1047 if (result != VK_SUCCESS)
1048 goto compile_fail;
1049 }
1050
1051 if (modules[MESA_SHADER_TESS_CTRL] || modules[MESA_SHADER_TESS_EVAL])
1052 anv_finishme("no tessellation support");
1053
1054 if (modules[MESA_SHADER_GEOMETRY]) {
1055 result = anv_pipeline_compile_gs(pipeline, cache, pCreateInfo,
1056 modules[MESA_SHADER_GEOMETRY],
1057 pStages[MESA_SHADER_GEOMETRY]->pName,
1058 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo);
1059 if (result != VK_SUCCESS)
1060 goto compile_fail;
1061 }
1062
1063 if (modules[MESA_SHADER_FRAGMENT]) {
1064 result = anv_pipeline_compile_fs(pipeline, cache, pCreateInfo,
1065 modules[MESA_SHADER_FRAGMENT],
1066 pStages[MESA_SHADER_FRAGMENT]->pName,
1067 pStages[MESA_SHADER_FRAGMENT]->pSpecializationInfo);
1068 if (result != VK_SUCCESS)
1069 goto compile_fail;
1070 }
1071
1072 assert(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT);
1073
1074 anv_pipeline_setup_l3_config(pipeline, false);
1075
1076 const VkPipelineVertexInputStateCreateInfo *vi_info =
1077 pCreateInfo->pVertexInputState;
1078
1079 const uint64_t inputs_read = get_vs_prog_data(pipeline)->inputs_read;
1080
1081 pipeline->vb_used = 0;
1082 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1083 const VkVertexInputAttributeDescription *desc =
1084 &vi_info->pVertexAttributeDescriptions[i];
1085
1086 if (inputs_read & (1 << (VERT_ATTRIB_GENERIC0 + desc->location)))
1087 pipeline->vb_used |= 1 << desc->binding;
1088 }
1089
1090 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1091 const VkVertexInputBindingDescription *desc =
1092 &vi_info->pVertexBindingDescriptions[i];
1093
1094 pipeline->binding_stride[desc->binding] = desc->stride;
1095
1096 /* Step rate is programmed per vertex element (attribute), not
1097 * binding. Set up a map of which bindings step per instance, for
1098 * reference by vertex element setup. */
1099 switch (desc->inputRate) {
1100 default:
1101 case VK_VERTEX_INPUT_RATE_VERTEX:
1102 pipeline->instancing_enable[desc->binding] = false;
1103 break;
1104 case VK_VERTEX_INPUT_RATE_INSTANCE:
1105 pipeline->instancing_enable[desc->binding] = true;
1106 break;
1107 }
1108 }
1109
1110 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1111 pCreateInfo->pInputAssemblyState;
1112 pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1113 pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1114
1115 return VK_SUCCESS;
1116
1117 compile_fail:
1118 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
1119 if (pipeline->shaders[s])
1120 anv_shader_bin_unref(device, pipeline->shaders[s]);
1121 }
1122
1123 anv_reloc_list_finish(&pipeline->batch_relocs, alloc);
1124
1125 return result;
1126 }