2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "util/os_time.h"
32 #include "common/gen_l3_config.h"
33 #include "common/gen_disasm.h"
34 #include "anv_private.h"
35 #include "compiler/brw_nir.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
41 /* Needed for SWIZZLE macros */
42 #include "program/prog_instruction.h"
46 VkResult
anv_CreateShaderModule(
48 const VkShaderModuleCreateInfo
* pCreateInfo
,
49 const VkAllocationCallbacks
* pAllocator
,
50 VkShaderModule
* pShaderModule
)
52 ANV_FROM_HANDLE(anv_device
, device
, _device
);
53 struct anv_shader_module
*module
;
55 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
56 assert(pCreateInfo
->flags
== 0);
58 module
= vk_alloc2(&device
->alloc
, pAllocator
,
59 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
60 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
62 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
64 module
->size
= pCreateInfo
->codeSize
;
65 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
67 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
69 *pShaderModule
= anv_shader_module_to_handle(module
);
74 void anv_DestroyShaderModule(
76 VkShaderModule _module
,
77 const VkAllocationCallbacks
* pAllocator
)
79 ANV_FROM_HANDLE(anv_device
, device
, _device
);
80 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
85 vk_free2(&device
->alloc
, pAllocator
, module
);
88 #define SPIR_V_MAGIC_NUMBER 0x07230203
90 struct anv_spirv_debug_data
{
91 struct anv_device
*device
;
92 const struct anv_shader_module
*module
;
95 static void anv_spirv_nir_debug(void *private_data
,
96 enum nir_spirv_debug_level level
,
100 struct anv_spirv_debug_data
*debug_data
= private_data
;
101 struct anv_instance
*instance
= debug_data
->device
->physical
->instance
;
103 static const VkDebugReportFlagsEXT vk_flags
[] = {
104 [NIR_SPIRV_DEBUG_LEVEL_INFO
] = VK_DEBUG_REPORT_INFORMATION_BIT_EXT
,
105 [NIR_SPIRV_DEBUG_LEVEL_WARNING
] = VK_DEBUG_REPORT_WARNING_BIT_EXT
,
106 [NIR_SPIRV_DEBUG_LEVEL_ERROR
] = VK_DEBUG_REPORT_ERROR_BIT_EXT
,
110 snprintf(buffer
, sizeof(buffer
), "SPIR-V offset %lu: %s", (unsigned long) spirv_offset
, message
);
112 vk_debug_report(&instance
->debug_report_callbacks
,
114 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT
,
115 (uint64_t) (uintptr_t) debug_data
->module
,
116 0, 0, "anv", buffer
);
119 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
120 * we can't do that yet because we don't have the ability to copy nir.
123 anv_shader_compile_to_nir(struct anv_device
*device
,
125 const struct anv_shader_module
*module
,
126 const char *entrypoint_name
,
127 gl_shader_stage stage
,
128 const VkSpecializationInfo
*spec_info
)
130 const struct anv_physical_device
*pdevice
= device
->physical
;
131 const struct brw_compiler
*compiler
= pdevice
->compiler
;
132 const nir_shader_compiler_options
*nir_options
=
133 compiler
->glsl_compiler_options
[stage
].NirOptions
;
135 uint32_t *spirv
= (uint32_t *) module
->data
;
136 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
137 assert(module
->size
% 4 == 0);
139 uint32_t num_spec_entries
= 0;
140 struct nir_spirv_specialization
*spec_entries
= NULL
;
141 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
142 num_spec_entries
= spec_info
->mapEntryCount
;
143 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
144 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
145 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
146 const void *data
= spec_info
->pData
+ entry
.offset
;
147 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
149 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
150 if (spec_info
->dataSize
== 8)
151 spec_entries
[i
].data64
= *(const uint64_t *)data
;
153 spec_entries
[i
].data32
= *(const uint32_t *)data
;
157 struct anv_spirv_debug_data spirv_debug_data
= {
161 struct spirv_to_nir_options spirv_options
= {
162 .frag_coord_is_sysval
= true,
164 .demote_to_helper_invocation
= true,
165 .derivative_group
= true,
166 .descriptor_array_dynamic_indexing
= true,
167 .descriptor_array_non_uniform_indexing
= true,
168 .descriptor_indexing
= true,
169 .device_group
= true,
170 .draw_parameters
= true,
171 .float16
= pdevice
->info
.gen
>= 8,
172 .float64
= pdevice
->info
.gen
>= 8,
173 .fragment_shader_sample_interlock
= pdevice
->info
.gen
>= 9,
174 .fragment_shader_pixel_interlock
= pdevice
->info
.gen
>= 9,
175 .geometry_streams
= true,
176 .image_write_without_format
= true,
177 .int8
= pdevice
->info
.gen
>= 8,
178 .int16
= pdevice
->info
.gen
>= 8,
179 .int64
= pdevice
->info
.gen
>= 8,
180 .int64_atomics
= pdevice
->info
.gen
>= 9 && pdevice
->use_softpin
,
181 .integer_functions2
= pdevice
->info
.gen
>= 8,
184 .physical_storage_buffer_address
= pdevice
->has_a64_buffer_access
,
185 .post_depth_coverage
= pdevice
->info
.gen
>= 9,
186 .runtime_descriptor_array
= true,
187 .float_controls
= pdevice
->info
.gen
>= 8,
188 .shader_clock
= true,
189 .shader_viewport_index_layer
= true,
190 .stencil_export
= pdevice
->info
.gen
>= 9,
191 .storage_8bit
= pdevice
->info
.gen
>= 8,
192 .storage_16bit
= pdevice
->info
.gen
>= 8,
193 .subgroup_arithmetic
= true,
194 .subgroup_basic
= true,
195 .subgroup_ballot
= true,
196 .subgroup_quad
= true,
197 .subgroup_shuffle
= true,
198 .subgroup_vote
= true,
199 .tessellation
= true,
200 .transform_feedback
= pdevice
->info
.gen
>= 8,
201 .variable_pointers
= true,
202 .vk_memory_model
= true,
203 .vk_memory_model_device_scope
= true,
205 .ubo_addr_format
= nir_address_format_32bit_index_offset
,
207 anv_nir_ssbo_addr_format(pdevice
, device
->robust_buffer_access
),
208 .phys_ssbo_addr_format
= nir_address_format_64bit_global
,
209 .push_const_addr_format
= nir_address_format_logical
,
211 /* TODO: Consider changing this to an address format that has the NULL
212 * pointer equals to 0. That might be a better format to play nice
213 * with certain code / code generators.
215 .shared_addr_format
= nir_address_format_32bit_offset
,
217 .func
= anv_spirv_nir_debug
,
218 .private_data
= &spirv_debug_data
,
224 spirv_to_nir(spirv
, module
->size
/ 4,
225 spec_entries
, num_spec_entries
,
226 stage
, entrypoint_name
, &spirv_options
, nir_options
);
227 assert(nir
->info
.stage
== stage
);
228 nir_validate_shader(nir
, "after spirv_to_nir");
229 ralloc_steal(mem_ctx
, nir
);
233 if (unlikely(INTEL_DEBUG
& intel_debug_flag_for_shader_stage(stage
))) {
234 fprintf(stderr
, "NIR (from SPIR-V) for %s shader:\n",
235 gl_shader_stage_name(stage
));
236 nir_print_shader(nir
, stderr
);
239 /* We have to lower away local constant initializers right before we
240 * inline functions. That way they get properly initialized at the top
241 * of the function and not at the top of its caller.
243 NIR_PASS_V(nir
, nir_lower_variable_initializers
, nir_var_function_temp
);
244 NIR_PASS_V(nir
, nir_lower_returns
);
245 NIR_PASS_V(nir
, nir_inline_functions
);
246 NIR_PASS_V(nir
, nir_opt_deref
);
248 /* Pick off the single entrypoint that we want */
249 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
250 if (!func
->is_entrypoint
)
251 exec_node_remove(&func
->node
);
253 assert(exec_list_length(&nir
->functions
) == 1);
255 /* Now that we've deleted all but the main function, we can go ahead and
256 * lower the rest of the constant initializers. We do this here so that
257 * nir_remove_dead_variables and split_per_member_structs below see the
258 * corresponding stores.
260 NIR_PASS_V(nir
, nir_lower_variable_initializers
, ~0);
262 /* Split member structs. We do this before lower_io_to_temporaries so that
263 * it doesn't lower system values to temporaries by accident.
265 NIR_PASS_V(nir
, nir_split_var_copies
);
266 NIR_PASS_V(nir
, nir_split_per_member_structs
);
268 NIR_PASS_V(nir
, nir_remove_dead_variables
,
269 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
271 NIR_PASS_V(nir
, nir_propagate_invariant
);
272 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
273 nir_shader_get_entrypoint(nir
), true, false);
275 NIR_PASS_V(nir
, nir_lower_frexp
);
277 /* Vulkan uses the separate-shader linking model */
278 nir
->info
.separate_shader
= true;
280 brw_preprocess_nir(compiler
, nir
, NULL
);
285 void anv_DestroyPipeline(
287 VkPipeline _pipeline
,
288 const VkAllocationCallbacks
* pAllocator
)
290 ANV_FROM_HANDLE(anv_device
, device
, _device
);
291 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
296 anv_reloc_list_finish(&pipeline
->batch_relocs
,
297 pAllocator
? pAllocator
: &device
->alloc
);
299 ralloc_free(pipeline
->mem_ctx
);
301 switch (pipeline
->type
) {
302 case ANV_PIPELINE_GRAPHICS
: {
303 struct anv_graphics_pipeline
*gfx_pipeline
=
304 anv_pipeline_to_graphics(pipeline
);
306 if (gfx_pipeline
->blend_state
.map
)
307 anv_state_pool_free(&device
->dynamic_state_pool
, gfx_pipeline
->blend_state
);
309 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
310 if (gfx_pipeline
->shaders
[s
])
311 anv_shader_bin_unref(device
, gfx_pipeline
->shaders
[s
]);
316 case ANV_PIPELINE_COMPUTE
: {
317 struct anv_compute_pipeline
*compute_pipeline
=
318 anv_pipeline_to_compute(pipeline
);
320 if (compute_pipeline
->cs
)
321 anv_shader_bin_unref(device
, compute_pipeline
->cs
);
327 unreachable("invalid pipeline type");
330 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
333 static const uint32_t vk_to_gen_primitive_type
[] = {
334 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
335 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
336 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
337 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
338 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
339 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
340 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
341 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
342 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
343 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
347 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
348 struct brw_sampler_prog_key_data
*key
)
350 /* Almost all multisampled textures are compressed. The only time when we
351 * don't compress a multisampled texture is for 16x MSAA with a surface
352 * width greater than 8k which is a bit of an edge case. Since the sampler
353 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
354 * to tell the compiler to always assume compression.
356 key
->compressed_multisample_layout_mask
= ~0;
358 /* SkyLake added support for 16x MSAA. With this came a new message for
359 * reading from a 16x MSAA surface with compression. The new message was
360 * needed because now the MCS data is 64 bits instead of 32 or lower as is
361 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
362 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
363 * so we can just use it unconditionally. This may not be quite as
364 * efficient but it saves us from recompiling.
366 if (devinfo
->gen
>= 9)
369 /* XXX: Handle texture swizzle on HSW- */
370 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
371 /* Assume color sampler, no swizzling. (Works for BDW+) */
372 key
->swizzles
[i
] = SWIZZLE_XYZW
;
377 populate_base_prog_key(const struct gen_device_info
*devinfo
,
378 VkPipelineShaderStageCreateFlags flags
,
379 struct brw_base_prog_key
*key
)
381 if (flags
& VK_PIPELINE_SHADER_STAGE_CREATE_ALLOW_VARYING_SUBGROUP_SIZE_BIT_EXT
)
382 key
->subgroup_size_type
= BRW_SUBGROUP_SIZE_VARYING
;
384 key
->subgroup_size_type
= BRW_SUBGROUP_SIZE_API_CONSTANT
;
386 populate_sampler_prog_key(devinfo
, &key
->tex
);
390 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
391 VkPipelineShaderStageCreateFlags flags
,
392 struct brw_vs_prog_key
*key
)
394 memset(key
, 0, sizeof(*key
));
396 populate_base_prog_key(devinfo
, flags
, &key
->base
);
398 /* XXX: Handle vertex input work-arounds */
400 /* XXX: Handle sampler_prog_key */
404 populate_tcs_prog_key(const struct gen_device_info
*devinfo
,
405 VkPipelineShaderStageCreateFlags flags
,
406 unsigned input_vertices
,
407 struct brw_tcs_prog_key
*key
)
409 memset(key
, 0, sizeof(*key
));
411 populate_base_prog_key(devinfo
, flags
, &key
->base
);
413 key
->input_vertices
= input_vertices
;
417 populate_tes_prog_key(const struct gen_device_info
*devinfo
,
418 VkPipelineShaderStageCreateFlags flags
,
419 struct brw_tes_prog_key
*key
)
421 memset(key
, 0, sizeof(*key
));
423 populate_base_prog_key(devinfo
, flags
, &key
->base
);
427 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
428 VkPipelineShaderStageCreateFlags flags
,
429 struct brw_gs_prog_key
*key
)
431 memset(key
, 0, sizeof(*key
));
433 populate_base_prog_key(devinfo
, flags
, &key
->base
);
437 populate_wm_prog_key(const struct gen_device_info
*devinfo
,
438 VkPipelineShaderStageCreateFlags flags
,
439 const struct anv_subpass
*subpass
,
440 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
441 struct brw_wm_prog_key
*key
)
443 memset(key
, 0, sizeof(*key
));
445 populate_base_prog_key(devinfo
, flags
, &key
->base
);
447 /* We set this to 0 here and set to the actual value before we call
450 key
->input_slots_valid
= 0;
452 /* Vulkan doesn't specify a default */
453 key
->high_quality_derivatives
= false;
455 /* XXX Vulkan doesn't appear to specify */
456 key
->clamp_fragment_color
= false;
458 assert(subpass
->color_count
<= MAX_RTS
);
459 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
460 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
461 key
->color_outputs_valid
|= (1 << i
);
464 key
->nr_color_regions
= subpass
->color_count
;
466 /* To reduce possible shader recompilations we would need to know if
467 * there is a SampleMask output variable to compute if we should emit
468 * code to workaround the issue that hardware disables alpha to coverage
469 * when there is SampleMask output.
471 key
->alpha_to_coverage
= ms_info
&& ms_info
->alphaToCoverageEnable
;
473 /* Vulkan doesn't support fixed-function alpha test */
474 key
->alpha_test_replicate_alpha
= false;
477 /* We should probably pull this out of the shader, but it's fairly
478 * harmless to compute it and then let dead-code take care of it.
480 if (ms_info
->rasterizationSamples
> 1) {
481 key
->persample_interp
= ms_info
->sampleShadingEnable
&&
482 (ms_info
->minSampleShading
* ms_info
->rasterizationSamples
) > 1;
483 key
->multisample_fbo
= true;
486 key
->frag_coord_adds_sample_pos
= key
->persample_interp
;
491 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
492 VkPipelineShaderStageCreateFlags flags
,
493 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*rss_info
,
494 struct brw_cs_prog_key
*key
)
496 memset(key
, 0, sizeof(*key
));
498 populate_base_prog_key(devinfo
, flags
, &key
->base
);
501 assert(key
->base
.subgroup_size_type
!= BRW_SUBGROUP_SIZE_VARYING
);
503 /* These enum values are expressly chosen to be equal to the subgroup
504 * size that they require.
506 assert(rss_info
->requiredSubgroupSize
== 8 ||
507 rss_info
->requiredSubgroupSize
== 16 ||
508 rss_info
->requiredSubgroupSize
== 32);
509 key
->base
.subgroup_size_type
= rss_info
->requiredSubgroupSize
;
510 } else if (flags
& VK_PIPELINE_SHADER_STAGE_CREATE_REQUIRE_FULL_SUBGROUPS_BIT_EXT
) {
511 /* If the client expressly requests full subgroups and they don't
512 * specify a subgroup size, we need to pick one. If they're requested
513 * varying subgroup sizes, we set it to UNIFORM and let the back-end
514 * compiler pick. Otherwise, we specify the API value of 32.
515 * Performance will likely be terrible in this case but there's nothing
516 * we can do about that. The client should have chosen a size.
518 if (flags
& VK_PIPELINE_SHADER_STAGE_CREATE_ALLOW_VARYING_SUBGROUP_SIZE_BIT_EXT
)
519 key
->base
.subgroup_size_type
= BRW_SUBGROUP_SIZE_UNIFORM
;
521 key
->base
.subgroup_size_type
= BRW_SUBGROUP_SIZE_REQUIRE_32
;
525 struct anv_pipeline_stage
{
526 gl_shader_stage stage
;
528 const struct anv_shader_module
*module
;
529 const char *entrypoint
;
530 const VkSpecializationInfo
*spec_info
;
532 unsigned char shader_sha1
[20];
534 union brw_any_prog_key key
;
537 gl_shader_stage stage
;
538 unsigned char sha1
[20];
543 struct anv_pipeline_binding surface_to_descriptor
[256];
544 struct anv_pipeline_binding sampler_to_descriptor
[256];
545 struct anv_pipeline_bind_map bind_map
;
547 union brw_any_prog_data prog_data
;
550 struct brw_compile_stats stats
[3];
553 VkPipelineCreationFeedbackEXT feedback
;
555 const unsigned *code
;
559 anv_pipeline_hash_shader(const struct anv_shader_module
*module
,
560 const char *entrypoint
,
561 gl_shader_stage stage
,
562 const VkSpecializationInfo
*spec_info
,
563 unsigned char *sha1_out
)
565 struct mesa_sha1 ctx
;
566 _mesa_sha1_init(&ctx
);
568 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
569 _mesa_sha1_update(&ctx
, entrypoint
, strlen(entrypoint
));
570 _mesa_sha1_update(&ctx
, &stage
, sizeof(stage
));
572 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
573 spec_info
->mapEntryCount
*
574 sizeof(*spec_info
->pMapEntries
));
575 _mesa_sha1_update(&ctx
, spec_info
->pData
,
576 spec_info
->dataSize
);
579 _mesa_sha1_final(&ctx
, sha1_out
);
583 anv_pipeline_hash_graphics(struct anv_graphics_pipeline
*pipeline
,
584 struct anv_pipeline_layout
*layout
,
585 struct anv_pipeline_stage
*stages
,
586 unsigned char *sha1_out
)
588 struct mesa_sha1 ctx
;
589 _mesa_sha1_init(&ctx
);
591 _mesa_sha1_update(&ctx
, &pipeline
->subpass
->view_mask
,
592 sizeof(pipeline
->subpass
->view_mask
));
595 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
597 const bool rba
= pipeline
->base
.device
->robust_buffer_access
;
598 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
600 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
601 if (stages
[s
].entrypoint
) {
602 _mesa_sha1_update(&ctx
, stages
[s
].shader_sha1
,
603 sizeof(stages
[s
].shader_sha1
));
604 _mesa_sha1_update(&ctx
, &stages
[s
].key
, brw_prog_key_size(s
));
608 _mesa_sha1_final(&ctx
, sha1_out
);
612 anv_pipeline_hash_compute(struct anv_compute_pipeline
*pipeline
,
613 struct anv_pipeline_layout
*layout
,
614 struct anv_pipeline_stage
*stage
,
615 unsigned char *sha1_out
)
617 struct mesa_sha1 ctx
;
618 _mesa_sha1_init(&ctx
);
621 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
623 const bool rba
= pipeline
->base
.device
->robust_buffer_access
;
624 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
626 _mesa_sha1_update(&ctx
, stage
->shader_sha1
,
627 sizeof(stage
->shader_sha1
));
628 _mesa_sha1_update(&ctx
, &stage
->key
.cs
, sizeof(stage
->key
.cs
));
630 _mesa_sha1_final(&ctx
, sha1_out
);
634 anv_pipeline_stage_get_nir(struct anv_pipeline
*pipeline
,
635 struct anv_pipeline_cache
*cache
,
637 struct anv_pipeline_stage
*stage
)
639 const struct brw_compiler
*compiler
=
640 pipeline
->device
->physical
->compiler
;
641 const nir_shader_compiler_options
*nir_options
=
642 compiler
->glsl_compiler_options
[stage
->stage
].NirOptions
;
645 nir
= anv_device_search_for_nir(pipeline
->device
, cache
,
650 assert(nir
->info
.stage
== stage
->stage
);
654 nir
= anv_shader_compile_to_nir(pipeline
->device
,
661 anv_device_upload_nir(pipeline
->device
, cache
, nir
, stage
->shader_sha1
);
669 anv_pipeline_lower_nir(struct anv_pipeline
*pipeline
,
671 struct anv_pipeline_stage
*stage
,
672 struct anv_pipeline_layout
*layout
)
674 const struct anv_physical_device
*pdevice
= pipeline
->device
->physical
;
675 const struct brw_compiler
*compiler
= pdevice
->compiler
;
677 struct brw_stage_prog_data
*prog_data
= &stage
->prog_data
.base
;
678 nir_shader
*nir
= stage
->nir
;
680 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
681 NIR_PASS_V(nir
, nir_lower_wpos_center
,
682 anv_pipeline_to_graphics(pipeline
)->sample_shading_enable
);
683 NIR_PASS_V(nir
, nir_lower_input_attachments
, true);
686 NIR_PASS_V(nir
, anv_nir_lower_ycbcr_textures
, layout
);
688 if (pipeline
->type
== ANV_PIPELINE_GRAPHICS
) {
689 NIR_PASS_V(nir
, anv_nir_lower_multiview
,
690 anv_pipeline_to_graphics(pipeline
)->subpass
->view_mask
);
693 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
695 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, compiler
->devinfo
, NULL
);
697 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_global
,
698 nir_address_format_64bit_global
);
700 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
701 anv_nir_apply_pipeline_layout(pdevice
,
702 pipeline
->device
->robust_buffer_access
,
703 layout
, nir
, &stage
->bind_map
);
705 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ubo
,
706 nir_address_format_32bit_index_offset
);
707 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ssbo
,
708 anv_nir_ssbo_addr_format(pdevice
,
709 pipeline
->device
->robust_buffer_access
));
711 NIR_PASS_V(nir
, nir_opt_constant_folding
);
713 /* We don't support non-uniform UBOs and non-uniform SSBO access is
714 * handled naturally by falling back to A64 messages.
716 NIR_PASS_V(nir
, nir_lower_non_uniform_access
,
717 nir_lower_non_uniform_texture_access
|
718 nir_lower_non_uniform_image_access
);
720 anv_nir_compute_push_layout(pdevice
, pipeline
->device
->robust_buffer_access
,
721 nir
, prog_data
, &stage
->bind_map
, mem_ctx
);
727 anv_pipeline_link_vs(const struct brw_compiler
*compiler
,
728 struct anv_pipeline_stage
*vs_stage
,
729 struct anv_pipeline_stage
*next_stage
)
732 brw_nir_link_shaders(compiler
, vs_stage
->nir
, next_stage
->nir
);
736 anv_pipeline_compile_vs(const struct brw_compiler
*compiler
,
738 struct anv_device
*device
,
739 struct anv_pipeline_stage
*vs_stage
)
741 brw_compute_vue_map(compiler
->devinfo
,
742 &vs_stage
->prog_data
.vs
.base
.vue_map
,
743 vs_stage
->nir
->info
.outputs_written
,
744 vs_stage
->nir
->info
.separate_shader
, 1);
746 vs_stage
->num_stats
= 1;
747 vs_stage
->code
= brw_compile_vs(compiler
, device
, mem_ctx
,
749 &vs_stage
->prog_data
.vs
,
751 vs_stage
->stats
, NULL
);
755 merge_tess_info(struct shader_info
*tes_info
,
756 const struct shader_info
*tcs_info
)
758 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
760 * "PointMode. Controls generation of points rather than triangles
761 * or lines. This functionality defaults to disabled, and is
762 * enabled if either shader stage includes the execution mode.
764 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
765 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
766 * and OutputVertices, it says:
768 * "One mode must be set in at least one of the tessellation
771 * So, the fields can be set in either the TCS or TES, but they must
772 * agree if set in both. Our backend looks at TES, so bitwise-or in
773 * the values from the TCS.
775 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
776 tes_info
->tess
.tcs_vertices_out
== 0 ||
777 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
778 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
780 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
781 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
782 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
783 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
785 assert(tcs_info
->tess
.primitive_mode
== 0 ||
786 tes_info
->tess
.primitive_mode
== 0 ||
787 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
788 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
789 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
790 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
794 anv_pipeline_link_tcs(const struct brw_compiler
*compiler
,
795 struct anv_pipeline_stage
*tcs_stage
,
796 struct anv_pipeline_stage
*tes_stage
)
798 assert(tes_stage
&& tes_stage
->stage
== MESA_SHADER_TESS_EVAL
);
800 brw_nir_link_shaders(compiler
, tcs_stage
->nir
, tes_stage
->nir
);
802 nir_lower_patch_vertices(tes_stage
->nir
,
803 tcs_stage
->nir
->info
.tess
.tcs_vertices_out
,
806 /* Copy TCS info into the TES info */
807 merge_tess_info(&tes_stage
->nir
->info
, &tcs_stage
->nir
->info
);
809 /* Whacking the key after cache lookup is a bit sketchy, but all of
810 * this comes from the SPIR-V, which is part of the hash used for the
811 * pipeline cache. So it should be safe.
813 tcs_stage
->key
.tcs
.tes_primitive_mode
=
814 tes_stage
->nir
->info
.tess
.primitive_mode
;
815 tcs_stage
->key
.tcs
.quads_workaround
=
816 compiler
->devinfo
->gen
< 9 &&
817 tes_stage
->nir
->info
.tess
.primitive_mode
== 7 /* GL_QUADS */ &&
818 tes_stage
->nir
->info
.tess
.spacing
== TESS_SPACING_EQUAL
;
822 anv_pipeline_compile_tcs(const struct brw_compiler
*compiler
,
824 struct anv_device
*device
,
825 struct anv_pipeline_stage
*tcs_stage
,
826 struct anv_pipeline_stage
*prev_stage
)
828 tcs_stage
->key
.tcs
.outputs_written
=
829 tcs_stage
->nir
->info
.outputs_written
;
830 tcs_stage
->key
.tcs
.patch_outputs_written
=
831 tcs_stage
->nir
->info
.patch_outputs_written
;
833 tcs_stage
->num_stats
= 1;
834 tcs_stage
->code
= brw_compile_tcs(compiler
, device
, mem_ctx
,
836 &tcs_stage
->prog_data
.tcs
,
838 tcs_stage
->stats
, NULL
);
842 anv_pipeline_link_tes(const struct brw_compiler
*compiler
,
843 struct anv_pipeline_stage
*tes_stage
,
844 struct anv_pipeline_stage
*next_stage
)
847 brw_nir_link_shaders(compiler
, tes_stage
->nir
, next_stage
->nir
);
851 anv_pipeline_compile_tes(const struct brw_compiler
*compiler
,
853 struct anv_device
*device
,
854 struct anv_pipeline_stage
*tes_stage
,
855 struct anv_pipeline_stage
*tcs_stage
)
857 tes_stage
->key
.tes
.inputs_read
=
858 tcs_stage
->nir
->info
.outputs_written
;
859 tes_stage
->key
.tes
.patch_inputs_read
=
860 tcs_stage
->nir
->info
.patch_outputs_written
;
862 tes_stage
->num_stats
= 1;
863 tes_stage
->code
= brw_compile_tes(compiler
, device
, mem_ctx
,
865 &tcs_stage
->prog_data
.tcs
.base
.vue_map
,
866 &tes_stage
->prog_data
.tes
,
868 tes_stage
->stats
, NULL
);
872 anv_pipeline_link_gs(const struct brw_compiler
*compiler
,
873 struct anv_pipeline_stage
*gs_stage
,
874 struct anv_pipeline_stage
*next_stage
)
877 brw_nir_link_shaders(compiler
, gs_stage
->nir
, next_stage
->nir
);
881 anv_pipeline_compile_gs(const struct brw_compiler
*compiler
,
883 struct anv_device
*device
,
884 struct anv_pipeline_stage
*gs_stage
,
885 struct anv_pipeline_stage
*prev_stage
)
887 brw_compute_vue_map(compiler
->devinfo
,
888 &gs_stage
->prog_data
.gs
.base
.vue_map
,
889 gs_stage
->nir
->info
.outputs_written
,
890 gs_stage
->nir
->info
.separate_shader
, 1);
892 gs_stage
->num_stats
= 1;
893 gs_stage
->code
= brw_compile_gs(compiler
, device
, mem_ctx
,
895 &gs_stage
->prog_data
.gs
,
896 gs_stage
->nir
, NULL
, -1,
897 gs_stage
->stats
, NULL
);
901 anv_pipeline_link_fs(const struct brw_compiler
*compiler
,
902 struct anv_pipeline_stage
*stage
)
904 unsigned num_rt_bindings
;
905 struct anv_pipeline_binding rt_bindings
[MAX_RTS
];
906 if (stage
->key
.wm
.nr_color_regions
> 0) {
907 assert(stage
->key
.wm
.nr_color_regions
<= MAX_RTS
);
908 for (unsigned rt
= 0; rt
< stage
->key
.wm
.nr_color_regions
; rt
++) {
909 if (stage
->key
.wm
.color_outputs_valid
& BITFIELD_BIT(rt
)) {
910 rt_bindings
[rt
] = (struct anv_pipeline_binding
) {
911 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
915 /* Setup a null render target */
916 rt_bindings
[rt
] = (struct anv_pipeline_binding
) {
917 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
922 num_rt_bindings
= stage
->key
.wm
.nr_color_regions
;
924 /* Setup a null render target */
925 rt_bindings
[0] = (struct anv_pipeline_binding
) {
926 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
932 assert(num_rt_bindings
<= MAX_RTS
);
933 assert(stage
->bind_map
.surface_count
== 0);
934 typed_memcpy(stage
->bind_map
.surface_to_descriptor
,
935 rt_bindings
, num_rt_bindings
);
936 stage
->bind_map
.surface_count
+= num_rt_bindings
;
938 /* Now that we've set up the color attachments, we can go through and
939 * eliminate any shader outputs that map to VK_ATTACHMENT_UNUSED in the
940 * hopes that dead code can clean them up in this and any earlier shader
943 nir_function_impl
*impl
= nir_shader_get_entrypoint(stage
->nir
);
944 bool deleted_output
= false;
945 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
946 /* TODO: We don't delete depth/stencil writes. We probably could if the
947 * subpass doesn't have a depth/stencil attachment.
949 if (var
->data
.location
< FRAG_RESULT_DATA0
)
952 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
954 /* If this is the RT at location 0 and we have alpha to coverage
955 * enabled we still need that write because it will affect the coverage
956 * mask even if it's never written to a color target.
958 if (rt
== 0 && stage
->key
.wm
.alpha_to_coverage
)
961 const unsigned array_len
=
962 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
963 assert(rt
+ array_len
<= MAX_RTS
);
965 if (rt
>= MAX_RTS
|| !(stage
->key
.wm
.color_outputs_valid
&
966 BITFIELD_RANGE(rt
, array_len
))) {
967 deleted_output
= true;
968 var
->data
.mode
= nir_var_function_temp
;
969 exec_node_remove(&var
->node
);
970 exec_list_push_tail(&impl
->locals
, &var
->node
);
975 nir_fixup_deref_modes(stage
->nir
);
977 /* We stored the number of subpass color attachments in nr_color_regions
978 * when calculating the key for caching. Now that we've computed the bind
979 * map, we can reduce this to the actual max before we go into the back-end
982 stage
->key
.wm
.nr_color_regions
=
983 util_last_bit(stage
->key
.wm
.color_outputs_valid
);
987 anv_pipeline_compile_fs(const struct brw_compiler
*compiler
,
989 struct anv_device
*device
,
990 struct anv_pipeline_stage
*fs_stage
,
991 struct anv_pipeline_stage
*prev_stage
)
993 /* TODO: we could set this to 0 based on the information in nir_shader, but
994 * we need this before we call spirv_to_nir.
997 fs_stage
->key
.wm
.input_slots_valid
=
998 prev_stage
->prog_data
.vue
.vue_map
.slots_valid
;
1000 fs_stage
->code
= brw_compile_fs(compiler
, device
, mem_ctx
,
1002 &fs_stage
->prog_data
.wm
,
1003 fs_stage
->nir
, -1, -1, -1,
1005 fs_stage
->stats
, NULL
);
1007 fs_stage
->num_stats
= (uint32_t)fs_stage
->prog_data
.wm
.dispatch_8
+
1008 (uint32_t)fs_stage
->prog_data
.wm
.dispatch_16
+
1009 (uint32_t)fs_stage
->prog_data
.wm
.dispatch_32
;
1011 if (fs_stage
->key
.wm
.color_outputs_valid
== 0 &&
1012 !fs_stage
->prog_data
.wm
.has_side_effects
&&
1013 !fs_stage
->prog_data
.wm
.uses_omask
&&
1014 !fs_stage
->key
.wm
.alpha_to_coverage
&&
1015 !fs_stage
->prog_data
.wm
.uses_kill
&&
1016 fs_stage
->prog_data
.wm
.computed_depth_mode
== BRW_PSCDEPTH_OFF
&&
1017 !fs_stage
->prog_data
.wm
.computed_stencil
) {
1018 /* This fragment shader has no outputs and no side effects. Go ahead
1019 * and return the code pointer so we don't accidentally think the
1020 * compile failed but zero out prog_data which will set program_size to
1021 * zero and disable the stage.
1023 memset(&fs_stage
->prog_data
, 0, sizeof(fs_stage
->prog_data
));
1028 anv_pipeline_add_executable(struct anv_pipeline
*pipeline
,
1029 struct anv_pipeline_stage
*stage
,
1030 struct brw_compile_stats
*stats
,
1031 uint32_t code_offset
)
1036 VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
)) {
1037 char *stream_data
= NULL
;
1038 size_t stream_size
= 0;
1039 FILE *stream
= open_memstream(&stream_data
, &stream_size
);
1041 nir_print_shader(stage
->nir
, stream
);
1045 /* Copy it to a ralloc'd thing */
1046 nir
= ralloc_size(pipeline
->mem_ctx
, stream_size
+ 1);
1047 memcpy(nir
, stream_data
, stream_size
);
1048 nir
[stream_size
] = 0;
1053 char *disasm
= NULL
;
1056 VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
)) {
1057 char *stream_data
= NULL
;
1058 size_t stream_size
= 0;
1059 FILE *stream
= open_memstream(&stream_data
, &stream_size
);
1061 uint32_t push_size
= 0;
1062 for (unsigned i
= 0; i
< 4; i
++)
1063 push_size
+= stage
->bind_map
.push_ranges
[i
].length
;
1064 if (push_size
> 0) {
1065 fprintf(stream
, "Push constant ranges:\n");
1066 for (unsigned i
= 0; i
< 4; i
++) {
1067 if (stage
->bind_map
.push_ranges
[i
].length
== 0)
1070 fprintf(stream
, " RANGE%d (%dB): ", i
,
1071 stage
->bind_map
.push_ranges
[i
].length
* 32);
1073 switch (stage
->bind_map
.push_ranges
[i
].set
) {
1074 case ANV_DESCRIPTOR_SET_NULL
:
1075 fprintf(stream
, "NULL");
1078 case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
:
1079 fprintf(stream
, "Vulkan push constants and API params");
1082 case ANV_DESCRIPTOR_SET_DESCRIPTORS
:
1083 fprintf(stream
, "Descriptor buffer for set %d (start=%dB)",
1084 stage
->bind_map
.push_ranges
[i
].index
,
1085 stage
->bind_map
.push_ranges
[i
].start
* 32);
1088 case ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
:
1089 unreachable("gl_NumWorkgroups is never pushed");
1091 case ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
:
1092 fprintf(stream
, "Inline shader constant data (start=%dB)",
1093 stage
->bind_map
.push_ranges
[i
].start
* 32);
1096 case ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
:
1097 unreachable("Color attachments can't be pushed");
1100 fprintf(stream
, "UBO (set=%d binding=%d start=%dB)",
1101 stage
->bind_map
.push_ranges
[i
].set
,
1102 stage
->bind_map
.push_ranges
[i
].index
,
1103 stage
->bind_map
.push_ranges
[i
].start
* 32);
1106 fprintf(stream
, "\n");
1108 fprintf(stream
, "\n");
1111 /* Creating this is far cheaper than it looks. It's perfectly fine to
1112 * do it for every binary.
1114 struct gen_disasm
*d
= gen_disasm_create(&pipeline
->device
->info
);
1115 gen_disasm_disassemble(d
, stage
->code
, code_offset
, stream
);
1116 gen_disasm_destroy(d
);
1120 /* Copy it to a ralloc'd thing */
1121 disasm
= ralloc_size(pipeline
->mem_ctx
, stream_size
+ 1);
1122 memcpy(disasm
, stream_data
, stream_size
);
1123 disasm
[stream_size
] = 0;
1128 const struct anv_pipeline_executable exe
= {
1129 .stage
= stage
->stage
,
1134 util_dynarray_append(&pipeline
->executables
,
1135 struct anv_pipeline_executable
, exe
);
1139 anv_pipeline_add_executables(struct anv_pipeline
*pipeline
,
1140 struct anv_pipeline_stage
*stage
,
1141 struct anv_shader_bin
*bin
)
1143 if (stage
->stage
== MESA_SHADER_FRAGMENT
) {
1144 /* We pull the prog data and stats out of the anv_shader_bin because
1145 * the anv_pipeline_stage may not be fully populated if we successfully
1146 * looked up the shader in a cache.
1148 const struct brw_wm_prog_data
*wm_prog_data
=
1149 (const struct brw_wm_prog_data
*)bin
->prog_data
;
1150 struct brw_compile_stats
*stats
= bin
->stats
;
1152 if (wm_prog_data
->dispatch_8
) {
1153 anv_pipeline_add_executable(pipeline
, stage
, stats
++, 0);
1156 if (wm_prog_data
->dispatch_16
) {
1157 anv_pipeline_add_executable(pipeline
, stage
, stats
++,
1158 wm_prog_data
->prog_offset_16
);
1161 if (wm_prog_data
->dispatch_32
) {
1162 anv_pipeline_add_executable(pipeline
, stage
, stats
++,
1163 wm_prog_data
->prog_offset_32
);
1166 anv_pipeline_add_executable(pipeline
, stage
, bin
->stats
, 0);
1171 anv_pipeline_compile_graphics(struct anv_graphics_pipeline
*pipeline
,
1172 struct anv_pipeline_cache
*cache
,
1173 const VkGraphicsPipelineCreateInfo
*info
)
1175 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1176 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1178 int64_t pipeline_start
= os_time_get_nano();
1180 const struct brw_compiler
*compiler
= pipeline
->base
.device
->physical
->compiler
;
1181 struct anv_pipeline_stage stages
[MESA_SHADER_STAGES
] = {};
1183 pipeline
->active_stages
= 0;
1186 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1187 const VkPipelineShaderStageCreateInfo
*sinfo
= &info
->pStages
[i
];
1188 gl_shader_stage stage
= vk_to_mesa_shader_stage(sinfo
->stage
);
1190 pipeline
->active_stages
|= sinfo
->stage
;
1192 int64_t stage_start
= os_time_get_nano();
1194 stages
[stage
].stage
= stage
;
1195 stages
[stage
].module
= anv_shader_module_from_handle(sinfo
->module
);
1196 stages
[stage
].entrypoint
= sinfo
->pName
;
1197 stages
[stage
].spec_info
= sinfo
->pSpecializationInfo
;
1198 anv_pipeline_hash_shader(stages
[stage
].module
,
1199 stages
[stage
].entrypoint
,
1201 stages
[stage
].spec_info
,
1202 stages
[stage
].shader_sha1
);
1204 const struct gen_device_info
*devinfo
= &pipeline
->base
.device
->info
;
1206 case MESA_SHADER_VERTEX
:
1207 populate_vs_prog_key(devinfo
, sinfo
->flags
, &stages
[stage
].key
.vs
);
1209 case MESA_SHADER_TESS_CTRL
:
1210 populate_tcs_prog_key(devinfo
, sinfo
->flags
,
1211 info
->pTessellationState
->patchControlPoints
,
1212 &stages
[stage
].key
.tcs
);
1214 case MESA_SHADER_TESS_EVAL
:
1215 populate_tes_prog_key(devinfo
, sinfo
->flags
, &stages
[stage
].key
.tes
);
1217 case MESA_SHADER_GEOMETRY
:
1218 populate_gs_prog_key(devinfo
, sinfo
->flags
, &stages
[stage
].key
.gs
);
1220 case MESA_SHADER_FRAGMENT
: {
1221 const bool raster_enabled
=
1222 !info
->pRasterizationState
->rasterizerDiscardEnable
;
1223 populate_wm_prog_key(devinfo
, sinfo
->flags
,
1225 raster_enabled
? info
->pMultisampleState
: NULL
,
1226 &stages
[stage
].key
.wm
);
1230 unreachable("Invalid graphics shader stage");
1233 stages
[stage
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1234 stages
[stage
].feedback
.flags
|= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
1237 if (pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
)
1238 pipeline
->active_stages
|= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
1240 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1242 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1244 unsigned char sha1
[20];
1245 anv_pipeline_hash_graphics(pipeline
, layout
, stages
, sha1
);
1247 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1248 if (!stages
[s
].entrypoint
)
1251 stages
[s
].cache_key
.stage
= s
;
1252 memcpy(stages
[s
].cache_key
.sha1
, sha1
, sizeof(sha1
));
1255 const bool skip_cache_lookup
=
1256 (pipeline
->base
.flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
);
1258 if (!skip_cache_lookup
) {
1260 unsigned cache_hits
= 0;
1261 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1262 if (!stages
[s
].entrypoint
)
1265 int64_t stage_start
= os_time_get_nano();
1268 struct anv_shader_bin
*bin
=
1269 anv_device_search_for_kernel(pipeline
->base
.device
, cache
,
1270 &stages
[s
].cache_key
,
1271 sizeof(stages
[s
].cache_key
), &cache_hit
);
1274 pipeline
->shaders
[s
] = bin
;
1279 stages
[s
].feedback
.flags
|=
1280 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1282 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1285 if (found
== __builtin_popcount(pipeline
->active_stages
)) {
1286 if (cache_hits
== found
) {
1287 pipeline_feedback
.flags
|=
1288 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1290 /* We found all our shaders in the cache. We're done. */
1291 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1292 if (!stages
[s
].entrypoint
)
1295 anv_pipeline_add_executables(&pipeline
->base
, &stages
[s
],
1296 pipeline
->shaders
[s
]);
1299 } else if (found
> 0) {
1300 /* We found some but not all of our shaders. This shouldn't happen
1301 * most of the time but it can if we have a partially populated
1304 assert(found
< __builtin_popcount(pipeline
->active_stages
));
1306 vk_debug_report(&pipeline
->base
.device
->physical
->instance
->debug_report_callbacks
,
1307 VK_DEBUG_REPORT_WARNING_BIT_EXT
|
1308 VK_DEBUG_REPORT_PERFORMANCE_WARNING_BIT_EXT
,
1309 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT
,
1310 (uint64_t)(uintptr_t)cache
,
1312 "Found a partial pipeline in the cache. This is "
1313 "most likely caused by an incomplete pipeline cache "
1314 "import or export");
1316 /* We're going to have to recompile anyway, so just throw away our
1317 * references to the shaders in the cache. We'll get them out of the
1318 * cache again as part of the compilation process.
1320 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1321 stages
[s
].feedback
.flags
= 0;
1322 if (pipeline
->shaders
[s
]) {
1323 anv_shader_bin_unref(pipeline
->base
.device
, pipeline
->shaders
[s
]);
1324 pipeline
->shaders
[s
] = NULL
;
1330 void *pipeline_ctx
= ralloc_context(NULL
);
1332 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1333 if (!stages
[s
].entrypoint
)
1336 int64_t stage_start
= os_time_get_nano();
1338 assert(stages
[s
].stage
== s
);
1339 assert(pipeline
->shaders
[s
] == NULL
);
1341 stages
[s
].bind_map
= (struct anv_pipeline_bind_map
) {
1342 .surface_to_descriptor
= stages
[s
].surface_to_descriptor
,
1343 .sampler_to_descriptor
= stages
[s
].sampler_to_descriptor
1346 stages
[s
].nir
= anv_pipeline_stage_get_nir(&pipeline
->base
, cache
,
1349 if (stages
[s
].nir
== NULL
) {
1350 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1354 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1357 /* Walk backwards to link */
1358 struct anv_pipeline_stage
*next_stage
= NULL
;
1359 for (int s
= MESA_SHADER_STAGES
- 1; s
>= 0; s
--) {
1360 if (!stages
[s
].entrypoint
)
1364 case MESA_SHADER_VERTEX
:
1365 anv_pipeline_link_vs(compiler
, &stages
[s
], next_stage
);
1367 case MESA_SHADER_TESS_CTRL
:
1368 anv_pipeline_link_tcs(compiler
, &stages
[s
], next_stage
);
1370 case MESA_SHADER_TESS_EVAL
:
1371 anv_pipeline_link_tes(compiler
, &stages
[s
], next_stage
);
1373 case MESA_SHADER_GEOMETRY
:
1374 anv_pipeline_link_gs(compiler
, &stages
[s
], next_stage
);
1376 case MESA_SHADER_FRAGMENT
:
1377 anv_pipeline_link_fs(compiler
, &stages
[s
]);
1380 unreachable("Invalid graphics shader stage");
1383 next_stage
= &stages
[s
];
1386 struct anv_pipeline_stage
*prev_stage
= NULL
;
1387 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1388 if (!stages
[s
].entrypoint
)
1391 int64_t stage_start
= os_time_get_nano();
1393 void *stage_ctx
= ralloc_context(NULL
);
1395 nir_xfb_info
*xfb_info
= NULL
;
1396 if (s
== MESA_SHADER_VERTEX
||
1397 s
== MESA_SHADER_TESS_EVAL
||
1398 s
== MESA_SHADER_GEOMETRY
)
1399 xfb_info
= nir_gather_xfb_info(stages
[s
].nir
, stage_ctx
);
1401 anv_pipeline_lower_nir(&pipeline
->base
, stage_ctx
, &stages
[s
], layout
);
1404 case MESA_SHADER_VERTEX
:
1405 anv_pipeline_compile_vs(compiler
, stage_ctx
, pipeline
->base
.device
,
1408 case MESA_SHADER_TESS_CTRL
:
1409 anv_pipeline_compile_tcs(compiler
, stage_ctx
, pipeline
->base
.device
,
1410 &stages
[s
], prev_stage
);
1412 case MESA_SHADER_TESS_EVAL
:
1413 anv_pipeline_compile_tes(compiler
, stage_ctx
, pipeline
->base
.device
,
1414 &stages
[s
], prev_stage
);
1416 case MESA_SHADER_GEOMETRY
:
1417 anv_pipeline_compile_gs(compiler
, stage_ctx
, pipeline
->base
.device
,
1418 &stages
[s
], prev_stage
);
1420 case MESA_SHADER_FRAGMENT
:
1421 anv_pipeline_compile_fs(compiler
, stage_ctx
, pipeline
->base
.device
,
1422 &stages
[s
], prev_stage
);
1425 unreachable("Invalid graphics shader stage");
1427 if (stages
[s
].code
== NULL
) {
1428 ralloc_free(stage_ctx
);
1429 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1433 anv_nir_validate_push_layout(&stages
[s
].prog_data
.base
,
1434 &stages
[s
].bind_map
);
1436 struct anv_shader_bin
*bin
=
1437 anv_device_upload_kernel(pipeline
->base
.device
, cache
, s
,
1438 &stages
[s
].cache_key
,
1439 sizeof(stages
[s
].cache_key
),
1441 stages
[s
].prog_data
.base
.program_size
,
1442 stages
[s
].nir
->constant_data
,
1443 stages
[s
].nir
->constant_data_size
,
1444 &stages
[s
].prog_data
.base
,
1445 brw_prog_data_size(s
),
1446 stages
[s
].stats
, stages
[s
].num_stats
,
1447 xfb_info
, &stages
[s
].bind_map
);
1449 ralloc_free(stage_ctx
);
1450 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1454 anv_pipeline_add_executables(&pipeline
->base
, &stages
[s
], bin
);
1456 pipeline
->shaders
[s
] = bin
;
1457 ralloc_free(stage_ctx
);
1459 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1461 prev_stage
= &stages
[s
];
1464 ralloc_free(pipeline_ctx
);
1468 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
] &&
1469 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->prog_data
->program_size
== 0) {
1470 /* This can happen if we decided to implicitly disable the fragment
1471 * shader. See anv_pipeline_compile_fs().
1473 anv_shader_bin_unref(pipeline
->base
.device
,
1474 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
1475 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] = NULL
;
1476 pipeline
->active_stages
&= ~VK_SHADER_STAGE_FRAGMENT_BIT
;
1479 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1481 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1482 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1483 if (create_feedback
) {
1484 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1486 assert(info
->stageCount
== create_feedback
->pipelineStageCreationFeedbackCount
);
1487 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1488 gl_shader_stage s
= vk_to_mesa_shader_stage(info
->pStages
[i
].stage
);
1489 create_feedback
->pPipelineStageCreationFeedbacks
[i
] = stages
[s
].feedback
;
1496 ralloc_free(pipeline_ctx
);
1498 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1499 if (pipeline
->shaders
[s
])
1500 anv_shader_bin_unref(pipeline
->base
.device
, pipeline
->shaders
[s
]);
1507 shared_type_info(const struct glsl_type
*type
, unsigned *size
, unsigned *align
)
1509 assert(glsl_type_is_vector_or_scalar(type
));
1511 uint32_t comp_size
= glsl_type_is_boolean(type
)
1512 ? 4 : glsl_get_bit_size(type
) / 8;
1513 unsigned length
= glsl_get_vector_elements(type
);
1514 *size
= comp_size
* length
,
1515 *align
= comp_size
* (length
== 3 ? 4 : length
);
1519 anv_pipeline_compile_cs(struct anv_compute_pipeline
*pipeline
,
1520 struct anv_pipeline_cache
*cache
,
1521 const VkComputePipelineCreateInfo
*info
,
1522 const struct anv_shader_module
*module
,
1523 const char *entrypoint
,
1524 const VkSpecializationInfo
*spec_info
)
1526 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1527 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1529 int64_t pipeline_start
= os_time_get_nano();
1531 const struct brw_compiler
*compiler
= pipeline
->base
.device
->physical
->compiler
;
1533 struct anv_pipeline_stage stage
= {
1534 .stage
= MESA_SHADER_COMPUTE
,
1536 .entrypoint
= entrypoint
,
1537 .spec_info
= spec_info
,
1539 .stage
= MESA_SHADER_COMPUTE
,
1542 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1545 anv_pipeline_hash_shader(stage
.module
,
1547 MESA_SHADER_COMPUTE
,
1551 struct anv_shader_bin
*bin
= NULL
;
1553 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*rss_info
=
1554 vk_find_struct_const(info
->stage
.pNext
,
1555 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
1557 populate_cs_prog_key(&pipeline
->base
.device
->info
, info
->stage
.flags
,
1558 rss_info
, &stage
.key
.cs
);
1560 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1562 const bool skip_cache_lookup
=
1563 (pipeline
->base
.flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
);
1565 anv_pipeline_hash_compute(pipeline
, layout
, &stage
, stage
.cache_key
.sha1
);
1567 bool cache_hit
= false;
1568 if (!skip_cache_lookup
) {
1569 bin
= anv_device_search_for_kernel(pipeline
->base
.device
, cache
,
1571 sizeof(stage
.cache_key
),
1575 void *mem_ctx
= ralloc_context(NULL
);
1577 int64_t stage_start
= os_time_get_nano();
1579 stage
.bind_map
= (struct anv_pipeline_bind_map
) {
1580 .surface_to_descriptor
= stage
.surface_to_descriptor
,
1581 .sampler_to_descriptor
= stage
.sampler_to_descriptor
1584 /* Set up a binding for the gl_NumWorkGroups */
1585 stage
.bind_map
.surface_count
= 1;
1586 stage
.bind_map
.surface_to_descriptor
[0] = (struct anv_pipeline_binding
) {
1587 .set
= ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
,
1590 stage
.nir
= anv_pipeline_stage_get_nir(&pipeline
->base
, cache
, mem_ctx
, &stage
);
1591 if (stage
.nir
== NULL
) {
1592 ralloc_free(mem_ctx
);
1593 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1596 NIR_PASS_V(stage
.nir
, anv_nir_add_base_work_group_id
);
1598 anv_pipeline_lower_nir(&pipeline
->base
, mem_ctx
, &stage
, layout
);
1600 NIR_PASS_V(stage
.nir
, nir_lower_vars_to_explicit_types
,
1601 nir_var_mem_shared
, shared_type_info
);
1602 NIR_PASS_V(stage
.nir
, nir_lower_explicit_io
,
1603 nir_var_mem_shared
, nir_address_format_32bit_offset
);
1605 stage
.num_stats
= 1;
1606 stage
.code
= brw_compile_cs(compiler
, pipeline
->base
.device
, mem_ctx
,
1607 &stage
.key
.cs
, &stage
.prog_data
.cs
,
1608 stage
.nir
, -1, stage
.stats
, NULL
);
1609 if (stage
.code
== NULL
) {
1610 ralloc_free(mem_ctx
);
1611 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1614 anv_nir_validate_push_layout(&stage
.prog_data
.base
, &stage
.bind_map
);
1616 if (!stage
.prog_data
.cs
.uses_num_work_groups
) {
1617 assert(stage
.bind_map
.surface_to_descriptor
[0].set
==
1618 ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
);
1619 stage
.bind_map
.surface_to_descriptor
[0].set
= ANV_DESCRIPTOR_SET_NULL
;
1622 const unsigned code_size
= stage
.prog_data
.base
.program_size
;
1623 bin
= anv_device_upload_kernel(pipeline
->base
.device
, cache
,
1624 MESA_SHADER_COMPUTE
,
1625 &stage
.cache_key
, sizeof(stage
.cache_key
),
1626 stage
.code
, code_size
,
1627 stage
.nir
->constant_data
,
1628 stage
.nir
->constant_data_size
,
1629 &stage
.prog_data
.base
,
1630 sizeof(stage
.prog_data
.cs
),
1631 stage
.stats
, stage
.num_stats
,
1632 NULL
, &stage
.bind_map
);
1634 ralloc_free(mem_ctx
);
1635 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1638 stage
.feedback
.duration
= os_time_get_nano() - stage_start
;
1641 anv_pipeline_add_executables(&pipeline
->base
, &stage
, bin
);
1643 ralloc_free(mem_ctx
);
1646 stage
.feedback
.flags
|=
1647 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1648 pipeline_feedback
.flags
|=
1649 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1651 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1653 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1654 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1655 if (create_feedback
) {
1656 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1658 assert(create_feedback
->pipelineStageCreationFeedbackCount
== 1);
1659 create_feedback
->pPipelineStageCreationFeedbacks
[0] = stage
.feedback
;
1668 * Copy pipeline state not marked as dynamic.
1669 * Dynamic state is pipeline state which hasn't been provided at pipeline
1670 * creation time, but is dynamically provided afterwards using various
1671 * vkCmdSet* functions.
1673 * The set of state considered "non_dynamic" is determined by the pieces of
1674 * state that have their corresponding VkDynamicState enums omitted from
1675 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1677 * @param[out] pipeline Destination non_dynamic state.
1678 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1681 copy_non_dynamic_state(struct anv_graphics_pipeline
*pipeline
,
1682 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1684 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
1685 struct anv_subpass
*subpass
= pipeline
->subpass
;
1687 pipeline
->dynamic_state
= default_dynamic_state
;
1689 if (pCreateInfo
->pDynamicState
) {
1690 /* Remove all of the states that are marked as dynamic */
1691 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1692 for (uint32_t s
= 0; s
< count
; s
++) {
1693 states
&= ~anv_cmd_dirty_bit_for_vk_dynamic_state(
1694 pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1698 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1700 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1702 * pViewportState is [...] NULL if the pipeline
1703 * has rasterization disabled.
1705 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1706 assert(pCreateInfo
->pViewportState
);
1708 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1709 if (states
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
) {
1710 typed_memcpy(dynamic
->viewport
.viewports
,
1711 pCreateInfo
->pViewportState
->pViewports
,
1712 pCreateInfo
->pViewportState
->viewportCount
);
1715 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1716 if (states
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
) {
1717 typed_memcpy(dynamic
->scissor
.scissors
,
1718 pCreateInfo
->pViewportState
->pScissors
,
1719 pCreateInfo
->pViewportState
->scissorCount
);
1723 if (states
& ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
) {
1724 assert(pCreateInfo
->pRasterizationState
);
1725 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1728 if (states
& ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
) {
1729 assert(pCreateInfo
->pRasterizationState
);
1730 dynamic
->depth_bias
.bias
=
1731 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1732 dynamic
->depth_bias
.clamp
=
1733 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1734 dynamic
->depth_bias
.slope
=
1735 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1738 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1740 * pColorBlendState is [...] NULL if the pipeline has rasterization
1741 * disabled or if the subpass of the render pass the pipeline is
1742 * created against does not use any color attachments.
1744 bool uses_color_att
= false;
1745 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1746 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1747 uses_color_att
= true;
1752 if (uses_color_att
&&
1753 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1754 assert(pCreateInfo
->pColorBlendState
);
1756 if (states
& ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
1757 typed_memcpy(dynamic
->blend_constants
,
1758 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1761 /* If there is no depthstencil attachment, then don't read
1762 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1763 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1764 * no need to override the depthstencil defaults in
1765 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1767 * Section 9.2 of the Vulkan 1.0.15 spec says:
1769 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1770 * disabled or if the subpass of the render pass the pipeline is created
1771 * against does not use a depth/stencil attachment.
1773 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1774 subpass
->depth_stencil_attachment
) {
1775 assert(pCreateInfo
->pDepthStencilState
);
1777 if (states
& ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
) {
1778 dynamic
->depth_bounds
.min
=
1779 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1780 dynamic
->depth_bounds
.max
=
1781 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1784 if (states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
) {
1785 dynamic
->stencil_compare_mask
.front
=
1786 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1787 dynamic
->stencil_compare_mask
.back
=
1788 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1791 if (states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
) {
1792 dynamic
->stencil_write_mask
.front
=
1793 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1794 dynamic
->stencil_write_mask
.back
=
1795 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1798 if (states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
) {
1799 dynamic
->stencil_reference
.front
=
1800 pCreateInfo
->pDepthStencilState
->front
.reference
;
1801 dynamic
->stencil_reference
.back
=
1802 pCreateInfo
->pDepthStencilState
->back
.reference
;
1806 const VkPipelineRasterizationLineStateCreateInfoEXT
*line_state
=
1807 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1808 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1810 if (states
& ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
) {
1811 dynamic
->line_stipple
.factor
= line_state
->lineStippleFactor
;
1812 dynamic
->line_stipple
.pattern
= line_state
->lineStipplePattern
;
1816 pipeline
->dynamic_state_mask
= states
;
1820 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1823 struct anv_render_pass
*renderpass
= NULL
;
1824 struct anv_subpass
*subpass
= NULL
;
1826 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1827 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1829 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1831 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1834 assert(info
->subpass
< renderpass
->subpass_count
);
1835 subpass
= &renderpass
->subpasses
[info
->subpass
];
1837 assert(info
->stageCount
>= 1);
1838 assert(info
->pVertexInputState
);
1839 assert(info
->pInputAssemblyState
);
1840 assert(info
->pRasterizationState
);
1841 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1842 assert(info
->pViewportState
);
1843 assert(info
->pMultisampleState
);
1845 if (subpass
&& subpass
->depth_stencil_attachment
)
1846 assert(info
->pDepthStencilState
);
1848 if (subpass
&& subpass
->color_count
> 0) {
1849 bool all_color_unused
= true;
1850 for (int i
= 0; i
< subpass
->color_count
; i
++) {
1851 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
1852 all_color_unused
= false;
1854 /* pColorBlendState is ignored if the pipeline has rasterization
1855 * disabled or if the subpass of the render pass the pipeline is
1856 * created against does not use any color attachments.
1858 assert(info
->pColorBlendState
|| all_color_unused
);
1862 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1863 switch (info
->pStages
[i
].stage
) {
1864 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1865 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1866 assert(info
->pTessellationState
);
1876 * Calculate the desired L3 partitioning based on the current state of the
1877 * pipeline. For now this simply returns the conservative defaults calculated
1878 * by get_default_l3_weights(), but we could probably do better by gathering
1879 * more statistics from the pipeline state (e.g. guess of expected URB usage
1880 * and bound surfaces), or by using feed-back from performance counters.
1883 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1885 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1887 const struct gen_l3_weights w
=
1888 gen_get_default_l3_weights(devinfo
, true, needs_slm
);
1890 pipeline
->l3_config
= gen_get_l3_config(devinfo
, w
);
1894 anv_pipeline_init(struct anv_graphics_pipeline
*pipeline
,
1895 struct anv_device
*device
,
1896 struct anv_pipeline_cache
*cache
,
1897 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1898 const VkAllocationCallbacks
*alloc
)
1902 anv_pipeline_validate_create_info(pCreateInfo
);
1905 alloc
= &device
->alloc
;
1907 pipeline
->base
.device
= device
;
1908 pipeline
->base
.type
= ANV_PIPELINE_GRAPHICS
;
1910 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, pCreateInfo
->renderPass
);
1911 assert(pCreateInfo
->subpass
< render_pass
->subpass_count
);
1912 pipeline
->subpass
= &render_pass
->subpasses
[pCreateInfo
->subpass
];
1914 result
= anv_reloc_list_init(&pipeline
->base
.batch_relocs
, alloc
);
1915 if (result
!= VK_SUCCESS
)
1918 pipeline
->base
.batch
.alloc
= alloc
;
1919 pipeline
->base
.batch
.next
= pipeline
->base
.batch
.start
= pipeline
->batch_data
;
1920 pipeline
->base
.batch
.end
= pipeline
->base
.batch
.start
+ sizeof(pipeline
->batch_data
);
1921 pipeline
->base
.batch
.relocs
= &pipeline
->base
.batch_relocs
;
1922 pipeline
->base
.batch
.status
= VK_SUCCESS
;
1924 pipeline
->base
.mem_ctx
= ralloc_context(NULL
);
1925 pipeline
->base
.flags
= pCreateInfo
->flags
;
1927 assert(pCreateInfo
->pRasterizationState
);
1929 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1930 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
->depthClampEnable
;
1932 /* Previously we enabled depth clipping when !depthClampEnable.
1933 * DepthClipStateCreateInfo now makes depth clipping explicit so if the
1934 * clipping info is available, use its enable value to determine clipping,
1935 * otherwise fallback to the previous !depthClampEnable logic.
1937 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*clip_info
=
1938 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1939 PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
1940 pipeline
->depth_clip_enable
= clip_info
? clip_info
->depthClipEnable
: !pipeline
->depth_clamp_enable
;
1942 pipeline
->sample_shading_enable
=
1943 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1944 pCreateInfo
->pMultisampleState
&&
1945 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
1947 /* When we free the pipeline, we detect stages based on the NULL status
1948 * of various prog_data pointers. Make them NULL by default.
1950 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1952 util_dynarray_init(&pipeline
->base
.executables
, pipeline
->base
.mem_ctx
);
1954 result
= anv_pipeline_compile_graphics(pipeline
, cache
, pCreateInfo
);
1955 if (result
!= VK_SUCCESS
) {
1956 ralloc_free(pipeline
->base
.mem_ctx
);
1957 anv_reloc_list_finish(&pipeline
->base
.batch_relocs
, alloc
);
1961 assert(pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1963 anv_pipeline_setup_l3_config(&pipeline
->base
, false);
1965 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1966 pCreateInfo
->pVertexInputState
;
1968 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1970 pipeline
->vb_used
= 0;
1971 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1972 const VkVertexInputAttributeDescription
*desc
=
1973 &vi_info
->pVertexAttributeDescriptions
[i
];
1975 if (inputs_read
& (1ull << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1976 pipeline
->vb_used
|= 1 << desc
->binding
;
1979 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1980 const VkVertexInputBindingDescription
*desc
=
1981 &vi_info
->pVertexBindingDescriptions
[i
];
1983 pipeline
->vb
[desc
->binding
].stride
= desc
->stride
;
1985 /* Step rate is programmed per vertex element (attribute), not
1986 * binding. Set up a map of which bindings step per instance, for
1987 * reference by vertex element setup. */
1988 switch (desc
->inputRate
) {
1990 case VK_VERTEX_INPUT_RATE_VERTEX
:
1991 pipeline
->vb
[desc
->binding
].instanced
= false;
1993 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1994 pipeline
->vb
[desc
->binding
].instanced
= true;
1998 pipeline
->vb
[desc
->binding
].instance_divisor
= 1;
2001 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*vi_div_state
=
2002 vk_find_struct_const(vi_info
->pNext
,
2003 PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
2005 for (uint32_t i
= 0; i
< vi_div_state
->vertexBindingDivisorCount
; i
++) {
2006 const VkVertexInputBindingDivisorDescriptionEXT
*desc
=
2007 &vi_div_state
->pVertexBindingDivisors
[i
];
2009 pipeline
->vb
[desc
->binding
].instance_divisor
= desc
->divisor
;
2013 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2014 * different views. If the client asks for instancing, we need to multiply
2015 * the instance divisor by the number of views ensure that we repeat the
2016 * client's per-instance data once for each view.
2018 if (pipeline
->subpass
->view_mask
) {
2019 const uint32_t view_count
= anv_subpass_view_count(pipeline
->subpass
);
2020 for (uint32_t vb
= 0; vb
< MAX_VBS
; vb
++) {
2021 if (pipeline
->vb
[vb
].instanced
)
2022 pipeline
->vb
[vb
].instance_divisor
*= view_count
;
2026 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
2027 pCreateInfo
->pInputAssemblyState
;
2028 const VkPipelineTessellationStateCreateInfo
*tess_info
=
2029 pCreateInfo
->pTessellationState
;
2030 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
2032 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
2033 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
2035 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];
2040 #define WRITE_STR(field, ...) ({ \
2041 memset(field, 0, sizeof(field)); \
2042 UNUSED int i = snprintf(field, sizeof(field), __VA_ARGS__); \
2043 assert(i > 0 && i < sizeof(field)); \
2046 VkResult
anv_GetPipelineExecutablePropertiesKHR(
2048 const VkPipelineInfoKHR
* pPipelineInfo
,
2049 uint32_t* pExecutableCount
,
2050 VkPipelineExecutablePropertiesKHR
* pProperties
)
2052 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
2053 VK_OUTARRAY_MAKE(out
, pProperties
, pExecutableCount
);
2055 util_dynarray_foreach (&pipeline
->executables
, struct anv_pipeline_executable
, exe
) {
2056 vk_outarray_append(&out
, props
) {
2057 gl_shader_stage stage
= exe
->stage
;
2058 props
->stages
= mesa_to_vk_shader_stage(stage
);
2060 unsigned simd_width
= exe
->stats
.dispatch_width
;
2061 if (stage
== MESA_SHADER_FRAGMENT
) {
2062 WRITE_STR(props
->name
, "%s%d %s",
2063 simd_width
? "SIMD" : "vec",
2064 simd_width
? simd_width
: 4,
2065 _mesa_shader_stage_to_string(stage
));
2067 WRITE_STR(props
->name
, "%s", _mesa_shader_stage_to_string(stage
));
2069 WRITE_STR(props
->description
, "%s%d %s shader",
2070 simd_width
? "SIMD" : "vec",
2071 simd_width
? simd_width
: 4,
2072 _mesa_shader_stage_to_string(stage
));
2074 /* The compiler gives us a dispatch width of 0 for vec4 but Vulkan
2075 * wants a subgroup size of 1.
2077 props
->subgroupSize
= MAX2(simd_width
, 1);
2081 return vk_outarray_status(&out
);
2084 static const struct anv_pipeline_executable
*
2085 anv_pipeline_get_executable(struct anv_pipeline
*pipeline
, uint32_t index
)
2087 assert(index
< util_dynarray_num_elements(&pipeline
->executables
,
2088 struct anv_pipeline_executable
));
2089 return util_dynarray_element(
2090 &pipeline
->executables
, struct anv_pipeline_executable
, index
);
2093 VkResult
anv_GetPipelineExecutableStatisticsKHR(
2095 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
2096 uint32_t* pStatisticCount
,
2097 VkPipelineExecutableStatisticKHR
* pStatistics
)
2099 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
2100 VK_OUTARRAY_MAKE(out
, pStatistics
, pStatisticCount
);
2102 const struct anv_pipeline_executable
*exe
=
2103 anv_pipeline_get_executable(pipeline
, pExecutableInfo
->executableIndex
);
2105 const struct brw_stage_prog_data
*prog_data
;
2106 switch (pipeline
->type
) {
2107 case ANV_PIPELINE_GRAPHICS
: {
2108 prog_data
= anv_pipeline_to_graphics(pipeline
)->shaders
[exe
->stage
]->prog_data
;
2111 case ANV_PIPELINE_COMPUTE
: {
2112 prog_data
= anv_pipeline_to_compute(pipeline
)->cs
->prog_data
;
2116 unreachable("invalid pipeline type");
2119 vk_outarray_append(&out
, stat
) {
2120 WRITE_STR(stat
->name
, "Instruction Count");
2121 WRITE_STR(stat
->description
,
2122 "Number of GEN instructions in the final generated "
2123 "shader executable.");
2124 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2125 stat
->value
.u64
= exe
->stats
.instructions
;
2128 vk_outarray_append(&out
, stat
) {
2129 WRITE_STR(stat
->name
, "Loop Count");
2130 WRITE_STR(stat
->description
,
2131 "Number of loops (not unrolled) in the final generated "
2132 "shader executable.");
2133 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2134 stat
->value
.u64
= exe
->stats
.loops
;
2137 vk_outarray_append(&out
, stat
) {
2138 WRITE_STR(stat
->name
, "Cycle Count");
2139 WRITE_STR(stat
->description
,
2140 "Estimate of the number of EU cycles required to execute "
2141 "the final generated executable. This is an estimate only "
2142 "and may vary greatly from actual run-time performance.");
2143 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2144 stat
->value
.u64
= exe
->stats
.cycles
;
2147 vk_outarray_append(&out
, stat
) {
2148 WRITE_STR(stat
->name
, "Spill Count");
2149 WRITE_STR(stat
->description
,
2150 "Number of scratch spill operations. This gives a rough "
2151 "estimate of the cost incurred due to spilling temporary "
2152 "values to memory. If this is non-zero, you may want to "
2153 "adjust your shader to reduce register pressure.");
2154 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2155 stat
->value
.u64
= exe
->stats
.spills
;
2158 vk_outarray_append(&out
, stat
) {
2159 WRITE_STR(stat
->name
, "Fill Count");
2160 WRITE_STR(stat
->description
,
2161 "Number of scratch fill operations. This gives a rough "
2162 "estimate of the cost incurred due to spilling temporary "
2163 "values to memory. If this is non-zero, you may want to "
2164 "adjust your shader to reduce register pressure.");
2165 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2166 stat
->value
.u64
= exe
->stats
.fills
;
2169 vk_outarray_append(&out
, stat
) {
2170 WRITE_STR(stat
->name
, "Scratch Memory Size");
2171 WRITE_STR(stat
->description
,
2172 "Number of bytes of scratch memory required by the "
2173 "generated shader executable. If this is non-zero, you "
2174 "may want to adjust your shader to reduce register "
2176 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2177 stat
->value
.u64
= prog_data
->total_scratch
;
2180 if (exe
->stage
== MESA_SHADER_COMPUTE
) {
2181 vk_outarray_append(&out
, stat
) {
2182 WRITE_STR(stat
->name
, "Workgroup Memory Size");
2183 WRITE_STR(stat
->description
,
2184 "Number of bytes of workgroup shared memory used by this "
2185 "compute shader including any padding.");
2186 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2187 stat
->value
.u64
= prog_data
->total_scratch
;
2191 return vk_outarray_status(&out
);
2195 write_ir_text(VkPipelineExecutableInternalRepresentationKHR
* ir
,
2198 ir
->isText
= VK_TRUE
;
2200 size_t data_len
= strlen(data
) + 1;
2202 if (ir
->pData
== NULL
) {
2203 ir
->dataSize
= data_len
;
2207 strncpy(ir
->pData
, data
, ir
->dataSize
);
2208 if (ir
->dataSize
< data_len
)
2211 ir
->dataSize
= data_len
;
2215 VkResult
anv_GetPipelineExecutableInternalRepresentationsKHR(
2217 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
2218 uint32_t* pInternalRepresentationCount
,
2219 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
2221 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
2222 VK_OUTARRAY_MAKE(out
, pInternalRepresentations
,
2223 pInternalRepresentationCount
);
2224 bool incomplete_text
= false;
2226 const struct anv_pipeline_executable
*exe
=
2227 anv_pipeline_get_executable(pipeline
, pExecutableInfo
->executableIndex
);
2230 vk_outarray_append(&out
, ir
) {
2231 WRITE_STR(ir
->name
, "Final NIR");
2232 WRITE_STR(ir
->description
,
2233 "Final NIR before going into the back-end compiler");
2235 if (!write_ir_text(ir
, exe
->nir
))
2236 incomplete_text
= true;
2241 vk_outarray_append(&out
, ir
) {
2242 WRITE_STR(ir
->name
, "GEN Assembly");
2243 WRITE_STR(ir
->description
,
2244 "Final GEN assembly for the generated shader binary");
2246 if (!write_ir_text(ir
, exe
->disasm
))
2247 incomplete_text
= true;
2251 return incomplete_text
? VK_INCOMPLETE
: vk_outarray_status(&out
);