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anv/descriptor_set: Ensure that bindings are always in increasing order
[mesa.git] / src / intel / vulkan / anv_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "util/mesa-sha1.h"
31 #include "anv_private.h"
32 #include "brw_nir.h"
33 #include "anv_nir.h"
34 #include "spirv/nir_spirv.h"
35
36 /* Needed for SWIZZLE macros */
37 #include "program/prog_instruction.h"
38
39 // Shader functions
40
41 VkResult anv_CreateShaderModule(
42 VkDevice _device,
43 const VkShaderModuleCreateInfo* pCreateInfo,
44 const VkAllocationCallbacks* pAllocator,
45 VkShaderModule* pShaderModule)
46 {
47 ANV_FROM_HANDLE(anv_device, device, _device);
48 struct anv_shader_module *module;
49
50 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
51 assert(pCreateInfo->flags == 0);
52
53 module = anv_alloc2(&device->alloc, pAllocator,
54 sizeof(*module) + pCreateInfo->codeSize, 8,
55 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
56 if (module == NULL)
57 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
58
59 module->nir = NULL;
60 module->size = pCreateInfo->codeSize;
61 memcpy(module->data, pCreateInfo->pCode, module->size);
62
63 _mesa_sha1_compute(module->data, module->size, module->sha1);
64
65 *pShaderModule = anv_shader_module_to_handle(module);
66
67 return VK_SUCCESS;
68 }
69
70 void anv_DestroyShaderModule(
71 VkDevice _device,
72 VkShaderModule _module,
73 const VkAllocationCallbacks* pAllocator)
74 {
75 ANV_FROM_HANDLE(anv_device, device, _device);
76 ANV_FROM_HANDLE(anv_shader_module, module, _module);
77
78 anv_free2(&device->alloc, pAllocator, module);
79 }
80
81 #define SPIR_V_MAGIC_NUMBER 0x07230203
82
83 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
84 * we can't do that yet because we don't have the ability to copy nir.
85 */
86 static nir_shader *
87 anv_shader_compile_to_nir(struct anv_device *device,
88 struct anv_shader_module *module,
89 const char *entrypoint_name,
90 gl_shader_stage stage,
91 const VkSpecializationInfo *spec_info)
92 {
93 if (strcmp(entrypoint_name, "main") != 0) {
94 anv_finishme("Multiple shaders per module not really supported");
95 }
96
97 const struct brw_compiler *compiler =
98 device->instance->physicalDevice.compiler;
99 const nir_shader_compiler_options *nir_options =
100 compiler->glsl_compiler_options[stage].NirOptions;
101
102 nir_shader *nir;
103 nir_function *entry_point;
104 if (module->nir) {
105 /* Some things such as our meta clear/blit code will give us a NIR
106 * shader directly. In that case, we just ignore the SPIR-V entirely
107 * and just use the NIR shader */
108 nir = module->nir;
109 nir->options = nir_options;
110 nir_validate_shader(nir);
111
112 assert(exec_list_length(&nir->functions) == 1);
113 struct exec_node *node = exec_list_get_head(&nir->functions);
114 entry_point = exec_node_data(nir_function, node, node);
115 } else {
116 uint32_t *spirv = (uint32_t *) module->data;
117 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
118 assert(module->size % 4 == 0);
119
120 uint32_t num_spec_entries = 0;
121 struct nir_spirv_specialization *spec_entries = NULL;
122 if (spec_info && spec_info->mapEntryCount > 0) {
123 num_spec_entries = spec_info->mapEntryCount;
124 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
125 for (uint32_t i = 0; i < num_spec_entries; i++) {
126 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
127 const void *data = spec_info->pData + entry.offset;
128 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
129
130 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
131 spec_entries[i].data = *(const uint32_t *)data;
132 }
133 }
134
135 entry_point = spirv_to_nir(spirv, module->size / 4,
136 spec_entries, num_spec_entries,
137 stage, entrypoint_name, nir_options);
138 nir = entry_point->shader;
139 assert(nir->stage == stage);
140 nir_validate_shader(nir);
141
142 free(spec_entries);
143
144 if (stage == MESA_SHADER_FRAGMENT) {
145 nir_lower_wpos_center(nir);
146 nir_validate_shader(nir);
147 }
148
149 nir_lower_returns(nir);
150 nir_validate_shader(nir);
151
152 nir_inline_functions(nir);
153 nir_validate_shader(nir);
154
155 /* Pick off the single entrypoint that we want */
156 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
157 if (func != entry_point)
158 exec_node_remove(&func->node);
159 }
160 assert(exec_list_length(&nir->functions) == 1);
161 entry_point->name = ralloc_strdup(entry_point, "main");
162
163 nir_remove_dead_variables(nir, nir_var_shader_in);
164 nir_remove_dead_variables(nir, nir_var_shader_out);
165 nir_remove_dead_variables(nir, nir_var_system_value);
166 nir_validate_shader(nir);
167
168 nir_lower_io_to_temporaries(entry_point->shader, entry_point, true, false);
169
170 nir_lower_system_values(nir);
171 nir_validate_shader(nir);
172 }
173
174 /* Vulkan uses the separate-shader linking model */
175 nir->info.separate_shader = true;
176
177 nir = brw_preprocess_nir(compiler, nir);
178
179 nir_shader_gather_info(nir, entry_point->impl);
180
181 nir_variable_mode indirect_mask = 0;
182 if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput)
183 indirect_mask |= nir_var_shader_in;
184 if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
185 indirect_mask |= nir_var_local;
186
187 nir_lower_indirect_derefs(nir, indirect_mask);
188
189 return nir;
190 }
191
192 void anv_DestroyPipeline(
193 VkDevice _device,
194 VkPipeline _pipeline,
195 const VkAllocationCallbacks* pAllocator)
196 {
197 ANV_FROM_HANDLE(anv_device, device, _device);
198 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
199
200 anv_reloc_list_finish(&pipeline->batch_relocs,
201 pAllocator ? pAllocator : &device->alloc);
202 if (pipeline->blend_state.map)
203 anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
204 anv_free2(&device->alloc, pAllocator, pipeline);
205 }
206
207 static const uint32_t vk_to_gen_primitive_type[] = {
208 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
209 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
210 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
211 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
212 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
213 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
214 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
215 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
216 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
217 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
218 /* [VK_PRIMITIVE_TOPOLOGY_PATCH_LIST] = _3DPRIM_PATCHLIST_1 */
219 };
220
221 static void
222 populate_sampler_prog_key(const struct brw_device_info *devinfo,
223 struct brw_sampler_prog_key_data *key)
224 {
225 /* XXX: Handle texture swizzle on HSW- */
226 for (int i = 0; i < MAX_SAMPLERS; i++) {
227 /* Assume color sampler, no swizzling. (Works for BDW+) */
228 key->swizzles[i] = SWIZZLE_XYZW;
229 }
230 }
231
232 static void
233 populate_vs_prog_key(const struct brw_device_info *devinfo,
234 struct brw_vs_prog_key *key)
235 {
236 memset(key, 0, sizeof(*key));
237
238 populate_sampler_prog_key(devinfo, &key->tex);
239
240 /* XXX: Handle vertex input work-arounds */
241
242 /* XXX: Handle sampler_prog_key */
243 }
244
245 static void
246 populate_gs_prog_key(const struct brw_device_info *devinfo,
247 struct brw_gs_prog_key *key)
248 {
249 memset(key, 0, sizeof(*key));
250
251 populate_sampler_prog_key(devinfo, &key->tex);
252 }
253
254 static void
255 populate_wm_prog_key(const struct brw_device_info *devinfo,
256 const VkGraphicsPipelineCreateInfo *info,
257 const struct anv_graphics_pipeline_create_info *extra,
258 struct brw_wm_prog_key *key)
259 {
260 ANV_FROM_HANDLE(anv_render_pass, render_pass, info->renderPass);
261
262 memset(key, 0, sizeof(*key));
263
264 populate_sampler_prog_key(devinfo, &key->tex);
265
266 /* TODO: Fill out key->input_slots_valid */
267
268 /* Vulkan doesn't specify a default */
269 key->high_quality_derivatives = false;
270
271 /* XXX Vulkan doesn't appear to specify */
272 key->clamp_fragment_color = false;
273
274 if (extra && extra->color_attachment_count >= 0) {
275 key->nr_color_regions = extra->color_attachment_count;
276 } else {
277 key->nr_color_regions =
278 render_pass->subpasses[info->subpass].color_count;
279 }
280
281 key->replicate_alpha = key->nr_color_regions > 1 &&
282 info->pMultisampleState &&
283 info->pMultisampleState->alphaToCoverageEnable;
284
285 if (info->pMultisampleState && info->pMultisampleState->rasterizationSamples > 1) {
286 /* We should probably pull this out of the shader, but it's fairly
287 * harmless to compute it and then let dead-code take care of it.
288 */
289 key->persample_interp =
290 (info->pMultisampleState->minSampleShading *
291 info->pMultisampleState->rasterizationSamples) > 1;
292 key->multisample_fbo = true;
293 }
294 }
295
296 static void
297 populate_cs_prog_key(const struct brw_device_info *devinfo,
298 struct brw_cs_prog_key *key)
299 {
300 memset(key, 0, sizeof(*key));
301
302 populate_sampler_prog_key(devinfo, &key->tex);
303 }
304
305 static nir_shader *
306 anv_pipeline_compile(struct anv_pipeline *pipeline,
307 struct anv_shader_module *module,
308 const char *entrypoint,
309 gl_shader_stage stage,
310 const VkSpecializationInfo *spec_info,
311 struct brw_stage_prog_data *prog_data,
312 struct anv_pipeline_bind_map *map)
313 {
314 nir_shader *nir = anv_shader_compile_to_nir(pipeline->device,
315 module, entrypoint, stage,
316 spec_info);
317 if (nir == NULL)
318 return NULL;
319
320 anv_nir_lower_push_constants(nir);
321
322 /* Figure out the number of parameters */
323 prog_data->nr_params = 0;
324
325 if (nir->num_uniforms > 0) {
326 /* If the shader uses any push constants at all, we'll just give
327 * them the maximum possible number
328 */
329 prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
330 }
331
332 if (pipeline->layout && pipeline->layout->stage[stage].has_dynamic_offsets)
333 prog_data->nr_params += MAX_DYNAMIC_BUFFERS * 2;
334
335 if (nir->info.num_images > 0) {
336 prog_data->nr_params += nir->info.num_images * BRW_IMAGE_PARAM_SIZE;
337 pipeline->needs_data_cache = true;
338 }
339
340 if (stage == MESA_SHADER_COMPUTE)
341 ((struct brw_cs_prog_data *)prog_data)->thread_local_id_index =
342 prog_data->nr_params++; /* The CS Thread ID uniform */
343
344 if (nir->info.num_ssbos > 0)
345 pipeline->needs_data_cache = true;
346
347 if (prog_data->nr_params > 0) {
348 /* XXX: I think we're leaking this */
349 prog_data->param = (const union gl_constant_value **)
350 malloc(prog_data->nr_params * sizeof(union gl_constant_value *));
351
352 /* We now set the param values to be offsets into a
353 * anv_push_constant_data structure. Since the compiler doesn't
354 * actually dereference any of the gl_constant_value pointers in the
355 * params array, it doesn't really matter what we put here.
356 */
357 struct anv_push_constants *null_data = NULL;
358 if (nir->num_uniforms > 0) {
359 /* Fill out the push constants section of the param array */
360 for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++)
361 prog_data->param[i] = (const union gl_constant_value *)
362 &null_data->client_data[i * sizeof(float)];
363 }
364 }
365
366 /* Set up dynamic offsets */
367 anv_nir_apply_dynamic_offsets(pipeline, nir, prog_data);
368
369 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
370 if (pipeline->layout)
371 anv_nir_apply_pipeline_layout(pipeline, nir, prog_data, map);
372
373 /* nir_lower_io will only handle the push constants; we need to set this
374 * to the full number of possible uniforms.
375 */
376 nir->num_uniforms = prog_data->nr_params * 4;
377
378 return nir;
379 }
380
381 static void
382 anv_fill_binding_table(struct brw_stage_prog_data *prog_data, unsigned bias)
383 {
384 prog_data->binding_table.size_bytes = 0;
385 prog_data->binding_table.texture_start = bias;
386 prog_data->binding_table.ubo_start = bias;
387 prog_data->binding_table.ssbo_start = bias;
388 prog_data->binding_table.image_start = bias;
389 }
390
391 static void
392 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
393 gl_shader_stage stage,
394 const struct brw_stage_prog_data *prog_data,
395 struct anv_pipeline_bind_map *map)
396 {
397 struct brw_device_info *devinfo = &pipeline->device->info;
398 uint32_t max_threads[] = {
399 [MESA_SHADER_VERTEX] = devinfo->max_vs_threads,
400 [MESA_SHADER_TESS_CTRL] = devinfo->max_hs_threads,
401 [MESA_SHADER_TESS_EVAL] = devinfo->max_ds_threads,
402 [MESA_SHADER_GEOMETRY] = devinfo->max_gs_threads,
403 [MESA_SHADER_FRAGMENT] = devinfo->max_wm_threads,
404 [MESA_SHADER_COMPUTE] = devinfo->max_cs_threads,
405 };
406
407 pipeline->prog_data[stage] = prog_data;
408 pipeline->active_stages |= mesa_to_vk_shader_stage(stage);
409 pipeline->scratch_start[stage] = pipeline->total_scratch;
410 pipeline->total_scratch =
411 align_u32(pipeline->total_scratch, 1024) +
412 prog_data->total_scratch * max_threads[stage];
413 pipeline->bindings[stage] = *map;
414 }
415
416 static VkResult
417 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
418 struct anv_pipeline_cache *cache,
419 const VkGraphicsPipelineCreateInfo *info,
420 struct anv_shader_module *module,
421 const char *entrypoint,
422 const VkSpecializationInfo *spec_info)
423 {
424 const struct brw_compiler *compiler =
425 pipeline->device->instance->physicalDevice.compiler;
426 const struct brw_stage_prog_data *stage_prog_data;
427 struct anv_pipeline_bind_map map;
428 struct brw_vs_prog_key key;
429 uint32_t kernel = NO_KERNEL;
430 unsigned char sha1[20];
431
432 populate_vs_prog_key(&pipeline->device->info, &key);
433
434 if (module->size > 0) {
435 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, spec_info);
436 kernel = anv_pipeline_cache_search(cache, sha1, &stage_prog_data, &map);
437 }
438
439 if (kernel == NO_KERNEL) {
440 struct brw_vs_prog_data prog_data = { 0, };
441 struct anv_pipeline_binding surface_to_descriptor[256];
442 struct anv_pipeline_binding sampler_to_descriptor[256];
443
444 map = (struct anv_pipeline_bind_map) {
445 .surface_to_descriptor = surface_to_descriptor,
446 .sampler_to_descriptor = sampler_to_descriptor
447 };
448
449 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
450 MESA_SHADER_VERTEX, spec_info,
451 &prog_data.base.base, &map);
452 if (nir == NULL)
453 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
454
455 anv_fill_binding_table(&prog_data.base.base, 0);
456
457 void *mem_ctx = ralloc_context(NULL);
458
459 if (module->nir == NULL)
460 ralloc_steal(mem_ctx, nir);
461
462 prog_data.inputs_read = nir->info.inputs_read;
463
464 brw_compute_vue_map(&pipeline->device->info,
465 &prog_data.base.vue_map,
466 nir->info.outputs_written,
467 nir->info.separate_shader);
468
469 unsigned code_size;
470 const unsigned *shader_code =
471 brw_compile_vs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
472 NULL, false, -1, &code_size, NULL);
473 if (shader_code == NULL) {
474 ralloc_free(mem_ctx);
475 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
476 }
477
478 stage_prog_data = &prog_data.base.base;
479 kernel = anv_pipeline_cache_upload_kernel(cache,
480 module->size > 0 ? sha1 : NULL,
481 shader_code, code_size,
482 &stage_prog_data, sizeof(prog_data),
483 &map);
484 ralloc_free(mem_ctx);
485 }
486
487 const struct brw_vs_prog_data *vs_prog_data =
488 (const struct brw_vs_prog_data *) stage_prog_data;
489
490 if (vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8) {
491 pipeline->vs_simd8 = kernel;
492 pipeline->vs_vec4 = NO_KERNEL;
493 } else {
494 pipeline->vs_simd8 = NO_KERNEL;
495 pipeline->vs_vec4 = kernel;
496 }
497
498 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX,
499 stage_prog_data, &map);
500
501 return VK_SUCCESS;
502 }
503
504 static VkResult
505 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
506 struct anv_pipeline_cache *cache,
507 const VkGraphicsPipelineCreateInfo *info,
508 struct anv_shader_module *module,
509 const char *entrypoint,
510 const VkSpecializationInfo *spec_info)
511 {
512 const struct brw_compiler *compiler =
513 pipeline->device->instance->physicalDevice.compiler;
514 const struct brw_stage_prog_data *stage_prog_data;
515 struct anv_pipeline_bind_map map;
516 struct brw_gs_prog_key key;
517 uint32_t kernel = NO_KERNEL;
518 unsigned char sha1[20];
519
520 populate_gs_prog_key(&pipeline->device->info, &key);
521
522 if (module->size > 0) {
523 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, spec_info);
524 kernel = anv_pipeline_cache_search(cache, sha1, &stage_prog_data, &map);
525 }
526
527 if (kernel == NO_KERNEL) {
528 struct brw_gs_prog_data prog_data = { 0, };
529 struct anv_pipeline_binding surface_to_descriptor[256];
530 struct anv_pipeline_binding sampler_to_descriptor[256];
531
532 map = (struct anv_pipeline_bind_map) {
533 .surface_to_descriptor = surface_to_descriptor,
534 .sampler_to_descriptor = sampler_to_descriptor
535 };
536
537 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
538 MESA_SHADER_GEOMETRY, spec_info,
539 &prog_data.base.base, &map);
540 if (nir == NULL)
541 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
542
543 anv_fill_binding_table(&prog_data.base.base, 0);
544
545 void *mem_ctx = ralloc_context(NULL);
546
547 if (module->nir == NULL)
548 ralloc_steal(mem_ctx, nir);
549
550 brw_compute_vue_map(&pipeline->device->info,
551 &prog_data.base.vue_map,
552 nir->info.outputs_written,
553 nir->info.separate_shader);
554
555 unsigned code_size;
556 const unsigned *shader_code =
557 brw_compile_gs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
558 NULL, -1, &code_size, NULL);
559 if (shader_code == NULL) {
560 ralloc_free(mem_ctx);
561 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
562 }
563
564 /* TODO: SIMD8 GS */
565 stage_prog_data = &prog_data.base.base;
566 kernel = anv_pipeline_cache_upload_kernel(cache,
567 module->size > 0 ? sha1 : NULL,
568 shader_code, code_size,
569 &stage_prog_data, sizeof(prog_data),
570 &map);
571
572 ralloc_free(mem_ctx);
573 }
574
575 pipeline->gs_kernel = kernel;
576
577 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY,
578 stage_prog_data, &map);
579
580 return VK_SUCCESS;
581 }
582
583 static VkResult
584 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
585 struct anv_pipeline_cache *cache,
586 const VkGraphicsPipelineCreateInfo *info,
587 const struct anv_graphics_pipeline_create_info *extra,
588 struct anv_shader_module *module,
589 const char *entrypoint,
590 const VkSpecializationInfo *spec_info)
591 {
592 const struct brw_compiler *compiler =
593 pipeline->device->instance->physicalDevice.compiler;
594 const struct brw_stage_prog_data *stage_prog_data;
595 struct anv_pipeline_bind_map map;
596 struct brw_wm_prog_key key;
597 unsigned char sha1[20];
598
599 populate_wm_prog_key(&pipeline->device->info, info, extra, &key);
600
601 if (module->size > 0) {
602 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, spec_info);
603 pipeline->ps_ksp0 =
604 anv_pipeline_cache_search(cache, sha1, &stage_prog_data, &map);
605 }
606
607 if (pipeline->ps_ksp0 == NO_KERNEL) {
608 struct brw_wm_prog_data prog_data = { 0, };
609 struct anv_pipeline_binding surface_to_descriptor[256];
610 struct anv_pipeline_binding sampler_to_descriptor[256];
611
612 map = (struct anv_pipeline_bind_map) {
613 .surface_to_descriptor = surface_to_descriptor + 8,
614 .sampler_to_descriptor = sampler_to_descriptor
615 };
616
617 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
618 MESA_SHADER_FRAGMENT, spec_info,
619 &prog_data.base, &map);
620 if (nir == NULL)
621 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
622
623 unsigned num_rts = 0;
624 struct anv_pipeline_binding rt_bindings[8];
625 nir_function_impl *impl = nir_shader_get_entrypoint(nir)->impl;
626 nir_foreach_variable_safe(var, &nir->outputs) {
627 if (var->data.location < FRAG_RESULT_DATA0)
628 continue;
629
630 unsigned rt = var->data.location - FRAG_RESULT_DATA0;
631 if (rt >= key.nr_color_regions) {
632 /* Out-of-bounds, throw it away */
633 var->data.mode = nir_var_local;
634 exec_node_remove(&var->node);
635 exec_list_push_tail(&impl->locals, &var->node);
636 continue;
637 }
638
639 /* Give it a new, compacted, location */
640 var->data.location = FRAG_RESULT_DATA0 + num_rts;
641
642 unsigned array_len =
643 glsl_type_is_array(var->type) ? glsl_get_length(var->type) : 1;
644 assert(num_rts + array_len <= 8);
645
646 for (unsigned i = 0; i < array_len; i++) {
647 rt_bindings[num_rts] = (struct anv_pipeline_binding) {
648 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
649 .offset = rt + i,
650 };
651 }
652
653 num_rts += array_len;
654 }
655
656 if (pipeline->use_repclear) {
657 assert(num_rts == 1);
658 key.nr_color_regions = 1;
659 }
660
661 if (num_rts == 0) {
662 /* If we have no render targets, we need a null render target */
663 rt_bindings[0] = (struct anv_pipeline_binding) {
664 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
665 .offset = UINT16_MAX,
666 };
667 num_rts = 1;
668 }
669
670 assert(num_rts <= 8);
671 map.surface_to_descriptor -= num_rts;
672 map.surface_count += num_rts;
673 assert(map.surface_count <= 256);
674 memcpy(map.surface_to_descriptor, rt_bindings,
675 num_rts * sizeof(*rt_bindings));
676
677 anv_fill_binding_table(&prog_data.base, num_rts);
678
679 void *mem_ctx = ralloc_context(NULL);
680
681 if (module->nir == NULL)
682 ralloc_steal(mem_ctx, nir);
683
684 unsigned code_size;
685 const unsigned *shader_code =
686 brw_compile_fs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
687 NULL, -1, -1, true, pipeline->use_repclear,
688 &code_size, NULL);
689 if (shader_code == NULL) {
690 ralloc_free(mem_ctx);
691 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
692 }
693
694 stage_prog_data = &prog_data.base;
695 pipeline->ps_ksp0 =
696 anv_pipeline_cache_upload_kernel(cache,
697 module->size > 0 ? sha1 : NULL,
698 shader_code, code_size,
699 &stage_prog_data, sizeof(prog_data),
700 &map);
701
702 ralloc_free(mem_ctx);
703 }
704
705 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT,
706 stage_prog_data, &map);
707
708 return VK_SUCCESS;
709 }
710
711 VkResult
712 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
713 struct anv_pipeline_cache *cache,
714 const VkComputePipelineCreateInfo *info,
715 struct anv_shader_module *module,
716 const char *entrypoint,
717 const VkSpecializationInfo *spec_info)
718 {
719 const struct brw_compiler *compiler =
720 pipeline->device->instance->physicalDevice.compiler;
721 const struct brw_stage_prog_data *stage_prog_data;
722 struct anv_pipeline_bind_map map;
723 struct brw_cs_prog_key key;
724 uint32_t kernel = NO_KERNEL;
725 unsigned char sha1[20];
726
727 populate_cs_prog_key(&pipeline->device->info, &key);
728
729 if (module->size > 0) {
730 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, spec_info);
731 kernel = anv_pipeline_cache_search(cache, sha1, &stage_prog_data, &map);
732 }
733
734 if (module->size == 0 || kernel == NO_KERNEL) {
735 struct brw_cs_prog_data prog_data = { 0, };
736 struct anv_pipeline_binding surface_to_descriptor[256];
737 struct anv_pipeline_binding sampler_to_descriptor[256];
738
739 map = (struct anv_pipeline_bind_map) {
740 .surface_to_descriptor = surface_to_descriptor,
741 .sampler_to_descriptor = sampler_to_descriptor
742 };
743
744 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
745 MESA_SHADER_COMPUTE, spec_info,
746 &prog_data.base, &map);
747 if (nir == NULL)
748 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
749
750 anv_fill_binding_table(&prog_data.base, 1);
751
752 void *mem_ctx = ralloc_context(NULL);
753
754 if (module->nir == NULL)
755 ralloc_steal(mem_ctx, nir);
756
757 unsigned code_size;
758 const unsigned *shader_code =
759 brw_compile_cs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
760 -1, &code_size, NULL);
761 if (shader_code == NULL) {
762 ralloc_free(mem_ctx);
763 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
764 }
765
766 stage_prog_data = &prog_data.base;
767 kernel = anv_pipeline_cache_upload_kernel(cache,
768 module->size > 0 ? sha1 : NULL,
769 shader_code, code_size,
770 &stage_prog_data, sizeof(prog_data),
771 &map);
772
773 ralloc_free(mem_ctx);
774 }
775
776 pipeline->cs_simd = kernel;
777
778 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE,
779 stage_prog_data, &map);
780
781 return VK_SUCCESS;
782 }
783
784
785 void
786 anv_setup_pipeline_l3_config(struct anv_pipeline *pipeline)
787 {
788 const struct brw_device_info *devinfo = &pipeline->device->info;
789 switch (devinfo->gen) {
790 case 7:
791 if (devinfo->is_haswell)
792 gen75_setup_pipeline_l3_config(pipeline);
793 else
794 gen7_setup_pipeline_l3_config(pipeline);
795 break;
796 case 8:
797 gen8_setup_pipeline_l3_config(pipeline);
798 break;
799 case 9:
800 gen9_setup_pipeline_l3_config(pipeline);
801 break;
802 default:
803 unreachable("unsupported gen\n");
804 }
805 }
806
807 void
808 anv_compute_urb_partition(struct anv_pipeline *pipeline)
809 {
810 const struct brw_device_info *devinfo = &pipeline->device->info;
811
812 bool vs_present = pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT;
813 unsigned vs_size = vs_present ?
814 get_vs_prog_data(pipeline)->base.urb_entry_size : 1;
815 unsigned vs_entry_size_bytes = vs_size * 64;
816 bool gs_present = pipeline->active_stages & VK_SHADER_STAGE_GEOMETRY_BIT;
817 unsigned gs_size = gs_present ?
818 get_gs_prog_data(pipeline)->base.urb_entry_size : 1;
819 unsigned gs_entry_size_bytes = gs_size * 64;
820
821 /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
822 *
823 * VS Number of URB Entries must be divisible by 8 if the VS URB Entry
824 * Allocation Size is less than 9 512-bit URB entries.
825 *
826 * Similar text exists for GS.
827 */
828 unsigned vs_granularity = (vs_size < 9) ? 8 : 1;
829 unsigned gs_granularity = (gs_size < 9) ? 8 : 1;
830
831 /* URB allocations must be done in 8k chunks. */
832 unsigned chunk_size_bytes = 8192;
833
834 /* Determine the size of the URB in chunks. */
835 unsigned urb_chunks = pipeline->urb.total_size * 1024 / chunk_size_bytes;
836
837 /* Reserve space for push constants */
838 unsigned push_constant_kb;
839 if (pipeline->device->info.gen >= 8)
840 push_constant_kb = 32;
841 else if (pipeline->device->info.is_haswell)
842 push_constant_kb = pipeline->device->info.gt == 3 ? 32 : 16;
843 else
844 push_constant_kb = 16;
845
846 unsigned push_constant_bytes = push_constant_kb * 1024;
847 unsigned push_constant_chunks =
848 push_constant_bytes / chunk_size_bytes;
849
850 /* Initially, assign each stage the minimum amount of URB space it needs,
851 * and make a note of how much additional space it "wants" (the amount of
852 * additional space it could actually make use of).
853 */
854
855 /* VS has a lower limit on the number of URB entries */
856 unsigned vs_chunks =
857 ALIGN(devinfo->urb.min_vs_entries * vs_entry_size_bytes,
858 chunk_size_bytes) / chunk_size_bytes;
859 unsigned vs_wants =
860 ALIGN(devinfo->urb.max_vs_entries * vs_entry_size_bytes,
861 chunk_size_bytes) / chunk_size_bytes - vs_chunks;
862
863 unsigned gs_chunks = 0;
864 unsigned gs_wants = 0;
865 if (gs_present) {
866 /* There are two constraints on the minimum amount of URB space we can
867 * allocate:
868 *
869 * (1) We need room for at least 2 URB entries, since we always operate
870 * the GS in DUAL_OBJECT mode.
871 *
872 * (2) We can't allocate less than nr_gs_entries_granularity.
873 */
874 gs_chunks = ALIGN(MAX2(gs_granularity, 2) * gs_entry_size_bytes,
875 chunk_size_bytes) / chunk_size_bytes;
876 gs_wants =
877 ALIGN(devinfo->urb.max_gs_entries * gs_entry_size_bytes,
878 chunk_size_bytes) / chunk_size_bytes - gs_chunks;
879 }
880
881 /* There should always be enough URB space to satisfy the minimum
882 * requirements of each stage.
883 */
884 unsigned total_needs = push_constant_chunks + vs_chunks + gs_chunks;
885 assert(total_needs <= urb_chunks);
886
887 /* Mete out remaining space (if any) in proportion to "wants". */
888 unsigned total_wants = vs_wants + gs_wants;
889 unsigned remaining_space = urb_chunks - total_needs;
890 if (remaining_space > total_wants)
891 remaining_space = total_wants;
892 if (remaining_space > 0) {
893 unsigned vs_additional = (unsigned)
894 round(vs_wants * (((double) remaining_space) / total_wants));
895 vs_chunks += vs_additional;
896 remaining_space -= vs_additional;
897 gs_chunks += remaining_space;
898 }
899
900 /* Sanity check that we haven't over-allocated. */
901 assert(push_constant_chunks + vs_chunks + gs_chunks <= urb_chunks);
902
903 /* Finally, compute the number of entries that can fit in the space
904 * allocated to each stage.
905 */
906 unsigned nr_vs_entries = vs_chunks * chunk_size_bytes / vs_entry_size_bytes;
907 unsigned nr_gs_entries = gs_chunks * chunk_size_bytes / gs_entry_size_bytes;
908
909 /* Since we rounded up when computing *_wants, this may be slightly more
910 * than the maximum allowed amount, so correct for that.
911 */
912 nr_vs_entries = MIN2(nr_vs_entries, devinfo->urb.max_vs_entries);
913 nr_gs_entries = MIN2(nr_gs_entries, devinfo->urb.max_gs_entries);
914
915 /* Ensure that we program a multiple of the granularity. */
916 nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, vs_granularity);
917 nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, gs_granularity);
918
919 /* Finally, sanity check to make sure we have at least the minimum number
920 * of entries needed for each stage.
921 */
922 assert(nr_vs_entries >= devinfo->urb.min_vs_entries);
923 if (gs_present)
924 assert(nr_gs_entries >= 2);
925
926 /* Lay out the URB in the following order:
927 * - push constants
928 * - VS
929 * - GS
930 */
931 pipeline->urb.start[MESA_SHADER_VERTEX] = push_constant_chunks;
932 pipeline->urb.size[MESA_SHADER_VERTEX] = vs_size;
933 pipeline->urb.entries[MESA_SHADER_VERTEX] = nr_vs_entries;
934
935 pipeline->urb.start[MESA_SHADER_GEOMETRY] = push_constant_chunks + vs_chunks;
936 pipeline->urb.size[MESA_SHADER_GEOMETRY] = gs_size;
937 pipeline->urb.entries[MESA_SHADER_GEOMETRY] = nr_gs_entries;
938
939 pipeline->urb.start[MESA_SHADER_TESS_CTRL] = push_constant_chunks;
940 pipeline->urb.size[MESA_SHADER_TESS_CTRL] = 1;
941 pipeline->urb.entries[MESA_SHADER_TESS_CTRL] = 0;
942
943 pipeline->urb.start[MESA_SHADER_TESS_EVAL] = push_constant_chunks;
944 pipeline->urb.size[MESA_SHADER_TESS_EVAL] = 1;
945 pipeline->urb.entries[MESA_SHADER_TESS_EVAL] = 0;
946 }
947
948 static void
949 anv_pipeline_init_dynamic_state(struct anv_pipeline *pipeline,
950 const VkGraphicsPipelineCreateInfo *pCreateInfo)
951 {
952 anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
953 ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
954 struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
955
956 pipeline->dynamic_state = default_dynamic_state;
957
958 if (pCreateInfo->pDynamicState) {
959 /* Remove all of the states that are marked as dynamic */
960 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
961 for (uint32_t s = 0; s < count; s++)
962 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
963 }
964
965 struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
966
967 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
968 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
969 typed_memcpy(dynamic->viewport.viewports,
970 pCreateInfo->pViewportState->pViewports,
971 pCreateInfo->pViewportState->viewportCount);
972 }
973
974 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
975 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
976 typed_memcpy(dynamic->scissor.scissors,
977 pCreateInfo->pViewportState->pScissors,
978 pCreateInfo->pViewportState->scissorCount);
979 }
980
981 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
982 assert(pCreateInfo->pRasterizationState);
983 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
984 }
985
986 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
987 assert(pCreateInfo->pRasterizationState);
988 dynamic->depth_bias.bias =
989 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
990 dynamic->depth_bias.clamp =
991 pCreateInfo->pRasterizationState->depthBiasClamp;
992 dynamic->depth_bias.slope =
993 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
994 }
995
996 if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
997 assert(pCreateInfo->pColorBlendState);
998 typed_memcpy(dynamic->blend_constants,
999 pCreateInfo->pColorBlendState->blendConstants, 4);
1000 }
1001
1002 /* If there is no depthstencil attachment, then don't read
1003 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1004 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1005 * no need to override the depthstencil defaults in
1006 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1007 *
1008 * From the Vulkan spec (20 Oct 2015, git-aa308cb):
1009 *
1010 * pDepthStencilState [...] may only be NULL if renderPass and subpass
1011 * specify a subpass that has no depth/stencil attachment.
1012 */
1013 if (subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
1014 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1015 assert(pCreateInfo->pDepthStencilState);
1016 dynamic->depth_bounds.min =
1017 pCreateInfo->pDepthStencilState->minDepthBounds;
1018 dynamic->depth_bounds.max =
1019 pCreateInfo->pDepthStencilState->maxDepthBounds;
1020 }
1021
1022 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1023 assert(pCreateInfo->pDepthStencilState);
1024 dynamic->stencil_compare_mask.front =
1025 pCreateInfo->pDepthStencilState->front.compareMask;
1026 dynamic->stencil_compare_mask.back =
1027 pCreateInfo->pDepthStencilState->back.compareMask;
1028 }
1029
1030 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1031 assert(pCreateInfo->pDepthStencilState);
1032 dynamic->stencil_write_mask.front =
1033 pCreateInfo->pDepthStencilState->front.writeMask;
1034 dynamic->stencil_write_mask.back =
1035 pCreateInfo->pDepthStencilState->back.writeMask;
1036 }
1037
1038 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1039 assert(pCreateInfo->pDepthStencilState);
1040 dynamic->stencil_reference.front =
1041 pCreateInfo->pDepthStencilState->front.reference;
1042 dynamic->stencil_reference.back =
1043 pCreateInfo->pDepthStencilState->back.reference;
1044 }
1045 }
1046
1047 pipeline->dynamic_state_mask = states;
1048 }
1049
1050 static void
1051 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
1052 {
1053 struct anv_render_pass *renderpass = NULL;
1054 struct anv_subpass *subpass = NULL;
1055
1056 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1057 * present, as explained by the Vulkan (20 Oct 2015, git-aa308cb), Section
1058 * 4.2 Graphics Pipeline.
1059 */
1060 assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
1061
1062 renderpass = anv_render_pass_from_handle(info->renderPass);
1063 assert(renderpass);
1064
1065 if (renderpass != &anv_meta_dummy_renderpass) {
1066 assert(info->subpass < renderpass->subpass_count);
1067 subpass = &renderpass->subpasses[info->subpass];
1068 }
1069
1070 assert(info->stageCount >= 1);
1071 assert(info->pVertexInputState);
1072 assert(info->pInputAssemblyState);
1073 assert(info->pViewportState);
1074 assert(info->pRasterizationState);
1075
1076 if (subpass && subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED)
1077 assert(info->pDepthStencilState);
1078
1079 if (subpass && subpass->color_count > 0)
1080 assert(info->pColorBlendState);
1081
1082 for (uint32_t i = 0; i < info->stageCount; ++i) {
1083 switch (info->pStages[i].stage) {
1084 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
1085 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
1086 assert(info->pTessellationState);
1087 break;
1088 default:
1089 break;
1090 }
1091 }
1092 }
1093
1094 VkResult
1095 anv_pipeline_init(struct anv_pipeline *pipeline,
1096 struct anv_device *device,
1097 struct anv_pipeline_cache *cache,
1098 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1099 const struct anv_graphics_pipeline_create_info *extra,
1100 const VkAllocationCallbacks *alloc)
1101 {
1102 VkResult result;
1103
1104 anv_validate {
1105 anv_pipeline_validate_create_info(pCreateInfo);
1106 }
1107
1108 if (alloc == NULL)
1109 alloc = &device->alloc;
1110
1111 pipeline->device = device;
1112 pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
1113
1114 result = anv_reloc_list_init(&pipeline->batch_relocs, alloc);
1115 if (result != VK_SUCCESS)
1116 return result;
1117
1118 pipeline->batch.alloc = alloc;
1119 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
1120 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
1121 pipeline->batch.relocs = &pipeline->batch_relocs;
1122
1123 anv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1124
1125 pipeline->use_repclear = extra && extra->use_repclear;
1126
1127 pipeline->needs_data_cache = false;
1128
1129 /* When we free the pipeline, we detect stages based on the NULL status
1130 * of various prog_data pointers. Make them NULL by default.
1131 */
1132 memset(pipeline->prog_data, 0, sizeof(pipeline->prog_data));
1133 memset(pipeline->scratch_start, 0, sizeof(pipeline->scratch_start));
1134 memset(pipeline->bindings, 0, sizeof(pipeline->bindings));
1135
1136 pipeline->vs_simd8 = NO_KERNEL;
1137 pipeline->vs_vec4 = NO_KERNEL;
1138 pipeline->gs_kernel = NO_KERNEL;
1139 pipeline->ps_ksp0 = NO_KERNEL;
1140
1141 pipeline->active_stages = 0;
1142 pipeline->total_scratch = 0;
1143
1144 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1145 struct anv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1146 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1147 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1148 pStages[stage] = &pCreateInfo->pStages[i];
1149 modules[stage] = anv_shader_module_from_handle(pStages[stage]->module);
1150 }
1151
1152 if (modules[MESA_SHADER_VERTEX]) {
1153 anv_pipeline_compile_vs(pipeline, cache, pCreateInfo,
1154 modules[MESA_SHADER_VERTEX],
1155 pStages[MESA_SHADER_VERTEX]->pName,
1156 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo);
1157 }
1158
1159 if (modules[MESA_SHADER_TESS_CTRL] || modules[MESA_SHADER_TESS_EVAL])
1160 anv_finishme("no tessellation support");
1161
1162 if (modules[MESA_SHADER_GEOMETRY]) {
1163 anv_pipeline_compile_gs(pipeline, cache, pCreateInfo,
1164 modules[MESA_SHADER_GEOMETRY],
1165 pStages[MESA_SHADER_GEOMETRY]->pName,
1166 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo);
1167 }
1168
1169 if (modules[MESA_SHADER_FRAGMENT]) {
1170 anv_pipeline_compile_fs(pipeline, cache, pCreateInfo, extra,
1171 modules[MESA_SHADER_FRAGMENT],
1172 pStages[MESA_SHADER_FRAGMENT]->pName,
1173 pStages[MESA_SHADER_FRAGMENT]->pSpecializationInfo);
1174 }
1175
1176 if (!(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT)) {
1177 /* Vertex is only optional if disable_vs is set */
1178 assert(extra->disable_vs);
1179 }
1180
1181 anv_setup_pipeline_l3_config(pipeline);
1182 anv_compute_urb_partition(pipeline);
1183
1184 const VkPipelineVertexInputStateCreateInfo *vi_info =
1185 pCreateInfo->pVertexInputState;
1186
1187 uint64_t inputs_read;
1188 if (extra && extra->disable_vs) {
1189 /* If the VS is disabled, just assume the user knows what they're
1190 * doing and apply the layout blindly. This can only come from
1191 * meta, so this *should* be safe.
1192 */
1193 inputs_read = ~0ull;
1194 } else {
1195 inputs_read = get_vs_prog_data(pipeline)->inputs_read;
1196 }
1197
1198 pipeline->vb_used = 0;
1199 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1200 const VkVertexInputAttributeDescription *desc =
1201 &vi_info->pVertexAttributeDescriptions[i];
1202
1203 if (inputs_read & (1 << (VERT_ATTRIB_GENERIC0 + desc->location)))
1204 pipeline->vb_used |= 1 << desc->binding;
1205 }
1206
1207 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1208 const VkVertexInputBindingDescription *desc =
1209 &vi_info->pVertexBindingDescriptions[i];
1210
1211 pipeline->binding_stride[desc->binding] = desc->stride;
1212
1213 /* Step rate is programmed per vertex element (attribute), not
1214 * binding. Set up a map of which bindings step per instance, for
1215 * reference by vertex element setup. */
1216 switch (desc->inputRate) {
1217 default:
1218 case VK_VERTEX_INPUT_RATE_VERTEX:
1219 pipeline->instancing_enable[desc->binding] = false;
1220 break;
1221 case VK_VERTEX_INPUT_RATE_INSTANCE:
1222 pipeline->instancing_enable[desc->binding] = true;
1223 break;
1224 }
1225 }
1226
1227 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1228 pCreateInfo->pInputAssemblyState;
1229 pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1230 pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1231
1232 if (extra && extra->use_rectlist)
1233 pipeline->topology = _3DPRIM_RECTLIST;
1234
1235 while (anv_block_pool_size(&device->scratch_block_pool) <
1236 pipeline->total_scratch)
1237 anv_block_pool_alloc(&device->scratch_block_pool);
1238
1239 return VK_SUCCESS;
1240 }
1241
1242 VkResult
1243 anv_graphics_pipeline_create(
1244 VkDevice _device,
1245 VkPipelineCache _cache,
1246 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1247 const struct anv_graphics_pipeline_create_info *extra,
1248 const VkAllocationCallbacks *pAllocator,
1249 VkPipeline *pPipeline)
1250 {
1251 ANV_FROM_HANDLE(anv_device, device, _device);
1252 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
1253
1254 if (cache == NULL)
1255 cache = &device->default_pipeline_cache;
1256
1257 switch (device->info.gen) {
1258 case 7:
1259 if (device->info.is_haswell)
1260 return gen75_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1261 else
1262 return gen7_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1263 case 8:
1264 return gen8_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1265 case 9:
1266 return gen9_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1267 default:
1268 unreachable("unsupported gen\n");
1269 }
1270 }
1271
1272 VkResult anv_CreateGraphicsPipelines(
1273 VkDevice _device,
1274 VkPipelineCache pipelineCache,
1275 uint32_t count,
1276 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1277 const VkAllocationCallbacks* pAllocator,
1278 VkPipeline* pPipelines)
1279 {
1280 VkResult result = VK_SUCCESS;
1281
1282 unsigned i = 0;
1283 for (; i < count; i++) {
1284 result = anv_graphics_pipeline_create(_device,
1285 pipelineCache,
1286 &pCreateInfos[i],
1287 NULL, pAllocator, &pPipelines[i]);
1288 if (result != VK_SUCCESS) {
1289 for (unsigned j = 0; j < i; j++) {
1290 anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1291 }
1292
1293 return result;
1294 }
1295 }
1296
1297 return VK_SUCCESS;
1298 }
1299
1300 static VkResult anv_compute_pipeline_create(
1301 VkDevice _device,
1302 VkPipelineCache _cache,
1303 const VkComputePipelineCreateInfo* pCreateInfo,
1304 const VkAllocationCallbacks* pAllocator,
1305 VkPipeline* pPipeline)
1306 {
1307 ANV_FROM_HANDLE(anv_device, device, _device);
1308 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
1309
1310 if (cache == NULL)
1311 cache = &device->default_pipeline_cache;
1312
1313 switch (device->info.gen) {
1314 case 7:
1315 if (device->info.is_haswell)
1316 return gen75_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1317 else
1318 return gen7_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1319 case 8:
1320 return gen8_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1321 case 9:
1322 return gen9_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1323 default:
1324 unreachable("unsupported gen\n");
1325 }
1326 }
1327
1328 VkResult anv_CreateComputePipelines(
1329 VkDevice _device,
1330 VkPipelineCache pipelineCache,
1331 uint32_t count,
1332 const VkComputePipelineCreateInfo* pCreateInfos,
1333 const VkAllocationCallbacks* pAllocator,
1334 VkPipeline* pPipelines)
1335 {
1336 VkResult result = VK_SUCCESS;
1337
1338 unsigned i = 0;
1339 for (; i < count; i++) {
1340 result = anv_compute_pipeline_create(_device, pipelineCache,
1341 &pCreateInfos[i],
1342 pAllocator, &pPipelines[i]);
1343 if (result != VK_SUCCESS) {
1344 for (unsigned j = 0; j < i; j++) {
1345 anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1346 }
1347
1348 return result;
1349 }
1350 }
1351
1352 return VK_SUCCESS;
1353 }