2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "common/gen_l3_config.h"
32 #include "anv_private.h"
33 #include "compiler/brw_nir.h"
35 #include "spirv/nir_spirv.h"
37 /* Needed for SWIZZLE macros */
38 #include "program/prog_instruction.h"
42 VkResult
anv_CreateShaderModule(
44 const VkShaderModuleCreateInfo
* pCreateInfo
,
45 const VkAllocationCallbacks
* pAllocator
,
46 VkShaderModule
* pShaderModule
)
48 ANV_FROM_HANDLE(anv_device
, device
, _device
);
49 struct anv_shader_module
*module
;
51 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
52 assert(pCreateInfo
->flags
== 0);
54 module
= vk_alloc2(&device
->alloc
, pAllocator
,
55 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
56 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
58 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
60 module
->size
= pCreateInfo
->codeSize
;
61 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
63 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
65 *pShaderModule
= anv_shader_module_to_handle(module
);
70 void anv_DestroyShaderModule(
72 VkShaderModule _module
,
73 const VkAllocationCallbacks
* pAllocator
)
75 ANV_FROM_HANDLE(anv_device
, device
, _device
);
76 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
81 vk_free2(&device
->alloc
, pAllocator
, module
);
84 #define SPIR_V_MAGIC_NUMBER 0x07230203
86 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
87 * we can't do that yet because we don't have the ability to copy nir.
90 anv_shader_compile_to_nir(struct anv_pipeline
*pipeline
,
91 struct anv_shader_module
*module
,
92 const char *entrypoint_name
,
93 gl_shader_stage stage
,
94 const VkSpecializationInfo
*spec_info
)
96 const struct anv_device
*device
= pipeline
->device
;
98 const struct brw_compiler
*compiler
=
99 device
->instance
->physicalDevice
.compiler
;
100 const nir_shader_compiler_options
*nir_options
=
101 compiler
->glsl_compiler_options
[stage
].NirOptions
;
103 uint32_t *spirv
= (uint32_t *) module
->data
;
104 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
105 assert(module
->size
% 4 == 0);
107 uint32_t num_spec_entries
= 0;
108 struct nir_spirv_specialization
*spec_entries
= NULL
;
109 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
110 num_spec_entries
= spec_info
->mapEntryCount
;
111 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
112 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
113 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
114 const void *data
= spec_info
->pData
+ entry
.offset
;
115 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
117 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
118 if (spec_info
->dataSize
== 8)
119 spec_entries
[i
].data64
= *(const uint64_t *)data
;
121 spec_entries
[i
].data32
= *(const uint32_t *)data
;
125 const struct nir_spirv_supported_extensions supported_ext
= {
126 .float64
= device
->instance
->physicalDevice
.info
.gen
>= 8,
127 .int64
= device
->instance
->physicalDevice
.info
.gen
>= 8,
128 .tessellation
= true,
129 .draw_parameters
= true,
130 .image_write_without_format
= true,
132 .variable_pointers
= true,
135 nir_function
*entry_point
=
136 spirv_to_nir(spirv
, module
->size
/ 4,
137 spec_entries
, num_spec_entries
,
138 stage
, entrypoint_name
, &supported_ext
, nir_options
);
139 nir_shader
*nir
= entry_point
->shader
;
140 assert(nir
->stage
== stage
);
141 nir_validate_shader(nir
);
145 /* We have to lower away local constant initializers right before we
146 * inline functions. That way they get properly initialized at the top
147 * of the function and not at the top of its caller.
149 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_local
);
150 NIR_PASS_V(nir
, nir_lower_returns
);
151 NIR_PASS_V(nir
, nir_inline_functions
);
153 /* Pick off the single entrypoint that we want */
154 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
155 if (func
!= entry_point
)
156 exec_node_remove(&func
->node
);
158 assert(exec_list_length(&nir
->functions
) == 1);
159 entry_point
->name
= ralloc_strdup(entry_point
, "main");
161 NIR_PASS_V(nir
, nir_remove_dead_variables
,
162 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
164 if (stage
== MESA_SHADER_FRAGMENT
)
165 NIR_PASS_V(nir
, nir_lower_wpos_center
, pipeline
->sample_shading_enable
);
167 /* Now that we've deleted all but the main function, we can go ahead and
168 * lower the rest of the constant initializers.
170 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
171 NIR_PASS_V(nir
, nir_propagate_invariant
);
172 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
173 entry_point
->impl
, true, false);
174 NIR_PASS_V(nir
, nir_lower_system_values
);
176 /* Vulkan uses the separate-shader linking model */
177 nir
->info
.separate_shader
= true;
179 nir
= brw_preprocess_nir(compiler
, nir
);
181 NIR_PASS_V(nir
, nir_lower_clip_cull_distance_arrays
);
183 if (stage
== MESA_SHADER_FRAGMENT
)
184 NIR_PASS_V(nir
, anv_nir_lower_input_attachments
);
189 void anv_DestroyPipeline(
191 VkPipeline _pipeline
,
192 const VkAllocationCallbacks
* pAllocator
)
194 ANV_FROM_HANDLE(anv_device
, device
, _device
);
195 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
200 anv_reloc_list_finish(&pipeline
->batch_relocs
,
201 pAllocator
? pAllocator
: &device
->alloc
);
202 if (pipeline
->blend_state
.map
)
203 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
205 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
206 if (pipeline
->shaders
[s
])
207 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
210 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
213 static const uint32_t vk_to_gen_primitive_type
[] = {
214 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
215 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
216 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
217 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
218 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
219 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
220 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
221 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
222 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
223 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
227 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
228 struct brw_sampler_prog_key_data
*key
)
230 /* Almost all multisampled textures are compressed. The only time when we
231 * don't compress a multisampled texture is for 16x MSAA with a surface
232 * width greater than 8k which is a bit of an edge case. Since the sampler
233 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
234 * to tell the compiler to always assume compression.
236 key
->compressed_multisample_layout_mask
= ~0;
238 /* SkyLake added support for 16x MSAA. With this came a new message for
239 * reading from a 16x MSAA surface with compression. The new message was
240 * needed because now the MCS data is 64 bits instead of 32 or lower as is
241 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
242 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
243 * so we can just use it unconditionally. This may not be quite as
244 * efficient but it saves us from recompiling.
246 if (devinfo
->gen
>= 9)
249 /* XXX: Handle texture swizzle on HSW- */
250 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
251 /* Assume color sampler, no swizzling. (Works for BDW+) */
252 key
->swizzles
[i
] = SWIZZLE_XYZW
;
257 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
258 struct brw_vs_prog_key
*key
)
260 memset(key
, 0, sizeof(*key
));
262 populate_sampler_prog_key(devinfo
, &key
->tex
);
264 /* XXX: Handle vertex input work-arounds */
266 /* XXX: Handle sampler_prog_key */
270 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
271 struct brw_gs_prog_key
*key
)
273 memset(key
, 0, sizeof(*key
));
275 populate_sampler_prog_key(devinfo
, &key
->tex
);
279 populate_wm_prog_key(const struct anv_pipeline
*pipeline
,
280 const VkGraphicsPipelineCreateInfo
*info
,
281 struct brw_wm_prog_key
*key
)
283 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
285 memset(key
, 0, sizeof(*key
));
287 populate_sampler_prog_key(devinfo
, &key
->tex
);
289 /* TODO: we could set this to 0 based on the information in nir_shader, but
290 * this function is called before spirv_to_nir. */
291 const struct brw_vue_map
*vue_map
=
292 &anv_pipeline_get_last_vue_prog_data(pipeline
)->vue_map
;
293 key
->input_slots_valid
= vue_map
->slots_valid
;
295 /* Vulkan doesn't specify a default */
296 key
->high_quality_derivatives
= false;
298 /* XXX Vulkan doesn't appear to specify */
299 key
->clamp_fragment_color
= false;
301 key
->nr_color_regions
= pipeline
->subpass
->color_count
;
303 key
->replicate_alpha
= key
->nr_color_regions
> 1 &&
304 info
->pMultisampleState
&&
305 info
->pMultisampleState
->alphaToCoverageEnable
;
307 if (info
->pMultisampleState
) {
308 /* We should probably pull this out of the shader, but it's fairly
309 * harmless to compute it and then let dead-code take care of it.
311 if (info
->pMultisampleState
->rasterizationSamples
> 1) {
312 key
->persample_interp
=
313 (info
->pMultisampleState
->minSampleShading
*
314 info
->pMultisampleState
->rasterizationSamples
) > 1;
315 key
->multisample_fbo
= true;
318 key
->frag_coord_adds_sample_pos
=
319 info
->pMultisampleState
->sampleShadingEnable
;
324 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
325 struct brw_cs_prog_key
*key
)
327 memset(key
, 0, sizeof(*key
));
329 populate_sampler_prog_key(devinfo
, &key
->tex
);
333 anv_pipeline_hash_shader(struct anv_pipeline
*pipeline
,
334 struct anv_shader_module
*module
,
335 const char *entrypoint
,
336 gl_shader_stage stage
,
337 const VkSpecializationInfo
*spec_info
,
338 const void *key
, size_t key_size
,
339 unsigned char *sha1_out
)
341 struct mesa_sha1 ctx
;
343 _mesa_sha1_init(&ctx
);
344 if (stage
!= MESA_SHADER_COMPUTE
) {
345 _mesa_sha1_update(&ctx
, &pipeline
->subpass
->view_mask
,
346 sizeof(pipeline
->subpass
->view_mask
));
348 if (pipeline
->layout
) {
349 _mesa_sha1_update(&ctx
, pipeline
->layout
->sha1
,
350 sizeof(pipeline
->layout
->sha1
));
352 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
353 _mesa_sha1_update(&ctx
, entrypoint
, strlen(entrypoint
));
354 _mesa_sha1_update(&ctx
, &stage
, sizeof(stage
));
356 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
357 spec_info
->mapEntryCount
* sizeof(*spec_info
->pMapEntries
));
358 _mesa_sha1_update(&ctx
, spec_info
->pData
, spec_info
->dataSize
);
360 _mesa_sha1_update(&ctx
, key
, key_size
);
361 _mesa_sha1_final(&ctx
, sha1_out
);
365 anv_pipeline_compile(struct anv_pipeline
*pipeline
,
366 struct anv_shader_module
*module
,
367 const char *entrypoint
,
368 gl_shader_stage stage
,
369 const VkSpecializationInfo
*spec_info
,
370 struct brw_stage_prog_data
*prog_data
,
371 struct anv_pipeline_bind_map
*map
)
373 nir_shader
*nir
= anv_shader_compile_to_nir(pipeline
,
374 module
, entrypoint
, stage
,
379 NIR_PASS_V(nir
, anv_nir_lower_ycbcr_textures
, pipeline
);
381 NIR_PASS_V(nir
, anv_nir_lower_push_constants
);
383 if (stage
!= MESA_SHADER_COMPUTE
)
384 NIR_PASS_V(nir
, anv_nir_lower_multiview
, pipeline
->subpass
->view_mask
);
386 if (stage
== MESA_SHADER_COMPUTE
) {
387 NIR_PASS_V(nir
, brw_nir_lower_cs_shared
);
388 prog_data
->total_shared
= nir
->num_shared
;
391 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
393 /* Figure out the number of parameters */
394 prog_data
->nr_params
= 0;
396 if (nir
->num_uniforms
> 0) {
397 /* If the shader uses any push constants at all, we'll just give
398 * them the maximum possible number
400 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
401 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
404 if (nir
->info
.num_images
> 0) {
405 prog_data
->nr_params
+= nir
->info
.num_images
* BRW_IMAGE_PARAM_SIZE
;
406 pipeline
->needs_data_cache
= true;
409 if (stage
== MESA_SHADER_COMPUTE
)
410 ((struct brw_cs_prog_data
*)prog_data
)->thread_local_id_index
=
411 prog_data
->nr_params
++; /* The CS Thread ID uniform */
413 if (nir
->info
.num_ssbos
> 0)
414 pipeline
->needs_data_cache
= true;
416 if (prog_data
->nr_params
> 0) {
417 /* XXX: I think we're leaking this */
418 prog_data
->param
= malloc(prog_data
->nr_params
* sizeof(uint32_t));
420 /* We now set the param values to be offsets into a
421 * anv_push_constant_data structure. Since the compiler doesn't
422 * actually dereference any of the gl_constant_value pointers in the
423 * params array, it doesn't really matter what we put here.
425 struct anv_push_constants
*null_data
= NULL
;
426 if (nir
->num_uniforms
> 0) {
427 /* Fill out the push constants section of the param array */
428 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++)
429 prog_data
->param
[i
] = ANV_PARAM_PUSH(
430 (uintptr_t)&null_data
->client_data
[i
* sizeof(float)]);
434 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
435 if (pipeline
->layout
)
436 anv_nir_apply_pipeline_layout(pipeline
, nir
, prog_data
, map
);
438 /* nir_lower_io will only handle the push constants; we need to set this
439 * to the full number of possible uniforms.
441 nir
->num_uniforms
= prog_data
->nr_params
* 4;
447 anv_fill_binding_table(struct brw_stage_prog_data
*prog_data
, unsigned bias
)
449 prog_data
->binding_table
.size_bytes
= 0;
450 prog_data
->binding_table
.texture_start
= bias
;
451 prog_data
->binding_table
.gather_texture_start
= bias
;
452 prog_data
->binding_table
.ubo_start
= bias
;
453 prog_data
->binding_table
.ssbo_start
= bias
;
454 prog_data
->binding_table
.image_start
= bias
;
457 static struct anv_shader_bin
*
458 anv_pipeline_upload_kernel(struct anv_pipeline
*pipeline
,
459 struct anv_pipeline_cache
*cache
,
460 const void *key_data
, uint32_t key_size
,
461 const void *kernel_data
, uint32_t kernel_size
,
462 const struct brw_stage_prog_data
*prog_data
,
463 uint32_t prog_data_size
,
464 const struct anv_pipeline_bind_map
*bind_map
)
467 return anv_pipeline_cache_upload_kernel(cache
, key_data
, key_size
,
468 kernel_data
, kernel_size
,
469 prog_data
, prog_data_size
,
472 return anv_shader_bin_create(pipeline
->device
, key_data
, key_size
,
473 kernel_data
, kernel_size
,
474 prog_data
, prog_data_size
,
475 prog_data
->param
, bind_map
);
481 anv_pipeline_add_compiled_stage(struct anv_pipeline
*pipeline
,
482 gl_shader_stage stage
,
483 struct anv_shader_bin
*shader
)
485 pipeline
->shaders
[stage
] = shader
;
486 pipeline
->active_stages
|= mesa_to_vk_shader_stage(stage
);
490 anv_pipeline_compile_vs(struct anv_pipeline
*pipeline
,
491 struct anv_pipeline_cache
*cache
,
492 const VkGraphicsPipelineCreateInfo
*info
,
493 struct anv_shader_module
*module
,
494 const char *entrypoint
,
495 const VkSpecializationInfo
*spec_info
)
497 const struct brw_compiler
*compiler
=
498 pipeline
->device
->instance
->physicalDevice
.compiler
;
499 struct brw_vs_prog_key key
;
500 struct anv_shader_bin
*bin
= NULL
;
501 unsigned char sha1
[20];
503 populate_vs_prog_key(&pipeline
->device
->info
, &key
);
506 anv_pipeline_hash_shader(pipeline
, module
, entrypoint
,
507 MESA_SHADER_VERTEX
, spec_info
,
508 &key
, sizeof(key
), sha1
);
509 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
513 struct brw_vs_prog_data prog_data
= {};
514 struct anv_pipeline_binding surface_to_descriptor
[256];
515 struct anv_pipeline_binding sampler_to_descriptor
[256];
517 struct anv_pipeline_bind_map map
= {
518 .surface_to_descriptor
= surface_to_descriptor
,
519 .sampler_to_descriptor
= sampler_to_descriptor
522 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
523 MESA_SHADER_VERTEX
, spec_info
,
524 &prog_data
.base
.base
, &map
);
526 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
528 anv_fill_binding_table(&prog_data
.base
.base
, 0);
530 void *mem_ctx
= ralloc_context(NULL
);
532 ralloc_steal(mem_ctx
, nir
);
534 brw_compute_vue_map(&pipeline
->device
->info
,
535 &prog_data
.base
.vue_map
,
536 nir
->info
.outputs_written
,
537 nir
->info
.separate_shader
);
540 const unsigned *shader_code
=
541 brw_compile_vs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
542 false, -1, &code_size
, NULL
);
543 if (shader_code
== NULL
) {
544 ralloc_free(mem_ctx
);
545 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
548 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
549 shader_code
, code_size
,
550 &prog_data
.base
.base
, sizeof(prog_data
),
553 ralloc_free(mem_ctx
);
554 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
557 ralloc_free(mem_ctx
);
560 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_VERTEX
, bin
);
566 merge_tess_info(struct shader_info
*tes_info
,
567 const struct shader_info
*tcs_info
)
569 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
571 * "PointMode. Controls generation of points rather than triangles
572 * or lines. This functionality defaults to disabled, and is
573 * enabled if either shader stage includes the execution mode.
575 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
576 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
577 * and OutputVertices, it says:
579 * "One mode must be set in at least one of the tessellation
582 * So, the fields can be set in either the TCS or TES, but they must
583 * agree if set in both. Our backend looks at TES, so bitwise-or in
584 * the values from the TCS.
586 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
587 tes_info
->tess
.tcs_vertices_out
== 0 ||
588 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
589 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
591 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
592 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
593 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
594 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
596 assert(tcs_info
->tess
.primitive_mode
== 0 ||
597 tes_info
->tess
.primitive_mode
== 0 ||
598 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
599 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
600 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
601 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
605 anv_pipeline_compile_tcs_tes(struct anv_pipeline
*pipeline
,
606 struct anv_pipeline_cache
*cache
,
607 const VkGraphicsPipelineCreateInfo
*info
,
608 struct anv_shader_module
*tcs_module
,
609 const char *tcs_entrypoint
,
610 const VkSpecializationInfo
*tcs_spec_info
,
611 struct anv_shader_module
*tes_module
,
612 const char *tes_entrypoint
,
613 const VkSpecializationInfo
*tes_spec_info
)
615 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
616 const struct brw_compiler
*compiler
=
617 pipeline
->device
->instance
->physicalDevice
.compiler
;
618 struct brw_tcs_prog_key tcs_key
= {};
619 struct brw_tes_prog_key tes_key
= {};
620 struct anv_shader_bin
*tcs_bin
= NULL
;
621 struct anv_shader_bin
*tes_bin
= NULL
;
622 unsigned char tcs_sha1
[40];
623 unsigned char tes_sha1
[40];
625 populate_sampler_prog_key(&pipeline
->device
->info
, &tcs_key
.tex
);
626 populate_sampler_prog_key(&pipeline
->device
->info
, &tes_key
.tex
);
627 tcs_key
.input_vertices
= info
->pTessellationState
->patchControlPoints
;
630 anv_pipeline_hash_shader(pipeline
, tcs_module
, tcs_entrypoint
,
631 MESA_SHADER_TESS_CTRL
, tcs_spec_info
,
632 &tcs_key
, sizeof(tcs_key
), tcs_sha1
);
633 anv_pipeline_hash_shader(pipeline
, tes_module
, tes_entrypoint
,
634 MESA_SHADER_TESS_EVAL
, tes_spec_info
,
635 &tes_key
, sizeof(tes_key
), tes_sha1
);
636 memcpy(&tcs_sha1
[20], tes_sha1
, 20);
637 memcpy(&tes_sha1
[20], tcs_sha1
, 20);
638 tcs_bin
= anv_pipeline_cache_search(cache
, tcs_sha1
, sizeof(tcs_sha1
));
639 tes_bin
= anv_pipeline_cache_search(cache
, tes_sha1
, sizeof(tes_sha1
));
642 if (tcs_bin
== NULL
|| tes_bin
== NULL
) {
643 struct brw_tcs_prog_data tcs_prog_data
= {};
644 struct brw_tes_prog_data tes_prog_data
= {};
645 struct anv_pipeline_binding tcs_surface_to_descriptor
[256];
646 struct anv_pipeline_binding tcs_sampler_to_descriptor
[256];
647 struct anv_pipeline_binding tes_surface_to_descriptor
[256];
648 struct anv_pipeline_binding tes_sampler_to_descriptor
[256];
650 struct anv_pipeline_bind_map tcs_map
= {
651 .surface_to_descriptor
= tcs_surface_to_descriptor
,
652 .sampler_to_descriptor
= tcs_sampler_to_descriptor
654 struct anv_pipeline_bind_map tes_map
= {
655 .surface_to_descriptor
= tes_surface_to_descriptor
,
656 .sampler_to_descriptor
= tes_sampler_to_descriptor
659 nir_shader
*tcs_nir
=
660 anv_pipeline_compile(pipeline
, tcs_module
, tcs_entrypoint
,
661 MESA_SHADER_TESS_CTRL
, tcs_spec_info
,
662 &tcs_prog_data
.base
.base
, &tcs_map
);
663 nir_shader
*tes_nir
=
664 anv_pipeline_compile(pipeline
, tes_module
, tes_entrypoint
,
665 MESA_SHADER_TESS_EVAL
, tes_spec_info
,
666 &tes_prog_data
.base
.base
, &tes_map
);
667 if (tcs_nir
== NULL
|| tes_nir
== NULL
)
668 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
670 nir_lower_tes_patch_vertices(tes_nir
,
671 tcs_nir
->info
.tess
.tcs_vertices_out
);
673 /* Copy TCS info into the TES info */
674 merge_tess_info(&tes_nir
->info
, &tcs_nir
->info
);
676 anv_fill_binding_table(&tcs_prog_data
.base
.base
, 0);
677 anv_fill_binding_table(&tes_prog_data
.base
.base
, 0);
679 void *mem_ctx
= ralloc_context(NULL
);
681 ralloc_steal(mem_ctx
, tcs_nir
);
682 ralloc_steal(mem_ctx
, tes_nir
);
684 /* Whacking the key after cache lookup is a bit sketchy, but all of
685 * this comes from the SPIR-V, which is part of the hash used for the
686 * pipeline cache. So it should be safe.
688 tcs_key
.tes_primitive_mode
= tes_nir
->info
.tess
.primitive_mode
;
689 tcs_key
.outputs_written
= tcs_nir
->info
.outputs_written
;
690 tcs_key
.patch_outputs_written
= tcs_nir
->info
.patch_outputs_written
;
691 tcs_key
.quads_workaround
=
693 tes_nir
->info
.tess
.primitive_mode
== 7 /* GL_QUADS */ &&
694 tes_nir
->info
.tess
.spacing
== TESS_SPACING_EQUAL
;
696 tes_key
.inputs_read
= tcs_key
.outputs_written
;
697 tes_key
.patch_inputs_read
= tcs_key
.patch_outputs_written
;
700 const int shader_time_index
= -1;
701 const unsigned *shader_code
;
704 brw_compile_tcs(compiler
, NULL
, mem_ctx
, &tcs_key
, &tcs_prog_data
,
705 tcs_nir
, shader_time_index
, &code_size
, NULL
);
706 if (shader_code
== NULL
) {
707 ralloc_free(mem_ctx
);
708 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
711 tcs_bin
= anv_pipeline_upload_kernel(pipeline
, cache
,
712 tcs_sha1
, sizeof(tcs_sha1
),
713 shader_code
, code_size
,
714 &tcs_prog_data
.base
.base
,
715 sizeof(tcs_prog_data
),
718 ralloc_free(mem_ctx
);
719 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
723 brw_compile_tes(compiler
, NULL
, mem_ctx
, &tes_key
,
724 &tcs_prog_data
.base
.vue_map
, &tes_prog_data
, tes_nir
,
725 NULL
, shader_time_index
, &code_size
, NULL
);
726 if (shader_code
== NULL
) {
727 ralloc_free(mem_ctx
);
728 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
731 tes_bin
= anv_pipeline_upload_kernel(pipeline
, cache
,
732 tes_sha1
, sizeof(tes_sha1
),
733 shader_code
, code_size
,
734 &tes_prog_data
.base
.base
,
735 sizeof(tes_prog_data
),
738 ralloc_free(mem_ctx
);
739 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
742 ralloc_free(mem_ctx
);
745 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_TESS_CTRL
, tcs_bin
);
746 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_TESS_EVAL
, tes_bin
);
752 anv_pipeline_compile_gs(struct anv_pipeline
*pipeline
,
753 struct anv_pipeline_cache
*cache
,
754 const VkGraphicsPipelineCreateInfo
*info
,
755 struct anv_shader_module
*module
,
756 const char *entrypoint
,
757 const VkSpecializationInfo
*spec_info
)
759 const struct brw_compiler
*compiler
=
760 pipeline
->device
->instance
->physicalDevice
.compiler
;
761 struct brw_gs_prog_key key
;
762 struct anv_shader_bin
*bin
= NULL
;
763 unsigned char sha1
[20];
765 populate_gs_prog_key(&pipeline
->device
->info
, &key
);
768 anv_pipeline_hash_shader(pipeline
, module
, entrypoint
,
769 MESA_SHADER_GEOMETRY
, spec_info
,
770 &key
, sizeof(key
), sha1
);
771 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
775 struct brw_gs_prog_data prog_data
= {};
776 struct anv_pipeline_binding surface_to_descriptor
[256];
777 struct anv_pipeline_binding sampler_to_descriptor
[256];
779 struct anv_pipeline_bind_map map
= {
780 .surface_to_descriptor
= surface_to_descriptor
,
781 .sampler_to_descriptor
= sampler_to_descriptor
784 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
785 MESA_SHADER_GEOMETRY
, spec_info
,
786 &prog_data
.base
.base
, &map
);
788 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
790 anv_fill_binding_table(&prog_data
.base
.base
, 0);
792 void *mem_ctx
= ralloc_context(NULL
);
794 ralloc_steal(mem_ctx
, nir
);
796 brw_compute_vue_map(&pipeline
->device
->info
,
797 &prog_data
.base
.vue_map
,
798 nir
->info
.outputs_written
,
799 nir
->info
.separate_shader
);
802 const unsigned *shader_code
=
803 brw_compile_gs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
804 NULL
, -1, &code_size
, NULL
);
805 if (shader_code
== NULL
) {
806 ralloc_free(mem_ctx
);
807 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
811 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
812 shader_code
, code_size
,
813 &prog_data
.base
.base
, sizeof(prog_data
),
816 ralloc_free(mem_ctx
);
817 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
820 ralloc_free(mem_ctx
);
823 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_GEOMETRY
, bin
);
829 anv_pipeline_compile_fs(struct anv_pipeline
*pipeline
,
830 struct anv_pipeline_cache
*cache
,
831 const VkGraphicsPipelineCreateInfo
*info
,
832 struct anv_shader_module
*module
,
833 const char *entrypoint
,
834 const VkSpecializationInfo
*spec_info
)
836 const struct brw_compiler
*compiler
=
837 pipeline
->device
->instance
->physicalDevice
.compiler
;
838 struct brw_wm_prog_key key
;
839 struct anv_shader_bin
*bin
= NULL
;
840 unsigned char sha1
[20];
842 populate_wm_prog_key(pipeline
, info
, &key
);
845 anv_pipeline_hash_shader(pipeline
, module
, entrypoint
,
846 MESA_SHADER_FRAGMENT
, spec_info
,
847 &key
, sizeof(key
), sha1
);
848 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
852 struct brw_wm_prog_data prog_data
= {};
853 struct anv_pipeline_binding surface_to_descriptor
[256];
854 struct anv_pipeline_binding sampler_to_descriptor
[256];
856 struct anv_pipeline_bind_map map
= {
857 .surface_to_descriptor
= surface_to_descriptor
+ 8,
858 .sampler_to_descriptor
= sampler_to_descriptor
861 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
862 MESA_SHADER_FRAGMENT
, spec_info
,
863 &prog_data
.base
, &map
);
865 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
867 unsigned num_rts
= 0;
868 struct anv_pipeline_binding rt_bindings
[8];
869 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
870 nir_foreach_variable_safe(var
, &nir
->outputs
) {
871 if (var
->data
.location
< FRAG_RESULT_DATA0
)
874 unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
875 if (rt
>= key
.nr_color_regions
) {
876 /* Out-of-bounds, throw it away */
877 var
->data
.mode
= nir_var_local
;
878 exec_node_remove(&var
->node
);
879 exec_list_push_tail(&impl
->locals
, &var
->node
);
883 /* Give it a new, compacted, location */
884 var
->data
.location
= FRAG_RESULT_DATA0
+ num_rts
;
887 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
888 assert(num_rts
+ array_len
<= 8);
890 for (unsigned i
= 0; i
< array_len
; i
++) {
891 rt_bindings
[num_rts
+ i
] = (struct anv_pipeline_binding
) {
892 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
898 num_rts
+= array_len
;
902 /* If we have no render targets, we need a null render target */
903 rt_bindings
[0] = (struct anv_pipeline_binding
) {
904 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
911 assert(num_rts
<= 8);
912 map
.surface_to_descriptor
-= num_rts
;
913 map
.surface_count
+= num_rts
;
914 assert(map
.surface_count
<= 256);
915 memcpy(map
.surface_to_descriptor
, rt_bindings
,
916 num_rts
* sizeof(*rt_bindings
));
918 anv_fill_binding_table(&prog_data
.base
, num_rts
);
920 void *mem_ctx
= ralloc_context(NULL
);
922 ralloc_steal(mem_ctx
, nir
);
925 const unsigned *shader_code
=
926 brw_compile_fs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
927 NULL
, -1, -1, true, false, NULL
, &code_size
, NULL
);
928 if (shader_code
== NULL
) {
929 ralloc_free(mem_ctx
);
930 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
933 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
934 shader_code
, code_size
,
935 &prog_data
.base
, sizeof(prog_data
),
938 ralloc_free(mem_ctx
);
939 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
942 ralloc_free(mem_ctx
);
945 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_FRAGMENT
, bin
);
951 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
952 struct anv_pipeline_cache
*cache
,
953 const VkComputePipelineCreateInfo
*info
,
954 struct anv_shader_module
*module
,
955 const char *entrypoint
,
956 const VkSpecializationInfo
*spec_info
)
958 const struct brw_compiler
*compiler
=
959 pipeline
->device
->instance
->physicalDevice
.compiler
;
960 struct brw_cs_prog_key key
;
961 struct anv_shader_bin
*bin
= NULL
;
962 unsigned char sha1
[20];
964 populate_cs_prog_key(&pipeline
->device
->info
, &key
);
967 anv_pipeline_hash_shader(pipeline
, module
, entrypoint
,
968 MESA_SHADER_COMPUTE
, spec_info
,
969 &key
, sizeof(key
), sha1
);
970 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
974 struct brw_cs_prog_data prog_data
= {};
975 struct anv_pipeline_binding surface_to_descriptor
[256];
976 struct anv_pipeline_binding sampler_to_descriptor
[256];
978 struct anv_pipeline_bind_map map
= {
979 .surface_to_descriptor
= surface_to_descriptor
,
980 .sampler_to_descriptor
= sampler_to_descriptor
983 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
984 MESA_SHADER_COMPUTE
, spec_info
,
985 &prog_data
.base
, &map
);
987 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
989 anv_fill_binding_table(&prog_data
.base
, 1);
991 void *mem_ctx
= ralloc_context(NULL
);
993 ralloc_steal(mem_ctx
, nir
);
996 const unsigned *shader_code
=
997 brw_compile_cs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
998 -1, &code_size
, NULL
);
999 if (shader_code
== NULL
) {
1000 ralloc_free(mem_ctx
);
1001 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1004 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
1005 shader_code
, code_size
,
1006 &prog_data
.base
, sizeof(prog_data
),
1009 ralloc_free(mem_ctx
);
1010 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1013 ralloc_free(mem_ctx
);
1016 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_COMPUTE
, bin
);
1022 * Copy pipeline state not marked as dynamic.
1023 * Dynamic state is pipeline state which hasn't been provided at pipeline
1024 * creation time, but is dynamically provided afterwards using various
1025 * vkCmdSet* functions.
1027 * The set of state considered "non_dynamic" is determined by the pieces of
1028 * state that have their corresponding VkDynamicState enums omitted from
1029 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1031 * @param[out] pipeline Destination non_dynamic state.
1032 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1035 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
1036 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1038 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
1039 struct anv_subpass
*subpass
= pipeline
->subpass
;
1041 pipeline
->dynamic_state
= default_dynamic_state
;
1043 if (pCreateInfo
->pDynamicState
) {
1044 /* Remove all of the states that are marked as dynamic */
1045 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1046 for (uint32_t s
= 0; s
< count
; s
++)
1047 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1050 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1052 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1054 * pViewportState is [...] NULL if the pipeline
1055 * has rasterization disabled.
1057 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1058 assert(pCreateInfo
->pViewportState
);
1060 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1061 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
1062 typed_memcpy(dynamic
->viewport
.viewports
,
1063 pCreateInfo
->pViewportState
->pViewports
,
1064 pCreateInfo
->pViewportState
->viewportCount
);
1067 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1068 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
1069 typed_memcpy(dynamic
->scissor
.scissors
,
1070 pCreateInfo
->pViewportState
->pScissors
,
1071 pCreateInfo
->pViewportState
->scissorCount
);
1075 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1076 assert(pCreateInfo
->pRasterizationState
);
1077 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1080 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1081 assert(pCreateInfo
->pRasterizationState
);
1082 dynamic
->depth_bias
.bias
=
1083 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1084 dynamic
->depth_bias
.clamp
=
1085 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1086 dynamic
->depth_bias
.slope
=
1087 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1090 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1092 * pColorBlendState is [...] NULL if the pipeline has rasterization
1093 * disabled or if the subpass of the render pass the pipeline is
1094 * created against does not use any color attachments.
1096 bool uses_color_att
= false;
1097 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1098 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1099 uses_color_att
= true;
1104 if (uses_color_att
&&
1105 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1106 assert(pCreateInfo
->pColorBlendState
);
1108 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
1109 typed_memcpy(dynamic
->blend_constants
,
1110 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1113 /* If there is no depthstencil attachment, then don't read
1114 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1115 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1116 * no need to override the depthstencil defaults in
1117 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1119 * Section 9.2 of the Vulkan 1.0.15 spec says:
1121 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1122 * disabled or if the subpass of the render pass the pipeline is created
1123 * against does not use a depth/stencil attachment.
1125 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1126 subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1127 assert(pCreateInfo
->pDepthStencilState
);
1129 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1130 dynamic
->depth_bounds
.min
=
1131 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1132 dynamic
->depth_bounds
.max
=
1133 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1136 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1137 dynamic
->stencil_compare_mask
.front
=
1138 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1139 dynamic
->stencil_compare_mask
.back
=
1140 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1143 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1144 dynamic
->stencil_write_mask
.front
=
1145 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1146 dynamic
->stencil_write_mask
.back
=
1147 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1150 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1151 dynamic
->stencil_reference
.front
=
1152 pCreateInfo
->pDepthStencilState
->front
.reference
;
1153 dynamic
->stencil_reference
.back
=
1154 pCreateInfo
->pDepthStencilState
->back
.reference
;
1158 pipeline
->dynamic_state_mask
= states
;
1162 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1165 struct anv_render_pass
*renderpass
= NULL
;
1166 struct anv_subpass
*subpass
= NULL
;
1168 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1169 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1171 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1173 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1176 assert(info
->subpass
< renderpass
->subpass_count
);
1177 subpass
= &renderpass
->subpasses
[info
->subpass
];
1179 assert(info
->stageCount
>= 1);
1180 assert(info
->pVertexInputState
);
1181 assert(info
->pInputAssemblyState
);
1182 assert(info
->pRasterizationState
);
1183 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1184 assert(info
->pViewportState
);
1185 assert(info
->pMultisampleState
);
1187 if (subpass
&& subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
)
1188 assert(info
->pDepthStencilState
);
1190 if (subpass
&& subpass
->color_count
> 0)
1191 assert(info
->pColorBlendState
);
1194 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1195 switch (info
->pStages
[i
].stage
) {
1196 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1197 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1198 assert(info
->pTessellationState
);
1208 * Calculate the desired L3 partitioning based on the current state of the
1209 * pipeline. For now this simply returns the conservative defaults calculated
1210 * by get_default_l3_weights(), but we could probably do better by gathering
1211 * more statistics from the pipeline state (e.g. guess of expected URB usage
1212 * and bound surfaces), or by using feed-back from performance counters.
1215 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1217 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1219 const struct gen_l3_weights w
=
1220 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
1222 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
1223 pipeline
->urb
.total_size
=
1224 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
1228 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1229 struct anv_device
*device
,
1230 struct anv_pipeline_cache
*cache
,
1231 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1232 const VkAllocationCallbacks
*alloc
)
1236 anv_pipeline_validate_create_info(pCreateInfo
);
1239 alloc
= &device
->alloc
;
1241 pipeline
->device
= device
;
1243 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, pCreateInfo
->renderPass
);
1244 assert(pCreateInfo
->subpass
< render_pass
->subpass_count
);
1245 pipeline
->subpass
= &render_pass
->subpasses
[pCreateInfo
->subpass
];
1247 pipeline
->layout
= anv_pipeline_layout_from_handle(pCreateInfo
->layout
);
1249 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1250 if (result
!= VK_SUCCESS
)
1253 pipeline
->batch
.alloc
= alloc
;
1254 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1255 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1256 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1257 pipeline
->batch
.status
= VK_SUCCESS
;
1259 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1260 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1261 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1263 pipeline
->sample_shading_enable
= pCreateInfo
->pMultisampleState
&&
1264 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
1266 pipeline
->needs_data_cache
= false;
1268 /* When we free the pipeline, we detect stages based on the NULL status
1269 * of various prog_data pointers. Make them NULL by default.
1271 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1273 pipeline
->active_stages
= 0;
1275 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = {};
1276 struct anv_shader_module
*modules
[MESA_SHADER_STAGES
] = {};
1277 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
1278 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
1279 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
1280 modules
[stage
] = anv_shader_module_from_handle(pStages
[stage
]->module
);
1283 if (modules
[MESA_SHADER_VERTEX
]) {
1284 result
= anv_pipeline_compile_vs(pipeline
, cache
, pCreateInfo
,
1285 modules
[MESA_SHADER_VERTEX
],
1286 pStages
[MESA_SHADER_VERTEX
]->pName
,
1287 pStages
[MESA_SHADER_VERTEX
]->pSpecializationInfo
);
1288 if (result
!= VK_SUCCESS
)
1292 if (modules
[MESA_SHADER_TESS_EVAL
]) {
1293 anv_pipeline_compile_tcs_tes(pipeline
, cache
, pCreateInfo
,
1294 modules
[MESA_SHADER_TESS_CTRL
],
1295 pStages
[MESA_SHADER_TESS_CTRL
]->pName
,
1296 pStages
[MESA_SHADER_TESS_CTRL
]->pSpecializationInfo
,
1297 modules
[MESA_SHADER_TESS_EVAL
],
1298 pStages
[MESA_SHADER_TESS_EVAL
]->pName
,
1299 pStages
[MESA_SHADER_TESS_EVAL
]->pSpecializationInfo
);
1302 if (modules
[MESA_SHADER_GEOMETRY
]) {
1303 result
= anv_pipeline_compile_gs(pipeline
, cache
, pCreateInfo
,
1304 modules
[MESA_SHADER_GEOMETRY
],
1305 pStages
[MESA_SHADER_GEOMETRY
]->pName
,
1306 pStages
[MESA_SHADER_GEOMETRY
]->pSpecializationInfo
);
1307 if (result
!= VK_SUCCESS
)
1311 if (modules
[MESA_SHADER_FRAGMENT
]) {
1312 result
= anv_pipeline_compile_fs(pipeline
, cache
, pCreateInfo
,
1313 modules
[MESA_SHADER_FRAGMENT
],
1314 pStages
[MESA_SHADER_FRAGMENT
]->pName
,
1315 pStages
[MESA_SHADER_FRAGMENT
]->pSpecializationInfo
);
1316 if (result
!= VK_SUCCESS
)
1320 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1322 anv_pipeline_setup_l3_config(pipeline
, false);
1324 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1325 pCreateInfo
->pVertexInputState
;
1327 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1329 pipeline
->vb_used
= 0;
1330 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1331 const VkVertexInputAttributeDescription
*desc
=
1332 &vi_info
->pVertexAttributeDescriptions
[i
];
1334 if (inputs_read
& (1ull << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1335 pipeline
->vb_used
|= 1 << desc
->binding
;
1338 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1339 const VkVertexInputBindingDescription
*desc
=
1340 &vi_info
->pVertexBindingDescriptions
[i
];
1342 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
1344 /* Step rate is programmed per vertex element (attribute), not
1345 * binding. Set up a map of which bindings step per instance, for
1346 * reference by vertex element setup. */
1347 switch (desc
->inputRate
) {
1349 case VK_VERTEX_INPUT_RATE_VERTEX
:
1350 pipeline
->instancing_enable
[desc
->binding
] = false;
1352 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1353 pipeline
->instancing_enable
[desc
->binding
] = true;
1358 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1359 pCreateInfo
->pInputAssemblyState
;
1360 const VkPipelineTessellationStateCreateInfo
*tess_info
=
1361 pCreateInfo
->pTessellationState
;
1362 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1364 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1365 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
1367 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];
1372 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1373 if (pipeline
->shaders
[s
])
1374 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
1377 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);