2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "anv_private.h"
34 #include "spirv/nir_spirv.h"
36 /* Needed for SWIZZLE macros */
37 #include "program/prog_instruction.h"
41 VkResult
anv_CreateShaderModule(
43 const VkShaderModuleCreateInfo
* pCreateInfo
,
44 const VkAllocationCallbacks
* pAllocator
,
45 VkShaderModule
* pShaderModule
)
47 ANV_FROM_HANDLE(anv_device
, device
, _device
);
48 struct anv_shader_module
*module
;
50 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
51 assert(pCreateInfo
->flags
== 0);
53 module
= anv_alloc2(&device
->alloc
, pAllocator
,
54 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
55 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
57 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
60 module
->size
= pCreateInfo
->codeSize
;
61 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
63 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
65 *pShaderModule
= anv_shader_module_to_handle(module
);
70 void anv_DestroyShaderModule(
72 VkShaderModule _module
,
73 const VkAllocationCallbacks
* pAllocator
)
75 ANV_FROM_HANDLE(anv_device
, device
, _device
);
76 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
78 anv_free2(&device
->alloc
, pAllocator
, module
);
81 #define SPIR_V_MAGIC_NUMBER 0x07230203
83 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
84 * we can't do that yet because we don't have the ability to copy nir.
87 anv_shader_compile_to_nir(struct anv_device
*device
,
88 struct anv_shader_module
*module
,
89 const char *entrypoint_name
,
90 gl_shader_stage stage
,
91 const VkSpecializationInfo
*spec_info
)
93 if (strcmp(entrypoint_name
, "main") != 0) {
94 anv_finishme("Multiple shaders per module not really supported");
97 const struct brw_compiler
*compiler
=
98 device
->instance
->physicalDevice
.compiler
;
99 const nir_shader_compiler_options
*nir_options
=
100 compiler
->glsl_compiler_options
[stage
].NirOptions
;
103 nir_function
*entry_point
;
105 /* Some things such as our meta clear/blit code will give us a NIR
106 * shader directly. In that case, we just ignore the SPIR-V entirely
107 * and just use the NIR shader */
109 nir
->options
= nir_options
;
110 nir_validate_shader(nir
);
112 assert(exec_list_length(&nir
->functions
) == 1);
113 struct exec_node
*node
= exec_list_get_head(&nir
->functions
);
114 entry_point
= exec_node_data(nir_function
, node
, node
);
116 uint32_t *spirv
= (uint32_t *) module
->data
;
117 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
118 assert(module
->size
% 4 == 0);
120 uint32_t num_spec_entries
= 0;
121 struct nir_spirv_specialization
*spec_entries
= NULL
;
122 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
123 num_spec_entries
= spec_info
->mapEntryCount
;
124 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
125 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
126 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
127 const void *data
= spec_info
->pData
+ entry
.offset
;
128 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
130 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
131 spec_entries
[i
].data
= *(const uint32_t *)data
;
135 entry_point
= spirv_to_nir(spirv
, module
->size
/ 4,
136 spec_entries
, num_spec_entries
,
137 stage
, entrypoint_name
, nir_options
);
138 nir
= entry_point
->shader
;
139 assert(nir
->stage
== stage
);
140 nir_validate_shader(nir
);
144 if (stage
== MESA_SHADER_FRAGMENT
) {
145 nir_lower_wpos_center(nir
);
146 nir_validate_shader(nir
);
149 nir_lower_returns(nir
);
150 nir_validate_shader(nir
);
152 nir_inline_functions(nir
);
153 nir_validate_shader(nir
);
155 /* Pick off the single entrypoint that we want */
156 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
157 if (func
!= entry_point
)
158 exec_node_remove(&func
->node
);
160 assert(exec_list_length(&nir
->functions
) == 1);
161 entry_point
->name
= ralloc_strdup(entry_point
, "main");
163 nir_remove_dead_variables(nir
, nir_var_shader_in
);
164 nir_remove_dead_variables(nir
, nir_var_shader_out
);
165 nir_remove_dead_variables(nir
, nir_var_system_value
);
166 nir_validate_shader(nir
);
168 nir_propagate_invariant(nir
);
169 nir_validate_shader(nir
);
171 nir_lower_io_to_temporaries(entry_point
->shader
, entry_point
->impl
,
174 nir_lower_system_values(nir
);
175 nir_validate_shader(nir
);
178 /* Vulkan uses the separate-shader linking model */
179 nir
->info
.separate_shader
= true;
181 nir
= brw_preprocess_nir(compiler
, nir
);
183 nir_shader_gather_info(nir
, entry_point
->impl
);
185 nir_variable_mode indirect_mask
= 0;
186 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectInput
)
187 indirect_mask
|= nir_var_shader_in
;
188 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectTemp
)
189 indirect_mask
|= nir_var_local
;
191 nir_lower_indirect_derefs(nir
, indirect_mask
);
196 void anv_DestroyPipeline(
198 VkPipeline _pipeline
,
199 const VkAllocationCallbacks
* pAllocator
)
201 ANV_FROM_HANDLE(anv_device
, device
, _device
);
202 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
204 anv_reloc_list_finish(&pipeline
->batch_relocs
,
205 pAllocator
? pAllocator
: &device
->alloc
);
206 if (pipeline
->blend_state
.map
)
207 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
208 anv_free2(&device
->alloc
, pAllocator
, pipeline
);
211 static const uint32_t vk_to_gen_primitive_type
[] = {
212 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
213 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
214 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
215 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
216 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
217 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
218 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
219 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
220 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
221 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
222 /* [VK_PRIMITIVE_TOPOLOGY_PATCH_LIST] = _3DPRIM_PATCHLIST_1 */
226 populate_sampler_prog_key(const struct brw_device_info
*devinfo
,
227 struct brw_sampler_prog_key_data
*key
)
229 /* XXX: Handle texture swizzle on HSW- */
230 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
231 /* Assume color sampler, no swizzling. (Works for BDW+) */
232 key
->swizzles
[i
] = SWIZZLE_XYZW
;
237 populate_vs_prog_key(const struct brw_device_info
*devinfo
,
238 struct brw_vs_prog_key
*key
)
240 memset(key
, 0, sizeof(*key
));
242 populate_sampler_prog_key(devinfo
, &key
->tex
);
244 /* XXX: Handle vertex input work-arounds */
246 /* XXX: Handle sampler_prog_key */
250 populate_gs_prog_key(const struct brw_device_info
*devinfo
,
251 struct brw_gs_prog_key
*key
)
253 memset(key
, 0, sizeof(*key
));
255 populate_sampler_prog_key(devinfo
, &key
->tex
);
259 populate_wm_prog_key(const struct brw_device_info
*devinfo
,
260 const VkGraphicsPipelineCreateInfo
*info
,
261 const struct anv_graphics_pipeline_create_info
*extra
,
262 struct brw_wm_prog_key
*key
)
264 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, info
->renderPass
);
266 memset(key
, 0, sizeof(*key
));
268 populate_sampler_prog_key(devinfo
, &key
->tex
);
270 /* TODO: Fill out key->input_slots_valid */
272 /* Vulkan doesn't specify a default */
273 key
->high_quality_derivatives
= false;
275 /* XXX Vulkan doesn't appear to specify */
276 key
->clamp_fragment_color
= false;
278 if (extra
&& extra
->color_attachment_count
>= 0) {
279 key
->nr_color_regions
= extra
->color_attachment_count
;
281 key
->nr_color_regions
=
282 render_pass
->subpasses
[info
->subpass
].color_count
;
285 key
->replicate_alpha
= key
->nr_color_regions
> 1 &&
286 info
->pMultisampleState
&&
287 info
->pMultisampleState
->alphaToCoverageEnable
;
289 if (info
->pMultisampleState
&& info
->pMultisampleState
->rasterizationSamples
> 1) {
290 /* We should probably pull this out of the shader, but it's fairly
291 * harmless to compute it and then let dead-code take care of it.
293 key
->persample_interp
=
294 (info
->pMultisampleState
->minSampleShading
*
295 info
->pMultisampleState
->rasterizationSamples
) > 1;
296 key
->multisample_fbo
= true;
301 populate_cs_prog_key(const struct brw_device_info
*devinfo
,
302 struct brw_cs_prog_key
*key
)
304 memset(key
, 0, sizeof(*key
));
306 populate_sampler_prog_key(devinfo
, &key
->tex
);
310 anv_pipeline_compile(struct anv_pipeline
*pipeline
,
311 struct anv_shader_module
*module
,
312 const char *entrypoint
,
313 gl_shader_stage stage
,
314 const VkSpecializationInfo
*spec_info
,
315 struct brw_stage_prog_data
*prog_data
,
316 struct anv_pipeline_bind_map
*map
)
318 nir_shader
*nir
= anv_shader_compile_to_nir(pipeline
->device
,
319 module
, entrypoint
, stage
,
324 anv_nir_lower_push_constants(nir
);
326 /* Figure out the number of parameters */
327 prog_data
->nr_params
= 0;
329 if (nir
->num_uniforms
> 0) {
330 /* If the shader uses any push constants at all, we'll just give
331 * them the maximum possible number
333 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
334 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
337 if (pipeline
->layout
&& pipeline
->layout
->stage
[stage
].has_dynamic_offsets
)
338 prog_data
->nr_params
+= MAX_DYNAMIC_BUFFERS
* 2;
340 if (nir
->info
.num_images
> 0) {
341 prog_data
->nr_params
+= nir
->info
.num_images
* BRW_IMAGE_PARAM_SIZE
;
342 pipeline
->needs_data_cache
= true;
345 if (stage
== MESA_SHADER_COMPUTE
)
346 ((struct brw_cs_prog_data
*)prog_data
)->thread_local_id_index
=
347 prog_data
->nr_params
++; /* The CS Thread ID uniform */
349 if (nir
->info
.num_ssbos
> 0)
350 pipeline
->needs_data_cache
= true;
352 if (prog_data
->nr_params
> 0) {
353 /* XXX: I think we're leaking this */
354 prog_data
->param
= (const union gl_constant_value
**)
355 malloc(prog_data
->nr_params
* sizeof(union gl_constant_value
*));
357 /* We now set the param values to be offsets into a
358 * anv_push_constant_data structure. Since the compiler doesn't
359 * actually dereference any of the gl_constant_value pointers in the
360 * params array, it doesn't really matter what we put here.
362 struct anv_push_constants
*null_data
= NULL
;
363 if (nir
->num_uniforms
> 0) {
364 /* Fill out the push constants section of the param array */
365 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++)
366 prog_data
->param
[i
] = (const union gl_constant_value
*)
367 &null_data
->client_data
[i
* sizeof(float)];
371 /* Set up dynamic offsets */
372 anv_nir_apply_dynamic_offsets(pipeline
, nir
, prog_data
);
374 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
375 if (pipeline
->layout
)
376 anv_nir_apply_pipeline_layout(pipeline
, nir
, prog_data
, map
);
378 /* nir_lower_io will only handle the push constants; we need to set this
379 * to the full number of possible uniforms.
381 nir
->num_uniforms
= prog_data
->nr_params
* 4;
387 anv_fill_binding_table(struct brw_stage_prog_data
*prog_data
, unsigned bias
)
389 prog_data
->binding_table
.size_bytes
= 0;
390 prog_data
->binding_table
.texture_start
= bias
;
391 prog_data
->binding_table
.gather_texture_start
= bias
;
392 prog_data
->binding_table
.ubo_start
= bias
;
393 prog_data
->binding_table
.ssbo_start
= bias
;
394 prog_data
->binding_table
.image_start
= bias
;
398 anv_pipeline_add_compiled_stage(struct anv_pipeline
*pipeline
,
399 gl_shader_stage stage
,
400 const struct brw_stage_prog_data
*prog_data
,
401 struct anv_pipeline_bind_map
*map
)
403 pipeline
->prog_data
[stage
] = prog_data
;
404 pipeline
->active_stages
|= mesa_to_vk_shader_stage(stage
);
405 pipeline
->bindings
[stage
] = *map
;
409 anv_pipeline_compile_vs(struct anv_pipeline
*pipeline
,
410 struct anv_pipeline_cache
*cache
,
411 const VkGraphicsPipelineCreateInfo
*info
,
412 struct anv_shader_module
*module
,
413 const char *entrypoint
,
414 const VkSpecializationInfo
*spec_info
)
416 const struct brw_compiler
*compiler
=
417 pipeline
->device
->instance
->physicalDevice
.compiler
;
418 const struct brw_stage_prog_data
*stage_prog_data
;
419 struct anv_pipeline_bind_map map
;
420 struct brw_vs_prog_key key
;
421 uint32_t kernel
= NO_KERNEL
;
422 unsigned char sha1
[20];
424 populate_vs_prog_key(&pipeline
->device
->info
, &key
);
426 if (module
->size
> 0) {
427 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
,
428 pipeline
->layout
, spec_info
);
429 kernel
= anv_pipeline_cache_search(cache
, sha1
, &stage_prog_data
, &map
);
432 if (kernel
== NO_KERNEL
) {
433 struct brw_vs_prog_data prog_data
= { 0, };
434 struct anv_pipeline_binding surface_to_descriptor
[256];
435 struct anv_pipeline_binding sampler_to_descriptor
[256];
437 map
= (struct anv_pipeline_bind_map
) {
438 .surface_to_descriptor
= surface_to_descriptor
,
439 .sampler_to_descriptor
= sampler_to_descriptor
442 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
443 MESA_SHADER_VERTEX
, spec_info
,
444 &prog_data
.base
.base
, &map
);
446 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
448 anv_fill_binding_table(&prog_data
.base
.base
, 0);
450 void *mem_ctx
= ralloc_context(NULL
);
452 if (module
->nir
== NULL
)
453 ralloc_steal(mem_ctx
, nir
);
455 prog_data
.inputs_read
= nir
->info
.inputs_read
;
457 brw_compute_vue_map(&pipeline
->device
->info
,
458 &prog_data
.base
.vue_map
,
459 nir
->info
.outputs_written
,
460 nir
->info
.separate_shader
);
463 const unsigned *shader_code
=
464 brw_compile_vs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
465 NULL
, false, -1, &code_size
, NULL
);
466 if (shader_code
== NULL
) {
467 ralloc_free(mem_ctx
);
468 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
471 stage_prog_data
= &prog_data
.base
.base
;
472 kernel
= anv_pipeline_cache_upload_kernel(cache
,
473 module
->size
> 0 ? sha1
: NULL
,
474 shader_code
, code_size
,
475 &stage_prog_data
, sizeof(prog_data
),
477 ralloc_free(mem_ctx
);
480 const struct brw_vs_prog_data
*vs_prog_data
=
481 (const struct brw_vs_prog_data
*) stage_prog_data
;
483 if (vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
) {
484 pipeline
->vs_simd8
= kernel
;
485 pipeline
->vs_vec4
= NO_KERNEL
;
487 pipeline
->vs_simd8
= NO_KERNEL
;
488 pipeline
->vs_vec4
= kernel
;
491 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_VERTEX
,
492 stage_prog_data
, &map
);
498 anv_pipeline_compile_gs(struct anv_pipeline
*pipeline
,
499 struct anv_pipeline_cache
*cache
,
500 const VkGraphicsPipelineCreateInfo
*info
,
501 struct anv_shader_module
*module
,
502 const char *entrypoint
,
503 const VkSpecializationInfo
*spec_info
)
505 const struct brw_compiler
*compiler
=
506 pipeline
->device
->instance
->physicalDevice
.compiler
;
507 const struct brw_stage_prog_data
*stage_prog_data
;
508 struct anv_pipeline_bind_map map
;
509 struct brw_gs_prog_key key
;
510 uint32_t kernel
= NO_KERNEL
;
511 unsigned char sha1
[20];
513 populate_gs_prog_key(&pipeline
->device
->info
, &key
);
515 if (module
->size
> 0) {
516 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
,
517 pipeline
->layout
, spec_info
);
518 kernel
= anv_pipeline_cache_search(cache
, sha1
, &stage_prog_data
, &map
);
521 if (kernel
== NO_KERNEL
) {
522 struct brw_gs_prog_data prog_data
= { 0, };
523 struct anv_pipeline_binding surface_to_descriptor
[256];
524 struct anv_pipeline_binding sampler_to_descriptor
[256];
526 map
= (struct anv_pipeline_bind_map
) {
527 .surface_to_descriptor
= surface_to_descriptor
,
528 .sampler_to_descriptor
= sampler_to_descriptor
531 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
532 MESA_SHADER_GEOMETRY
, spec_info
,
533 &prog_data
.base
.base
, &map
);
535 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
537 anv_fill_binding_table(&prog_data
.base
.base
, 0);
539 void *mem_ctx
= ralloc_context(NULL
);
541 if (module
->nir
== NULL
)
542 ralloc_steal(mem_ctx
, nir
);
544 brw_compute_vue_map(&pipeline
->device
->info
,
545 &prog_data
.base
.vue_map
,
546 nir
->info
.outputs_written
,
547 nir
->info
.separate_shader
);
550 const unsigned *shader_code
=
551 brw_compile_gs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
552 NULL
, -1, &code_size
, NULL
);
553 if (shader_code
== NULL
) {
554 ralloc_free(mem_ctx
);
555 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
559 stage_prog_data
= &prog_data
.base
.base
;
560 kernel
= anv_pipeline_cache_upload_kernel(cache
,
561 module
->size
> 0 ? sha1
: NULL
,
562 shader_code
, code_size
,
563 &stage_prog_data
, sizeof(prog_data
),
566 ralloc_free(mem_ctx
);
569 pipeline
->gs_kernel
= kernel
;
571 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_GEOMETRY
,
572 stage_prog_data
, &map
);
578 anv_pipeline_compile_fs(struct anv_pipeline
*pipeline
,
579 struct anv_pipeline_cache
*cache
,
580 const VkGraphicsPipelineCreateInfo
*info
,
581 const struct anv_graphics_pipeline_create_info
*extra
,
582 struct anv_shader_module
*module
,
583 const char *entrypoint
,
584 const VkSpecializationInfo
*spec_info
)
586 const struct brw_compiler
*compiler
=
587 pipeline
->device
->instance
->physicalDevice
.compiler
;
588 const struct brw_stage_prog_data
*stage_prog_data
;
589 struct anv_pipeline_bind_map map
;
590 struct brw_wm_prog_key key
;
591 unsigned char sha1
[20];
593 populate_wm_prog_key(&pipeline
->device
->info
, info
, extra
, &key
);
595 if (module
->size
> 0) {
596 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
,
597 pipeline
->layout
, spec_info
);
599 anv_pipeline_cache_search(cache
, sha1
, &stage_prog_data
, &map
);
602 if (pipeline
->ps_ksp0
== NO_KERNEL
) {
603 struct brw_wm_prog_data prog_data
= { 0, };
604 struct anv_pipeline_binding surface_to_descriptor
[256];
605 struct anv_pipeline_binding sampler_to_descriptor
[256];
607 map
= (struct anv_pipeline_bind_map
) {
608 .surface_to_descriptor
= surface_to_descriptor
+ 8,
609 .sampler_to_descriptor
= sampler_to_descriptor
612 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
613 MESA_SHADER_FRAGMENT
, spec_info
,
614 &prog_data
.base
, &map
);
616 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
618 unsigned num_rts
= 0;
619 struct anv_pipeline_binding rt_bindings
[8];
620 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
621 nir_foreach_variable_safe(var
, &nir
->outputs
) {
622 if (var
->data
.location
< FRAG_RESULT_DATA0
)
625 unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
626 if (rt
>= key
.nr_color_regions
) {
627 /* Out-of-bounds, throw it away */
628 var
->data
.mode
= nir_var_local
;
629 exec_node_remove(&var
->node
);
630 exec_list_push_tail(&impl
->locals
, &var
->node
);
634 /* Give it a new, compacted, location */
635 var
->data
.location
= FRAG_RESULT_DATA0
+ num_rts
;
638 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
639 assert(num_rts
+ array_len
<= 8);
641 for (unsigned i
= 0; i
< array_len
; i
++) {
642 rt_bindings
[num_rts
+ i
] = (struct anv_pipeline_binding
) {
643 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
649 num_rts
+= array_len
;
652 if (pipeline
->use_repclear
) {
653 assert(num_rts
== 1);
654 key
.nr_color_regions
= 1;
658 /* If we have no render targets, we need a null render target */
659 rt_bindings
[0] = (struct anv_pipeline_binding
) {
660 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
667 assert(num_rts
<= 8);
668 map
.surface_to_descriptor
-= num_rts
;
669 map
.surface_count
+= num_rts
;
670 assert(map
.surface_count
<= 256);
671 memcpy(map
.surface_to_descriptor
, rt_bindings
,
672 num_rts
* sizeof(*rt_bindings
));
674 anv_fill_binding_table(&prog_data
.base
, num_rts
);
676 void *mem_ctx
= ralloc_context(NULL
);
678 if (module
->nir
== NULL
)
679 ralloc_steal(mem_ctx
, nir
);
682 const unsigned *shader_code
=
683 brw_compile_fs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
684 NULL
, -1, -1, true, pipeline
->use_repclear
,
686 if (shader_code
== NULL
) {
687 ralloc_free(mem_ctx
);
688 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
691 stage_prog_data
= &prog_data
.base
;
693 anv_pipeline_cache_upload_kernel(cache
,
694 module
->size
> 0 ? sha1
: NULL
,
695 shader_code
, code_size
,
696 &stage_prog_data
, sizeof(prog_data
),
699 ralloc_free(mem_ctx
);
702 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_FRAGMENT
,
703 stage_prog_data
, &map
);
709 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
710 struct anv_pipeline_cache
*cache
,
711 const VkComputePipelineCreateInfo
*info
,
712 struct anv_shader_module
*module
,
713 const char *entrypoint
,
714 const VkSpecializationInfo
*spec_info
)
716 const struct brw_compiler
*compiler
=
717 pipeline
->device
->instance
->physicalDevice
.compiler
;
718 const struct brw_stage_prog_data
*stage_prog_data
;
719 struct anv_pipeline_bind_map map
;
720 struct brw_cs_prog_key key
;
721 uint32_t kernel
= NO_KERNEL
;
722 unsigned char sha1
[20];
724 populate_cs_prog_key(&pipeline
->device
->info
, &key
);
726 if (module
->size
> 0) {
727 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
,
728 pipeline
->layout
, spec_info
);
729 kernel
= anv_pipeline_cache_search(cache
, sha1
, &stage_prog_data
, &map
);
732 if (module
->size
== 0 || kernel
== NO_KERNEL
) {
733 struct brw_cs_prog_data prog_data
= { 0, };
734 struct anv_pipeline_binding surface_to_descriptor
[256];
735 struct anv_pipeline_binding sampler_to_descriptor
[256];
737 map
= (struct anv_pipeline_bind_map
) {
738 .surface_to_descriptor
= surface_to_descriptor
,
739 .sampler_to_descriptor
= sampler_to_descriptor
742 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
743 MESA_SHADER_COMPUTE
, spec_info
,
744 &prog_data
.base
, &map
);
746 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
748 anv_fill_binding_table(&prog_data
.base
, 1);
750 void *mem_ctx
= ralloc_context(NULL
);
752 if (module
->nir
== NULL
)
753 ralloc_steal(mem_ctx
, nir
);
756 const unsigned *shader_code
=
757 brw_compile_cs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
758 -1, &code_size
, NULL
);
759 if (shader_code
== NULL
) {
760 ralloc_free(mem_ctx
);
761 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
764 stage_prog_data
= &prog_data
.base
;
765 kernel
= anv_pipeline_cache_upload_kernel(cache
,
766 module
->size
> 0 ? sha1
: NULL
,
767 shader_code
, code_size
,
768 &stage_prog_data
, sizeof(prog_data
),
771 ralloc_free(mem_ctx
);
774 pipeline
->cs_simd
= kernel
;
776 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_COMPUTE
,
777 stage_prog_data
, &map
);
784 anv_setup_pipeline_l3_config(struct anv_pipeline
*pipeline
)
786 const struct brw_device_info
*devinfo
= &pipeline
->device
->info
;
787 switch (devinfo
->gen
) {
789 if (devinfo
->is_haswell
)
790 gen75_setup_pipeline_l3_config(pipeline
);
792 gen7_setup_pipeline_l3_config(pipeline
);
795 gen8_setup_pipeline_l3_config(pipeline
);
798 gen9_setup_pipeline_l3_config(pipeline
);
801 unreachable("unsupported gen\n");
806 anv_compute_urb_partition(struct anv_pipeline
*pipeline
)
808 const struct brw_device_info
*devinfo
= &pipeline
->device
->info
;
810 bool vs_present
= pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
;
811 unsigned vs_size
= vs_present
?
812 get_vs_prog_data(pipeline
)->base
.urb_entry_size
: 1;
813 unsigned vs_entry_size_bytes
= vs_size
* 64;
814 bool gs_present
= pipeline
->active_stages
& VK_SHADER_STAGE_GEOMETRY_BIT
;
815 unsigned gs_size
= gs_present
?
816 get_gs_prog_data(pipeline
)->base
.urb_entry_size
: 1;
817 unsigned gs_entry_size_bytes
= gs_size
* 64;
819 /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
821 * VS Number of URB Entries must be divisible by 8 if the VS URB Entry
822 * Allocation Size is less than 9 512-bit URB entries.
824 * Similar text exists for GS.
826 unsigned vs_granularity
= (vs_size
< 9) ? 8 : 1;
827 unsigned gs_granularity
= (gs_size
< 9) ? 8 : 1;
829 /* URB allocations must be done in 8k chunks. */
830 unsigned chunk_size_bytes
= 8192;
832 /* Determine the size of the URB in chunks. */
833 unsigned urb_chunks
= pipeline
->urb
.total_size
* 1024 / chunk_size_bytes
;
835 /* Reserve space for push constants */
836 unsigned push_constant_kb
;
837 if (pipeline
->device
->info
.gen
>= 8)
838 push_constant_kb
= 32;
839 else if (pipeline
->device
->info
.is_haswell
)
840 push_constant_kb
= pipeline
->device
->info
.gt
== 3 ? 32 : 16;
842 push_constant_kb
= 16;
844 unsigned push_constant_bytes
= push_constant_kb
* 1024;
845 unsigned push_constant_chunks
=
846 push_constant_bytes
/ chunk_size_bytes
;
848 /* Initially, assign each stage the minimum amount of URB space it needs,
849 * and make a note of how much additional space it "wants" (the amount of
850 * additional space it could actually make use of).
853 /* VS has a lower limit on the number of URB entries */
855 ALIGN(devinfo
->urb
.min_vs_entries
* vs_entry_size_bytes
,
856 chunk_size_bytes
) / chunk_size_bytes
;
858 ALIGN(devinfo
->urb
.max_vs_entries
* vs_entry_size_bytes
,
859 chunk_size_bytes
) / chunk_size_bytes
- vs_chunks
;
861 unsigned gs_chunks
= 0;
862 unsigned gs_wants
= 0;
864 /* There are two constraints on the minimum amount of URB space we can
867 * (1) We need room for at least 2 URB entries, since we always operate
868 * the GS in DUAL_OBJECT mode.
870 * (2) We can't allocate less than nr_gs_entries_granularity.
872 gs_chunks
= ALIGN(MAX2(gs_granularity
, 2) * gs_entry_size_bytes
,
873 chunk_size_bytes
) / chunk_size_bytes
;
875 ALIGN(devinfo
->urb
.max_gs_entries
* gs_entry_size_bytes
,
876 chunk_size_bytes
) / chunk_size_bytes
- gs_chunks
;
879 /* There should always be enough URB space to satisfy the minimum
880 * requirements of each stage.
882 unsigned total_needs
= push_constant_chunks
+ vs_chunks
+ gs_chunks
;
883 assert(total_needs
<= urb_chunks
);
885 /* Mete out remaining space (if any) in proportion to "wants". */
886 unsigned total_wants
= vs_wants
+ gs_wants
;
887 unsigned remaining_space
= urb_chunks
- total_needs
;
888 if (remaining_space
> total_wants
)
889 remaining_space
= total_wants
;
890 if (remaining_space
> 0) {
891 unsigned vs_additional
= (unsigned)
892 round(vs_wants
* (((double) remaining_space
) / total_wants
));
893 vs_chunks
+= vs_additional
;
894 remaining_space
-= vs_additional
;
895 gs_chunks
+= remaining_space
;
898 /* Sanity check that we haven't over-allocated. */
899 assert(push_constant_chunks
+ vs_chunks
+ gs_chunks
<= urb_chunks
);
901 /* Finally, compute the number of entries that can fit in the space
902 * allocated to each stage.
904 unsigned nr_vs_entries
= vs_chunks
* chunk_size_bytes
/ vs_entry_size_bytes
;
905 unsigned nr_gs_entries
= gs_chunks
* chunk_size_bytes
/ gs_entry_size_bytes
;
907 /* Since we rounded up when computing *_wants, this may be slightly more
908 * than the maximum allowed amount, so correct for that.
910 nr_vs_entries
= MIN2(nr_vs_entries
, devinfo
->urb
.max_vs_entries
);
911 nr_gs_entries
= MIN2(nr_gs_entries
, devinfo
->urb
.max_gs_entries
);
913 /* Ensure that we program a multiple of the granularity. */
914 nr_vs_entries
= ROUND_DOWN_TO(nr_vs_entries
, vs_granularity
);
915 nr_gs_entries
= ROUND_DOWN_TO(nr_gs_entries
, gs_granularity
);
917 /* Finally, sanity check to make sure we have at least the minimum number
918 * of entries needed for each stage.
920 assert(nr_vs_entries
>= devinfo
->urb
.min_vs_entries
);
922 assert(nr_gs_entries
>= 2);
924 /* Lay out the URB in the following order:
929 pipeline
->urb
.start
[MESA_SHADER_VERTEX
] = push_constant_chunks
;
930 pipeline
->urb
.size
[MESA_SHADER_VERTEX
] = vs_size
;
931 pipeline
->urb
.entries
[MESA_SHADER_VERTEX
] = nr_vs_entries
;
933 pipeline
->urb
.start
[MESA_SHADER_GEOMETRY
] = push_constant_chunks
+ vs_chunks
;
934 pipeline
->urb
.size
[MESA_SHADER_GEOMETRY
] = gs_size
;
935 pipeline
->urb
.entries
[MESA_SHADER_GEOMETRY
] = nr_gs_entries
;
937 pipeline
->urb
.start
[MESA_SHADER_TESS_CTRL
] = push_constant_chunks
;
938 pipeline
->urb
.size
[MESA_SHADER_TESS_CTRL
] = 1;
939 pipeline
->urb
.entries
[MESA_SHADER_TESS_CTRL
] = 0;
941 pipeline
->urb
.start
[MESA_SHADER_TESS_EVAL
] = push_constant_chunks
;
942 pipeline
->urb
.size
[MESA_SHADER_TESS_EVAL
] = 1;
943 pipeline
->urb
.entries
[MESA_SHADER_TESS_EVAL
] = 0;
947 * Copy pipeline state not marked as dynamic.
948 * Dynamic state is pipeline state which hasn't been provided at pipeline
949 * creation time, but is dynamically provided afterwards using various
950 * vkCmdSet* functions.
952 * The set of state considered "non_dynamic" is determined by the pieces of
953 * state that have their corresponding VkDynamicState enums omitted from
954 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
956 * @param[out] pipeline Destination non_dynamic state.
957 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
960 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
961 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
963 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
964 ANV_FROM_HANDLE(anv_render_pass
, pass
, pCreateInfo
->renderPass
);
965 struct anv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
967 pipeline
->dynamic_state
= default_dynamic_state
;
969 if (pCreateInfo
->pDynamicState
) {
970 /* Remove all of the states that are marked as dynamic */
971 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
972 for (uint32_t s
= 0; s
< count
; s
++)
973 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
976 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
978 /* Section 9.2 of the Vulkan 1.0.15 spec says:
980 * pViewportState is [...] NULL if the pipeline
981 * has rasterization disabled.
983 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
984 assert(pCreateInfo
->pViewportState
);
986 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
987 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
988 typed_memcpy(dynamic
->viewport
.viewports
,
989 pCreateInfo
->pViewportState
->pViewports
,
990 pCreateInfo
->pViewportState
->viewportCount
);
993 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
994 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
995 typed_memcpy(dynamic
->scissor
.scissors
,
996 pCreateInfo
->pViewportState
->pScissors
,
997 pCreateInfo
->pViewportState
->scissorCount
);
1001 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1002 assert(pCreateInfo
->pRasterizationState
);
1003 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1006 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1007 assert(pCreateInfo
->pRasterizationState
);
1008 dynamic
->depth_bias
.bias
=
1009 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1010 dynamic
->depth_bias
.clamp
=
1011 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1012 dynamic
->depth_bias
.slope
=
1013 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1016 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1018 * pColorBlendState is [...] NULL if the pipeline has rasterization
1019 * disabled or if the subpass of the render pass the pipeline is
1020 * created against does not use any color attachments.
1022 bool uses_color_att
= false;
1023 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1024 if (subpass
->color_attachments
[i
] != VK_ATTACHMENT_UNUSED
) {
1025 uses_color_att
= true;
1030 if (uses_color_att
&&
1031 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1032 assert(pCreateInfo
->pColorBlendState
);
1034 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
1035 typed_memcpy(dynamic
->blend_constants
,
1036 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1039 /* If there is no depthstencil attachment, then don't read
1040 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1041 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1042 * no need to override the depthstencil defaults in
1043 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1045 * Section 9.2 of the Vulkan 1.0.15 spec says:
1047 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1048 * disabled or if the subpass of the render pass the pipeline is created
1049 * against does not use a depth/stencil attachment.
1051 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1052 subpass
->depth_stencil_attachment
!= VK_ATTACHMENT_UNUSED
) {
1053 assert(pCreateInfo
->pDepthStencilState
);
1055 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1056 dynamic
->depth_bounds
.min
=
1057 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1058 dynamic
->depth_bounds
.max
=
1059 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1062 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1063 dynamic
->stencil_compare_mask
.front
=
1064 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1065 dynamic
->stencil_compare_mask
.back
=
1066 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1069 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1070 dynamic
->stencil_write_mask
.front
=
1071 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1072 dynamic
->stencil_write_mask
.back
=
1073 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1076 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1077 dynamic
->stencil_reference
.front
=
1078 pCreateInfo
->pDepthStencilState
->front
.reference
;
1079 dynamic
->stencil_reference
.back
=
1080 pCreateInfo
->pDepthStencilState
->back
.reference
;
1084 pipeline
->dynamic_state_mask
= states
;
1088 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1090 struct anv_render_pass
*renderpass
= NULL
;
1091 struct anv_subpass
*subpass
= NULL
;
1093 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1094 * present, as explained by the Vulkan (20 Oct 2015, git-aa308cb), Section
1095 * 4.2 Graphics Pipeline.
1097 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1099 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1102 if (renderpass
!= &anv_meta_dummy_renderpass
) {
1103 assert(info
->subpass
< renderpass
->subpass_count
);
1104 subpass
= &renderpass
->subpasses
[info
->subpass
];
1107 assert(info
->stageCount
>= 1);
1108 assert(info
->pVertexInputState
);
1109 assert(info
->pInputAssemblyState
);
1110 assert(info
->pViewportState
);
1111 assert(info
->pRasterizationState
);
1113 if (subpass
&& subpass
->depth_stencil_attachment
!= VK_ATTACHMENT_UNUSED
)
1114 assert(info
->pDepthStencilState
);
1116 if (subpass
&& subpass
->color_count
> 0)
1117 assert(info
->pColorBlendState
);
1119 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1120 switch (info
->pStages
[i
].stage
) {
1121 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1122 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1123 assert(info
->pTessellationState
);
1132 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1133 struct anv_device
*device
,
1134 struct anv_pipeline_cache
*cache
,
1135 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1136 const struct anv_graphics_pipeline_create_info
*extra
,
1137 const VkAllocationCallbacks
*alloc
)
1142 anv_pipeline_validate_create_info(pCreateInfo
);
1146 alloc
= &device
->alloc
;
1148 pipeline
->device
= device
;
1149 pipeline
->layout
= anv_pipeline_layout_from_handle(pCreateInfo
->layout
);
1151 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1152 if (result
!= VK_SUCCESS
)
1155 pipeline
->batch
.alloc
= alloc
;
1156 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1157 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1158 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1160 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1161 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1162 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1164 pipeline
->use_repclear
= extra
&& extra
->use_repclear
;
1166 pipeline
->needs_data_cache
= false;
1168 /* When we free the pipeline, we detect stages based on the NULL status
1169 * of various prog_data pointers. Make them NULL by default.
1171 memset(pipeline
->prog_data
, 0, sizeof(pipeline
->prog_data
));
1172 memset(pipeline
->bindings
, 0, sizeof(pipeline
->bindings
));
1174 pipeline
->vs_simd8
= NO_KERNEL
;
1175 pipeline
->vs_vec4
= NO_KERNEL
;
1176 pipeline
->gs_kernel
= NO_KERNEL
;
1177 pipeline
->ps_ksp0
= NO_KERNEL
;
1179 pipeline
->active_stages
= 0;
1181 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
1182 struct anv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
1183 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
1184 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
1185 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
1186 modules
[stage
] = anv_shader_module_from_handle(pStages
[stage
]->module
);
1189 if (modules
[MESA_SHADER_VERTEX
]) {
1190 result
= anv_pipeline_compile_vs(pipeline
, cache
, pCreateInfo
,
1191 modules
[MESA_SHADER_VERTEX
],
1192 pStages
[MESA_SHADER_VERTEX
]->pName
,
1193 pStages
[MESA_SHADER_VERTEX
]->pSpecializationInfo
);
1194 if (result
!= VK_SUCCESS
)
1198 if (modules
[MESA_SHADER_TESS_CTRL
] || modules
[MESA_SHADER_TESS_EVAL
])
1199 anv_finishme("no tessellation support");
1201 if (modules
[MESA_SHADER_GEOMETRY
]) {
1202 result
= anv_pipeline_compile_gs(pipeline
, cache
, pCreateInfo
,
1203 modules
[MESA_SHADER_GEOMETRY
],
1204 pStages
[MESA_SHADER_GEOMETRY
]->pName
,
1205 pStages
[MESA_SHADER_GEOMETRY
]->pSpecializationInfo
);
1206 if (result
!= VK_SUCCESS
)
1210 if (modules
[MESA_SHADER_FRAGMENT
]) {
1211 result
= anv_pipeline_compile_fs(pipeline
, cache
, pCreateInfo
, extra
,
1212 modules
[MESA_SHADER_FRAGMENT
],
1213 pStages
[MESA_SHADER_FRAGMENT
]->pName
,
1214 pStages
[MESA_SHADER_FRAGMENT
]->pSpecializationInfo
);
1215 if (result
!= VK_SUCCESS
)
1219 if (!(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
)) {
1220 /* Vertex is only optional if disable_vs is set */
1221 assert(extra
->disable_vs
);
1224 anv_setup_pipeline_l3_config(pipeline
);
1225 anv_compute_urb_partition(pipeline
);
1227 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1228 pCreateInfo
->pVertexInputState
;
1230 uint64_t inputs_read
;
1231 if (extra
&& extra
->disable_vs
) {
1232 /* If the VS is disabled, just assume the user knows what they're
1233 * doing and apply the layout blindly. This can only come from
1234 * meta, so this *should* be safe.
1236 inputs_read
= ~0ull;
1238 inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1241 pipeline
->vb_used
= 0;
1242 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1243 const VkVertexInputAttributeDescription
*desc
=
1244 &vi_info
->pVertexAttributeDescriptions
[i
];
1246 if (inputs_read
& (1 << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1247 pipeline
->vb_used
|= 1 << desc
->binding
;
1250 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1251 const VkVertexInputBindingDescription
*desc
=
1252 &vi_info
->pVertexBindingDescriptions
[i
];
1254 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
1256 /* Step rate is programmed per vertex element (attribute), not
1257 * binding. Set up a map of which bindings step per instance, for
1258 * reference by vertex element setup. */
1259 switch (desc
->inputRate
) {
1261 case VK_VERTEX_INPUT_RATE_VERTEX
:
1262 pipeline
->instancing_enable
[desc
->binding
] = false;
1264 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1265 pipeline
->instancing_enable
[desc
->binding
] = true;
1270 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1271 pCreateInfo
->pInputAssemblyState
;
1272 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1273 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];
1275 if (extra
&& extra
->use_rectlist
)
1276 pipeline
->topology
= _3DPRIM_RECTLIST
;
1281 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);
1287 anv_graphics_pipeline_create(
1289 VkPipelineCache _cache
,
1290 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1291 const struct anv_graphics_pipeline_create_info
*extra
,
1292 const VkAllocationCallbacks
*pAllocator
,
1293 VkPipeline
*pPipeline
)
1295 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1296 ANV_FROM_HANDLE(anv_pipeline_cache
, cache
, _cache
);
1299 cache
= &device
->default_pipeline_cache
;
1301 switch (device
->info
.gen
) {
1303 if (device
->info
.is_haswell
)
1304 return gen75_graphics_pipeline_create(_device
, cache
, pCreateInfo
, extra
, pAllocator
, pPipeline
);
1306 return gen7_graphics_pipeline_create(_device
, cache
, pCreateInfo
, extra
, pAllocator
, pPipeline
);
1308 return gen8_graphics_pipeline_create(_device
, cache
, pCreateInfo
, extra
, pAllocator
, pPipeline
);
1310 return gen9_graphics_pipeline_create(_device
, cache
, pCreateInfo
, extra
, pAllocator
, pPipeline
);
1312 unreachable("unsupported gen\n");
1316 VkResult
anv_CreateGraphicsPipelines(
1318 VkPipelineCache pipelineCache
,
1320 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
1321 const VkAllocationCallbacks
* pAllocator
,
1322 VkPipeline
* pPipelines
)
1324 VkResult result
= VK_SUCCESS
;
1327 for (; i
< count
; i
++) {
1328 result
= anv_graphics_pipeline_create(_device
,
1331 NULL
, pAllocator
, &pPipelines
[i
]);
1332 if (result
!= VK_SUCCESS
) {
1333 for (unsigned j
= 0; j
< i
; j
++) {
1334 anv_DestroyPipeline(_device
, pPipelines
[j
], pAllocator
);
1344 static VkResult
anv_compute_pipeline_create(
1346 VkPipelineCache _cache
,
1347 const VkComputePipelineCreateInfo
* pCreateInfo
,
1348 const VkAllocationCallbacks
* pAllocator
,
1349 VkPipeline
* pPipeline
)
1351 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1352 ANV_FROM_HANDLE(anv_pipeline_cache
, cache
, _cache
);
1355 cache
= &device
->default_pipeline_cache
;
1357 switch (device
->info
.gen
) {
1359 if (device
->info
.is_haswell
)
1360 return gen75_compute_pipeline_create(_device
, cache
, pCreateInfo
, pAllocator
, pPipeline
);
1362 return gen7_compute_pipeline_create(_device
, cache
, pCreateInfo
, pAllocator
, pPipeline
);
1364 return gen8_compute_pipeline_create(_device
, cache
, pCreateInfo
, pAllocator
, pPipeline
);
1366 return gen9_compute_pipeline_create(_device
, cache
, pCreateInfo
, pAllocator
, pPipeline
);
1368 unreachable("unsupported gen\n");
1372 VkResult
anv_CreateComputePipelines(
1374 VkPipelineCache pipelineCache
,
1376 const VkComputePipelineCreateInfo
* pCreateInfos
,
1377 const VkAllocationCallbacks
* pAllocator
,
1378 VkPipeline
* pPipelines
)
1380 VkResult result
= VK_SUCCESS
;
1383 for (; i
< count
; i
++) {
1384 result
= anv_compute_pipeline_create(_device
, pipelineCache
,
1386 pAllocator
, &pPipelines
[i
]);
1387 if (result
!= VK_SUCCESS
) {
1388 for (unsigned j
= 0; j
< i
; j
++) {
1389 anv_DestroyPipeline(_device
, pPipelines
[j
], pAllocator
);