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[mesa.git] / src / intel / vulkan / anv_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "util/mesa-sha1.h"
31 #include "common/gen_l3_config.h"
32 #include "anv_private.h"
33 #include "compiler/brw_nir.h"
34 #include "anv_nir.h"
35 #include "spirv/nir_spirv.h"
36
37 /* Needed for SWIZZLE macros */
38 #include "program/prog_instruction.h"
39
40 // Shader functions
41
42 VkResult anv_CreateShaderModule(
43 VkDevice _device,
44 const VkShaderModuleCreateInfo* pCreateInfo,
45 const VkAllocationCallbacks* pAllocator,
46 VkShaderModule* pShaderModule)
47 {
48 ANV_FROM_HANDLE(anv_device, device, _device);
49 struct anv_shader_module *module;
50
51 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
52 assert(pCreateInfo->flags == 0);
53
54 module = vk_alloc2(&device->alloc, pAllocator,
55 sizeof(*module) + pCreateInfo->codeSize, 8,
56 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
57 if (module == NULL)
58 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
59
60 module->size = pCreateInfo->codeSize;
61 memcpy(module->data, pCreateInfo->pCode, module->size);
62
63 _mesa_sha1_compute(module->data, module->size, module->sha1);
64
65 *pShaderModule = anv_shader_module_to_handle(module);
66
67 return VK_SUCCESS;
68 }
69
70 void anv_DestroyShaderModule(
71 VkDevice _device,
72 VkShaderModule _module,
73 const VkAllocationCallbacks* pAllocator)
74 {
75 ANV_FROM_HANDLE(anv_device, device, _device);
76 ANV_FROM_HANDLE(anv_shader_module, module, _module);
77
78 if (!module)
79 return;
80
81 vk_free2(&device->alloc, pAllocator, module);
82 }
83
84 #define SPIR_V_MAGIC_NUMBER 0x07230203
85
86 static const uint64_t stage_to_debug[] = {
87 [MESA_SHADER_VERTEX] = DEBUG_VS,
88 [MESA_SHADER_TESS_CTRL] = DEBUG_TCS,
89 [MESA_SHADER_TESS_EVAL] = DEBUG_TES,
90 [MESA_SHADER_GEOMETRY] = DEBUG_GS,
91 [MESA_SHADER_FRAGMENT] = DEBUG_WM,
92 [MESA_SHADER_COMPUTE] = DEBUG_CS,
93 };
94
95 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
96 * we can't do that yet because we don't have the ability to copy nir.
97 */
98 static nir_shader *
99 anv_shader_compile_to_nir(struct anv_pipeline *pipeline,
100 void *mem_ctx,
101 struct anv_shader_module *module,
102 const char *entrypoint_name,
103 gl_shader_stage stage,
104 const VkSpecializationInfo *spec_info)
105 {
106 const struct anv_device *device = pipeline->device;
107
108 const struct brw_compiler *compiler =
109 device->instance->physicalDevice.compiler;
110 const nir_shader_compiler_options *nir_options =
111 compiler->glsl_compiler_options[stage].NirOptions;
112
113 uint32_t *spirv = (uint32_t *) module->data;
114 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
115 assert(module->size % 4 == 0);
116
117 uint32_t num_spec_entries = 0;
118 struct nir_spirv_specialization *spec_entries = NULL;
119 if (spec_info && spec_info->mapEntryCount > 0) {
120 num_spec_entries = spec_info->mapEntryCount;
121 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
122 for (uint32_t i = 0; i < num_spec_entries; i++) {
123 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
124 const void *data = spec_info->pData + entry.offset;
125 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
126
127 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
128 if (spec_info->dataSize == 8)
129 spec_entries[i].data64 = *(const uint64_t *)data;
130 else
131 spec_entries[i].data32 = *(const uint32_t *)data;
132 }
133 }
134
135 struct spirv_to_nir_options spirv_options = {
136 .lower_workgroup_access_to_offsets = true,
137 .caps = {
138 .float64 = device->instance->physicalDevice.info.gen >= 8,
139 .int64 = device->instance->physicalDevice.info.gen >= 8,
140 .tessellation = true,
141 .draw_parameters = true,
142 .image_write_without_format = true,
143 .multiview = true,
144 .variable_pointers = true,
145 .storage_16bit = device->instance->physicalDevice.info.gen >= 8,
146 },
147 };
148
149 nir_function *entry_point =
150 spirv_to_nir(spirv, module->size / 4,
151 spec_entries, num_spec_entries,
152 stage, entrypoint_name, &spirv_options, nir_options);
153 nir_shader *nir = entry_point->shader;
154 assert(nir->info.stage == stage);
155 nir_validate_shader(nir);
156 ralloc_steal(mem_ctx, nir);
157
158 free(spec_entries);
159
160 if (unlikely(INTEL_DEBUG & stage_to_debug[stage])) {
161 fprintf(stderr, "NIR (from SPIR-V) for %s shader:\n",
162 gl_shader_stage_name(stage));
163 nir_print_shader(nir, stderr);
164 }
165
166 /* We have to lower away local constant initializers right before we
167 * inline functions. That way they get properly initialized at the top
168 * of the function and not at the top of its caller.
169 */
170 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
171 NIR_PASS_V(nir, nir_lower_returns);
172 NIR_PASS_V(nir, nir_inline_functions);
173
174 /* Pick off the single entrypoint that we want */
175 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
176 if (func != entry_point)
177 exec_node_remove(&func->node);
178 }
179 assert(exec_list_length(&nir->functions) == 1);
180 entry_point->name = ralloc_strdup(entry_point, "main");
181
182 /* Make sure we lower constant initializers on output variables so that
183 * nir_remove_dead_variables below sees the corresponding stores
184 */
185 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
186
187 NIR_PASS_V(nir, nir_remove_dead_variables,
188 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
189
190 if (stage == MESA_SHADER_FRAGMENT)
191 NIR_PASS_V(nir, nir_lower_wpos_center, pipeline->sample_shading_enable);
192
193 /* Now that we've deleted all but the main function, we can go ahead and
194 * lower the rest of the constant initializers.
195 */
196 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
197 NIR_PASS_V(nir, nir_propagate_invariant);
198 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
199 entry_point->impl, true, false);
200
201 /* Vulkan uses the separate-shader linking model */
202 nir->info.separate_shader = true;
203
204 nir = brw_preprocess_nir(compiler, nir);
205
206 if (stage == MESA_SHADER_FRAGMENT)
207 NIR_PASS_V(nir, anv_nir_lower_input_attachments);
208
209 return nir;
210 }
211
212 void anv_DestroyPipeline(
213 VkDevice _device,
214 VkPipeline _pipeline,
215 const VkAllocationCallbacks* pAllocator)
216 {
217 ANV_FROM_HANDLE(anv_device, device, _device);
218 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
219
220 if (!pipeline)
221 return;
222
223 anv_reloc_list_finish(&pipeline->batch_relocs,
224 pAllocator ? pAllocator : &device->alloc);
225 if (pipeline->blend_state.map)
226 anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
227
228 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
229 if (pipeline->shaders[s])
230 anv_shader_bin_unref(device, pipeline->shaders[s]);
231 }
232
233 vk_free2(&device->alloc, pAllocator, pipeline);
234 }
235
236 static const uint32_t vk_to_gen_primitive_type[] = {
237 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
238 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
239 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
240 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
241 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
242 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
243 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
244 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
245 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
246 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
247 };
248
249 static void
250 populate_sampler_prog_key(const struct gen_device_info *devinfo,
251 struct brw_sampler_prog_key_data *key)
252 {
253 /* Almost all multisampled textures are compressed. The only time when we
254 * don't compress a multisampled texture is for 16x MSAA with a surface
255 * width greater than 8k which is a bit of an edge case. Since the sampler
256 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
257 * to tell the compiler to always assume compression.
258 */
259 key->compressed_multisample_layout_mask = ~0;
260
261 /* SkyLake added support for 16x MSAA. With this came a new message for
262 * reading from a 16x MSAA surface with compression. The new message was
263 * needed because now the MCS data is 64 bits instead of 32 or lower as is
264 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
265 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
266 * so we can just use it unconditionally. This may not be quite as
267 * efficient but it saves us from recompiling.
268 */
269 if (devinfo->gen >= 9)
270 key->msaa_16 = ~0;
271
272 /* XXX: Handle texture swizzle on HSW- */
273 for (int i = 0; i < MAX_SAMPLERS; i++) {
274 /* Assume color sampler, no swizzling. (Works for BDW+) */
275 key->swizzles[i] = SWIZZLE_XYZW;
276 }
277 }
278
279 static void
280 populate_vs_prog_key(const struct gen_device_info *devinfo,
281 struct brw_vs_prog_key *key)
282 {
283 memset(key, 0, sizeof(*key));
284
285 populate_sampler_prog_key(devinfo, &key->tex);
286
287 /* XXX: Handle vertex input work-arounds */
288
289 /* XXX: Handle sampler_prog_key */
290 }
291
292 static void
293 populate_gs_prog_key(const struct gen_device_info *devinfo,
294 struct brw_gs_prog_key *key)
295 {
296 memset(key, 0, sizeof(*key));
297
298 populate_sampler_prog_key(devinfo, &key->tex);
299 }
300
301 static void
302 populate_wm_prog_key(const struct anv_pipeline *pipeline,
303 const VkGraphicsPipelineCreateInfo *info,
304 struct brw_wm_prog_key *key)
305 {
306 const struct gen_device_info *devinfo = &pipeline->device->info;
307
308 memset(key, 0, sizeof(*key));
309
310 populate_sampler_prog_key(devinfo, &key->tex);
311
312 /* TODO: we could set this to 0 based on the information in nir_shader, but
313 * this function is called before spirv_to_nir. */
314 const struct brw_vue_map *vue_map =
315 &anv_pipeline_get_last_vue_prog_data(pipeline)->vue_map;
316 key->input_slots_valid = vue_map->slots_valid;
317
318 /* Vulkan doesn't specify a default */
319 key->high_quality_derivatives = false;
320
321 /* XXX Vulkan doesn't appear to specify */
322 key->clamp_fragment_color = false;
323
324 key->nr_color_regions = pipeline->subpass->color_count;
325
326 key->replicate_alpha = key->nr_color_regions > 1 &&
327 info->pMultisampleState &&
328 info->pMultisampleState->alphaToCoverageEnable;
329
330 if (info->pMultisampleState) {
331 /* We should probably pull this out of the shader, but it's fairly
332 * harmless to compute it and then let dead-code take care of it.
333 */
334 if (info->pMultisampleState->rasterizationSamples > 1) {
335 key->persample_interp =
336 (info->pMultisampleState->minSampleShading *
337 info->pMultisampleState->rasterizationSamples) > 1;
338 key->multisample_fbo = true;
339 }
340
341 key->frag_coord_adds_sample_pos =
342 info->pMultisampleState->sampleShadingEnable;
343 }
344 }
345
346 static void
347 populate_cs_prog_key(const struct gen_device_info *devinfo,
348 struct brw_cs_prog_key *key)
349 {
350 memset(key, 0, sizeof(*key));
351
352 populate_sampler_prog_key(devinfo, &key->tex);
353 }
354
355 static void
356 anv_pipeline_hash_shader(struct anv_pipeline *pipeline,
357 struct anv_pipeline_layout *layout,
358 struct anv_shader_module *module,
359 const char *entrypoint,
360 gl_shader_stage stage,
361 const VkSpecializationInfo *spec_info,
362 const void *key, size_t key_size,
363 unsigned char *sha1_out)
364 {
365 struct mesa_sha1 ctx;
366
367 _mesa_sha1_init(&ctx);
368 if (stage != MESA_SHADER_COMPUTE) {
369 _mesa_sha1_update(&ctx, &pipeline->subpass->view_mask,
370 sizeof(pipeline->subpass->view_mask));
371 }
372 if (layout)
373 _mesa_sha1_update(&ctx, layout->sha1, sizeof(layout->sha1));
374 _mesa_sha1_update(&ctx, module->sha1, sizeof(module->sha1));
375 _mesa_sha1_update(&ctx, entrypoint, strlen(entrypoint));
376 _mesa_sha1_update(&ctx, &stage, sizeof(stage));
377 if (spec_info) {
378 _mesa_sha1_update(&ctx, spec_info->pMapEntries,
379 spec_info->mapEntryCount * sizeof(*spec_info->pMapEntries));
380 _mesa_sha1_update(&ctx, spec_info->pData, spec_info->dataSize);
381 }
382 _mesa_sha1_update(&ctx, key, key_size);
383 _mesa_sha1_final(&ctx, sha1_out);
384 }
385
386 static nir_shader *
387 anv_pipeline_compile(struct anv_pipeline *pipeline,
388 void *mem_ctx,
389 struct anv_pipeline_layout *layout,
390 struct anv_shader_module *module,
391 const char *entrypoint,
392 gl_shader_stage stage,
393 const VkSpecializationInfo *spec_info,
394 struct brw_stage_prog_data *prog_data,
395 struct anv_pipeline_bind_map *map)
396 {
397 const struct brw_compiler *compiler =
398 pipeline->device->instance->physicalDevice.compiler;
399
400 nir_shader *nir = anv_shader_compile_to_nir(pipeline, mem_ctx,
401 module, entrypoint, stage,
402 spec_info);
403 if (nir == NULL)
404 return NULL;
405
406 NIR_PASS_V(nir, anv_nir_lower_ycbcr_textures, layout);
407
408 NIR_PASS_V(nir, anv_nir_lower_push_constants);
409
410 if (stage != MESA_SHADER_COMPUTE)
411 NIR_PASS_V(nir, anv_nir_lower_multiview, pipeline->subpass->view_mask);
412
413 if (stage == MESA_SHADER_COMPUTE)
414 prog_data->total_shared = nir->num_shared;
415
416 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
417
418 if (nir->num_uniforms > 0) {
419 assert(prog_data->nr_params == 0);
420
421 /* If the shader uses any push constants at all, we'll just give
422 * them the maximum possible number
423 */
424 assert(nir->num_uniforms <= MAX_PUSH_CONSTANTS_SIZE);
425 nir->num_uniforms = MAX_PUSH_CONSTANTS_SIZE;
426 prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
427 prog_data->param = ralloc_array(mem_ctx, uint32_t, prog_data->nr_params);
428
429 /* We now set the param values to be offsets into a
430 * anv_push_constant_data structure. Since the compiler doesn't
431 * actually dereference any of the gl_constant_value pointers in the
432 * params array, it doesn't really matter what we put here.
433 */
434 struct anv_push_constants *null_data = NULL;
435 /* Fill out the push constants section of the param array */
436 for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++) {
437 prog_data->param[i] = ANV_PARAM_PUSH(
438 (uintptr_t)&null_data->client_data[i * sizeof(float)]);
439 }
440 }
441
442 if (nir->info.num_ssbos > 0 || nir->info.num_images > 0)
443 pipeline->needs_data_cache = true;
444
445 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
446 if (layout)
447 anv_nir_apply_pipeline_layout(pipeline, layout, nir, prog_data, map);
448
449 if (stage != MESA_SHADER_COMPUTE)
450 brw_nir_analyze_ubo_ranges(compiler, nir, prog_data->ubo_ranges);
451
452 assert(nir->num_uniforms == prog_data->nr_params * 4);
453
454 return nir;
455 }
456
457 static void
458 anv_fill_binding_table(struct brw_stage_prog_data *prog_data, unsigned bias)
459 {
460 prog_data->binding_table.size_bytes = 0;
461 prog_data->binding_table.texture_start = bias;
462 prog_data->binding_table.gather_texture_start = bias;
463 prog_data->binding_table.ubo_start = bias;
464 prog_data->binding_table.ssbo_start = bias;
465 prog_data->binding_table.image_start = bias;
466 }
467
468 static struct anv_shader_bin *
469 anv_pipeline_upload_kernel(struct anv_pipeline *pipeline,
470 struct anv_pipeline_cache *cache,
471 const void *key_data, uint32_t key_size,
472 const void *kernel_data, uint32_t kernel_size,
473 const struct brw_stage_prog_data *prog_data,
474 uint32_t prog_data_size,
475 const struct anv_pipeline_bind_map *bind_map)
476 {
477 if (cache) {
478 return anv_pipeline_cache_upload_kernel(cache, key_data, key_size,
479 kernel_data, kernel_size,
480 prog_data, prog_data_size,
481 bind_map);
482 } else {
483 return anv_shader_bin_create(pipeline->device, key_data, key_size,
484 kernel_data, kernel_size,
485 prog_data, prog_data_size,
486 prog_data->param, bind_map);
487 }
488 }
489
490
491 static void
492 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
493 gl_shader_stage stage,
494 struct anv_shader_bin *shader)
495 {
496 pipeline->shaders[stage] = shader;
497 pipeline->active_stages |= mesa_to_vk_shader_stage(stage);
498 }
499
500 static VkResult
501 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
502 struct anv_pipeline_cache *cache,
503 const VkGraphicsPipelineCreateInfo *info,
504 struct anv_shader_module *module,
505 const char *entrypoint,
506 const VkSpecializationInfo *spec_info)
507 {
508 const struct brw_compiler *compiler =
509 pipeline->device->instance->physicalDevice.compiler;
510 struct brw_vs_prog_key key;
511 struct anv_shader_bin *bin = NULL;
512 unsigned char sha1[20];
513
514 populate_vs_prog_key(&pipeline->device->info, &key);
515
516 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
517
518 if (cache) {
519 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
520 MESA_SHADER_VERTEX, spec_info,
521 &key, sizeof(key), sha1);
522 bin = anv_pipeline_cache_search(cache, sha1, 20);
523 }
524
525 if (bin == NULL) {
526 struct brw_vs_prog_data prog_data = {};
527 struct anv_pipeline_binding surface_to_descriptor[256];
528 struct anv_pipeline_binding sampler_to_descriptor[256];
529
530 struct anv_pipeline_bind_map map = {
531 .surface_to_descriptor = surface_to_descriptor,
532 .sampler_to_descriptor = sampler_to_descriptor
533 };
534
535 void *mem_ctx = ralloc_context(NULL);
536
537 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
538 module, entrypoint,
539 MESA_SHADER_VERTEX, spec_info,
540 &prog_data.base.base, &map);
541 if (nir == NULL) {
542 ralloc_free(mem_ctx);
543 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
544 }
545
546 anv_fill_binding_table(&prog_data.base.base, 0);
547
548 brw_compute_vue_map(&pipeline->device->info,
549 &prog_data.base.vue_map,
550 nir->info.outputs_written,
551 nir->info.separate_shader);
552
553 const unsigned *shader_code =
554 brw_compile_vs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
555 -1, NULL);
556 if (shader_code == NULL) {
557 ralloc_free(mem_ctx);
558 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
559 }
560
561 unsigned code_size = prog_data.base.base.program_size;
562 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
563 shader_code, code_size,
564 &prog_data.base.base, sizeof(prog_data),
565 &map);
566 if (!bin) {
567 ralloc_free(mem_ctx);
568 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
569 }
570
571 ralloc_free(mem_ctx);
572 }
573
574 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX, bin);
575
576 return VK_SUCCESS;
577 }
578
579 static void
580 merge_tess_info(struct shader_info *tes_info,
581 const struct shader_info *tcs_info)
582 {
583 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
584 *
585 * "PointMode. Controls generation of points rather than triangles
586 * or lines. This functionality defaults to disabled, and is
587 * enabled if either shader stage includes the execution mode.
588 *
589 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
590 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
591 * and OutputVertices, it says:
592 *
593 * "One mode must be set in at least one of the tessellation
594 * shader stages."
595 *
596 * So, the fields can be set in either the TCS or TES, but they must
597 * agree if set in both. Our backend looks at TES, so bitwise-or in
598 * the values from the TCS.
599 */
600 assert(tcs_info->tess.tcs_vertices_out == 0 ||
601 tes_info->tess.tcs_vertices_out == 0 ||
602 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
603 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
604
605 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
606 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
607 tcs_info->tess.spacing == tes_info->tess.spacing);
608 tes_info->tess.spacing |= tcs_info->tess.spacing;
609
610 assert(tcs_info->tess.primitive_mode == 0 ||
611 tes_info->tess.primitive_mode == 0 ||
612 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
613 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
614 tes_info->tess.ccw |= tcs_info->tess.ccw;
615 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
616 }
617
618 static VkResult
619 anv_pipeline_compile_tcs_tes(struct anv_pipeline *pipeline,
620 struct anv_pipeline_cache *cache,
621 const VkGraphicsPipelineCreateInfo *info,
622 struct anv_shader_module *tcs_module,
623 const char *tcs_entrypoint,
624 const VkSpecializationInfo *tcs_spec_info,
625 struct anv_shader_module *tes_module,
626 const char *tes_entrypoint,
627 const VkSpecializationInfo *tes_spec_info)
628 {
629 const struct gen_device_info *devinfo = &pipeline->device->info;
630 const struct brw_compiler *compiler =
631 pipeline->device->instance->physicalDevice.compiler;
632 struct brw_tcs_prog_key tcs_key = {};
633 struct brw_tes_prog_key tes_key = {};
634 struct anv_shader_bin *tcs_bin = NULL;
635 struct anv_shader_bin *tes_bin = NULL;
636 unsigned char tcs_sha1[40];
637 unsigned char tes_sha1[40];
638
639 populate_sampler_prog_key(&pipeline->device->info, &tcs_key.tex);
640 populate_sampler_prog_key(&pipeline->device->info, &tes_key.tex);
641 tcs_key.input_vertices = info->pTessellationState->patchControlPoints;
642
643 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
644
645 if (cache) {
646 anv_pipeline_hash_shader(pipeline, layout, tcs_module, tcs_entrypoint,
647 MESA_SHADER_TESS_CTRL, tcs_spec_info,
648 &tcs_key, sizeof(tcs_key), tcs_sha1);
649 anv_pipeline_hash_shader(pipeline, layout, tes_module, tes_entrypoint,
650 MESA_SHADER_TESS_EVAL, tes_spec_info,
651 &tes_key, sizeof(tes_key), tes_sha1);
652 memcpy(&tcs_sha1[20], tes_sha1, 20);
653 memcpy(&tes_sha1[20], tcs_sha1, 20);
654 tcs_bin = anv_pipeline_cache_search(cache, tcs_sha1, sizeof(tcs_sha1));
655 tes_bin = anv_pipeline_cache_search(cache, tes_sha1, sizeof(tes_sha1));
656 }
657
658 if (tcs_bin == NULL || tes_bin == NULL) {
659 struct brw_tcs_prog_data tcs_prog_data = {};
660 struct brw_tes_prog_data tes_prog_data = {};
661 struct anv_pipeline_binding tcs_surface_to_descriptor[256];
662 struct anv_pipeline_binding tcs_sampler_to_descriptor[256];
663 struct anv_pipeline_binding tes_surface_to_descriptor[256];
664 struct anv_pipeline_binding tes_sampler_to_descriptor[256];
665
666 struct anv_pipeline_bind_map tcs_map = {
667 .surface_to_descriptor = tcs_surface_to_descriptor,
668 .sampler_to_descriptor = tcs_sampler_to_descriptor
669 };
670 struct anv_pipeline_bind_map tes_map = {
671 .surface_to_descriptor = tes_surface_to_descriptor,
672 .sampler_to_descriptor = tes_sampler_to_descriptor
673 };
674
675 void *mem_ctx = ralloc_context(NULL);
676
677 nir_shader *tcs_nir =
678 anv_pipeline_compile(pipeline, mem_ctx, layout,
679 tcs_module, tcs_entrypoint,
680 MESA_SHADER_TESS_CTRL, tcs_spec_info,
681 &tcs_prog_data.base.base, &tcs_map);
682 nir_shader *tes_nir =
683 anv_pipeline_compile(pipeline, mem_ctx, layout,
684 tes_module, tes_entrypoint,
685 MESA_SHADER_TESS_EVAL, tes_spec_info,
686 &tes_prog_data.base.base, &tes_map);
687 if (tcs_nir == NULL || tes_nir == NULL) {
688 ralloc_free(mem_ctx);
689 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
690 }
691
692 nir_lower_tes_patch_vertices(tes_nir,
693 tcs_nir->info.tess.tcs_vertices_out);
694
695 /* Copy TCS info into the TES info */
696 merge_tess_info(&tes_nir->info, &tcs_nir->info);
697
698 anv_fill_binding_table(&tcs_prog_data.base.base, 0);
699 anv_fill_binding_table(&tes_prog_data.base.base, 0);
700
701 /* Whacking the key after cache lookup is a bit sketchy, but all of
702 * this comes from the SPIR-V, which is part of the hash used for the
703 * pipeline cache. So it should be safe.
704 */
705 tcs_key.tes_primitive_mode = tes_nir->info.tess.primitive_mode;
706 tcs_key.outputs_written = tcs_nir->info.outputs_written;
707 tcs_key.patch_outputs_written = tcs_nir->info.patch_outputs_written;
708 tcs_key.quads_workaround =
709 devinfo->gen < 9 &&
710 tes_nir->info.tess.primitive_mode == 7 /* GL_QUADS */ &&
711 tes_nir->info.tess.spacing == TESS_SPACING_EQUAL;
712
713 tes_key.inputs_read = tcs_key.outputs_written;
714 tes_key.patch_inputs_read = tcs_key.patch_outputs_written;
715
716 const int shader_time_index = -1;
717 const unsigned *shader_code;
718
719 shader_code =
720 brw_compile_tcs(compiler, NULL, mem_ctx, &tcs_key, &tcs_prog_data,
721 tcs_nir, shader_time_index, NULL);
722 if (shader_code == NULL) {
723 ralloc_free(mem_ctx);
724 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
725 }
726
727 unsigned code_size = tcs_prog_data.base.base.program_size;
728 tcs_bin = anv_pipeline_upload_kernel(pipeline, cache,
729 tcs_sha1, sizeof(tcs_sha1),
730 shader_code, code_size,
731 &tcs_prog_data.base.base,
732 sizeof(tcs_prog_data),
733 &tcs_map);
734 if (!tcs_bin) {
735 ralloc_free(mem_ctx);
736 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
737 }
738
739 shader_code =
740 brw_compile_tes(compiler, NULL, mem_ctx, &tes_key,
741 &tcs_prog_data.base.vue_map, &tes_prog_data, tes_nir,
742 NULL, shader_time_index, NULL);
743 if (shader_code == NULL) {
744 ralloc_free(mem_ctx);
745 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
746 }
747
748 code_size = tes_prog_data.base.base.program_size;
749 tes_bin = anv_pipeline_upload_kernel(pipeline, cache,
750 tes_sha1, sizeof(tes_sha1),
751 shader_code, code_size,
752 &tes_prog_data.base.base,
753 sizeof(tes_prog_data),
754 &tes_map);
755 if (!tes_bin) {
756 ralloc_free(mem_ctx);
757 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
758 }
759
760 ralloc_free(mem_ctx);
761 }
762
763 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_TESS_CTRL, tcs_bin);
764 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_TESS_EVAL, tes_bin);
765
766 return VK_SUCCESS;
767 }
768
769 static VkResult
770 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
771 struct anv_pipeline_cache *cache,
772 const VkGraphicsPipelineCreateInfo *info,
773 struct anv_shader_module *module,
774 const char *entrypoint,
775 const VkSpecializationInfo *spec_info)
776 {
777 const struct brw_compiler *compiler =
778 pipeline->device->instance->physicalDevice.compiler;
779 struct brw_gs_prog_key key;
780 struct anv_shader_bin *bin = NULL;
781 unsigned char sha1[20];
782
783 populate_gs_prog_key(&pipeline->device->info, &key);
784
785 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
786
787 if (cache) {
788 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
789 MESA_SHADER_GEOMETRY, spec_info,
790 &key, sizeof(key), sha1);
791 bin = anv_pipeline_cache_search(cache, sha1, 20);
792 }
793
794 if (bin == NULL) {
795 struct brw_gs_prog_data prog_data = {};
796 struct anv_pipeline_binding surface_to_descriptor[256];
797 struct anv_pipeline_binding sampler_to_descriptor[256];
798
799 struct anv_pipeline_bind_map map = {
800 .surface_to_descriptor = surface_to_descriptor,
801 .sampler_to_descriptor = sampler_to_descriptor
802 };
803
804 void *mem_ctx = ralloc_context(NULL);
805
806 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
807 module, entrypoint,
808 MESA_SHADER_GEOMETRY, spec_info,
809 &prog_data.base.base, &map);
810 if (nir == NULL) {
811 ralloc_free(mem_ctx);
812 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
813 }
814
815 anv_fill_binding_table(&prog_data.base.base, 0);
816
817 brw_compute_vue_map(&pipeline->device->info,
818 &prog_data.base.vue_map,
819 nir->info.outputs_written,
820 nir->info.separate_shader);
821
822 const unsigned *shader_code =
823 brw_compile_gs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
824 NULL, -1, NULL);
825 if (shader_code == NULL) {
826 ralloc_free(mem_ctx);
827 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
828 }
829
830 /* TODO: SIMD8 GS */
831 const unsigned code_size = prog_data.base.base.program_size;
832 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
833 shader_code, code_size,
834 &prog_data.base.base, sizeof(prog_data),
835 &map);
836 if (!bin) {
837 ralloc_free(mem_ctx);
838 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
839 }
840
841 ralloc_free(mem_ctx);
842 }
843
844 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY, bin);
845
846 return VK_SUCCESS;
847 }
848
849 static VkResult
850 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
851 struct anv_pipeline_cache *cache,
852 const VkGraphicsPipelineCreateInfo *info,
853 struct anv_shader_module *module,
854 const char *entrypoint,
855 const VkSpecializationInfo *spec_info)
856 {
857 const struct brw_compiler *compiler =
858 pipeline->device->instance->physicalDevice.compiler;
859 struct brw_wm_prog_key key;
860 struct anv_shader_bin *bin = NULL;
861 unsigned char sha1[20];
862
863 populate_wm_prog_key(pipeline, info, &key);
864
865 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
866
867 if (cache) {
868 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
869 MESA_SHADER_FRAGMENT, spec_info,
870 &key, sizeof(key), sha1);
871 bin = anv_pipeline_cache_search(cache, sha1, 20);
872 }
873
874 if (bin == NULL) {
875 struct brw_wm_prog_data prog_data = {};
876 struct anv_pipeline_binding surface_to_descriptor[256];
877 struct anv_pipeline_binding sampler_to_descriptor[256];
878
879 struct anv_pipeline_bind_map map = {
880 .surface_to_descriptor = surface_to_descriptor + 8,
881 .sampler_to_descriptor = sampler_to_descriptor
882 };
883
884 void *mem_ctx = ralloc_context(NULL);
885
886 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
887 module, entrypoint,
888 MESA_SHADER_FRAGMENT, spec_info,
889 &prog_data.base, &map);
890 if (nir == NULL) {
891 ralloc_free(mem_ctx);
892 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
893 }
894
895 unsigned num_rts = 0;
896 const int max_rt = FRAG_RESULT_DATA7 - FRAG_RESULT_DATA0 + 1;
897 struct anv_pipeline_binding rt_bindings[max_rt];
898 nir_function_impl *impl = nir_shader_get_entrypoint(nir);
899 int rt_to_bindings[max_rt];
900 memset(rt_to_bindings, -1, sizeof(rt_to_bindings));
901 bool rt_used[max_rt];
902 memset(rt_used, 0, sizeof(rt_used));
903
904 /* Flag used render targets */
905 nir_foreach_variable_safe(var, &nir->outputs) {
906 if (var->data.location < FRAG_RESULT_DATA0)
907 continue;
908
909 const unsigned rt = var->data.location - FRAG_RESULT_DATA0;
910 /* Out-of-bounds */
911 if (rt >= key.nr_color_regions)
912 continue;
913
914 const unsigned array_len =
915 glsl_type_is_array(var->type) ? glsl_get_length(var->type) : 1;
916 assert(rt + array_len <= max_rt);
917
918 for (unsigned i = 0; i < array_len; i++)
919 rt_used[rt + i] = true;
920 }
921
922 /* Set new, compacted, location */
923 for (unsigned i = 0; i < max_rt; i++) {
924 if (!rt_used[i])
925 continue;
926
927 rt_to_bindings[i] = num_rts;
928 rt_bindings[rt_to_bindings[i]] = (struct anv_pipeline_binding) {
929 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
930 .binding = 0,
931 .index = i,
932 };
933 num_rts++;
934 }
935
936 nir_foreach_variable_safe(var, &nir->outputs) {
937 if (var->data.location < FRAG_RESULT_DATA0)
938 continue;
939
940 const unsigned rt = var->data.location - FRAG_RESULT_DATA0;
941 if (rt >= key.nr_color_regions) {
942 /* Out-of-bounds, throw it away */
943 var->data.mode = nir_var_local;
944 exec_node_remove(&var->node);
945 exec_list_push_tail(&impl->locals, &var->node);
946 continue;
947 }
948
949 /* Give it the new location */
950 assert(rt_to_bindings[rt] != -1);
951 var->data.location = rt_to_bindings[rt] + FRAG_RESULT_DATA0;
952 }
953
954 if (num_rts == 0) {
955 /* If we have no render targets, we need a null render target */
956 rt_bindings[0] = (struct anv_pipeline_binding) {
957 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
958 .binding = 0,
959 .index = UINT32_MAX,
960 };
961 num_rts = 1;
962 }
963
964 assert(num_rts <= max_rt);
965 map.surface_to_descriptor -= num_rts;
966 map.surface_count += num_rts;
967 assert(map.surface_count <= 256);
968 memcpy(map.surface_to_descriptor, rt_bindings,
969 num_rts * sizeof(*rt_bindings));
970
971 anv_fill_binding_table(&prog_data.base, num_rts);
972
973 const unsigned *shader_code =
974 brw_compile_fs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
975 NULL, -1, -1, true, false, NULL, NULL);
976 if (shader_code == NULL) {
977 ralloc_free(mem_ctx);
978 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
979 }
980
981 unsigned code_size = prog_data.base.program_size;
982 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
983 shader_code, code_size,
984 &prog_data.base, sizeof(prog_data),
985 &map);
986 if (!bin) {
987 ralloc_free(mem_ctx);
988 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
989 }
990
991 ralloc_free(mem_ctx);
992 }
993
994 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT, bin);
995
996 return VK_SUCCESS;
997 }
998
999 VkResult
1000 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
1001 struct anv_pipeline_cache *cache,
1002 const VkComputePipelineCreateInfo *info,
1003 struct anv_shader_module *module,
1004 const char *entrypoint,
1005 const VkSpecializationInfo *spec_info)
1006 {
1007 const struct brw_compiler *compiler =
1008 pipeline->device->instance->physicalDevice.compiler;
1009 struct brw_cs_prog_key key;
1010 struct anv_shader_bin *bin = NULL;
1011 unsigned char sha1[20];
1012
1013 populate_cs_prog_key(&pipeline->device->info, &key);
1014
1015 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
1016
1017 if (cache) {
1018 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
1019 MESA_SHADER_COMPUTE, spec_info,
1020 &key, sizeof(key), sha1);
1021 bin = anv_pipeline_cache_search(cache, sha1, 20);
1022 }
1023
1024 if (bin == NULL) {
1025 struct brw_cs_prog_data prog_data = {};
1026 struct anv_pipeline_binding surface_to_descriptor[256];
1027 struct anv_pipeline_binding sampler_to_descriptor[256];
1028
1029 struct anv_pipeline_bind_map map = {
1030 .surface_to_descriptor = surface_to_descriptor,
1031 .sampler_to_descriptor = sampler_to_descriptor
1032 };
1033
1034 void *mem_ctx = ralloc_context(NULL);
1035
1036 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
1037 module, entrypoint,
1038 MESA_SHADER_COMPUTE, spec_info,
1039 &prog_data.base, &map);
1040 if (nir == NULL) {
1041 ralloc_free(mem_ctx);
1042 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1043 }
1044
1045 NIR_PASS_V(nir, anv_nir_add_base_work_group_id, &prog_data);
1046
1047 anv_fill_binding_table(&prog_data.base, 1);
1048
1049 const unsigned *shader_code =
1050 brw_compile_cs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
1051 -1, NULL);
1052 if (shader_code == NULL) {
1053 ralloc_free(mem_ctx);
1054 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1055 }
1056
1057 const unsigned code_size = prog_data.base.program_size;
1058 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
1059 shader_code, code_size,
1060 &prog_data.base, sizeof(prog_data),
1061 &map);
1062 if (!bin) {
1063 ralloc_free(mem_ctx);
1064 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1065 }
1066
1067 ralloc_free(mem_ctx);
1068 }
1069
1070 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE, bin);
1071
1072 return VK_SUCCESS;
1073 }
1074
1075 /**
1076 * Copy pipeline state not marked as dynamic.
1077 * Dynamic state is pipeline state which hasn't been provided at pipeline
1078 * creation time, but is dynamically provided afterwards using various
1079 * vkCmdSet* functions.
1080 *
1081 * The set of state considered "non_dynamic" is determined by the pieces of
1082 * state that have their corresponding VkDynamicState enums omitted from
1083 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1084 *
1085 * @param[out] pipeline Destination non_dynamic state.
1086 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1087 */
1088 static void
1089 copy_non_dynamic_state(struct anv_pipeline *pipeline,
1090 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1091 {
1092 anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
1093 struct anv_subpass *subpass = pipeline->subpass;
1094
1095 pipeline->dynamic_state = default_dynamic_state;
1096
1097 if (pCreateInfo->pDynamicState) {
1098 /* Remove all of the states that are marked as dynamic */
1099 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1100 for (uint32_t s = 0; s < count; s++)
1101 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1102 }
1103
1104 struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
1105
1106 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1107 *
1108 * pViewportState is [...] NULL if the pipeline
1109 * has rasterization disabled.
1110 */
1111 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1112 assert(pCreateInfo->pViewportState);
1113
1114 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1115 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1116 typed_memcpy(dynamic->viewport.viewports,
1117 pCreateInfo->pViewportState->pViewports,
1118 pCreateInfo->pViewportState->viewportCount);
1119 }
1120
1121 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1122 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1123 typed_memcpy(dynamic->scissor.scissors,
1124 pCreateInfo->pViewportState->pScissors,
1125 pCreateInfo->pViewportState->scissorCount);
1126 }
1127 }
1128
1129 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1130 assert(pCreateInfo->pRasterizationState);
1131 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1132 }
1133
1134 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1135 assert(pCreateInfo->pRasterizationState);
1136 dynamic->depth_bias.bias =
1137 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1138 dynamic->depth_bias.clamp =
1139 pCreateInfo->pRasterizationState->depthBiasClamp;
1140 dynamic->depth_bias.slope =
1141 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1142 }
1143
1144 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1145 *
1146 * pColorBlendState is [...] NULL if the pipeline has rasterization
1147 * disabled or if the subpass of the render pass the pipeline is
1148 * created against does not use any color attachments.
1149 */
1150 bool uses_color_att = false;
1151 for (unsigned i = 0; i < subpass->color_count; ++i) {
1152 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1153 uses_color_att = true;
1154 break;
1155 }
1156 }
1157
1158 if (uses_color_att &&
1159 !pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1160 assert(pCreateInfo->pColorBlendState);
1161
1162 if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
1163 typed_memcpy(dynamic->blend_constants,
1164 pCreateInfo->pColorBlendState->blendConstants, 4);
1165 }
1166
1167 /* If there is no depthstencil attachment, then don't read
1168 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1169 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1170 * no need to override the depthstencil defaults in
1171 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1172 *
1173 * Section 9.2 of the Vulkan 1.0.15 spec says:
1174 *
1175 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1176 * disabled or if the subpass of the render pass the pipeline is created
1177 * against does not use a depth/stencil attachment.
1178 */
1179 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1180 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1181 assert(pCreateInfo->pDepthStencilState);
1182
1183 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1184 dynamic->depth_bounds.min =
1185 pCreateInfo->pDepthStencilState->minDepthBounds;
1186 dynamic->depth_bounds.max =
1187 pCreateInfo->pDepthStencilState->maxDepthBounds;
1188 }
1189
1190 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1191 dynamic->stencil_compare_mask.front =
1192 pCreateInfo->pDepthStencilState->front.compareMask;
1193 dynamic->stencil_compare_mask.back =
1194 pCreateInfo->pDepthStencilState->back.compareMask;
1195 }
1196
1197 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1198 dynamic->stencil_write_mask.front =
1199 pCreateInfo->pDepthStencilState->front.writeMask;
1200 dynamic->stencil_write_mask.back =
1201 pCreateInfo->pDepthStencilState->back.writeMask;
1202 }
1203
1204 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1205 dynamic->stencil_reference.front =
1206 pCreateInfo->pDepthStencilState->front.reference;
1207 dynamic->stencil_reference.back =
1208 pCreateInfo->pDepthStencilState->back.reference;
1209 }
1210 }
1211
1212 pipeline->dynamic_state_mask = states;
1213 }
1214
1215 static void
1216 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
1217 {
1218 #ifdef DEBUG
1219 struct anv_render_pass *renderpass = NULL;
1220 struct anv_subpass *subpass = NULL;
1221
1222 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1223 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1224 */
1225 assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
1226
1227 renderpass = anv_render_pass_from_handle(info->renderPass);
1228 assert(renderpass);
1229
1230 assert(info->subpass < renderpass->subpass_count);
1231 subpass = &renderpass->subpasses[info->subpass];
1232
1233 assert(info->stageCount >= 1);
1234 assert(info->pVertexInputState);
1235 assert(info->pInputAssemblyState);
1236 assert(info->pRasterizationState);
1237 if (!info->pRasterizationState->rasterizerDiscardEnable) {
1238 assert(info->pViewportState);
1239 assert(info->pMultisampleState);
1240
1241 if (subpass && subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
1242 assert(info->pDepthStencilState);
1243
1244 if (subpass && subpass->color_count > 0)
1245 assert(info->pColorBlendState);
1246 }
1247
1248 for (uint32_t i = 0; i < info->stageCount; ++i) {
1249 switch (info->pStages[i].stage) {
1250 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
1251 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
1252 assert(info->pTessellationState);
1253 break;
1254 default:
1255 break;
1256 }
1257 }
1258 #endif
1259 }
1260
1261 /**
1262 * Calculate the desired L3 partitioning based on the current state of the
1263 * pipeline. For now this simply returns the conservative defaults calculated
1264 * by get_default_l3_weights(), but we could probably do better by gathering
1265 * more statistics from the pipeline state (e.g. guess of expected URB usage
1266 * and bound surfaces), or by using feed-back from performance counters.
1267 */
1268 void
1269 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm)
1270 {
1271 const struct gen_device_info *devinfo = &pipeline->device->info;
1272
1273 const struct gen_l3_weights w =
1274 gen_get_default_l3_weights(devinfo, pipeline->needs_data_cache, needs_slm);
1275
1276 pipeline->urb.l3_config = gen_get_l3_config(devinfo, w);
1277 pipeline->urb.total_size =
1278 gen_get_l3_config_urb_size(devinfo, pipeline->urb.l3_config);
1279 }
1280
1281 VkResult
1282 anv_pipeline_init(struct anv_pipeline *pipeline,
1283 struct anv_device *device,
1284 struct anv_pipeline_cache *cache,
1285 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1286 const VkAllocationCallbacks *alloc)
1287 {
1288 VkResult result;
1289
1290 anv_pipeline_validate_create_info(pCreateInfo);
1291
1292 if (alloc == NULL)
1293 alloc = &device->alloc;
1294
1295 pipeline->device = device;
1296
1297 ANV_FROM_HANDLE(anv_render_pass, render_pass, pCreateInfo->renderPass);
1298 assert(pCreateInfo->subpass < render_pass->subpass_count);
1299 pipeline->subpass = &render_pass->subpasses[pCreateInfo->subpass];
1300
1301 result = anv_reloc_list_init(&pipeline->batch_relocs, alloc);
1302 if (result != VK_SUCCESS)
1303 return result;
1304
1305 pipeline->batch.alloc = alloc;
1306 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
1307 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
1308 pipeline->batch.relocs = &pipeline->batch_relocs;
1309 pipeline->batch.status = VK_SUCCESS;
1310
1311 copy_non_dynamic_state(pipeline, pCreateInfo);
1312 pipeline->depth_clamp_enable = pCreateInfo->pRasterizationState &&
1313 pCreateInfo->pRasterizationState->depthClampEnable;
1314
1315 pipeline->sample_shading_enable = pCreateInfo->pMultisampleState &&
1316 pCreateInfo->pMultisampleState->sampleShadingEnable;
1317
1318 pipeline->needs_data_cache = false;
1319
1320 /* When we free the pipeline, we detect stages based on the NULL status
1321 * of various prog_data pointers. Make them NULL by default.
1322 */
1323 memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
1324
1325 pipeline->active_stages = 0;
1326
1327 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = {};
1328 struct anv_shader_module *modules[MESA_SHADER_STAGES] = {};
1329 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1330 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1331 pStages[stage] = &pCreateInfo->pStages[i];
1332 modules[stage] = anv_shader_module_from_handle(pStages[stage]->module);
1333 }
1334
1335 if (modules[MESA_SHADER_VERTEX]) {
1336 result = anv_pipeline_compile_vs(pipeline, cache, pCreateInfo,
1337 modules[MESA_SHADER_VERTEX],
1338 pStages[MESA_SHADER_VERTEX]->pName,
1339 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo);
1340 if (result != VK_SUCCESS)
1341 goto compile_fail;
1342 }
1343
1344 if (modules[MESA_SHADER_TESS_EVAL]) {
1345 anv_pipeline_compile_tcs_tes(pipeline, cache, pCreateInfo,
1346 modules[MESA_SHADER_TESS_CTRL],
1347 pStages[MESA_SHADER_TESS_CTRL]->pName,
1348 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
1349 modules[MESA_SHADER_TESS_EVAL],
1350 pStages[MESA_SHADER_TESS_EVAL]->pName,
1351 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo);
1352 }
1353
1354 if (modules[MESA_SHADER_GEOMETRY]) {
1355 result = anv_pipeline_compile_gs(pipeline, cache, pCreateInfo,
1356 modules[MESA_SHADER_GEOMETRY],
1357 pStages[MESA_SHADER_GEOMETRY]->pName,
1358 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo);
1359 if (result != VK_SUCCESS)
1360 goto compile_fail;
1361 }
1362
1363 if (modules[MESA_SHADER_FRAGMENT]) {
1364 result = anv_pipeline_compile_fs(pipeline, cache, pCreateInfo,
1365 modules[MESA_SHADER_FRAGMENT],
1366 pStages[MESA_SHADER_FRAGMENT]->pName,
1367 pStages[MESA_SHADER_FRAGMENT]->pSpecializationInfo);
1368 if (result != VK_SUCCESS)
1369 goto compile_fail;
1370 }
1371
1372 assert(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT);
1373
1374 anv_pipeline_setup_l3_config(pipeline, false);
1375
1376 const VkPipelineVertexInputStateCreateInfo *vi_info =
1377 pCreateInfo->pVertexInputState;
1378
1379 const uint64_t inputs_read = get_vs_prog_data(pipeline)->inputs_read;
1380
1381 pipeline->vb_used = 0;
1382 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1383 const VkVertexInputAttributeDescription *desc =
1384 &vi_info->pVertexAttributeDescriptions[i];
1385
1386 if (inputs_read & (1ull << (VERT_ATTRIB_GENERIC0 + desc->location)))
1387 pipeline->vb_used |= 1 << desc->binding;
1388 }
1389
1390 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1391 const VkVertexInputBindingDescription *desc =
1392 &vi_info->pVertexBindingDescriptions[i];
1393
1394 pipeline->binding_stride[desc->binding] = desc->stride;
1395
1396 /* Step rate is programmed per vertex element (attribute), not
1397 * binding. Set up a map of which bindings step per instance, for
1398 * reference by vertex element setup. */
1399 switch (desc->inputRate) {
1400 default:
1401 case VK_VERTEX_INPUT_RATE_VERTEX:
1402 pipeline->instancing_enable[desc->binding] = false;
1403 break;
1404 case VK_VERTEX_INPUT_RATE_INSTANCE:
1405 pipeline->instancing_enable[desc->binding] = true;
1406 break;
1407 }
1408 }
1409
1410 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1411 pCreateInfo->pInputAssemblyState;
1412 const VkPipelineTessellationStateCreateInfo *tess_info =
1413 pCreateInfo->pTessellationState;
1414 pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1415
1416 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
1417 pipeline->topology = _3DPRIM_PATCHLIST(tess_info->patchControlPoints);
1418 else
1419 pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1420
1421 return VK_SUCCESS;
1422
1423 compile_fail:
1424 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
1425 if (pipeline->shaders[s])
1426 anv_shader_bin_unref(device, pipeline->shaders[s]);
1427 }
1428
1429 anv_reloc_list_finish(&pipeline->batch_relocs, alloc);
1430
1431 return result;
1432 }