2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "util/os_time.h"
32 #include "common/gen_l3_config.h"
33 #include "anv_private.h"
34 #include "compiler/brw_nir.h"
36 #include "nir/nir_xfb_info.h"
37 #include "spirv/nir_spirv.h"
40 /* Needed for SWIZZLE macros */
41 #include "program/prog_instruction.h"
45 VkResult
anv_CreateShaderModule(
47 const VkShaderModuleCreateInfo
* pCreateInfo
,
48 const VkAllocationCallbacks
* pAllocator
,
49 VkShaderModule
* pShaderModule
)
51 ANV_FROM_HANDLE(anv_device
, device
, _device
);
52 struct anv_shader_module
*module
;
54 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
55 assert(pCreateInfo
->flags
== 0);
57 module
= vk_alloc2(&device
->alloc
, pAllocator
,
58 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
59 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
61 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
63 module
->size
= pCreateInfo
->codeSize
;
64 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
66 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
68 *pShaderModule
= anv_shader_module_to_handle(module
);
73 void anv_DestroyShaderModule(
75 VkShaderModule _module
,
76 const VkAllocationCallbacks
* pAllocator
)
78 ANV_FROM_HANDLE(anv_device
, device
, _device
);
79 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
84 vk_free2(&device
->alloc
, pAllocator
, module
);
87 #define SPIR_V_MAGIC_NUMBER 0x07230203
89 static const uint64_t stage_to_debug
[] = {
90 [MESA_SHADER_VERTEX
] = DEBUG_VS
,
91 [MESA_SHADER_TESS_CTRL
] = DEBUG_TCS
,
92 [MESA_SHADER_TESS_EVAL
] = DEBUG_TES
,
93 [MESA_SHADER_GEOMETRY
] = DEBUG_GS
,
94 [MESA_SHADER_FRAGMENT
] = DEBUG_WM
,
95 [MESA_SHADER_COMPUTE
] = DEBUG_CS
,
98 struct anv_spirv_debug_data
{
99 struct anv_device
*device
;
100 const struct anv_shader_module
*module
;
103 static void anv_spirv_nir_debug(void *private_data
,
104 enum nir_spirv_debug_level level
,
108 struct anv_spirv_debug_data
*debug_data
= private_data
;
109 static const VkDebugReportFlagsEXT vk_flags
[] = {
110 [NIR_SPIRV_DEBUG_LEVEL_INFO
] = VK_DEBUG_REPORT_INFORMATION_BIT_EXT
,
111 [NIR_SPIRV_DEBUG_LEVEL_WARNING
] = VK_DEBUG_REPORT_WARNING_BIT_EXT
,
112 [NIR_SPIRV_DEBUG_LEVEL_ERROR
] = VK_DEBUG_REPORT_ERROR_BIT_EXT
,
116 snprintf(buffer
, sizeof(buffer
), "SPIR-V offset %lu: %s", (unsigned long) spirv_offset
, message
);
118 vk_debug_report(&debug_data
->device
->instance
->debug_report_callbacks
,
120 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT
,
121 (uint64_t) (uintptr_t) debug_data
->module
,
122 0, 0, "anv", buffer
);
125 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
126 * we can't do that yet because we don't have the ability to copy nir.
129 anv_shader_compile_to_nir(struct anv_device
*device
,
131 const struct anv_shader_module
*module
,
132 const char *entrypoint_name
,
133 gl_shader_stage stage
,
134 const VkSpecializationInfo
*spec_info
)
136 const struct anv_physical_device
*pdevice
=
137 &device
->instance
->physicalDevice
;
138 const struct brw_compiler
*compiler
= pdevice
->compiler
;
139 const nir_shader_compiler_options
*nir_options
=
140 compiler
->glsl_compiler_options
[stage
].NirOptions
;
142 uint32_t *spirv
= (uint32_t *) module
->data
;
143 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
144 assert(module
->size
% 4 == 0);
146 uint32_t num_spec_entries
= 0;
147 struct nir_spirv_specialization
*spec_entries
= NULL
;
148 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
149 num_spec_entries
= spec_info
->mapEntryCount
;
150 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
151 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
152 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
153 const void *data
= spec_info
->pData
+ entry
.offset
;
154 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
156 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
157 if (spec_info
->dataSize
== 8)
158 spec_entries
[i
].data64
= *(const uint64_t *)data
;
160 spec_entries
[i
].data32
= *(const uint32_t *)data
;
164 struct anv_spirv_debug_data spirv_debug_data
= {
168 struct spirv_to_nir_options spirv_options
= {
169 .frag_coord_is_sysval
= true,
171 .demote_to_helper_invocation
= true,
172 .derivative_group
= true,
173 .descriptor_array_dynamic_indexing
= true,
174 .descriptor_array_non_uniform_indexing
= true,
175 .descriptor_indexing
= true,
176 .device_group
= true,
177 .draw_parameters
= true,
178 .float16
= pdevice
->info
.gen
>= 8,
179 .float64
= pdevice
->info
.gen
>= 8,
180 .fragment_shader_sample_interlock
= pdevice
->info
.gen
>= 9,
181 .fragment_shader_pixel_interlock
= pdevice
->info
.gen
>= 9,
182 .geometry_streams
= true,
183 .image_write_without_format
= true,
184 .int8
= pdevice
->info
.gen
>= 8,
185 .int16
= pdevice
->info
.gen
>= 8,
186 .int64
= pdevice
->info
.gen
>= 8,
187 .int64_atomics
= pdevice
->info
.gen
>= 9 && pdevice
->use_softpin
,
190 .physical_storage_buffer_address
= pdevice
->has_a64_buffer_access
,
191 .post_depth_coverage
= pdevice
->info
.gen
>= 9,
192 .runtime_descriptor_array
= true,
193 .shader_viewport_index_layer
= true,
194 .stencil_export
= pdevice
->info
.gen
>= 9,
195 .storage_8bit
= pdevice
->info
.gen
>= 8,
196 .storage_16bit
= pdevice
->info
.gen
>= 8,
197 .subgroup_arithmetic
= true,
198 .subgroup_basic
= true,
199 .subgroup_ballot
= true,
200 .subgroup_quad
= true,
201 .subgroup_shuffle
= true,
202 .subgroup_vote
= true,
203 .tessellation
= true,
204 .transform_feedback
= pdevice
->info
.gen
>= 8,
205 .variable_pointers
= true,
207 .ubo_addr_format
= nir_address_format_32bit_index_offset
,
209 anv_nir_ssbo_addr_format(pdevice
, device
->robust_buffer_access
),
210 .phys_ssbo_addr_format
= nir_address_format_64bit_global
,
211 .push_const_addr_format
= nir_address_format_logical
,
213 /* TODO: Consider changing this to an address format that has the NULL
214 * pointer equals to 0. That might be a better format to play nice
215 * with certain code / code generators.
217 .shared_addr_format
= nir_address_format_32bit_offset
,
219 .func
= anv_spirv_nir_debug
,
220 .private_data
= &spirv_debug_data
,
226 spirv_to_nir(spirv
, module
->size
/ 4,
227 spec_entries
, num_spec_entries
,
228 stage
, entrypoint_name
, &spirv_options
, nir_options
);
229 assert(nir
->info
.stage
== stage
);
230 nir_validate_shader(nir
, "after spirv_to_nir");
231 ralloc_steal(mem_ctx
, nir
);
235 if (unlikely(INTEL_DEBUG
& stage_to_debug
[stage
])) {
236 fprintf(stderr
, "NIR (from SPIR-V) for %s shader:\n",
237 gl_shader_stage_name(stage
));
238 nir_print_shader(nir
, stderr
);
241 /* We have to lower away local constant initializers right before we
242 * inline functions. That way they get properly initialized at the top
243 * of the function and not at the top of its caller.
245 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_function_temp
);
246 NIR_PASS_V(nir
, nir_lower_returns
);
247 NIR_PASS_V(nir
, nir_inline_functions
);
248 NIR_PASS_V(nir
, nir_opt_deref
);
250 /* Pick off the single entrypoint that we want */
251 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
252 if (!func
->is_entrypoint
)
253 exec_node_remove(&func
->node
);
255 assert(exec_list_length(&nir
->functions
) == 1);
257 /* Now that we've deleted all but the main function, we can go ahead and
258 * lower the rest of the constant initializers. We do this here so that
259 * nir_remove_dead_variables and split_per_member_structs below see the
260 * corresponding stores.
262 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
264 /* Split member structs. We do this before lower_io_to_temporaries so that
265 * it doesn't lower system values to temporaries by accident.
267 NIR_PASS_V(nir
, nir_split_var_copies
);
268 NIR_PASS_V(nir
, nir_split_per_member_structs
);
270 NIR_PASS_V(nir
, nir_remove_dead_variables
,
271 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
273 NIR_PASS_V(nir
, nir_propagate_invariant
);
274 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
275 nir_shader_get_entrypoint(nir
), true, false);
277 NIR_PASS_V(nir
, nir_lower_frexp
);
279 /* Vulkan uses the separate-shader linking model */
280 nir
->info
.separate_shader
= true;
282 brw_preprocess_nir(compiler
, nir
, NULL
);
287 void anv_DestroyPipeline(
289 VkPipeline _pipeline
,
290 const VkAllocationCallbacks
* pAllocator
)
292 ANV_FROM_HANDLE(anv_device
, device
, _device
);
293 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
298 anv_reloc_list_finish(&pipeline
->batch_relocs
,
299 pAllocator
? pAllocator
: &device
->alloc
);
301 ralloc_free(pipeline
->mem_ctx
);
303 if (pipeline
->blend_state
.map
)
304 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
306 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
307 if (pipeline
->shaders
[s
])
308 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
311 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
314 static const uint32_t vk_to_gen_primitive_type
[] = {
315 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
316 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
317 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
318 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
319 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
320 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
321 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
322 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
323 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
324 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
328 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
329 struct brw_sampler_prog_key_data
*key
)
331 /* Almost all multisampled textures are compressed. The only time when we
332 * don't compress a multisampled texture is for 16x MSAA with a surface
333 * width greater than 8k which is a bit of an edge case. Since the sampler
334 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
335 * to tell the compiler to always assume compression.
337 key
->compressed_multisample_layout_mask
= ~0;
339 /* SkyLake added support for 16x MSAA. With this came a new message for
340 * reading from a 16x MSAA surface with compression. The new message was
341 * needed because now the MCS data is 64 bits instead of 32 or lower as is
342 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
343 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
344 * so we can just use it unconditionally. This may not be quite as
345 * efficient but it saves us from recompiling.
347 if (devinfo
->gen
>= 9)
350 /* XXX: Handle texture swizzle on HSW- */
351 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
352 /* Assume color sampler, no swizzling. (Works for BDW+) */
353 key
->swizzles
[i
] = SWIZZLE_XYZW
;
358 populate_base_prog_key(const struct gen_device_info
*devinfo
,
359 VkPipelineShaderStageCreateFlags flags
,
360 struct brw_base_prog_key
*key
)
362 if (flags
& VK_PIPELINE_SHADER_STAGE_CREATE_ALLOW_VARYING_SUBGROUP_SIZE_BIT_EXT
)
363 key
->subgroup_size_type
= BRW_SUBGROUP_SIZE_VARYING
;
365 key
->subgroup_size_type
= BRW_SUBGROUP_SIZE_API_CONSTANT
;
367 populate_sampler_prog_key(devinfo
, &key
->tex
);
371 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
372 VkPipelineShaderStageCreateFlags flags
,
373 struct brw_vs_prog_key
*key
)
375 memset(key
, 0, sizeof(*key
));
377 populate_base_prog_key(devinfo
, flags
, &key
->base
);
379 /* XXX: Handle vertex input work-arounds */
381 /* XXX: Handle sampler_prog_key */
385 populate_tcs_prog_key(const struct gen_device_info
*devinfo
,
386 VkPipelineShaderStageCreateFlags flags
,
387 unsigned input_vertices
,
388 struct brw_tcs_prog_key
*key
)
390 memset(key
, 0, sizeof(*key
));
392 populate_base_prog_key(devinfo
, flags
, &key
->base
);
394 key
->input_vertices
= input_vertices
;
398 populate_tes_prog_key(const struct gen_device_info
*devinfo
,
399 VkPipelineShaderStageCreateFlags flags
,
400 struct brw_tes_prog_key
*key
)
402 memset(key
, 0, sizeof(*key
));
404 populate_base_prog_key(devinfo
, flags
, &key
->base
);
408 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
409 VkPipelineShaderStageCreateFlags flags
,
410 struct brw_gs_prog_key
*key
)
412 memset(key
, 0, sizeof(*key
));
414 populate_base_prog_key(devinfo
, flags
, &key
->base
);
418 populate_wm_prog_key(const struct gen_device_info
*devinfo
,
419 VkPipelineShaderStageCreateFlags flags
,
420 const struct anv_subpass
*subpass
,
421 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
422 struct brw_wm_prog_key
*key
)
424 memset(key
, 0, sizeof(*key
));
426 populate_base_prog_key(devinfo
, flags
, &key
->base
);
428 /* We set this to 0 here and set to the actual value before we call
431 key
->input_slots_valid
= 0;
433 /* Vulkan doesn't specify a default */
434 key
->high_quality_derivatives
= false;
436 /* XXX Vulkan doesn't appear to specify */
437 key
->clamp_fragment_color
= false;
439 assert(subpass
->color_count
<= MAX_RTS
);
440 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
441 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
442 key
->color_outputs_valid
|= (1 << i
);
445 key
->nr_color_regions
= util_bitcount(key
->color_outputs_valid
);
447 /* To reduce possible shader recompilations we would need to know if
448 * there is a SampleMask output variable to compute if we should emit
449 * code to workaround the issue that hardware disables alpha to coverage
450 * when there is SampleMask output.
452 key
->alpha_to_coverage
= ms_info
&& ms_info
->alphaToCoverageEnable
;
454 /* Vulkan doesn't support fixed-function alpha test */
455 key
->alpha_test_replicate_alpha
= false;
458 /* We should probably pull this out of the shader, but it's fairly
459 * harmless to compute it and then let dead-code take care of it.
461 if (ms_info
->rasterizationSamples
> 1) {
462 key
->persample_interp
= ms_info
->sampleShadingEnable
&&
463 (ms_info
->minSampleShading
* ms_info
->rasterizationSamples
) > 1;
464 key
->multisample_fbo
= true;
467 key
->frag_coord_adds_sample_pos
= key
->persample_interp
;
472 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
473 VkPipelineShaderStageCreateFlags flags
,
474 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*rss_info
,
475 struct brw_cs_prog_key
*key
)
477 memset(key
, 0, sizeof(*key
));
479 populate_base_prog_key(devinfo
, flags
, &key
->base
);
482 assert(key
->base
.subgroup_size_type
!= BRW_SUBGROUP_SIZE_VARYING
);
484 /* These enum values are expressly chosen to be equal to the subgroup
485 * size that they require.
487 assert(rss_info
->requiredSubgroupSize
== 8 ||
488 rss_info
->requiredSubgroupSize
== 16 ||
489 rss_info
->requiredSubgroupSize
== 32);
490 key
->base
.subgroup_size_type
= rss_info
->requiredSubgroupSize
;
491 } else if (flags
& VK_PIPELINE_SHADER_STAGE_CREATE_REQUIRE_FULL_SUBGROUPS_BIT_EXT
) {
492 /* If the client expressly requests full subgroups and they don't
493 * specify a subgroup size, we need to pick one. If they're requested
494 * varying subgroup sizes, we set it to UNIFORM and let the back-end
495 * compiler pick. Otherwise, we specify the API value of 32.
496 * Performance will likely be terrible in this case but there's nothing
497 * we can do about that. The client should have chosen a size.
499 if (flags
& VK_PIPELINE_SHADER_STAGE_CREATE_ALLOW_VARYING_SUBGROUP_SIZE_BIT_EXT
)
500 key
->base
.subgroup_size_type
= BRW_SUBGROUP_SIZE_UNIFORM
;
502 key
->base
.subgroup_size_type
= BRW_SUBGROUP_SIZE_REQUIRE_32
;
506 struct anv_pipeline_stage
{
507 gl_shader_stage stage
;
509 const struct anv_shader_module
*module
;
510 const char *entrypoint
;
511 const VkSpecializationInfo
*spec_info
;
513 unsigned char shader_sha1
[20];
515 union brw_any_prog_key key
;
518 gl_shader_stage stage
;
519 unsigned char sha1
[20];
524 struct anv_pipeline_binding surface_to_descriptor
[256];
525 struct anv_pipeline_binding sampler_to_descriptor
[256];
526 struct anv_pipeline_bind_map bind_map
;
528 union brw_any_prog_data prog_data
;
531 struct brw_compile_stats stats
[3];
533 VkPipelineCreationFeedbackEXT feedback
;
535 const unsigned *code
;
539 anv_pipeline_hash_shader(const struct anv_shader_module
*module
,
540 const char *entrypoint
,
541 gl_shader_stage stage
,
542 const VkSpecializationInfo
*spec_info
,
543 unsigned char *sha1_out
)
545 struct mesa_sha1 ctx
;
546 _mesa_sha1_init(&ctx
);
548 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
549 _mesa_sha1_update(&ctx
, entrypoint
, strlen(entrypoint
));
550 _mesa_sha1_update(&ctx
, &stage
, sizeof(stage
));
552 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
553 spec_info
->mapEntryCount
*
554 sizeof(*spec_info
->pMapEntries
));
555 _mesa_sha1_update(&ctx
, spec_info
->pData
,
556 spec_info
->dataSize
);
559 _mesa_sha1_final(&ctx
, sha1_out
);
563 anv_pipeline_hash_graphics(struct anv_pipeline
*pipeline
,
564 struct anv_pipeline_layout
*layout
,
565 struct anv_pipeline_stage
*stages
,
566 unsigned char *sha1_out
)
568 struct mesa_sha1 ctx
;
569 _mesa_sha1_init(&ctx
);
571 _mesa_sha1_update(&ctx
, &pipeline
->subpass
->view_mask
,
572 sizeof(pipeline
->subpass
->view_mask
));
575 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
577 const bool rba
= pipeline
->device
->robust_buffer_access
;
578 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
580 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
581 if (stages
[s
].entrypoint
) {
582 _mesa_sha1_update(&ctx
, stages
[s
].shader_sha1
,
583 sizeof(stages
[s
].shader_sha1
));
584 _mesa_sha1_update(&ctx
, &stages
[s
].key
, brw_prog_key_size(s
));
588 _mesa_sha1_final(&ctx
, sha1_out
);
592 anv_pipeline_hash_compute(struct anv_pipeline
*pipeline
,
593 struct anv_pipeline_layout
*layout
,
594 struct anv_pipeline_stage
*stage
,
595 unsigned char *sha1_out
)
597 struct mesa_sha1 ctx
;
598 _mesa_sha1_init(&ctx
);
601 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
603 const bool rba
= pipeline
->device
->robust_buffer_access
;
604 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
606 _mesa_sha1_update(&ctx
, stage
->shader_sha1
,
607 sizeof(stage
->shader_sha1
));
608 _mesa_sha1_update(&ctx
, &stage
->key
.cs
, sizeof(stage
->key
.cs
));
610 _mesa_sha1_final(&ctx
, sha1_out
);
614 anv_pipeline_stage_get_nir(struct anv_pipeline
*pipeline
,
615 struct anv_pipeline_cache
*cache
,
617 struct anv_pipeline_stage
*stage
)
619 const struct brw_compiler
*compiler
=
620 pipeline
->device
->instance
->physicalDevice
.compiler
;
621 const nir_shader_compiler_options
*nir_options
=
622 compiler
->glsl_compiler_options
[stage
->stage
].NirOptions
;
625 nir
= anv_device_search_for_nir(pipeline
->device
, cache
,
630 assert(nir
->info
.stage
== stage
->stage
);
634 nir
= anv_shader_compile_to_nir(pipeline
->device
,
641 anv_device_upload_nir(pipeline
->device
, cache
, nir
, stage
->shader_sha1
);
649 anv_pipeline_lower_nir(struct anv_pipeline
*pipeline
,
651 struct anv_pipeline_stage
*stage
,
652 struct anv_pipeline_layout
*layout
)
654 const struct anv_physical_device
*pdevice
=
655 &pipeline
->device
->instance
->physicalDevice
;
656 const struct brw_compiler
*compiler
= pdevice
->compiler
;
658 struct brw_stage_prog_data
*prog_data
= &stage
->prog_data
.base
;
659 nir_shader
*nir
= stage
->nir
;
661 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
662 NIR_PASS_V(nir
, nir_lower_wpos_center
, pipeline
->sample_shading_enable
);
663 NIR_PASS_V(nir
, nir_lower_input_attachments
, true);
666 NIR_PASS_V(nir
, anv_nir_lower_ycbcr_textures
, layout
);
668 NIR_PASS_V(nir
, anv_nir_lower_push_constants
);
670 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
671 NIR_PASS_V(nir
, anv_nir_lower_multiview
, pipeline
->subpass
->view_mask
);
673 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
675 if (nir
->num_uniforms
> 0) {
676 assert(prog_data
->nr_params
== 0);
678 /* If the shader uses any push constants at all, we'll just give
679 * them the maximum possible number
681 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
682 nir
->num_uniforms
= MAX_PUSH_CONSTANTS_SIZE
;
683 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
684 prog_data
->param
= ralloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
686 /* We now set the param values to be offsets into a
687 * anv_push_constant_data structure. Since the compiler doesn't
688 * actually dereference any of the gl_constant_value pointers in the
689 * params array, it doesn't really matter what we put here.
691 struct anv_push_constants
*null_data
= NULL
;
692 /* Fill out the push constants section of the param array */
693 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++) {
694 prog_data
->param
[i
] = ANV_PARAM_PUSH(
695 (uintptr_t)&null_data
->client_data
[i
* sizeof(float)]);
699 if (nir
->info
.num_ssbos
> 0 || nir
->info
.num_images
> 0)
700 pipeline
->needs_data_cache
= true;
702 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, compiler
->devinfo
);
704 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_global
,
705 nir_address_format_64bit_global
);
707 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
709 anv_nir_apply_pipeline_layout(pdevice
,
710 pipeline
->device
->robust_buffer_access
,
711 layout
, nir
, prog_data
,
714 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ubo
,
715 nir_address_format_32bit_index_offset
);
716 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ssbo
,
717 anv_nir_ssbo_addr_format(pdevice
,
718 pipeline
->device
->robust_buffer_access
));
720 NIR_PASS_V(nir
, nir_opt_constant_folding
);
722 /* We don't support non-uniform UBOs and non-uniform SSBO access is
723 * handled naturally by falling back to A64 messages.
725 NIR_PASS_V(nir
, nir_lower_non_uniform_access
,
726 nir_lower_non_uniform_texture_access
|
727 nir_lower_non_uniform_image_access
);
730 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
731 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
733 assert(nir
->num_uniforms
== prog_data
->nr_params
* 4);
739 anv_pipeline_link_vs(const struct brw_compiler
*compiler
,
740 struct anv_pipeline_stage
*vs_stage
,
741 struct anv_pipeline_stage
*next_stage
)
744 brw_nir_link_shaders(compiler
, vs_stage
->nir
, next_stage
->nir
);
748 anv_pipeline_compile_vs(const struct brw_compiler
*compiler
,
750 struct anv_device
*device
,
751 struct anv_pipeline_stage
*vs_stage
)
753 brw_compute_vue_map(compiler
->devinfo
,
754 &vs_stage
->prog_data
.vs
.base
.vue_map
,
755 vs_stage
->nir
->info
.outputs_written
,
756 vs_stage
->nir
->info
.separate_shader
);
758 vs_stage
->num_stats
= 1;
759 vs_stage
->code
= brw_compile_vs(compiler
, device
, mem_ctx
,
761 &vs_stage
->prog_data
.vs
,
763 vs_stage
->stats
, NULL
);
767 merge_tess_info(struct shader_info
*tes_info
,
768 const struct shader_info
*tcs_info
)
770 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
772 * "PointMode. Controls generation of points rather than triangles
773 * or lines. This functionality defaults to disabled, and is
774 * enabled if either shader stage includes the execution mode.
776 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
777 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
778 * and OutputVertices, it says:
780 * "One mode must be set in at least one of the tessellation
783 * So, the fields can be set in either the TCS or TES, but they must
784 * agree if set in both. Our backend looks at TES, so bitwise-or in
785 * the values from the TCS.
787 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
788 tes_info
->tess
.tcs_vertices_out
== 0 ||
789 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
790 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
792 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
793 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
794 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
795 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
797 assert(tcs_info
->tess
.primitive_mode
== 0 ||
798 tes_info
->tess
.primitive_mode
== 0 ||
799 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
800 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
801 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
802 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
806 anv_pipeline_link_tcs(const struct brw_compiler
*compiler
,
807 struct anv_pipeline_stage
*tcs_stage
,
808 struct anv_pipeline_stage
*tes_stage
)
810 assert(tes_stage
&& tes_stage
->stage
== MESA_SHADER_TESS_EVAL
);
812 brw_nir_link_shaders(compiler
, tcs_stage
->nir
, tes_stage
->nir
);
814 nir_lower_patch_vertices(tes_stage
->nir
,
815 tcs_stage
->nir
->info
.tess
.tcs_vertices_out
,
818 /* Copy TCS info into the TES info */
819 merge_tess_info(&tes_stage
->nir
->info
, &tcs_stage
->nir
->info
);
821 /* Whacking the key after cache lookup is a bit sketchy, but all of
822 * this comes from the SPIR-V, which is part of the hash used for the
823 * pipeline cache. So it should be safe.
825 tcs_stage
->key
.tcs
.tes_primitive_mode
=
826 tes_stage
->nir
->info
.tess
.primitive_mode
;
827 tcs_stage
->key
.tcs
.quads_workaround
=
828 compiler
->devinfo
->gen
< 9 &&
829 tes_stage
->nir
->info
.tess
.primitive_mode
== 7 /* GL_QUADS */ &&
830 tes_stage
->nir
->info
.tess
.spacing
== TESS_SPACING_EQUAL
;
834 anv_pipeline_compile_tcs(const struct brw_compiler
*compiler
,
836 struct anv_device
*device
,
837 struct anv_pipeline_stage
*tcs_stage
,
838 struct anv_pipeline_stage
*prev_stage
)
840 tcs_stage
->key
.tcs
.outputs_written
=
841 tcs_stage
->nir
->info
.outputs_written
;
842 tcs_stage
->key
.tcs
.patch_outputs_written
=
843 tcs_stage
->nir
->info
.patch_outputs_written
;
845 tcs_stage
->num_stats
= 1;
846 tcs_stage
->code
= brw_compile_tcs(compiler
, device
, mem_ctx
,
848 &tcs_stage
->prog_data
.tcs
,
850 tcs_stage
->stats
, NULL
);
854 anv_pipeline_link_tes(const struct brw_compiler
*compiler
,
855 struct anv_pipeline_stage
*tes_stage
,
856 struct anv_pipeline_stage
*next_stage
)
859 brw_nir_link_shaders(compiler
, tes_stage
->nir
, next_stage
->nir
);
863 anv_pipeline_compile_tes(const struct brw_compiler
*compiler
,
865 struct anv_device
*device
,
866 struct anv_pipeline_stage
*tes_stage
,
867 struct anv_pipeline_stage
*tcs_stage
)
869 tes_stage
->key
.tes
.inputs_read
=
870 tcs_stage
->nir
->info
.outputs_written
;
871 tes_stage
->key
.tes
.patch_inputs_read
=
872 tcs_stage
->nir
->info
.patch_outputs_written
;
874 tes_stage
->num_stats
= 1;
875 tes_stage
->code
= brw_compile_tes(compiler
, device
, mem_ctx
,
877 &tcs_stage
->prog_data
.tcs
.base
.vue_map
,
878 &tes_stage
->prog_data
.tes
,
879 tes_stage
->nir
, NULL
, -1,
880 tes_stage
->stats
, NULL
);
884 anv_pipeline_link_gs(const struct brw_compiler
*compiler
,
885 struct anv_pipeline_stage
*gs_stage
,
886 struct anv_pipeline_stage
*next_stage
)
889 brw_nir_link_shaders(compiler
, gs_stage
->nir
, next_stage
->nir
);
893 anv_pipeline_compile_gs(const struct brw_compiler
*compiler
,
895 struct anv_device
*device
,
896 struct anv_pipeline_stage
*gs_stage
,
897 struct anv_pipeline_stage
*prev_stage
)
899 brw_compute_vue_map(compiler
->devinfo
,
900 &gs_stage
->prog_data
.gs
.base
.vue_map
,
901 gs_stage
->nir
->info
.outputs_written
,
902 gs_stage
->nir
->info
.separate_shader
);
904 gs_stage
->num_stats
= 1;
905 gs_stage
->code
= brw_compile_gs(compiler
, device
, mem_ctx
,
907 &gs_stage
->prog_data
.gs
,
908 gs_stage
->nir
, NULL
, -1,
909 gs_stage
->stats
, NULL
);
913 anv_pipeline_link_fs(const struct brw_compiler
*compiler
,
914 struct anv_pipeline_stage
*stage
)
916 unsigned num_rts
= 0;
917 const int max_rt
= FRAG_RESULT_DATA7
- FRAG_RESULT_DATA0
+ 1;
918 struct anv_pipeline_binding rt_bindings
[max_rt
];
919 nir_function_impl
*impl
= nir_shader_get_entrypoint(stage
->nir
);
920 int rt_to_bindings
[max_rt
];
921 memset(rt_to_bindings
, -1, sizeof(rt_to_bindings
));
922 bool rt_used
[max_rt
];
923 memset(rt_used
, 0, sizeof(rt_used
));
925 /* Flag used render targets */
926 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
927 if (var
->data
.location
< FRAG_RESULT_DATA0
)
930 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
935 const unsigned array_len
=
936 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
937 assert(rt
+ array_len
<= max_rt
);
940 if (!(stage
->key
.wm
.color_outputs_valid
& BITFIELD_RANGE(rt
, array_len
))) {
941 /* If this is the RT at location 0 and we have alpha to coverage
942 * enabled we will have to create a null RT for it, so mark it as
945 if (rt
> 0 || !stage
->key
.wm
.alpha_to_coverage
)
949 for (unsigned i
= 0; i
< array_len
; i
++)
950 rt_used
[rt
+ i
] = true;
953 /* Set new, compacted, location */
954 for (unsigned i
= 0; i
< max_rt
; i
++) {
958 rt_to_bindings
[i
] = num_rts
;
960 if (stage
->key
.wm
.color_outputs_valid
& (1 << i
)) {
961 rt_bindings
[rt_to_bindings
[i
]] = (struct anv_pipeline_binding
) {
962 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
967 /* Setup a null render target */
968 rt_bindings
[rt_to_bindings
[i
]] = (struct anv_pipeline_binding
) {
969 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
978 bool deleted_output
= false;
979 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
980 if (var
->data
.location
< FRAG_RESULT_DATA0
)
983 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
985 if (rt
>= MAX_RTS
|| !rt_used
[rt
]) {
986 /* Unused or out-of-bounds, throw it away, unless it is the first
987 * RT and we have alpha to coverage enabled.
989 deleted_output
= true;
990 var
->data
.mode
= nir_var_function_temp
;
991 exec_node_remove(&var
->node
);
992 exec_list_push_tail(&impl
->locals
, &var
->node
);
996 /* Give it the new location */
997 assert(rt_to_bindings
[rt
] != -1);
998 var
->data
.location
= rt_to_bindings
[rt
] + FRAG_RESULT_DATA0
;
1002 nir_fixup_deref_modes(stage
->nir
);
1005 /* If we have no render targets, we need a null render target */
1006 rt_bindings
[0] = (struct anv_pipeline_binding
) {
1007 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
1009 .index
= UINT32_MAX
,
1014 /* Now that we've determined the actual number of render targets, adjust
1015 * the key accordingly.
1017 stage
->key
.wm
.nr_color_regions
= num_rts
;
1018 stage
->key
.wm
.color_outputs_valid
= (1 << num_rts
) - 1;
1020 assert(num_rts
<= max_rt
);
1021 assert(stage
->bind_map
.surface_count
== 0);
1022 typed_memcpy(stage
->bind_map
.surface_to_descriptor
,
1023 rt_bindings
, num_rts
);
1024 stage
->bind_map
.surface_count
+= num_rts
;
1028 anv_pipeline_compile_fs(const struct brw_compiler
*compiler
,
1030 struct anv_device
*device
,
1031 struct anv_pipeline_stage
*fs_stage
,
1032 struct anv_pipeline_stage
*prev_stage
)
1034 /* TODO: we could set this to 0 based on the information in nir_shader, but
1035 * we need this before we call spirv_to_nir.
1038 fs_stage
->key
.wm
.input_slots_valid
=
1039 prev_stage
->prog_data
.vue
.vue_map
.slots_valid
;
1041 fs_stage
->code
= brw_compile_fs(compiler
, device
, mem_ctx
,
1043 &fs_stage
->prog_data
.wm
,
1044 fs_stage
->nir
, NULL
, -1, -1, -1,
1046 fs_stage
->stats
, NULL
);
1048 fs_stage
->num_stats
= (uint32_t)fs_stage
->prog_data
.wm
.dispatch_8
+
1049 (uint32_t)fs_stage
->prog_data
.wm
.dispatch_16
+
1050 (uint32_t)fs_stage
->prog_data
.wm
.dispatch_32
;
1052 if (fs_stage
->key
.wm
.nr_color_regions
== 0 &&
1053 !fs_stage
->prog_data
.wm
.has_side_effects
&&
1054 !fs_stage
->prog_data
.wm
.uses_kill
&&
1055 fs_stage
->prog_data
.wm
.computed_depth_mode
== BRW_PSCDEPTH_OFF
&&
1056 !fs_stage
->prog_data
.wm
.computed_stencil
) {
1057 /* This fragment shader has no outputs and no side effects. Go ahead
1058 * and return the code pointer so we don't accidentally think the
1059 * compile failed but zero out prog_data which will set program_size to
1060 * zero and disable the stage.
1062 memset(&fs_stage
->prog_data
, 0, sizeof(fs_stage
->prog_data
));
1067 anv_pipeline_compile_graphics(struct anv_pipeline
*pipeline
,
1068 struct anv_pipeline_cache
*cache
,
1069 const VkGraphicsPipelineCreateInfo
*info
)
1071 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1072 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1074 int64_t pipeline_start
= os_time_get_nano();
1076 const struct brw_compiler
*compiler
=
1077 pipeline
->device
->instance
->physicalDevice
.compiler
;
1078 struct anv_pipeline_stage stages
[MESA_SHADER_STAGES
] = {};
1080 pipeline
->active_stages
= 0;
1083 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1084 const VkPipelineShaderStageCreateInfo
*sinfo
= &info
->pStages
[i
];
1085 gl_shader_stage stage
= vk_to_mesa_shader_stage(sinfo
->stage
);
1087 pipeline
->active_stages
|= sinfo
->stage
;
1089 int64_t stage_start
= os_time_get_nano();
1091 stages
[stage
].stage
= stage
;
1092 stages
[stage
].module
= anv_shader_module_from_handle(sinfo
->module
);
1093 stages
[stage
].entrypoint
= sinfo
->pName
;
1094 stages
[stage
].spec_info
= sinfo
->pSpecializationInfo
;
1095 anv_pipeline_hash_shader(stages
[stage
].module
,
1096 stages
[stage
].entrypoint
,
1098 stages
[stage
].spec_info
,
1099 stages
[stage
].shader_sha1
);
1101 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1103 case MESA_SHADER_VERTEX
:
1104 populate_vs_prog_key(devinfo
, sinfo
->flags
, &stages
[stage
].key
.vs
);
1106 case MESA_SHADER_TESS_CTRL
:
1107 populate_tcs_prog_key(devinfo
, sinfo
->flags
,
1108 info
->pTessellationState
->patchControlPoints
,
1109 &stages
[stage
].key
.tcs
);
1111 case MESA_SHADER_TESS_EVAL
:
1112 populate_tes_prog_key(devinfo
, sinfo
->flags
, &stages
[stage
].key
.tes
);
1114 case MESA_SHADER_GEOMETRY
:
1115 populate_gs_prog_key(devinfo
, sinfo
->flags
, &stages
[stage
].key
.gs
);
1117 case MESA_SHADER_FRAGMENT
:
1118 populate_wm_prog_key(devinfo
, sinfo
->flags
,
1120 info
->pMultisampleState
,
1121 &stages
[stage
].key
.wm
);
1124 unreachable("Invalid graphics shader stage");
1127 stages
[stage
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1128 stages
[stage
].feedback
.flags
|= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
1131 if (pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
)
1132 pipeline
->active_stages
|= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
1134 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1136 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1138 unsigned char sha1
[20];
1139 anv_pipeline_hash_graphics(pipeline
, layout
, stages
, sha1
);
1141 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1142 if (!stages
[s
].entrypoint
)
1145 stages
[s
].cache_key
.stage
= s
;
1146 memcpy(stages
[s
].cache_key
.sha1
, sha1
, sizeof(sha1
));
1149 const bool skip_cache_lookup
=
1150 (pipeline
->flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
);
1152 if (!skip_cache_lookup
) {
1154 unsigned cache_hits
= 0;
1155 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1156 if (!stages
[s
].entrypoint
)
1159 int64_t stage_start
= os_time_get_nano();
1162 struct anv_shader_bin
*bin
=
1163 anv_device_search_for_kernel(pipeline
->device
, cache
,
1164 &stages
[s
].cache_key
,
1165 sizeof(stages
[s
].cache_key
), &cache_hit
);
1168 pipeline
->shaders
[s
] = bin
;
1173 stages
[s
].feedback
.flags
|=
1174 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1176 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1179 if (found
== __builtin_popcount(pipeline
->active_stages
)) {
1180 if (cache_hits
== found
) {
1181 pipeline_feedback
.flags
|=
1182 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1184 /* We found all our shaders in the cache. We're done. */
1186 } else if (found
> 0) {
1187 /* We found some but not all of our shaders. This shouldn't happen
1188 * most of the time but it can if we have a partially populated
1191 assert(found
< __builtin_popcount(pipeline
->active_stages
));
1193 vk_debug_report(&pipeline
->device
->instance
->debug_report_callbacks
,
1194 VK_DEBUG_REPORT_WARNING_BIT_EXT
|
1195 VK_DEBUG_REPORT_PERFORMANCE_WARNING_BIT_EXT
,
1196 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT
,
1197 (uint64_t)(uintptr_t)cache
,
1199 "Found a partial pipeline in the cache. This is "
1200 "most likely caused by an incomplete pipeline cache "
1201 "import or export");
1203 /* We're going to have to recompile anyway, so just throw away our
1204 * references to the shaders in the cache. We'll get them out of the
1205 * cache again as part of the compilation process.
1207 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1208 stages
[s
].feedback
.flags
= 0;
1209 if (pipeline
->shaders
[s
]) {
1210 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1211 pipeline
->shaders
[s
] = NULL
;
1217 void *pipeline_ctx
= ralloc_context(NULL
);
1219 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1220 if (!stages
[s
].entrypoint
)
1223 int64_t stage_start
= os_time_get_nano();
1225 assert(stages
[s
].stage
== s
);
1226 assert(pipeline
->shaders
[s
] == NULL
);
1228 stages
[s
].bind_map
= (struct anv_pipeline_bind_map
) {
1229 .surface_to_descriptor
= stages
[s
].surface_to_descriptor
,
1230 .sampler_to_descriptor
= stages
[s
].sampler_to_descriptor
1233 stages
[s
].nir
= anv_pipeline_stage_get_nir(pipeline
, cache
,
1236 if (stages
[s
].nir
== NULL
) {
1237 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1241 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1244 /* Walk backwards to link */
1245 struct anv_pipeline_stage
*next_stage
= NULL
;
1246 for (int s
= MESA_SHADER_STAGES
- 1; s
>= 0; s
--) {
1247 if (!stages
[s
].entrypoint
)
1251 case MESA_SHADER_VERTEX
:
1252 anv_pipeline_link_vs(compiler
, &stages
[s
], next_stage
);
1254 case MESA_SHADER_TESS_CTRL
:
1255 anv_pipeline_link_tcs(compiler
, &stages
[s
], next_stage
);
1257 case MESA_SHADER_TESS_EVAL
:
1258 anv_pipeline_link_tes(compiler
, &stages
[s
], next_stage
);
1260 case MESA_SHADER_GEOMETRY
:
1261 anv_pipeline_link_gs(compiler
, &stages
[s
], next_stage
);
1263 case MESA_SHADER_FRAGMENT
:
1264 anv_pipeline_link_fs(compiler
, &stages
[s
]);
1267 unreachable("Invalid graphics shader stage");
1270 next_stage
= &stages
[s
];
1273 struct anv_pipeline_stage
*prev_stage
= NULL
;
1274 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1275 if (!stages
[s
].entrypoint
)
1278 int64_t stage_start
= os_time_get_nano();
1280 void *stage_ctx
= ralloc_context(NULL
);
1282 nir_xfb_info
*xfb_info
= NULL
;
1283 if (s
== MESA_SHADER_VERTEX
||
1284 s
== MESA_SHADER_TESS_EVAL
||
1285 s
== MESA_SHADER_GEOMETRY
)
1286 xfb_info
= nir_gather_xfb_info(stages
[s
].nir
, stage_ctx
);
1288 anv_pipeline_lower_nir(pipeline
, stage_ctx
, &stages
[s
], layout
);
1291 case MESA_SHADER_VERTEX
:
1292 anv_pipeline_compile_vs(compiler
, stage_ctx
, pipeline
->device
,
1295 case MESA_SHADER_TESS_CTRL
:
1296 anv_pipeline_compile_tcs(compiler
, stage_ctx
, pipeline
->device
,
1297 &stages
[s
], prev_stage
);
1299 case MESA_SHADER_TESS_EVAL
:
1300 anv_pipeline_compile_tes(compiler
, stage_ctx
, pipeline
->device
,
1301 &stages
[s
], prev_stage
);
1303 case MESA_SHADER_GEOMETRY
:
1304 anv_pipeline_compile_gs(compiler
, stage_ctx
, pipeline
->device
,
1305 &stages
[s
], prev_stage
);
1307 case MESA_SHADER_FRAGMENT
:
1308 anv_pipeline_compile_fs(compiler
, stage_ctx
, pipeline
->device
,
1309 &stages
[s
], prev_stage
);
1312 unreachable("Invalid graphics shader stage");
1314 if (stages
[s
].code
== NULL
) {
1315 ralloc_free(stage_ctx
);
1316 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1320 struct anv_shader_bin
*bin
=
1321 anv_device_upload_kernel(pipeline
->device
, cache
,
1322 &stages
[s
].cache_key
,
1323 sizeof(stages
[s
].cache_key
),
1325 stages
[s
].prog_data
.base
.program_size
,
1326 stages
[s
].nir
->constant_data
,
1327 stages
[s
].nir
->constant_data_size
,
1328 &stages
[s
].prog_data
.base
,
1329 brw_prog_data_size(s
),
1330 stages
[s
].stats
, stages
[s
].num_stats
,
1331 xfb_info
, &stages
[s
].bind_map
);
1333 ralloc_free(stage_ctx
);
1334 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1338 pipeline
->shaders
[s
] = bin
;
1339 ralloc_free(stage_ctx
);
1341 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1343 prev_stage
= &stages
[s
];
1346 ralloc_free(pipeline_ctx
);
1350 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
] &&
1351 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->prog_data
->program_size
== 0) {
1352 /* This can happen if we decided to implicitly disable the fragment
1353 * shader. See anv_pipeline_compile_fs().
1355 anv_shader_bin_unref(pipeline
->device
,
1356 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
1357 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] = NULL
;
1358 pipeline
->active_stages
&= ~VK_SHADER_STAGE_FRAGMENT_BIT
;
1361 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1363 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1364 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1365 if (create_feedback
) {
1366 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1368 assert(info
->stageCount
== create_feedback
->pipelineStageCreationFeedbackCount
);
1369 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1370 gl_shader_stage s
= vk_to_mesa_shader_stage(info
->pStages
[i
].stage
);
1371 create_feedback
->pPipelineStageCreationFeedbacks
[i
] = stages
[s
].feedback
;
1378 ralloc_free(pipeline_ctx
);
1380 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1381 if (pipeline
->shaders
[s
])
1382 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1389 shared_type_info(const struct glsl_type
*type
, unsigned *size
, unsigned *align
)
1391 assert(glsl_type_is_vector_or_scalar(type
));
1393 uint32_t comp_size
= glsl_type_is_boolean(type
)
1394 ? 4 : glsl_get_bit_size(type
) / 8;
1395 unsigned length
= glsl_get_vector_elements(type
);
1396 *size
= comp_size
* length
,
1397 *align
= comp_size
* (length
== 3 ? 4 : length
);
1401 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1402 struct anv_pipeline_cache
*cache
,
1403 const VkComputePipelineCreateInfo
*info
,
1404 const struct anv_shader_module
*module
,
1405 const char *entrypoint
,
1406 const VkSpecializationInfo
*spec_info
)
1408 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1409 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1411 int64_t pipeline_start
= os_time_get_nano();
1413 const struct brw_compiler
*compiler
=
1414 pipeline
->device
->instance
->physicalDevice
.compiler
;
1416 struct anv_pipeline_stage stage
= {
1417 .stage
= MESA_SHADER_COMPUTE
,
1419 .entrypoint
= entrypoint
,
1420 .spec_info
= spec_info
,
1422 .stage
= MESA_SHADER_COMPUTE
,
1425 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1428 anv_pipeline_hash_shader(stage
.module
,
1430 MESA_SHADER_COMPUTE
,
1434 struct anv_shader_bin
*bin
= NULL
;
1436 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*rss_info
=
1437 vk_find_struct_const(info
->stage
.pNext
,
1438 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
1440 populate_cs_prog_key(&pipeline
->device
->info
, info
->stage
.flags
,
1441 rss_info
, &stage
.key
.cs
);
1443 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1445 const bool skip_cache_lookup
=
1446 (pipeline
->flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
);
1448 anv_pipeline_hash_compute(pipeline
, layout
, &stage
, stage
.cache_key
.sha1
);
1450 bool cache_hit
= false;
1451 if (!skip_cache_lookup
) {
1452 bin
= anv_device_search_for_kernel(pipeline
->device
, cache
,
1454 sizeof(stage
.cache_key
),
1459 int64_t stage_start
= os_time_get_nano();
1461 stage
.bind_map
= (struct anv_pipeline_bind_map
) {
1462 .surface_to_descriptor
= stage
.surface_to_descriptor
,
1463 .sampler_to_descriptor
= stage
.sampler_to_descriptor
1466 /* Set up a binding for the gl_NumWorkGroups */
1467 stage
.bind_map
.surface_count
= 1;
1468 stage
.bind_map
.surface_to_descriptor
[0] = (struct anv_pipeline_binding
) {
1469 .set
= ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
,
1472 void *mem_ctx
= ralloc_context(NULL
);
1474 stage
.nir
= anv_pipeline_stage_get_nir(pipeline
, cache
, mem_ctx
, &stage
);
1475 if (stage
.nir
== NULL
) {
1476 ralloc_free(mem_ctx
);
1477 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1480 anv_pipeline_lower_nir(pipeline
, mem_ctx
, &stage
, layout
);
1482 NIR_PASS_V(stage
.nir
, anv_nir_add_base_work_group_id
,
1483 &stage
.prog_data
.cs
);
1485 NIR_PASS_V(stage
.nir
, nir_lower_vars_to_explicit_types
,
1486 nir_var_mem_shared
, shared_type_info
);
1487 NIR_PASS_V(stage
.nir
, nir_lower_explicit_io
,
1488 nir_var_mem_shared
, nir_address_format_32bit_offset
);
1490 stage
.num_stats
= 1;
1491 stage
.code
= brw_compile_cs(compiler
, pipeline
->device
, mem_ctx
,
1492 &stage
.key
.cs
, &stage
.prog_data
.cs
,
1493 stage
.nir
, -1, stage
.stats
, NULL
);
1494 if (stage
.code
== NULL
) {
1495 ralloc_free(mem_ctx
);
1496 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1499 const unsigned code_size
= stage
.prog_data
.base
.program_size
;
1500 bin
= anv_device_upload_kernel(pipeline
->device
, cache
,
1501 &stage
.cache_key
, sizeof(stage
.cache_key
),
1502 stage
.code
, code_size
,
1503 stage
.nir
->constant_data
,
1504 stage
.nir
->constant_data_size
,
1505 &stage
.prog_data
.base
,
1506 sizeof(stage
.prog_data
.cs
),
1507 stage
.stats
, stage
.num_stats
,
1508 NULL
, &stage
.bind_map
);
1510 ralloc_free(mem_ctx
);
1511 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1514 ralloc_free(mem_ctx
);
1516 stage
.feedback
.duration
= os_time_get_nano() - stage_start
;
1520 stage
.feedback
.flags
|=
1521 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1522 pipeline_feedback
.flags
|=
1523 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1525 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1527 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1528 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1529 if (create_feedback
) {
1530 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1532 assert(create_feedback
->pipelineStageCreationFeedbackCount
== 1);
1533 create_feedback
->pPipelineStageCreationFeedbacks
[0] = stage
.feedback
;
1536 pipeline
->active_stages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1537 pipeline
->shaders
[MESA_SHADER_COMPUTE
] = bin
;
1543 * Copy pipeline state not marked as dynamic.
1544 * Dynamic state is pipeline state which hasn't been provided at pipeline
1545 * creation time, but is dynamically provided afterwards using various
1546 * vkCmdSet* functions.
1548 * The set of state considered "non_dynamic" is determined by the pieces of
1549 * state that have their corresponding VkDynamicState enums omitted from
1550 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1552 * @param[out] pipeline Destination non_dynamic state.
1553 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1556 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
1557 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1559 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
1560 struct anv_subpass
*subpass
= pipeline
->subpass
;
1562 pipeline
->dynamic_state
= default_dynamic_state
;
1564 if (pCreateInfo
->pDynamicState
) {
1565 /* Remove all of the states that are marked as dynamic */
1566 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1567 for (uint32_t s
= 0; s
< count
; s
++) {
1568 states
&= ~anv_cmd_dirty_bit_for_vk_dynamic_state(
1569 pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1573 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1575 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1577 * pViewportState is [...] NULL if the pipeline
1578 * has rasterization disabled.
1580 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1581 assert(pCreateInfo
->pViewportState
);
1583 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1584 if (states
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
) {
1585 typed_memcpy(dynamic
->viewport
.viewports
,
1586 pCreateInfo
->pViewportState
->pViewports
,
1587 pCreateInfo
->pViewportState
->viewportCount
);
1590 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1591 if (states
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
) {
1592 typed_memcpy(dynamic
->scissor
.scissors
,
1593 pCreateInfo
->pViewportState
->pScissors
,
1594 pCreateInfo
->pViewportState
->scissorCount
);
1598 if (states
& ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
) {
1599 assert(pCreateInfo
->pRasterizationState
);
1600 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1603 if (states
& ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
) {
1604 assert(pCreateInfo
->pRasterizationState
);
1605 dynamic
->depth_bias
.bias
=
1606 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1607 dynamic
->depth_bias
.clamp
=
1608 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1609 dynamic
->depth_bias
.slope
=
1610 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1613 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1615 * pColorBlendState is [...] NULL if the pipeline has rasterization
1616 * disabled or if the subpass of the render pass the pipeline is
1617 * created against does not use any color attachments.
1619 bool uses_color_att
= false;
1620 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1621 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1622 uses_color_att
= true;
1627 if (uses_color_att
&&
1628 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1629 assert(pCreateInfo
->pColorBlendState
);
1631 if (states
& ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
1632 typed_memcpy(dynamic
->blend_constants
,
1633 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1636 /* If there is no depthstencil attachment, then don't read
1637 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1638 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1639 * no need to override the depthstencil defaults in
1640 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1642 * Section 9.2 of the Vulkan 1.0.15 spec says:
1644 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1645 * disabled or if the subpass of the render pass the pipeline is created
1646 * against does not use a depth/stencil attachment.
1648 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1649 subpass
->depth_stencil_attachment
) {
1650 assert(pCreateInfo
->pDepthStencilState
);
1652 if (states
& ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
) {
1653 dynamic
->depth_bounds
.min
=
1654 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1655 dynamic
->depth_bounds
.max
=
1656 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1659 if (states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
) {
1660 dynamic
->stencil_compare_mask
.front
=
1661 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1662 dynamic
->stencil_compare_mask
.back
=
1663 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1666 if (states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
) {
1667 dynamic
->stencil_write_mask
.front
=
1668 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1669 dynamic
->stencil_write_mask
.back
=
1670 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1673 if (states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
) {
1674 dynamic
->stencil_reference
.front
=
1675 pCreateInfo
->pDepthStencilState
->front
.reference
;
1676 dynamic
->stencil_reference
.back
=
1677 pCreateInfo
->pDepthStencilState
->back
.reference
;
1681 const VkPipelineRasterizationLineStateCreateInfoEXT
*line_state
=
1682 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1683 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1685 if (states
& ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
) {
1686 dynamic
->line_stipple
.factor
= line_state
->lineStippleFactor
;
1687 dynamic
->line_stipple
.pattern
= line_state
->lineStipplePattern
;
1691 pipeline
->dynamic_state_mask
= states
;
1695 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1698 struct anv_render_pass
*renderpass
= NULL
;
1699 struct anv_subpass
*subpass
= NULL
;
1701 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1702 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1704 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1706 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1709 assert(info
->subpass
< renderpass
->subpass_count
);
1710 subpass
= &renderpass
->subpasses
[info
->subpass
];
1712 assert(info
->stageCount
>= 1);
1713 assert(info
->pVertexInputState
);
1714 assert(info
->pInputAssemblyState
);
1715 assert(info
->pRasterizationState
);
1716 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1717 assert(info
->pViewportState
);
1718 assert(info
->pMultisampleState
);
1720 if (subpass
&& subpass
->depth_stencil_attachment
)
1721 assert(info
->pDepthStencilState
);
1723 if (subpass
&& subpass
->color_count
> 0) {
1724 bool all_color_unused
= true;
1725 for (int i
= 0; i
< subpass
->color_count
; i
++) {
1726 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
1727 all_color_unused
= false;
1729 /* pColorBlendState is ignored if the pipeline has rasterization
1730 * disabled or if the subpass of the render pass the pipeline is
1731 * created against does not use any color attachments.
1733 assert(info
->pColorBlendState
|| all_color_unused
);
1737 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1738 switch (info
->pStages
[i
].stage
) {
1739 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1740 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1741 assert(info
->pTessellationState
);
1751 * Calculate the desired L3 partitioning based on the current state of the
1752 * pipeline. For now this simply returns the conservative defaults calculated
1753 * by get_default_l3_weights(), but we could probably do better by gathering
1754 * more statistics from the pipeline state (e.g. guess of expected URB usage
1755 * and bound surfaces), or by using feed-back from performance counters.
1758 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1760 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1762 const struct gen_l3_weights w
=
1763 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
1765 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
1766 pipeline
->urb
.total_size
=
1767 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
1771 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1772 struct anv_device
*device
,
1773 struct anv_pipeline_cache
*cache
,
1774 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1775 const VkAllocationCallbacks
*alloc
)
1779 anv_pipeline_validate_create_info(pCreateInfo
);
1782 alloc
= &device
->alloc
;
1784 pipeline
->device
= device
;
1786 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, pCreateInfo
->renderPass
);
1787 assert(pCreateInfo
->subpass
< render_pass
->subpass_count
);
1788 pipeline
->subpass
= &render_pass
->subpasses
[pCreateInfo
->subpass
];
1790 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1791 if (result
!= VK_SUCCESS
)
1794 pipeline
->batch
.alloc
= alloc
;
1795 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1796 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1797 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1798 pipeline
->batch
.status
= VK_SUCCESS
;
1800 pipeline
->mem_ctx
= ralloc_context(NULL
);
1801 pipeline
->flags
= pCreateInfo
->flags
;
1803 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1804 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1805 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1807 /* Previously we enabled depth clipping when !depthClampEnable.
1808 * DepthClipStateCreateInfo now makes depth clipping explicit so if the
1809 * clipping info is available, use its enable value to determine clipping,
1810 * otherwise fallback to the previous !depthClampEnable logic.
1812 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*clip_info
=
1813 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1814 PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
1815 pipeline
->depth_clip_enable
= clip_info
? clip_info
->depthClipEnable
: !pipeline
->depth_clamp_enable
;
1817 pipeline
->sample_shading_enable
= pCreateInfo
->pMultisampleState
&&
1818 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
1820 pipeline
->needs_data_cache
= false;
1822 /* When we free the pipeline, we detect stages based on the NULL status
1823 * of various prog_data pointers. Make them NULL by default.
1825 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1827 result
= anv_pipeline_compile_graphics(pipeline
, cache
, pCreateInfo
);
1828 if (result
!= VK_SUCCESS
) {
1829 ralloc_free(pipeline
->mem_ctx
);
1830 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);
1834 assert(pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1836 anv_pipeline_setup_l3_config(pipeline
, false);
1838 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1839 pCreateInfo
->pVertexInputState
;
1841 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1843 pipeline
->vb_used
= 0;
1844 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1845 const VkVertexInputAttributeDescription
*desc
=
1846 &vi_info
->pVertexAttributeDescriptions
[i
];
1848 if (inputs_read
& (1ull << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1849 pipeline
->vb_used
|= 1 << desc
->binding
;
1852 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1853 const VkVertexInputBindingDescription
*desc
=
1854 &vi_info
->pVertexBindingDescriptions
[i
];
1856 pipeline
->vb
[desc
->binding
].stride
= desc
->stride
;
1858 /* Step rate is programmed per vertex element (attribute), not
1859 * binding. Set up a map of which bindings step per instance, for
1860 * reference by vertex element setup. */
1861 switch (desc
->inputRate
) {
1863 case VK_VERTEX_INPUT_RATE_VERTEX
:
1864 pipeline
->vb
[desc
->binding
].instanced
= false;
1866 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1867 pipeline
->vb
[desc
->binding
].instanced
= true;
1871 pipeline
->vb
[desc
->binding
].instance_divisor
= 1;
1874 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*vi_div_state
=
1875 vk_find_struct_const(vi_info
->pNext
,
1876 PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
1878 for (uint32_t i
= 0; i
< vi_div_state
->vertexBindingDivisorCount
; i
++) {
1879 const VkVertexInputBindingDivisorDescriptionEXT
*desc
=
1880 &vi_div_state
->pVertexBindingDivisors
[i
];
1882 pipeline
->vb
[desc
->binding
].instance_divisor
= desc
->divisor
;
1886 /* Our implementation of VK_KHR_multiview uses instancing to draw the
1887 * different views. If the client asks for instancing, we need to multiply
1888 * the instance divisor by the number of views ensure that we repeat the
1889 * client's per-instance data once for each view.
1891 if (pipeline
->subpass
->view_mask
) {
1892 const uint32_t view_count
= anv_subpass_view_count(pipeline
->subpass
);
1893 for (uint32_t vb
= 0; vb
< MAX_VBS
; vb
++) {
1894 if (pipeline
->vb
[vb
].instanced
)
1895 pipeline
->vb
[vb
].instance_divisor
*= view_count
;
1899 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1900 pCreateInfo
->pInputAssemblyState
;
1901 const VkPipelineTessellationStateCreateInfo
*tess_info
=
1902 pCreateInfo
->pTessellationState
;
1903 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1905 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1906 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
1908 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];