projects / mesa.git / blob
? search:


fdec3ce6227b5aaba182a5a81bf9d97383a257fa
[mesa.git] / src / intel / vulkan / anv_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "util/mesa-sha1.h"
31 #include "common/gen_l3_config.h"
32 #include "anv_private.h"
33 #include "brw_nir.h"
34 #include "anv_nir.h"
35 #include "spirv/nir_spirv.h"
36
37 /* Needed for SWIZZLE macros */
38 #include "program/prog_instruction.h"
39
40 // Shader functions
41
42 VkResult anv_CreateShaderModule(
43 VkDevice _device,
44 const VkShaderModuleCreateInfo* pCreateInfo,
45 const VkAllocationCallbacks* pAllocator,
46 VkShaderModule* pShaderModule)
47 {
48 ANV_FROM_HANDLE(anv_device, device, _device);
49 struct anv_shader_module *module;
50
51 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
52 assert(pCreateInfo->flags == 0);
53
54 module = vk_alloc2(&device->alloc, pAllocator,
55 sizeof(*module) + pCreateInfo->codeSize, 8,
56 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
57 if (module == NULL)
58 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
59
60 module->size = pCreateInfo->codeSize;
61 memcpy(module->data, pCreateInfo->pCode, module->size);
62
63 _mesa_sha1_compute(module->data, module->size, module->sha1);
64
65 *pShaderModule = anv_shader_module_to_handle(module);
66
67 return VK_SUCCESS;
68 }
69
70 void anv_DestroyShaderModule(
71 VkDevice _device,
72 VkShaderModule _module,
73 const VkAllocationCallbacks* pAllocator)
74 {
75 ANV_FROM_HANDLE(anv_device, device, _device);
76 ANV_FROM_HANDLE(anv_shader_module, module, _module);
77
78 if (!module)
79 return;
80
81 vk_free2(&device->alloc, pAllocator, module);
82 }
83
84 #define SPIR_V_MAGIC_NUMBER 0x07230203
85
86 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
87 * we can't do that yet because we don't have the ability to copy nir.
88 */
89 static nir_shader *
90 anv_shader_compile_to_nir(struct anv_device *device,
91 struct anv_shader_module *module,
92 const char *entrypoint_name,
93 gl_shader_stage stage,
94 const VkSpecializationInfo *spec_info)
95 {
96 if (strcmp(entrypoint_name, "main") != 0) {
97 anv_finishme("Multiple shaders per module not really supported");
98 }
99
100 const struct brw_compiler *compiler =
101 device->instance->physicalDevice.compiler;
102 const nir_shader_compiler_options *nir_options =
103 compiler->glsl_compiler_options[stage].NirOptions;
104
105 uint32_t *spirv = (uint32_t *) module->data;
106 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
107 assert(module->size % 4 == 0);
108
109 uint32_t num_spec_entries = 0;
110 struct nir_spirv_specialization *spec_entries = NULL;
111 if (spec_info && spec_info->mapEntryCount > 0) {
112 num_spec_entries = spec_info->mapEntryCount;
113 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
114 for (uint32_t i = 0; i < num_spec_entries; i++) {
115 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
116 const void *data = spec_info->pData + entry.offset;
117 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
118
119 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
120 if (spec_info->dataSize == 8)
121 spec_entries[i].data64 = *(const uint64_t *)data;
122 else
123 spec_entries[i].data32 = *(const uint32_t *)data;
124 }
125 }
126
127 const struct nir_spirv_supported_extensions supported_ext = {
128 .float64 = device->instance->physicalDevice.info.gen >= 8,
129 };
130
131 nir_function *entry_point =
132 spirv_to_nir(spirv, module->size / 4,
133 spec_entries, num_spec_entries,
134 stage, entrypoint_name, &supported_ext, nir_options);
135 nir_shader *nir = entry_point->shader;
136 assert(nir->stage == stage);
137 nir_validate_shader(nir);
138
139 free(spec_entries);
140
141 if (stage == MESA_SHADER_FRAGMENT)
142 NIR_PASS_V(nir, nir_lower_wpos_center);
143
144 /* We have to lower away local constant initializers right before we
145 * inline functions. That way they get properly initialized at the top
146 * of the function and not at the top of its caller.
147 */
148 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
149 NIR_PASS_V(nir, nir_lower_returns);
150 NIR_PASS_V(nir, nir_inline_functions);
151
152 /* Pick off the single entrypoint that we want */
153 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
154 if (func != entry_point)
155 exec_node_remove(&func->node);
156 }
157 assert(exec_list_length(&nir->functions) == 1);
158 entry_point->name = ralloc_strdup(entry_point, "main");
159
160 NIR_PASS_V(nir, nir_remove_dead_variables,
161 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
162
163 /* Now that we've deleted all but the main function, we can go ahead and
164 * lower the rest of the constant initializers.
165 */
166 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
167 NIR_PASS_V(nir, nir_propagate_invariant);
168 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
169 entry_point->impl, true, false);
170 NIR_PASS_V(nir, nir_lower_system_values);
171
172 /* Vulkan uses the separate-shader linking model */
173 nir->info->separate_shader = true;
174
175 nir = brw_preprocess_nir(compiler, nir);
176
177 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
178
179 if (stage == MESA_SHADER_FRAGMENT)
180 NIR_PASS_V(nir, anv_nir_lower_input_attachments);
181
182 nir_shader_gather_info(nir, entry_point->impl);
183
184 return nir;
185 }
186
187 void anv_DestroyPipeline(
188 VkDevice _device,
189 VkPipeline _pipeline,
190 const VkAllocationCallbacks* pAllocator)
191 {
192 ANV_FROM_HANDLE(anv_device, device, _device);
193 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
194
195 if (!pipeline)
196 return;
197
198 anv_reloc_list_finish(&pipeline->batch_relocs,
199 pAllocator ? pAllocator : &device->alloc);
200 if (pipeline->blend_state.map)
201 anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
202
203 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
204 if (pipeline->shaders[s])
205 anv_shader_bin_unref(device, pipeline->shaders[s]);
206 }
207
208 vk_free2(&device->alloc, pAllocator, pipeline);
209 }
210
211 static const uint32_t vk_to_gen_primitive_type[] = {
212 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
213 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
214 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
215 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
216 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
217 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
218 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
219 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
220 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
221 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
222 };
223
224 static void
225 populate_sampler_prog_key(const struct gen_device_info *devinfo,
226 struct brw_sampler_prog_key_data *key)
227 {
228 /* XXX: Handle texture swizzle on HSW- */
229 for (int i = 0; i < MAX_SAMPLERS; i++) {
230 /* Assume color sampler, no swizzling. (Works for BDW+) */
231 key->swizzles[i] = SWIZZLE_XYZW;
232 }
233 }
234
235 static void
236 populate_vs_prog_key(const struct gen_device_info *devinfo,
237 struct brw_vs_prog_key *key)
238 {
239 memset(key, 0, sizeof(*key));
240
241 populate_sampler_prog_key(devinfo, &key->tex);
242
243 /* XXX: Handle vertex input work-arounds */
244
245 /* XXX: Handle sampler_prog_key */
246 }
247
248 static void
249 populate_gs_prog_key(const struct gen_device_info *devinfo,
250 struct brw_gs_prog_key *key)
251 {
252 memset(key, 0, sizeof(*key));
253
254 populate_sampler_prog_key(devinfo, &key->tex);
255 }
256
257 static void
258 populate_wm_prog_key(const struct anv_pipeline *pipeline,
259 const VkGraphicsPipelineCreateInfo *info,
260 struct brw_wm_prog_key *key)
261 {
262 const struct gen_device_info *devinfo = &pipeline->device->info;
263 ANV_FROM_HANDLE(anv_render_pass, render_pass, info->renderPass);
264
265 memset(key, 0, sizeof(*key));
266
267 populate_sampler_prog_key(devinfo, &key->tex);
268
269 /* TODO: we could set this to 0 based on the information in nir_shader, but
270 * this function is called before spirv_to_nir. */
271 const struct brw_vue_map *vue_map =
272 anv_pipeline_get_fs_input_map(pipeline);
273 key->input_slots_valid = vue_map->slots_valid;
274
275 /* Vulkan doesn't specify a default */
276 key->high_quality_derivatives = false;
277
278 /* XXX Vulkan doesn't appear to specify */
279 key->clamp_fragment_color = false;
280
281 key->nr_color_regions =
282 render_pass->subpasses[info->subpass].color_count;
283
284 key->replicate_alpha = key->nr_color_regions > 1 &&
285 info->pMultisampleState &&
286 info->pMultisampleState->alphaToCoverageEnable;
287
288 if (info->pMultisampleState && info->pMultisampleState->rasterizationSamples > 1) {
289 /* We should probably pull this out of the shader, but it's fairly
290 * harmless to compute it and then let dead-code take care of it.
291 */
292 key->persample_interp =
293 (info->pMultisampleState->minSampleShading *
294 info->pMultisampleState->rasterizationSamples) > 1;
295 key->multisample_fbo = true;
296 }
297 }
298
299 static void
300 populate_cs_prog_key(const struct gen_device_info *devinfo,
301 struct brw_cs_prog_key *key)
302 {
303 memset(key, 0, sizeof(*key));
304
305 populate_sampler_prog_key(devinfo, &key->tex);
306 }
307
308 static nir_shader *
309 anv_pipeline_compile(struct anv_pipeline *pipeline,
310 struct anv_shader_module *module,
311 const char *entrypoint,
312 gl_shader_stage stage,
313 const VkSpecializationInfo *spec_info,
314 struct brw_stage_prog_data *prog_data,
315 struct anv_pipeline_bind_map *map)
316 {
317 nir_shader *nir = anv_shader_compile_to_nir(pipeline->device,
318 module, entrypoint, stage,
319 spec_info);
320 if (nir == NULL)
321 return NULL;
322
323 NIR_PASS_V(nir, anv_nir_lower_push_constants);
324
325 /* Figure out the number of parameters */
326 prog_data->nr_params = 0;
327
328 if (nir->num_uniforms > 0) {
329 /* If the shader uses any push constants at all, we'll just give
330 * them the maximum possible number
331 */
332 assert(nir->num_uniforms <= MAX_PUSH_CONSTANTS_SIZE);
333 prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
334 }
335
336 if (pipeline->layout && pipeline->layout->stage[stage].has_dynamic_offsets)
337 prog_data->nr_params += MAX_DYNAMIC_BUFFERS * 2;
338
339 if (nir->info->num_images > 0) {
340 prog_data->nr_params += nir->info->num_images * BRW_IMAGE_PARAM_SIZE;
341 pipeline->needs_data_cache = true;
342 }
343
344 if (stage == MESA_SHADER_COMPUTE)
345 ((struct brw_cs_prog_data *)prog_data)->thread_local_id_index =
346 prog_data->nr_params++; /* The CS Thread ID uniform */
347
348 if (nir->info->num_ssbos > 0)
349 pipeline->needs_data_cache = true;
350
351 if (prog_data->nr_params > 0) {
352 /* XXX: I think we're leaking this */
353 prog_data->param = (const union gl_constant_value **)
354 malloc(prog_data->nr_params * sizeof(union gl_constant_value *));
355
356 /* We now set the param values to be offsets into a
357 * anv_push_constant_data structure. Since the compiler doesn't
358 * actually dereference any of the gl_constant_value pointers in the
359 * params array, it doesn't really matter what we put here.
360 */
361 struct anv_push_constants *null_data = NULL;
362 if (nir->num_uniforms > 0) {
363 /* Fill out the push constants section of the param array */
364 for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++)
365 prog_data->param[i] = (const union gl_constant_value *)
366 &null_data->client_data[i * sizeof(float)];
367 }
368 }
369
370 /* Set up dynamic offsets */
371 anv_nir_apply_dynamic_offsets(pipeline, nir, prog_data);
372
373 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
374 if (pipeline->layout)
375 anv_nir_apply_pipeline_layout(pipeline, nir, prog_data, map);
376
377 /* nir_lower_io will only handle the push constants; we need to set this
378 * to the full number of possible uniforms.
379 */
380 nir->num_uniforms = prog_data->nr_params * 4;
381
382 return nir;
383 }
384
385 static void
386 anv_fill_binding_table(struct brw_stage_prog_data *prog_data, unsigned bias)
387 {
388 prog_data->binding_table.size_bytes = 0;
389 prog_data->binding_table.texture_start = bias;
390 prog_data->binding_table.gather_texture_start = bias;
391 prog_data->binding_table.ubo_start = bias;
392 prog_data->binding_table.ssbo_start = bias;
393 prog_data->binding_table.image_start = bias;
394 }
395
396 static struct anv_shader_bin *
397 anv_pipeline_upload_kernel(struct anv_pipeline *pipeline,
398 struct anv_pipeline_cache *cache,
399 const void *key_data, uint32_t key_size,
400 const void *kernel_data, uint32_t kernel_size,
401 const struct brw_stage_prog_data *prog_data,
402 uint32_t prog_data_size,
403 const struct anv_pipeline_bind_map *bind_map)
404 {
405 if (cache) {
406 return anv_pipeline_cache_upload_kernel(cache, key_data, key_size,
407 kernel_data, kernel_size,
408 prog_data, prog_data_size,
409 bind_map);
410 } else {
411 return anv_shader_bin_create(pipeline->device, key_data, key_size,
412 kernel_data, kernel_size,
413 prog_data, prog_data_size,
414 prog_data->param, bind_map);
415 }
416 }
417
418
419 static void
420 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
421 gl_shader_stage stage,
422 struct anv_shader_bin *shader)
423 {
424 pipeline->shaders[stage] = shader;
425 pipeline->active_stages |= mesa_to_vk_shader_stage(stage);
426 }
427
428 static VkResult
429 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
430 struct anv_pipeline_cache *cache,
431 const VkGraphicsPipelineCreateInfo *info,
432 struct anv_shader_module *module,
433 const char *entrypoint,
434 const VkSpecializationInfo *spec_info)
435 {
436 const struct brw_compiler *compiler =
437 pipeline->device->instance->physicalDevice.compiler;
438 struct anv_pipeline_bind_map map;
439 struct brw_vs_prog_key key;
440 struct anv_shader_bin *bin = NULL;
441 unsigned char sha1[20];
442
443 populate_vs_prog_key(&pipeline->device->info, &key);
444
445 if (cache) {
446 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint,
447 pipeline->layout, spec_info);
448 bin = anv_pipeline_cache_search(cache, sha1, 20);
449 }
450
451 if (bin == NULL) {
452 struct brw_vs_prog_data prog_data = { 0, };
453 struct anv_pipeline_binding surface_to_descriptor[256];
454 struct anv_pipeline_binding sampler_to_descriptor[256];
455
456 map = (struct anv_pipeline_bind_map) {
457 .surface_to_descriptor = surface_to_descriptor,
458 .sampler_to_descriptor = sampler_to_descriptor
459 };
460
461 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
462 MESA_SHADER_VERTEX, spec_info,
463 &prog_data.base.base, &map);
464 if (nir == NULL)
465 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
466
467 anv_fill_binding_table(&prog_data.base.base, 0);
468
469 void *mem_ctx = ralloc_context(NULL);
470
471 ralloc_steal(mem_ctx, nir);
472
473 prog_data.inputs_read = nir->info->inputs_read;
474 prog_data.double_inputs_read = nir->info->double_inputs_read;
475
476 brw_compute_vue_map(&pipeline->device->info,
477 &prog_data.base.vue_map,
478 nir->info->outputs_written,
479 nir->info->separate_shader);
480
481 unsigned code_size;
482 const unsigned *shader_code =
483 brw_compile_vs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
484 NULL, false, -1, &code_size, NULL);
485 if (shader_code == NULL) {
486 ralloc_free(mem_ctx);
487 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
488 }
489
490 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
491 shader_code, code_size,
492 &prog_data.base.base, sizeof(prog_data),
493 &map);
494 if (!bin) {
495 ralloc_free(mem_ctx);
496 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
497 }
498
499 ralloc_free(mem_ctx);
500 }
501
502 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX, bin);
503
504 return VK_SUCCESS;
505 }
506
507 static void
508 merge_tess_info(struct shader_info *tes_info,
509 const struct shader_info *tcs_info)
510 {
511 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
512 *
513 * "PointMode. Controls generation of points rather than triangles
514 * or lines. This functionality defaults to disabled, and is
515 * enabled if either shader stage includes the execution mode.
516 *
517 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
518 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
519 * and OutputVertices, it says:
520 *
521 * "One mode must be set in at least one of the tessellation
522 * shader stages."
523 *
524 * So, the fields can be set in either the TCS or TES, but they must
525 * agree if set in both. Our backend looks at TES, so bitwise-or in
526 * the values from the TCS.
527 */
528 assert(tcs_info->tess.tcs_vertices_out == 0 ||
529 tes_info->tess.tcs_vertices_out == 0 ||
530 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
531 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
532
533 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
534 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
535 tcs_info->tess.spacing == tes_info->tess.spacing);
536 tes_info->tess.spacing |= tcs_info->tess.spacing;
537
538 tes_info->tess.ccw |= tcs_info->tess.ccw;
539 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
540 }
541
542 static VkResult
543 anv_pipeline_compile_tcs_tes(struct anv_pipeline *pipeline,
544 struct anv_pipeline_cache *cache,
545 const VkGraphicsPipelineCreateInfo *info,
546 struct anv_shader_module *tcs_module,
547 const char *tcs_entrypoint,
548 const VkSpecializationInfo *tcs_spec_info,
549 struct anv_shader_module *tes_module,
550 const char *tes_entrypoint,
551 const VkSpecializationInfo *tes_spec_info)
552 {
553 const struct gen_device_info *devinfo = &pipeline->device->info;
554 const struct brw_compiler *compiler =
555 pipeline->device->instance->physicalDevice.compiler;
556 struct anv_pipeline_bind_map tcs_map;
557 struct anv_pipeline_bind_map tes_map;
558 struct brw_tcs_prog_key tcs_key = { 0, };
559 struct brw_tes_prog_key tes_key = { 0, };
560 struct anv_shader_bin *tcs_bin = NULL;
561 struct anv_shader_bin *tes_bin = NULL;
562 unsigned char tcs_sha1[40];
563 unsigned char tes_sha1[40];
564
565 populate_sampler_prog_key(&pipeline->device->info, &tcs_key.tex);
566 populate_sampler_prog_key(&pipeline->device->info, &tes_key.tex);
567 tcs_key.input_vertices = info->pTessellationState->patchControlPoints;
568
569 if (cache) {
570 anv_hash_shader(tcs_sha1, &tcs_key, sizeof(tcs_key), tcs_module,
571 tcs_entrypoint, pipeline->layout, tcs_spec_info);
572 anv_hash_shader(tes_sha1, &tes_key, sizeof(tes_key), tes_module,
573 tes_entrypoint, pipeline->layout, tes_spec_info);
574 memcpy(&tcs_sha1[20], tes_sha1, 20);
575 memcpy(&tes_sha1[20], tcs_sha1, 20);
576 tcs_bin = anv_pipeline_cache_search(cache, tcs_sha1, sizeof(tcs_sha1));
577 tes_bin = anv_pipeline_cache_search(cache, tes_sha1, sizeof(tes_sha1));
578 }
579
580 if (tcs_bin == NULL || tes_bin == NULL) {
581 struct brw_tcs_prog_data tcs_prog_data = { 0, };
582 struct brw_tes_prog_data tes_prog_data = { 0, };
583 struct anv_pipeline_binding tcs_surface_to_descriptor[256];
584 struct anv_pipeline_binding tcs_sampler_to_descriptor[256];
585 struct anv_pipeline_binding tes_surface_to_descriptor[256];
586 struct anv_pipeline_binding tes_sampler_to_descriptor[256];
587
588 tcs_map = (struct anv_pipeline_bind_map) {
589 .surface_to_descriptor = tcs_surface_to_descriptor,
590 .sampler_to_descriptor = tcs_sampler_to_descriptor
591 };
592 tes_map = (struct anv_pipeline_bind_map) {
593 .surface_to_descriptor = tes_surface_to_descriptor,
594 .sampler_to_descriptor = tes_sampler_to_descriptor
595 };
596
597 nir_shader *tcs_nir =
598 anv_pipeline_compile(pipeline, tcs_module, tcs_entrypoint,
599 MESA_SHADER_TESS_CTRL, tcs_spec_info,
600 &tcs_prog_data.base.base, &tcs_map);
601 nir_shader *tes_nir =
602 anv_pipeline_compile(pipeline, tes_module, tes_entrypoint,
603 MESA_SHADER_TESS_EVAL, tes_spec_info,
604 &tes_prog_data.base.base, &tes_map);
605 if (tcs_nir == NULL || tes_nir == NULL)
606 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
607
608 nir_lower_tes_patch_vertices(tes_nir,
609 tcs_nir->info->tess.tcs_vertices_out);
610
611 /* Copy TCS info into the TES info */
612 merge_tess_info(tes_nir->info, tcs_nir->info);
613
614 anv_fill_binding_table(&tcs_prog_data.base.base, 0);
615 anv_fill_binding_table(&tes_prog_data.base.base, 0);
616
617 void *mem_ctx = ralloc_context(NULL);
618
619 ralloc_steal(mem_ctx, tcs_nir);
620 ralloc_steal(mem_ctx, tes_nir);
621
622 /* Whacking the key after cache lookup is a bit sketchy, but all of
623 * this comes from the SPIR-V, which is part of the hash used for the
624 * pipeline cache. So it should be safe.
625 */
626 tcs_key.tes_primitive_mode = tes_nir->info->tess.primitive_mode;
627 tcs_key.outputs_written = tcs_nir->info->outputs_written;
628 tcs_key.patch_outputs_written = tcs_nir->info->patch_outputs_written;
629 tcs_key.quads_workaround =
630 devinfo->gen < 9 &&
631 tes_nir->info->tess.primitive_mode == 7 /* GL_QUADS */ &&
632 tes_nir->info->tess.spacing == TESS_SPACING_EQUAL;
633
634 tes_key.inputs_read = tcs_key.outputs_written;
635 tes_key.patch_inputs_read = tcs_key.patch_outputs_written;
636
637 unsigned code_size;
638 const int shader_time_index = -1;
639 const unsigned *shader_code;
640
641 shader_code =
642 brw_compile_tcs(compiler, NULL, mem_ctx, &tcs_key, &tcs_prog_data,
643 tcs_nir, shader_time_index, &code_size, NULL);
644 if (shader_code == NULL) {
645 ralloc_free(mem_ctx);
646 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
647 }
648
649 tcs_bin = anv_pipeline_upload_kernel(pipeline, cache,
650 tcs_sha1, sizeof(tcs_sha1),
651 shader_code, code_size,
652 &tcs_prog_data.base.base,
653 sizeof(tcs_prog_data),
654 &tcs_map);
655 if (!tcs_bin) {
656 ralloc_free(mem_ctx);
657 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
658 }
659
660 shader_code =
661 brw_compile_tes(compiler, NULL, mem_ctx, &tes_key,
662 &tcs_prog_data.base.vue_map, &tes_prog_data, tes_nir,
663 NULL, shader_time_index, &code_size, NULL);
664 if (shader_code == NULL) {
665 ralloc_free(mem_ctx);
666 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
667 }
668
669 tes_bin = anv_pipeline_upload_kernel(pipeline, cache,
670 tes_sha1, sizeof(tes_sha1),
671 shader_code, code_size,
672 &tes_prog_data.base.base,
673 sizeof(tes_prog_data),
674 &tes_map);
675 if (!tes_bin) {
676 ralloc_free(mem_ctx);
677 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
678 }
679
680 ralloc_free(mem_ctx);
681 }
682
683 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_TESS_CTRL, tcs_bin);
684 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_TESS_EVAL, tes_bin);
685
686 return VK_SUCCESS;
687 }
688
689 static VkResult
690 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
691 struct anv_pipeline_cache *cache,
692 const VkGraphicsPipelineCreateInfo *info,
693 struct anv_shader_module *module,
694 const char *entrypoint,
695 const VkSpecializationInfo *spec_info)
696 {
697 const struct brw_compiler *compiler =
698 pipeline->device->instance->physicalDevice.compiler;
699 struct anv_pipeline_bind_map map;
700 struct brw_gs_prog_key key;
701 struct anv_shader_bin *bin = NULL;
702 unsigned char sha1[20];
703
704 populate_gs_prog_key(&pipeline->device->info, &key);
705
706 if (cache) {
707 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint,
708 pipeline->layout, spec_info);
709 bin = anv_pipeline_cache_search(cache, sha1, 20);
710 }
711
712 if (bin == NULL) {
713 struct brw_gs_prog_data prog_data = { 0, };
714 struct anv_pipeline_binding surface_to_descriptor[256];
715 struct anv_pipeline_binding sampler_to_descriptor[256];
716
717 map = (struct anv_pipeline_bind_map) {
718 .surface_to_descriptor = surface_to_descriptor,
719 .sampler_to_descriptor = sampler_to_descriptor
720 };
721
722 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
723 MESA_SHADER_GEOMETRY, spec_info,
724 &prog_data.base.base, &map);
725 if (nir == NULL)
726 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
727
728 anv_fill_binding_table(&prog_data.base.base, 0);
729
730 void *mem_ctx = ralloc_context(NULL);
731
732 ralloc_steal(mem_ctx, nir);
733
734 brw_compute_vue_map(&pipeline->device->info,
735 &prog_data.base.vue_map,
736 nir->info->outputs_written,
737 nir->info->separate_shader);
738
739 unsigned code_size;
740 const unsigned *shader_code =
741 brw_compile_gs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
742 NULL, -1, &code_size, NULL);
743 if (shader_code == NULL) {
744 ralloc_free(mem_ctx);
745 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
746 }
747
748 /* TODO: SIMD8 GS */
749 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
750 shader_code, code_size,
751 &prog_data.base.base, sizeof(prog_data),
752 &map);
753 if (!bin) {
754 ralloc_free(mem_ctx);
755 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
756 }
757
758 ralloc_free(mem_ctx);
759 }
760
761 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY, bin);
762
763 return VK_SUCCESS;
764 }
765
766 static VkResult
767 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
768 struct anv_pipeline_cache *cache,
769 const VkGraphicsPipelineCreateInfo *info,
770 struct anv_shader_module *module,
771 const char *entrypoint,
772 const VkSpecializationInfo *spec_info)
773 {
774 const struct brw_compiler *compiler =
775 pipeline->device->instance->physicalDevice.compiler;
776 struct anv_pipeline_bind_map map;
777 struct brw_wm_prog_key key;
778 struct anv_shader_bin *bin = NULL;
779 unsigned char sha1[20];
780
781 populate_wm_prog_key(pipeline, info, &key);
782
783 if (cache) {
784 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint,
785 pipeline->layout, spec_info);
786 bin = anv_pipeline_cache_search(cache, sha1, 20);
787 }
788
789 if (bin == NULL) {
790 struct brw_wm_prog_data prog_data = { 0, };
791 struct anv_pipeline_binding surface_to_descriptor[256];
792 struct anv_pipeline_binding sampler_to_descriptor[256];
793
794 map = (struct anv_pipeline_bind_map) {
795 .surface_to_descriptor = surface_to_descriptor + 8,
796 .sampler_to_descriptor = sampler_to_descriptor
797 };
798
799 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
800 MESA_SHADER_FRAGMENT, spec_info,
801 &prog_data.base, &map);
802 if (nir == NULL)
803 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
804
805 unsigned num_rts = 0;
806 struct anv_pipeline_binding rt_bindings[8];
807 nir_function_impl *impl = nir_shader_get_entrypoint(nir);
808 nir_foreach_variable_safe(var, &nir->outputs) {
809 if (var->data.location < FRAG_RESULT_DATA0)
810 continue;
811
812 unsigned rt = var->data.location - FRAG_RESULT_DATA0;
813 if (rt >= key.nr_color_regions) {
814 /* Out-of-bounds, throw it away */
815 var->data.mode = nir_var_local;
816 exec_node_remove(&var->node);
817 exec_list_push_tail(&impl->locals, &var->node);
818 continue;
819 }
820
821 /* Give it a new, compacted, location */
822 var->data.location = FRAG_RESULT_DATA0 + num_rts;
823
824 unsigned array_len =
825 glsl_type_is_array(var->type) ? glsl_get_length(var->type) : 1;
826 assert(num_rts + array_len <= 8);
827
828 for (unsigned i = 0; i < array_len; i++) {
829 rt_bindings[num_rts + i] = (struct anv_pipeline_binding) {
830 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
831 .binding = 0,
832 .index = rt + i,
833 };
834 }
835
836 num_rts += array_len;
837 }
838
839 if (num_rts == 0) {
840 /* If we have no render targets, we need a null render target */
841 rt_bindings[0] = (struct anv_pipeline_binding) {
842 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
843 .binding = 0,
844 .index = UINT8_MAX,
845 };
846 num_rts = 1;
847 }
848
849 assert(num_rts <= 8);
850 map.surface_to_descriptor -= num_rts;
851 map.surface_count += num_rts;
852 assert(map.surface_count <= 256);
853 memcpy(map.surface_to_descriptor, rt_bindings,
854 num_rts * sizeof(*rt_bindings));
855
856 anv_fill_binding_table(&prog_data.base, num_rts);
857
858 void *mem_ctx = ralloc_context(NULL);
859
860 ralloc_steal(mem_ctx, nir);
861
862 unsigned code_size;
863 const unsigned *shader_code =
864 brw_compile_fs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
865 NULL, -1, -1, true, false, NULL, &code_size, NULL);
866 if (shader_code == NULL) {
867 ralloc_free(mem_ctx);
868 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
869 }
870
871 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
872 shader_code, code_size,
873 &prog_data.base, sizeof(prog_data),
874 &map);
875 if (!bin) {
876 ralloc_free(mem_ctx);
877 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
878 }
879
880 ralloc_free(mem_ctx);
881 }
882
883 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT, bin);
884
885 return VK_SUCCESS;
886 }
887
888 VkResult
889 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
890 struct anv_pipeline_cache *cache,
891 const VkComputePipelineCreateInfo *info,
892 struct anv_shader_module *module,
893 const char *entrypoint,
894 const VkSpecializationInfo *spec_info)
895 {
896 const struct brw_compiler *compiler =
897 pipeline->device->instance->physicalDevice.compiler;
898 struct anv_pipeline_bind_map map;
899 struct brw_cs_prog_key key;
900 struct anv_shader_bin *bin = NULL;
901 unsigned char sha1[20];
902
903 populate_cs_prog_key(&pipeline->device->info, &key);
904
905 if (cache) {
906 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint,
907 pipeline->layout, spec_info);
908 bin = anv_pipeline_cache_search(cache, sha1, 20);
909 }
910
911 if (bin == NULL) {
912 struct brw_cs_prog_data prog_data = { 0, };
913 struct anv_pipeline_binding surface_to_descriptor[256];
914 struct anv_pipeline_binding sampler_to_descriptor[256];
915
916 map = (struct anv_pipeline_bind_map) {
917 .surface_to_descriptor = surface_to_descriptor,
918 .sampler_to_descriptor = sampler_to_descriptor
919 };
920
921 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
922 MESA_SHADER_COMPUTE, spec_info,
923 &prog_data.base, &map);
924 if (nir == NULL)
925 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
926
927 anv_fill_binding_table(&prog_data.base, 1);
928
929 void *mem_ctx = ralloc_context(NULL);
930
931 ralloc_steal(mem_ctx, nir);
932
933 unsigned code_size;
934 const unsigned *shader_code =
935 brw_compile_cs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
936 -1, &code_size, NULL);
937 if (shader_code == NULL) {
938 ralloc_free(mem_ctx);
939 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
940 }
941
942 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
943 shader_code, code_size,
944 &prog_data.base, sizeof(prog_data),
945 &map);
946 if (!bin) {
947 ralloc_free(mem_ctx);
948 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
949 }
950
951 ralloc_free(mem_ctx);
952 }
953
954 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE, bin);
955
956 return VK_SUCCESS;
957 }
958
959 /**
960 * Copy pipeline state not marked as dynamic.
961 * Dynamic state is pipeline state which hasn't been provided at pipeline
962 * creation time, but is dynamically provided afterwards using various
963 * vkCmdSet* functions.
964 *
965 * The set of state considered "non_dynamic" is determined by the pieces of
966 * state that have their corresponding VkDynamicState enums omitted from
967 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
968 *
969 * @param[out] pipeline Destination non_dynamic state.
970 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
971 */
972 static void
973 copy_non_dynamic_state(struct anv_pipeline *pipeline,
974 const VkGraphicsPipelineCreateInfo *pCreateInfo)
975 {
976 anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
977 ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
978 struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
979
980 pipeline->dynamic_state = default_dynamic_state;
981
982 if (pCreateInfo->pDynamicState) {
983 /* Remove all of the states that are marked as dynamic */
984 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
985 for (uint32_t s = 0; s < count; s++)
986 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
987 }
988
989 struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
990
991 /* Section 9.2 of the Vulkan 1.0.15 spec says:
992 *
993 * pViewportState is [...] NULL if the pipeline
994 * has rasterization disabled.
995 */
996 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
997 assert(pCreateInfo->pViewportState);
998
999 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1000 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1001 typed_memcpy(dynamic->viewport.viewports,
1002 pCreateInfo->pViewportState->pViewports,
1003 pCreateInfo->pViewportState->viewportCount);
1004 }
1005
1006 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1007 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1008 typed_memcpy(dynamic->scissor.scissors,
1009 pCreateInfo->pViewportState->pScissors,
1010 pCreateInfo->pViewportState->scissorCount);
1011 }
1012 }
1013
1014 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1015 assert(pCreateInfo->pRasterizationState);
1016 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1017 }
1018
1019 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1020 assert(pCreateInfo->pRasterizationState);
1021 dynamic->depth_bias.bias =
1022 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1023 dynamic->depth_bias.clamp =
1024 pCreateInfo->pRasterizationState->depthBiasClamp;
1025 dynamic->depth_bias.slope =
1026 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1027 }
1028
1029 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1030 *
1031 * pColorBlendState is [...] NULL if the pipeline has rasterization
1032 * disabled or if the subpass of the render pass the pipeline is
1033 * created against does not use any color attachments.
1034 */
1035 bool uses_color_att = false;
1036 for (unsigned i = 0; i < subpass->color_count; ++i) {
1037 if (subpass->color_attachments[i] != VK_ATTACHMENT_UNUSED) {
1038 uses_color_att = true;
1039 break;
1040 }
1041 }
1042
1043 if (uses_color_att &&
1044 !pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1045 assert(pCreateInfo->pColorBlendState);
1046
1047 if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
1048 typed_memcpy(dynamic->blend_constants,
1049 pCreateInfo->pColorBlendState->blendConstants, 4);
1050 }
1051
1052 /* If there is no depthstencil attachment, then don't read
1053 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1054 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1055 * no need to override the depthstencil defaults in
1056 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1057 *
1058 * Section 9.2 of the Vulkan 1.0.15 spec says:
1059 *
1060 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1061 * disabled or if the subpass of the render pass the pipeline is created
1062 * against does not use a depth/stencil attachment.
1063 */
1064 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1065 subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
1066 assert(pCreateInfo->pDepthStencilState);
1067
1068 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1069 dynamic->depth_bounds.min =
1070 pCreateInfo->pDepthStencilState->minDepthBounds;
1071 dynamic->depth_bounds.max =
1072 pCreateInfo->pDepthStencilState->maxDepthBounds;
1073 }
1074
1075 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1076 dynamic->stencil_compare_mask.front =
1077 pCreateInfo->pDepthStencilState->front.compareMask;
1078 dynamic->stencil_compare_mask.back =
1079 pCreateInfo->pDepthStencilState->back.compareMask;
1080 }
1081
1082 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1083 dynamic->stencil_write_mask.front =
1084 pCreateInfo->pDepthStencilState->front.writeMask;
1085 dynamic->stencil_write_mask.back =
1086 pCreateInfo->pDepthStencilState->back.writeMask;
1087 }
1088
1089 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1090 dynamic->stencil_reference.front =
1091 pCreateInfo->pDepthStencilState->front.reference;
1092 dynamic->stencil_reference.back =
1093 pCreateInfo->pDepthStencilState->back.reference;
1094 }
1095 }
1096
1097 pipeline->dynamic_state_mask = states;
1098 }
1099
1100 static void
1101 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
1102 {
1103 struct anv_render_pass *renderpass = NULL;
1104 struct anv_subpass *subpass = NULL;
1105
1106 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1107 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1108 */
1109 assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
1110
1111 renderpass = anv_render_pass_from_handle(info->renderPass);
1112 assert(renderpass);
1113
1114 assert(info->subpass < renderpass->subpass_count);
1115 subpass = &renderpass->subpasses[info->subpass];
1116
1117 assert(info->stageCount >= 1);
1118 assert(info->pVertexInputState);
1119 assert(info->pInputAssemblyState);
1120 assert(info->pRasterizationState);
1121 if (!info->pRasterizationState->rasterizerDiscardEnable) {
1122 assert(info->pViewportState);
1123 assert(info->pMultisampleState);
1124
1125 if (subpass && subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED)
1126 assert(info->pDepthStencilState);
1127
1128 if (subpass && subpass->color_count > 0)
1129 assert(info->pColorBlendState);
1130 }
1131
1132 for (uint32_t i = 0; i < info->stageCount; ++i) {
1133 switch (info->pStages[i].stage) {
1134 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
1135 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
1136 assert(info->pTessellationState);
1137 break;
1138 default:
1139 break;
1140 }
1141 }
1142 }
1143
1144 /**
1145 * Calculate the desired L3 partitioning based on the current state of the
1146 * pipeline. For now this simply returns the conservative defaults calculated
1147 * by get_default_l3_weights(), but we could probably do better by gathering
1148 * more statistics from the pipeline state (e.g. guess of expected URB usage
1149 * and bound surfaces), or by using feed-back from performance counters.
1150 */
1151 void
1152 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm)
1153 {
1154 const struct gen_device_info *devinfo = &pipeline->device->info;
1155
1156 const struct gen_l3_weights w =
1157 gen_get_default_l3_weights(devinfo, pipeline->needs_data_cache, needs_slm);
1158
1159 pipeline->urb.l3_config = gen_get_l3_config(devinfo, w);
1160 pipeline->urb.total_size =
1161 gen_get_l3_config_urb_size(devinfo, pipeline->urb.l3_config);
1162 }
1163
1164 VkResult
1165 anv_pipeline_init(struct anv_pipeline *pipeline,
1166 struct anv_device *device,
1167 struct anv_pipeline_cache *cache,
1168 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1169 const VkAllocationCallbacks *alloc)
1170 {
1171 VkResult result;
1172
1173 anv_validate {
1174 anv_pipeline_validate_create_info(pCreateInfo);
1175 }
1176
1177 if (alloc == NULL)
1178 alloc = &device->alloc;
1179
1180 pipeline->device = device;
1181 pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
1182
1183 result = anv_reloc_list_init(&pipeline->batch_relocs, alloc);
1184 if (result != VK_SUCCESS)
1185 return result;
1186
1187 pipeline->batch.alloc = alloc;
1188 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
1189 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
1190 pipeline->batch.relocs = &pipeline->batch_relocs;
1191
1192 copy_non_dynamic_state(pipeline, pCreateInfo);
1193 pipeline->depth_clamp_enable = pCreateInfo->pRasterizationState &&
1194 pCreateInfo->pRasterizationState->depthClampEnable;
1195
1196 pipeline->needs_data_cache = false;
1197
1198 /* When we free the pipeline, we detect stages based on the NULL status
1199 * of various prog_data pointers. Make them NULL by default.
1200 */
1201 memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
1202
1203 pipeline->active_stages = 0;
1204
1205 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1206 struct anv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1207 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1208 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1209 pStages[stage] = &pCreateInfo->pStages[i];
1210 modules[stage] = anv_shader_module_from_handle(pStages[stage]->module);
1211 }
1212
1213 if (modules[MESA_SHADER_VERTEX]) {
1214 result = anv_pipeline_compile_vs(pipeline, cache, pCreateInfo,
1215 modules[MESA_SHADER_VERTEX],
1216 pStages[MESA_SHADER_VERTEX]->pName,
1217 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo);
1218 if (result != VK_SUCCESS)
1219 goto compile_fail;
1220 }
1221
1222 if (modules[MESA_SHADER_TESS_EVAL]) {
1223 anv_pipeline_compile_tcs_tes(pipeline, cache, pCreateInfo,
1224 modules[MESA_SHADER_TESS_CTRL],
1225 pStages[MESA_SHADER_TESS_CTRL]->pName,
1226 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
1227 modules[MESA_SHADER_TESS_EVAL],
1228 pStages[MESA_SHADER_TESS_EVAL]->pName,
1229 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo);
1230 }
1231
1232 if (modules[MESA_SHADER_GEOMETRY]) {
1233 result = anv_pipeline_compile_gs(pipeline, cache, pCreateInfo,
1234 modules[MESA_SHADER_GEOMETRY],
1235 pStages[MESA_SHADER_GEOMETRY]->pName,
1236 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo);
1237 if (result != VK_SUCCESS)
1238 goto compile_fail;
1239 }
1240
1241 if (modules[MESA_SHADER_FRAGMENT]) {
1242 result = anv_pipeline_compile_fs(pipeline, cache, pCreateInfo,
1243 modules[MESA_SHADER_FRAGMENT],
1244 pStages[MESA_SHADER_FRAGMENT]->pName,
1245 pStages[MESA_SHADER_FRAGMENT]->pSpecializationInfo);
1246 if (result != VK_SUCCESS)
1247 goto compile_fail;
1248 }
1249
1250 assert(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT);
1251
1252 anv_pipeline_setup_l3_config(pipeline, false);
1253
1254 const VkPipelineVertexInputStateCreateInfo *vi_info =
1255 pCreateInfo->pVertexInputState;
1256
1257 const uint64_t inputs_read = get_vs_prog_data(pipeline)->inputs_read;
1258
1259 pipeline->vb_used = 0;
1260 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1261 const VkVertexInputAttributeDescription *desc =
1262 &vi_info->pVertexAttributeDescriptions[i];
1263
1264 if (inputs_read & (1 << (VERT_ATTRIB_GENERIC0 + desc->location)))
1265 pipeline->vb_used |= 1 << desc->binding;
1266 }
1267
1268 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1269 const VkVertexInputBindingDescription *desc =
1270 &vi_info->pVertexBindingDescriptions[i];
1271
1272 pipeline->binding_stride[desc->binding] = desc->stride;
1273
1274 /* Step rate is programmed per vertex element (attribute), not
1275 * binding. Set up a map of which bindings step per instance, for
1276 * reference by vertex element setup. */
1277 switch (desc->inputRate) {
1278 default:
1279 case VK_VERTEX_INPUT_RATE_VERTEX:
1280 pipeline->instancing_enable[desc->binding] = false;
1281 break;
1282 case VK_VERTEX_INPUT_RATE_INSTANCE:
1283 pipeline->instancing_enable[desc->binding] = true;
1284 break;
1285 }
1286 }
1287
1288 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1289 pCreateInfo->pInputAssemblyState;
1290 const VkPipelineTessellationStateCreateInfo *tess_info =
1291 pCreateInfo->pTessellationState;
1292 pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1293
1294 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
1295 pipeline->topology = _3DPRIM_PATCHLIST(tess_info->patchControlPoints);
1296 else
1297 pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1298
1299 return VK_SUCCESS;
1300
1301 compile_fail:
1302 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
1303 if (pipeline->shaders[s])
1304 anv_shader_bin_unref(device, pipeline->shaders[s]);
1305 }
1306
1307 anv_reloc_list_finish(&pipeline->batch_relocs, alloc);
1308
1309 return result;
1310 }