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anv: Add support for SPIR-V 1.3 subgroup operations
[mesa.git] / src / intel / vulkan / anv_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "util/mesa-sha1.h"
31 #include "common/gen_l3_config.h"
32 #include "anv_private.h"
33 #include "compiler/brw_nir.h"
34 #include "anv_nir.h"
35 #include "spirv/nir_spirv.h"
36
37 /* Needed for SWIZZLE macros */
38 #include "program/prog_instruction.h"
39
40 // Shader functions
41
42 VkResult anv_CreateShaderModule(
43 VkDevice _device,
44 const VkShaderModuleCreateInfo* pCreateInfo,
45 const VkAllocationCallbacks* pAllocator,
46 VkShaderModule* pShaderModule)
47 {
48 ANV_FROM_HANDLE(anv_device, device, _device);
49 struct anv_shader_module *module;
50
51 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
52 assert(pCreateInfo->flags == 0);
53
54 module = vk_alloc2(&device->alloc, pAllocator,
55 sizeof(*module) + pCreateInfo->codeSize, 8,
56 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
57 if (module == NULL)
58 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
59
60 module->size = pCreateInfo->codeSize;
61 memcpy(module->data, pCreateInfo->pCode, module->size);
62
63 _mesa_sha1_compute(module->data, module->size, module->sha1);
64
65 *pShaderModule = anv_shader_module_to_handle(module);
66
67 return VK_SUCCESS;
68 }
69
70 void anv_DestroyShaderModule(
71 VkDevice _device,
72 VkShaderModule _module,
73 const VkAllocationCallbacks* pAllocator)
74 {
75 ANV_FROM_HANDLE(anv_device, device, _device);
76 ANV_FROM_HANDLE(anv_shader_module, module, _module);
77
78 if (!module)
79 return;
80
81 vk_free2(&device->alloc, pAllocator, module);
82 }
83
84 #define SPIR_V_MAGIC_NUMBER 0x07230203
85
86 static const uint64_t stage_to_debug[] = {
87 [MESA_SHADER_VERTEX] = DEBUG_VS,
88 [MESA_SHADER_TESS_CTRL] = DEBUG_TCS,
89 [MESA_SHADER_TESS_EVAL] = DEBUG_TES,
90 [MESA_SHADER_GEOMETRY] = DEBUG_GS,
91 [MESA_SHADER_FRAGMENT] = DEBUG_WM,
92 [MESA_SHADER_COMPUTE] = DEBUG_CS,
93 };
94
95 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
96 * we can't do that yet because we don't have the ability to copy nir.
97 */
98 static nir_shader *
99 anv_shader_compile_to_nir(struct anv_pipeline *pipeline,
100 void *mem_ctx,
101 struct anv_shader_module *module,
102 const char *entrypoint_name,
103 gl_shader_stage stage,
104 const VkSpecializationInfo *spec_info)
105 {
106 const struct anv_device *device = pipeline->device;
107
108 const struct brw_compiler *compiler =
109 device->instance->physicalDevice.compiler;
110 const nir_shader_compiler_options *nir_options =
111 compiler->glsl_compiler_options[stage].NirOptions;
112
113 uint32_t *spirv = (uint32_t *) module->data;
114 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
115 assert(module->size % 4 == 0);
116
117 uint32_t num_spec_entries = 0;
118 struct nir_spirv_specialization *spec_entries = NULL;
119 if (spec_info && spec_info->mapEntryCount > 0) {
120 num_spec_entries = spec_info->mapEntryCount;
121 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
122 for (uint32_t i = 0; i < num_spec_entries; i++) {
123 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
124 const void *data = spec_info->pData + entry.offset;
125 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
126
127 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
128 if (spec_info->dataSize == 8)
129 spec_entries[i].data64 = *(const uint64_t *)data;
130 else
131 spec_entries[i].data32 = *(const uint32_t *)data;
132 }
133 }
134
135 struct spirv_to_nir_options spirv_options = {
136 .lower_workgroup_access_to_offsets = true,
137 .caps = {
138 .float64 = device->instance->physicalDevice.info.gen >= 8,
139 .int64 = device->instance->physicalDevice.info.gen >= 8,
140 .tessellation = true,
141 .device_group = true,
142 .draw_parameters = true,
143 .image_write_without_format = true,
144 .multiview = true,
145 .variable_pointers = true,
146 .storage_16bit = device->instance->physicalDevice.info.gen >= 8,
147 .subgroup_arithmetic = true,
148 .subgroup_basic = true,
149 .subgroup_ballot = true,
150 .subgroup_quad = true,
151 .subgroup_shuffle = true,
152 .subgroup_vote = true,
153 },
154 };
155
156 nir_function *entry_point =
157 spirv_to_nir(spirv, module->size / 4,
158 spec_entries, num_spec_entries,
159 stage, entrypoint_name, &spirv_options, nir_options);
160 nir_shader *nir = entry_point->shader;
161 assert(nir->info.stage == stage);
162 nir_validate_shader(nir);
163 ralloc_steal(mem_ctx, nir);
164
165 free(spec_entries);
166
167 if (unlikely(INTEL_DEBUG & stage_to_debug[stage])) {
168 fprintf(stderr, "NIR (from SPIR-V) for %s shader:\n",
169 gl_shader_stage_name(stage));
170 nir_print_shader(nir, stderr);
171 }
172
173 /* We have to lower away local constant initializers right before we
174 * inline functions. That way they get properly initialized at the top
175 * of the function and not at the top of its caller.
176 */
177 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
178 NIR_PASS_V(nir, nir_lower_returns);
179 NIR_PASS_V(nir, nir_inline_functions);
180
181 /* Pick off the single entrypoint that we want */
182 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
183 if (func != entry_point)
184 exec_node_remove(&func->node);
185 }
186 assert(exec_list_length(&nir->functions) == 1);
187 entry_point->name = ralloc_strdup(entry_point, "main");
188
189 /* Make sure we lower constant initializers on output variables so that
190 * nir_remove_dead_variables below sees the corresponding stores
191 */
192 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
193
194 NIR_PASS_V(nir, nir_remove_dead_variables,
195 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
196
197 if (stage == MESA_SHADER_FRAGMENT)
198 NIR_PASS_V(nir, nir_lower_wpos_center, pipeline->sample_shading_enable);
199
200 /* Now that we've deleted all but the main function, we can go ahead and
201 * lower the rest of the constant initializers.
202 */
203 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
204 NIR_PASS_V(nir, nir_propagate_invariant);
205 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
206 entry_point->impl, true, false);
207
208 /* Vulkan uses the separate-shader linking model */
209 nir->info.separate_shader = true;
210
211 nir = brw_preprocess_nir(compiler, nir);
212
213 if (stage == MESA_SHADER_FRAGMENT)
214 NIR_PASS_V(nir, anv_nir_lower_input_attachments);
215
216 return nir;
217 }
218
219 void anv_DestroyPipeline(
220 VkDevice _device,
221 VkPipeline _pipeline,
222 const VkAllocationCallbacks* pAllocator)
223 {
224 ANV_FROM_HANDLE(anv_device, device, _device);
225 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
226
227 if (!pipeline)
228 return;
229
230 anv_reloc_list_finish(&pipeline->batch_relocs,
231 pAllocator ? pAllocator : &device->alloc);
232 if (pipeline->blend_state.map)
233 anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
234
235 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
236 if (pipeline->shaders[s])
237 anv_shader_bin_unref(device, pipeline->shaders[s]);
238 }
239
240 vk_free2(&device->alloc, pAllocator, pipeline);
241 }
242
243 static const uint32_t vk_to_gen_primitive_type[] = {
244 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
245 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
246 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
247 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
248 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
249 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
250 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
251 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
252 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
253 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
254 };
255
256 static void
257 populate_sampler_prog_key(const struct gen_device_info *devinfo,
258 struct brw_sampler_prog_key_data *key)
259 {
260 /* Almost all multisampled textures are compressed. The only time when we
261 * don't compress a multisampled texture is for 16x MSAA with a surface
262 * width greater than 8k which is a bit of an edge case. Since the sampler
263 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
264 * to tell the compiler to always assume compression.
265 */
266 key->compressed_multisample_layout_mask = ~0;
267
268 /* SkyLake added support for 16x MSAA. With this came a new message for
269 * reading from a 16x MSAA surface with compression. The new message was
270 * needed because now the MCS data is 64 bits instead of 32 or lower as is
271 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
272 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
273 * so we can just use it unconditionally. This may not be quite as
274 * efficient but it saves us from recompiling.
275 */
276 if (devinfo->gen >= 9)
277 key->msaa_16 = ~0;
278
279 /* XXX: Handle texture swizzle on HSW- */
280 for (int i = 0; i < MAX_SAMPLERS; i++) {
281 /* Assume color sampler, no swizzling. (Works for BDW+) */
282 key->swizzles[i] = SWIZZLE_XYZW;
283 }
284 }
285
286 static void
287 populate_vs_prog_key(const struct gen_device_info *devinfo,
288 struct brw_vs_prog_key *key)
289 {
290 memset(key, 0, sizeof(*key));
291
292 populate_sampler_prog_key(devinfo, &key->tex);
293
294 /* XXX: Handle vertex input work-arounds */
295
296 /* XXX: Handle sampler_prog_key */
297 }
298
299 static void
300 populate_gs_prog_key(const struct gen_device_info *devinfo,
301 struct brw_gs_prog_key *key)
302 {
303 memset(key, 0, sizeof(*key));
304
305 populate_sampler_prog_key(devinfo, &key->tex);
306 }
307
308 static void
309 populate_wm_prog_key(const struct anv_pipeline *pipeline,
310 const VkGraphicsPipelineCreateInfo *info,
311 struct brw_wm_prog_key *key)
312 {
313 const struct gen_device_info *devinfo = &pipeline->device->info;
314
315 memset(key, 0, sizeof(*key));
316
317 populate_sampler_prog_key(devinfo, &key->tex);
318
319 /* TODO: we could set this to 0 based on the information in nir_shader, but
320 * this function is called before spirv_to_nir. */
321 const struct brw_vue_map *vue_map =
322 &anv_pipeline_get_last_vue_prog_data(pipeline)->vue_map;
323 key->input_slots_valid = vue_map->slots_valid;
324
325 /* Vulkan doesn't specify a default */
326 key->high_quality_derivatives = false;
327
328 /* XXX Vulkan doesn't appear to specify */
329 key->clamp_fragment_color = false;
330
331 key->nr_color_regions = pipeline->subpass->color_count;
332
333 key->replicate_alpha = key->nr_color_regions > 1 &&
334 info->pMultisampleState &&
335 info->pMultisampleState->alphaToCoverageEnable;
336
337 if (info->pMultisampleState) {
338 /* We should probably pull this out of the shader, but it's fairly
339 * harmless to compute it and then let dead-code take care of it.
340 */
341 if (info->pMultisampleState->rasterizationSamples > 1) {
342 key->persample_interp =
343 (info->pMultisampleState->minSampleShading *
344 info->pMultisampleState->rasterizationSamples) > 1;
345 key->multisample_fbo = true;
346 }
347
348 key->frag_coord_adds_sample_pos =
349 info->pMultisampleState->sampleShadingEnable;
350 }
351 }
352
353 static void
354 populate_cs_prog_key(const struct gen_device_info *devinfo,
355 struct brw_cs_prog_key *key)
356 {
357 memset(key, 0, sizeof(*key));
358
359 populate_sampler_prog_key(devinfo, &key->tex);
360 }
361
362 static void
363 anv_pipeline_hash_shader(struct anv_pipeline *pipeline,
364 struct anv_pipeline_layout *layout,
365 struct anv_shader_module *module,
366 const char *entrypoint,
367 gl_shader_stage stage,
368 const VkSpecializationInfo *spec_info,
369 const void *key, size_t key_size,
370 unsigned char *sha1_out)
371 {
372 struct mesa_sha1 ctx;
373
374 _mesa_sha1_init(&ctx);
375 if (stage != MESA_SHADER_COMPUTE) {
376 _mesa_sha1_update(&ctx, &pipeline->subpass->view_mask,
377 sizeof(pipeline->subpass->view_mask));
378 }
379 if (layout)
380 _mesa_sha1_update(&ctx, layout->sha1, sizeof(layout->sha1));
381 _mesa_sha1_update(&ctx, module->sha1, sizeof(module->sha1));
382 _mesa_sha1_update(&ctx, entrypoint, strlen(entrypoint));
383 _mesa_sha1_update(&ctx, &stage, sizeof(stage));
384 if (spec_info) {
385 _mesa_sha1_update(&ctx, spec_info->pMapEntries,
386 spec_info->mapEntryCount * sizeof(*spec_info->pMapEntries));
387 _mesa_sha1_update(&ctx, spec_info->pData, spec_info->dataSize);
388 }
389 _mesa_sha1_update(&ctx, key, key_size);
390 _mesa_sha1_final(&ctx, sha1_out);
391 }
392
393 static nir_shader *
394 anv_pipeline_compile(struct anv_pipeline *pipeline,
395 void *mem_ctx,
396 struct anv_pipeline_layout *layout,
397 struct anv_shader_module *module,
398 const char *entrypoint,
399 gl_shader_stage stage,
400 const VkSpecializationInfo *spec_info,
401 struct brw_stage_prog_data *prog_data,
402 struct anv_pipeline_bind_map *map)
403 {
404 const struct brw_compiler *compiler =
405 pipeline->device->instance->physicalDevice.compiler;
406
407 nir_shader *nir = anv_shader_compile_to_nir(pipeline, mem_ctx,
408 module, entrypoint, stage,
409 spec_info);
410 if (nir == NULL)
411 return NULL;
412
413 NIR_PASS_V(nir, anv_nir_lower_ycbcr_textures, layout);
414
415 NIR_PASS_V(nir, anv_nir_lower_push_constants);
416
417 if (stage != MESA_SHADER_COMPUTE)
418 NIR_PASS_V(nir, anv_nir_lower_multiview, pipeline->subpass->view_mask);
419
420 if (stage == MESA_SHADER_COMPUTE)
421 prog_data->total_shared = nir->num_shared;
422
423 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
424
425 if (nir->num_uniforms > 0) {
426 assert(prog_data->nr_params == 0);
427
428 /* If the shader uses any push constants at all, we'll just give
429 * them the maximum possible number
430 */
431 assert(nir->num_uniforms <= MAX_PUSH_CONSTANTS_SIZE);
432 nir->num_uniforms = MAX_PUSH_CONSTANTS_SIZE;
433 prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
434 prog_data->param = ralloc_array(mem_ctx, uint32_t, prog_data->nr_params);
435
436 /* We now set the param values to be offsets into a
437 * anv_push_constant_data structure. Since the compiler doesn't
438 * actually dereference any of the gl_constant_value pointers in the
439 * params array, it doesn't really matter what we put here.
440 */
441 struct anv_push_constants *null_data = NULL;
442 /* Fill out the push constants section of the param array */
443 for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++) {
444 prog_data->param[i] = ANV_PARAM_PUSH(
445 (uintptr_t)&null_data->client_data[i * sizeof(float)]);
446 }
447 }
448
449 if (nir->info.num_ssbos > 0 || nir->info.num_images > 0)
450 pipeline->needs_data_cache = true;
451
452 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
453 if (layout)
454 anv_nir_apply_pipeline_layout(pipeline, layout, nir, prog_data, map);
455
456 if (stage != MESA_SHADER_COMPUTE)
457 brw_nir_analyze_ubo_ranges(compiler, nir, prog_data->ubo_ranges);
458
459 assert(nir->num_uniforms == prog_data->nr_params * 4);
460
461 return nir;
462 }
463
464 static void
465 anv_fill_binding_table(struct brw_stage_prog_data *prog_data, unsigned bias)
466 {
467 prog_data->binding_table.size_bytes = 0;
468 prog_data->binding_table.texture_start = bias;
469 prog_data->binding_table.gather_texture_start = bias;
470 prog_data->binding_table.ubo_start = bias;
471 prog_data->binding_table.ssbo_start = bias;
472 prog_data->binding_table.image_start = bias;
473 }
474
475 static struct anv_shader_bin *
476 anv_pipeline_upload_kernel(struct anv_pipeline *pipeline,
477 struct anv_pipeline_cache *cache,
478 const void *key_data, uint32_t key_size,
479 const void *kernel_data, uint32_t kernel_size,
480 const struct brw_stage_prog_data *prog_data,
481 uint32_t prog_data_size,
482 const struct anv_pipeline_bind_map *bind_map)
483 {
484 if (cache) {
485 return anv_pipeline_cache_upload_kernel(cache, key_data, key_size,
486 kernel_data, kernel_size,
487 prog_data, prog_data_size,
488 bind_map);
489 } else {
490 return anv_shader_bin_create(pipeline->device, key_data, key_size,
491 kernel_data, kernel_size,
492 prog_data, prog_data_size,
493 prog_data->param, bind_map);
494 }
495 }
496
497
498 static void
499 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
500 gl_shader_stage stage,
501 struct anv_shader_bin *shader)
502 {
503 pipeline->shaders[stage] = shader;
504 pipeline->active_stages |= mesa_to_vk_shader_stage(stage);
505 }
506
507 static VkResult
508 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
509 struct anv_pipeline_cache *cache,
510 const VkGraphicsPipelineCreateInfo *info,
511 struct anv_shader_module *module,
512 const char *entrypoint,
513 const VkSpecializationInfo *spec_info)
514 {
515 const struct brw_compiler *compiler =
516 pipeline->device->instance->physicalDevice.compiler;
517 struct brw_vs_prog_key key;
518 struct anv_shader_bin *bin = NULL;
519 unsigned char sha1[20];
520
521 populate_vs_prog_key(&pipeline->device->info, &key);
522
523 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
524
525 if (cache) {
526 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
527 MESA_SHADER_VERTEX, spec_info,
528 &key, sizeof(key), sha1);
529 bin = anv_pipeline_cache_search(cache, sha1, 20);
530 }
531
532 if (bin == NULL) {
533 struct brw_vs_prog_data prog_data = {};
534 struct anv_pipeline_binding surface_to_descriptor[256];
535 struct anv_pipeline_binding sampler_to_descriptor[256];
536
537 struct anv_pipeline_bind_map map = {
538 .surface_to_descriptor = surface_to_descriptor,
539 .sampler_to_descriptor = sampler_to_descriptor
540 };
541
542 void *mem_ctx = ralloc_context(NULL);
543
544 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
545 module, entrypoint,
546 MESA_SHADER_VERTEX, spec_info,
547 &prog_data.base.base, &map);
548 if (nir == NULL) {
549 ralloc_free(mem_ctx);
550 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
551 }
552
553 anv_fill_binding_table(&prog_data.base.base, 0);
554
555 brw_compute_vue_map(&pipeline->device->info,
556 &prog_data.base.vue_map,
557 nir->info.outputs_written,
558 nir->info.separate_shader);
559
560 const unsigned *shader_code =
561 brw_compile_vs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
562 -1, NULL);
563 if (shader_code == NULL) {
564 ralloc_free(mem_ctx);
565 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
566 }
567
568 unsigned code_size = prog_data.base.base.program_size;
569 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
570 shader_code, code_size,
571 &prog_data.base.base, sizeof(prog_data),
572 &map);
573 if (!bin) {
574 ralloc_free(mem_ctx);
575 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
576 }
577
578 ralloc_free(mem_ctx);
579 }
580
581 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX, bin);
582
583 return VK_SUCCESS;
584 }
585
586 static void
587 merge_tess_info(struct shader_info *tes_info,
588 const struct shader_info *tcs_info)
589 {
590 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
591 *
592 * "PointMode. Controls generation of points rather than triangles
593 * or lines. This functionality defaults to disabled, and is
594 * enabled if either shader stage includes the execution mode.
595 *
596 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
597 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
598 * and OutputVertices, it says:
599 *
600 * "One mode must be set in at least one of the tessellation
601 * shader stages."
602 *
603 * So, the fields can be set in either the TCS or TES, but they must
604 * agree if set in both. Our backend looks at TES, so bitwise-or in
605 * the values from the TCS.
606 */
607 assert(tcs_info->tess.tcs_vertices_out == 0 ||
608 tes_info->tess.tcs_vertices_out == 0 ||
609 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
610 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
611
612 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
613 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
614 tcs_info->tess.spacing == tes_info->tess.spacing);
615 tes_info->tess.spacing |= tcs_info->tess.spacing;
616
617 assert(tcs_info->tess.primitive_mode == 0 ||
618 tes_info->tess.primitive_mode == 0 ||
619 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
620 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
621 tes_info->tess.ccw |= tcs_info->tess.ccw;
622 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
623 }
624
625 static VkResult
626 anv_pipeline_compile_tcs_tes(struct anv_pipeline *pipeline,
627 struct anv_pipeline_cache *cache,
628 const VkGraphicsPipelineCreateInfo *info,
629 struct anv_shader_module *tcs_module,
630 const char *tcs_entrypoint,
631 const VkSpecializationInfo *tcs_spec_info,
632 struct anv_shader_module *tes_module,
633 const char *tes_entrypoint,
634 const VkSpecializationInfo *tes_spec_info)
635 {
636 const struct gen_device_info *devinfo = &pipeline->device->info;
637 const struct brw_compiler *compiler =
638 pipeline->device->instance->physicalDevice.compiler;
639 struct brw_tcs_prog_key tcs_key = {};
640 struct brw_tes_prog_key tes_key = {};
641 struct anv_shader_bin *tcs_bin = NULL;
642 struct anv_shader_bin *tes_bin = NULL;
643 unsigned char tcs_sha1[40];
644 unsigned char tes_sha1[40];
645
646 populate_sampler_prog_key(&pipeline->device->info, &tcs_key.tex);
647 populate_sampler_prog_key(&pipeline->device->info, &tes_key.tex);
648 tcs_key.input_vertices = info->pTessellationState->patchControlPoints;
649
650 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
651
652 if (cache) {
653 anv_pipeline_hash_shader(pipeline, layout, tcs_module, tcs_entrypoint,
654 MESA_SHADER_TESS_CTRL, tcs_spec_info,
655 &tcs_key, sizeof(tcs_key), tcs_sha1);
656 anv_pipeline_hash_shader(pipeline, layout, tes_module, tes_entrypoint,
657 MESA_SHADER_TESS_EVAL, tes_spec_info,
658 &tes_key, sizeof(tes_key), tes_sha1);
659 memcpy(&tcs_sha1[20], tes_sha1, 20);
660 memcpy(&tes_sha1[20], tcs_sha1, 20);
661 tcs_bin = anv_pipeline_cache_search(cache, tcs_sha1, sizeof(tcs_sha1));
662 tes_bin = anv_pipeline_cache_search(cache, tes_sha1, sizeof(tes_sha1));
663 }
664
665 if (tcs_bin == NULL || tes_bin == NULL) {
666 struct brw_tcs_prog_data tcs_prog_data = {};
667 struct brw_tes_prog_data tes_prog_data = {};
668 struct anv_pipeline_binding tcs_surface_to_descriptor[256];
669 struct anv_pipeline_binding tcs_sampler_to_descriptor[256];
670 struct anv_pipeline_binding tes_surface_to_descriptor[256];
671 struct anv_pipeline_binding tes_sampler_to_descriptor[256];
672
673 struct anv_pipeline_bind_map tcs_map = {
674 .surface_to_descriptor = tcs_surface_to_descriptor,
675 .sampler_to_descriptor = tcs_sampler_to_descriptor
676 };
677 struct anv_pipeline_bind_map tes_map = {
678 .surface_to_descriptor = tes_surface_to_descriptor,
679 .sampler_to_descriptor = tes_sampler_to_descriptor
680 };
681
682 void *mem_ctx = ralloc_context(NULL);
683
684 nir_shader *tcs_nir =
685 anv_pipeline_compile(pipeline, mem_ctx, layout,
686 tcs_module, tcs_entrypoint,
687 MESA_SHADER_TESS_CTRL, tcs_spec_info,
688 &tcs_prog_data.base.base, &tcs_map);
689 nir_shader *tes_nir =
690 anv_pipeline_compile(pipeline, mem_ctx, layout,
691 tes_module, tes_entrypoint,
692 MESA_SHADER_TESS_EVAL, tes_spec_info,
693 &tes_prog_data.base.base, &tes_map);
694 if (tcs_nir == NULL || tes_nir == NULL) {
695 ralloc_free(mem_ctx);
696 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
697 }
698
699 nir_lower_tes_patch_vertices(tes_nir,
700 tcs_nir->info.tess.tcs_vertices_out);
701
702 /* Copy TCS info into the TES info */
703 merge_tess_info(&tes_nir->info, &tcs_nir->info);
704
705 anv_fill_binding_table(&tcs_prog_data.base.base, 0);
706 anv_fill_binding_table(&tes_prog_data.base.base, 0);
707
708 /* Whacking the key after cache lookup is a bit sketchy, but all of
709 * this comes from the SPIR-V, which is part of the hash used for the
710 * pipeline cache. So it should be safe.
711 */
712 tcs_key.tes_primitive_mode = tes_nir->info.tess.primitive_mode;
713 tcs_key.outputs_written = tcs_nir->info.outputs_written;
714 tcs_key.patch_outputs_written = tcs_nir->info.patch_outputs_written;
715 tcs_key.quads_workaround =
716 devinfo->gen < 9 &&
717 tes_nir->info.tess.primitive_mode == 7 /* GL_QUADS */ &&
718 tes_nir->info.tess.spacing == TESS_SPACING_EQUAL;
719
720 tes_key.inputs_read = tcs_key.outputs_written;
721 tes_key.patch_inputs_read = tcs_key.patch_outputs_written;
722
723 const int shader_time_index = -1;
724 const unsigned *shader_code;
725
726 shader_code =
727 brw_compile_tcs(compiler, NULL, mem_ctx, &tcs_key, &tcs_prog_data,
728 tcs_nir, shader_time_index, NULL);
729 if (shader_code == NULL) {
730 ralloc_free(mem_ctx);
731 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
732 }
733
734 unsigned code_size = tcs_prog_data.base.base.program_size;
735 tcs_bin = anv_pipeline_upload_kernel(pipeline, cache,
736 tcs_sha1, sizeof(tcs_sha1),
737 shader_code, code_size,
738 &tcs_prog_data.base.base,
739 sizeof(tcs_prog_data),
740 &tcs_map);
741 if (!tcs_bin) {
742 ralloc_free(mem_ctx);
743 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
744 }
745
746 shader_code =
747 brw_compile_tes(compiler, NULL, mem_ctx, &tes_key,
748 &tcs_prog_data.base.vue_map, &tes_prog_data, tes_nir,
749 NULL, shader_time_index, NULL);
750 if (shader_code == NULL) {
751 ralloc_free(mem_ctx);
752 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
753 }
754
755 code_size = tes_prog_data.base.base.program_size;
756 tes_bin = anv_pipeline_upload_kernel(pipeline, cache,
757 tes_sha1, sizeof(tes_sha1),
758 shader_code, code_size,
759 &tes_prog_data.base.base,
760 sizeof(tes_prog_data),
761 &tes_map);
762 if (!tes_bin) {
763 ralloc_free(mem_ctx);
764 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
765 }
766
767 ralloc_free(mem_ctx);
768 }
769
770 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_TESS_CTRL, tcs_bin);
771 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_TESS_EVAL, tes_bin);
772
773 return VK_SUCCESS;
774 }
775
776 static VkResult
777 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
778 struct anv_pipeline_cache *cache,
779 const VkGraphicsPipelineCreateInfo *info,
780 struct anv_shader_module *module,
781 const char *entrypoint,
782 const VkSpecializationInfo *spec_info)
783 {
784 const struct brw_compiler *compiler =
785 pipeline->device->instance->physicalDevice.compiler;
786 struct brw_gs_prog_key key;
787 struct anv_shader_bin *bin = NULL;
788 unsigned char sha1[20];
789
790 populate_gs_prog_key(&pipeline->device->info, &key);
791
792 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
793
794 if (cache) {
795 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
796 MESA_SHADER_GEOMETRY, spec_info,
797 &key, sizeof(key), sha1);
798 bin = anv_pipeline_cache_search(cache, sha1, 20);
799 }
800
801 if (bin == NULL) {
802 struct brw_gs_prog_data prog_data = {};
803 struct anv_pipeline_binding surface_to_descriptor[256];
804 struct anv_pipeline_binding sampler_to_descriptor[256];
805
806 struct anv_pipeline_bind_map map = {
807 .surface_to_descriptor = surface_to_descriptor,
808 .sampler_to_descriptor = sampler_to_descriptor
809 };
810
811 void *mem_ctx = ralloc_context(NULL);
812
813 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
814 module, entrypoint,
815 MESA_SHADER_GEOMETRY, spec_info,
816 &prog_data.base.base, &map);
817 if (nir == NULL) {
818 ralloc_free(mem_ctx);
819 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
820 }
821
822 anv_fill_binding_table(&prog_data.base.base, 0);
823
824 brw_compute_vue_map(&pipeline->device->info,
825 &prog_data.base.vue_map,
826 nir->info.outputs_written,
827 nir->info.separate_shader);
828
829 const unsigned *shader_code =
830 brw_compile_gs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
831 NULL, -1, NULL);
832 if (shader_code == NULL) {
833 ralloc_free(mem_ctx);
834 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
835 }
836
837 /* TODO: SIMD8 GS */
838 const unsigned code_size = prog_data.base.base.program_size;
839 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
840 shader_code, code_size,
841 &prog_data.base.base, sizeof(prog_data),
842 &map);
843 if (!bin) {
844 ralloc_free(mem_ctx);
845 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
846 }
847
848 ralloc_free(mem_ctx);
849 }
850
851 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY, bin);
852
853 return VK_SUCCESS;
854 }
855
856 static VkResult
857 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
858 struct anv_pipeline_cache *cache,
859 const VkGraphicsPipelineCreateInfo *info,
860 struct anv_shader_module *module,
861 const char *entrypoint,
862 const VkSpecializationInfo *spec_info)
863 {
864 const struct brw_compiler *compiler =
865 pipeline->device->instance->physicalDevice.compiler;
866 struct brw_wm_prog_key key;
867 struct anv_shader_bin *bin = NULL;
868 unsigned char sha1[20];
869
870 populate_wm_prog_key(pipeline, info, &key);
871
872 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
873
874 if (cache) {
875 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
876 MESA_SHADER_FRAGMENT, spec_info,
877 &key, sizeof(key), sha1);
878 bin = anv_pipeline_cache_search(cache, sha1, 20);
879 }
880
881 if (bin == NULL) {
882 struct brw_wm_prog_data prog_data = {};
883 struct anv_pipeline_binding surface_to_descriptor[256];
884 struct anv_pipeline_binding sampler_to_descriptor[256];
885
886 struct anv_pipeline_bind_map map = {
887 .surface_to_descriptor = surface_to_descriptor + 8,
888 .sampler_to_descriptor = sampler_to_descriptor
889 };
890
891 void *mem_ctx = ralloc_context(NULL);
892
893 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
894 module, entrypoint,
895 MESA_SHADER_FRAGMENT, spec_info,
896 &prog_data.base, &map);
897 if (nir == NULL) {
898 ralloc_free(mem_ctx);
899 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
900 }
901
902 unsigned num_rts = 0;
903 const int max_rt = FRAG_RESULT_DATA7 - FRAG_RESULT_DATA0 + 1;
904 struct anv_pipeline_binding rt_bindings[max_rt];
905 nir_function_impl *impl = nir_shader_get_entrypoint(nir);
906 int rt_to_bindings[max_rt];
907 memset(rt_to_bindings, -1, sizeof(rt_to_bindings));
908 bool rt_used[max_rt];
909 memset(rt_used, 0, sizeof(rt_used));
910
911 /* Flag used render targets */
912 nir_foreach_variable_safe(var, &nir->outputs) {
913 if (var->data.location < FRAG_RESULT_DATA0)
914 continue;
915
916 const unsigned rt = var->data.location - FRAG_RESULT_DATA0;
917 /* Out-of-bounds */
918 if (rt >= key.nr_color_regions)
919 continue;
920
921 const unsigned array_len =
922 glsl_type_is_array(var->type) ? glsl_get_length(var->type) : 1;
923 assert(rt + array_len <= max_rt);
924
925 for (unsigned i = 0; i < array_len; i++)
926 rt_used[rt + i] = true;
927 }
928
929 /* Set new, compacted, location */
930 for (unsigned i = 0; i < max_rt; i++) {
931 if (!rt_used[i])
932 continue;
933
934 rt_to_bindings[i] = num_rts;
935 rt_bindings[rt_to_bindings[i]] = (struct anv_pipeline_binding) {
936 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
937 .binding = 0,
938 .index = i,
939 };
940 num_rts++;
941 }
942
943 nir_foreach_variable_safe(var, &nir->outputs) {
944 if (var->data.location < FRAG_RESULT_DATA0)
945 continue;
946
947 const unsigned rt = var->data.location - FRAG_RESULT_DATA0;
948 if (rt >= key.nr_color_regions) {
949 /* Out-of-bounds, throw it away */
950 var->data.mode = nir_var_local;
951 exec_node_remove(&var->node);
952 exec_list_push_tail(&impl->locals, &var->node);
953 continue;
954 }
955
956 /* Give it the new location */
957 assert(rt_to_bindings[rt] != -1);
958 var->data.location = rt_to_bindings[rt] + FRAG_RESULT_DATA0;
959 }
960
961 if (num_rts == 0) {
962 /* If we have no render targets, we need a null render target */
963 rt_bindings[0] = (struct anv_pipeline_binding) {
964 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
965 .binding = 0,
966 .index = UINT32_MAX,
967 };
968 num_rts = 1;
969 }
970
971 assert(num_rts <= max_rt);
972 map.surface_to_descriptor -= num_rts;
973 map.surface_count += num_rts;
974 assert(map.surface_count <= 256);
975 memcpy(map.surface_to_descriptor, rt_bindings,
976 num_rts * sizeof(*rt_bindings));
977
978 anv_fill_binding_table(&prog_data.base, num_rts);
979
980 const unsigned *shader_code =
981 brw_compile_fs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
982 NULL, -1, -1, true, false, NULL, NULL);
983 if (shader_code == NULL) {
984 ralloc_free(mem_ctx);
985 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
986 }
987
988 unsigned code_size = prog_data.base.program_size;
989 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
990 shader_code, code_size,
991 &prog_data.base, sizeof(prog_data),
992 &map);
993 if (!bin) {
994 ralloc_free(mem_ctx);
995 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
996 }
997
998 ralloc_free(mem_ctx);
999 }
1000
1001 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT, bin);
1002
1003 return VK_SUCCESS;
1004 }
1005
1006 VkResult
1007 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
1008 struct anv_pipeline_cache *cache,
1009 const VkComputePipelineCreateInfo *info,
1010 struct anv_shader_module *module,
1011 const char *entrypoint,
1012 const VkSpecializationInfo *spec_info)
1013 {
1014 const struct brw_compiler *compiler =
1015 pipeline->device->instance->physicalDevice.compiler;
1016 struct brw_cs_prog_key key;
1017 struct anv_shader_bin *bin = NULL;
1018 unsigned char sha1[20];
1019
1020 populate_cs_prog_key(&pipeline->device->info, &key);
1021
1022 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
1023
1024 if (cache) {
1025 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
1026 MESA_SHADER_COMPUTE, spec_info,
1027 &key, sizeof(key), sha1);
1028 bin = anv_pipeline_cache_search(cache, sha1, 20);
1029 }
1030
1031 if (bin == NULL) {
1032 struct brw_cs_prog_data prog_data = {};
1033 struct anv_pipeline_binding surface_to_descriptor[256];
1034 struct anv_pipeline_binding sampler_to_descriptor[256];
1035
1036 struct anv_pipeline_bind_map map = {
1037 .surface_to_descriptor = surface_to_descriptor,
1038 .sampler_to_descriptor = sampler_to_descriptor
1039 };
1040
1041 void *mem_ctx = ralloc_context(NULL);
1042
1043 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
1044 module, entrypoint,
1045 MESA_SHADER_COMPUTE, spec_info,
1046 &prog_data.base, &map);
1047 if (nir == NULL) {
1048 ralloc_free(mem_ctx);
1049 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1050 }
1051
1052 NIR_PASS_V(nir, anv_nir_add_base_work_group_id, &prog_data);
1053
1054 anv_fill_binding_table(&prog_data.base, 1);
1055
1056 const unsigned *shader_code =
1057 brw_compile_cs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
1058 -1, NULL);
1059 if (shader_code == NULL) {
1060 ralloc_free(mem_ctx);
1061 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1062 }
1063
1064 const unsigned code_size = prog_data.base.program_size;
1065 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
1066 shader_code, code_size,
1067 &prog_data.base, sizeof(prog_data),
1068 &map);
1069 if (!bin) {
1070 ralloc_free(mem_ctx);
1071 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1072 }
1073
1074 ralloc_free(mem_ctx);
1075 }
1076
1077 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE, bin);
1078
1079 return VK_SUCCESS;
1080 }
1081
1082 /**
1083 * Copy pipeline state not marked as dynamic.
1084 * Dynamic state is pipeline state which hasn't been provided at pipeline
1085 * creation time, but is dynamically provided afterwards using various
1086 * vkCmdSet* functions.
1087 *
1088 * The set of state considered "non_dynamic" is determined by the pieces of
1089 * state that have their corresponding VkDynamicState enums omitted from
1090 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1091 *
1092 * @param[out] pipeline Destination non_dynamic state.
1093 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1094 */
1095 static void
1096 copy_non_dynamic_state(struct anv_pipeline *pipeline,
1097 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1098 {
1099 anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
1100 struct anv_subpass *subpass = pipeline->subpass;
1101
1102 pipeline->dynamic_state = default_dynamic_state;
1103
1104 if (pCreateInfo->pDynamicState) {
1105 /* Remove all of the states that are marked as dynamic */
1106 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1107 for (uint32_t s = 0; s < count; s++)
1108 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1109 }
1110
1111 struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
1112
1113 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1114 *
1115 * pViewportState is [...] NULL if the pipeline
1116 * has rasterization disabled.
1117 */
1118 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1119 assert(pCreateInfo->pViewportState);
1120
1121 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1122 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1123 typed_memcpy(dynamic->viewport.viewports,
1124 pCreateInfo->pViewportState->pViewports,
1125 pCreateInfo->pViewportState->viewportCount);
1126 }
1127
1128 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1129 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1130 typed_memcpy(dynamic->scissor.scissors,
1131 pCreateInfo->pViewportState->pScissors,
1132 pCreateInfo->pViewportState->scissorCount);
1133 }
1134 }
1135
1136 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1137 assert(pCreateInfo->pRasterizationState);
1138 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1139 }
1140
1141 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1142 assert(pCreateInfo->pRasterizationState);
1143 dynamic->depth_bias.bias =
1144 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1145 dynamic->depth_bias.clamp =
1146 pCreateInfo->pRasterizationState->depthBiasClamp;
1147 dynamic->depth_bias.slope =
1148 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1149 }
1150
1151 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1152 *
1153 * pColorBlendState is [...] NULL if the pipeline has rasterization
1154 * disabled or if the subpass of the render pass the pipeline is
1155 * created against does not use any color attachments.
1156 */
1157 bool uses_color_att = false;
1158 for (unsigned i = 0; i < subpass->color_count; ++i) {
1159 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1160 uses_color_att = true;
1161 break;
1162 }
1163 }
1164
1165 if (uses_color_att &&
1166 !pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1167 assert(pCreateInfo->pColorBlendState);
1168
1169 if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
1170 typed_memcpy(dynamic->blend_constants,
1171 pCreateInfo->pColorBlendState->blendConstants, 4);
1172 }
1173
1174 /* If there is no depthstencil attachment, then don't read
1175 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1176 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1177 * no need to override the depthstencil defaults in
1178 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1179 *
1180 * Section 9.2 of the Vulkan 1.0.15 spec says:
1181 *
1182 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1183 * disabled or if the subpass of the render pass the pipeline is created
1184 * against does not use a depth/stencil attachment.
1185 */
1186 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1187 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1188 assert(pCreateInfo->pDepthStencilState);
1189
1190 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1191 dynamic->depth_bounds.min =
1192 pCreateInfo->pDepthStencilState->minDepthBounds;
1193 dynamic->depth_bounds.max =
1194 pCreateInfo->pDepthStencilState->maxDepthBounds;
1195 }
1196
1197 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1198 dynamic->stencil_compare_mask.front =
1199 pCreateInfo->pDepthStencilState->front.compareMask;
1200 dynamic->stencil_compare_mask.back =
1201 pCreateInfo->pDepthStencilState->back.compareMask;
1202 }
1203
1204 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1205 dynamic->stencil_write_mask.front =
1206 pCreateInfo->pDepthStencilState->front.writeMask;
1207 dynamic->stencil_write_mask.back =
1208 pCreateInfo->pDepthStencilState->back.writeMask;
1209 }
1210
1211 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1212 dynamic->stencil_reference.front =
1213 pCreateInfo->pDepthStencilState->front.reference;
1214 dynamic->stencil_reference.back =
1215 pCreateInfo->pDepthStencilState->back.reference;
1216 }
1217 }
1218
1219 pipeline->dynamic_state_mask = states;
1220 }
1221
1222 static void
1223 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
1224 {
1225 #ifdef DEBUG
1226 struct anv_render_pass *renderpass = NULL;
1227 struct anv_subpass *subpass = NULL;
1228
1229 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1230 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1231 */
1232 assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
1233
1234 renderpass = anv_render_pass_from_handle(info->renderPass);
1235 assert(renderpass);
1236
1237 assert(info->subpass < renderpass->subpass_count);
1238 subpass = &renderpass->subpasses[info->subpass];
1239
1240 assert(info->stageCount >= 1);
1241 assert(info->pVertexInputState);
1242 assert(info->pInputAssemblyState);
1243 assert(info->pRasterizationState);
1244 if (!info->pRasterizationState->rasterizerDiscardEnable) {
1245 assert(info->pViewportState);
1246 assert(info->pMultisampleState);
1247
1248 if (subpass && subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
1249 assert(info->pDepthStencilState);
1250
1251 if (subpass && subpass->color_count > 0)
1252 assert(info->pColorBlendState);
1253 }
1254
1255 for (uint32_t i = 0; i < info->stageCount; ++i) {
1256 switch (info->pStages[i].stage) {
1257 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
1258 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
1259 assert(info->pTessellationState);
1260 break;
1261 default:
1262 break;
1263 }
1264 }
1265 #endif
1266 }
1267
1268 /**
1269 * Calculate the desired L3 partitioning based on the current state of the
1270 * pipeline. For now this simply returns the conservative defaults calculated
1271 * by get_default_l3_weights(), but we could probably do better by gathering
1272 * more statistics from the pipeline state (e.g. guess of expected URB usage
1273 * and bound surfaces), or by using feed-back from performance counters.
1274 */
1275 void
1276 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm)
1277 {
1278 const struct gen_device_info *devinfo = &pipeline->device->info;
1279
1280 const struct gen_l3_weights w =
1281 gen_get_default_l3_weights(devinfo, pipeline->needs_data_cache, needs_slm);
1282
1283 pipeline->urb.l3_config = gen_get_l3_config(devinfo, w);
1284 pipeline->urb.total_size =
1285 gen_get_l3_config_urb_size(devinfo, pipeline->urb.l3_config);
1286 }
1287
1288 VkResult
1289 anv_pipeline_init(struct anv_pipeline *pipeline,
1290 struct anv_device *device,
1291 struct anv_pipeline_cache *cache,
1292 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1293 const VkAllocationCallbacks *alloc)
1294 {
1295 VkResult result;
1296
1297 anv_pipeline_validate_create_info(pCreateInfo);
1298
1299 if (alloc == NULL)
1300 alloc = &device->alloc;
1301
1302 pipeline->device = device;
1303
1304 ANV_FROM_HANDLE(anv_render_pass, render_pass, pCreateInfo->renderPass);
1305 assert(pCreateInfo->subpass < render_pass->subpass_count);
1306 pipeline->subpass = &render_pass->subpasses[pCreateInfo->subpass];
1307
1308 result = anv_reloc_list_init(&pipeline->batch_relocs, alloc);
1309 if (result != VK_SUCCESS)
1310 return result;
1311
1312 pipeline->batch.alloc = alloc;
1313 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
1314 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
1315 pipeline->batch.relocs = &pipeline->batch_relocs;
1316 pipeline->batch.status = VK_SUCCESS;
1317
1318 copy_non_dynamic_state(pipeline, pCreateInfo);
1319 pipeline->depth_clamp_enable = pCreateInfo->pRasterizationState &&
1320 pCreateInfo->pRasterizationState->depthClampEnable;
1321
1322 pipeline->sample_shading_enable = pCreateInfo->pMultisampleState &&
1323 pCreateInfo->pMultisampleState->sampleShadingEnable;
1324
1325 pipeline->needs_data_cache = false;
1326
1327 /* When we free the pipeline, we detect stages based on the NULL status
1328 * of various prog_data pointers. Make them NULL by default.
1329 */
1330 memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
1331
1332 pipeline->active_stages = 0;
1333
1334 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = {};
1335 struct anv_shader_module *modules[MESA_SHADER_STAGES] = {};
1336 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1337 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1338 pStages[stage] = &pCreateInfo->pStages[i];
1339 modules[stage] = anv_shader_module_from_handle(pStages[stage]->module);
1340 }
1341
1342 if (modules[MESA_SHADER_VERTEX]) {
1343 result = anv_pipeline_compile_vs(pipeline, cache, pCreateInfo,
1344 modules[MESA_SHADER_VERTEX],
1345 pStages[MESA_SHADER_VERTEX]->pName,
1346 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo);
1347 if (result != VK_SUCCESS)
1348 goto compile_fail;
1349 }
1350
1351 if (modules[MESA_SHADER_TESS_EVAL]) {
1352 anv_pipeline_compile_tcs_tes(pipeline, cache, pCreateInfo,
1353 modules[MESA_SHADER_TESS_CTRL],
1354 pStages[MESA_SHADER_TESS_CTRL]->pName,
1355 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
1356 modules[MESA_SHADER_TESS_EVAL],
1357 pStages[MESA_SHADER_TESS_EVAL]->pName,
1358 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo);
1359 }
1360
1361 if (modules[MESA_SHADER_GEOMETRY]) {
1362 result = anv_pipeline_compile_gs(pipeline, cache, pCreateInfo,
1363 modules[MESA_SHADER_GEOMETRY],
1364 pStages[MESA_SHADER_GEOMETRY]->pName,
1365 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo);
1366 if (result != VK_SUCCESS)
1367 goto compile_fail;
1368 }
1369
1370 if (modules[MESA_SHADER_FRAGMENT]) {
1371 result = anv_pipeline_compile_fs(pipeline, cache, pCreateInfo,
1372 modules[MESA_SHADER_FRAGMENT],
1373 pStages[MESA_SHADER_FRAGMENT]->pName,
1374 pStages[MESA_SHADER_FRAGMENT]->pSpecializationInfo);
1375 if (result != VK_SUCCESS)
1376 goto compile_fail;
1377 }
1378
1379 assert(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT);
1380
1381 anv_pipeline_setup_l3_config(pipeline, false);
1382
1383 const VkPipelineVertexInputStateCreateInfo *vi_info =
1384 pCreateInfo->pVertexInputState;
1385
1386 const uint64_t inputs_read = get_vs_prog_data(pipeline)->inputs_read;
1387
1388 pipeline->vb_used = 0;
1389 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1390 const VkVertexInputAttributeDescription *desc =
1391 &vi_info->pVertexAttributeDescriptions[i];
1392
1393 if (inputs_read & (1ull << (VERT_ATTRIB_GENERIC0 + desc->location)))
1394 pipeline->vb_used |= 1 << desc->binding;
1395 }
1396
1397 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1398 const VkVertexInputBindingDescription *desc =
1399 &vi_info->pVertexBindingDescriptions[i];
1400
1401 pipeline->binding_stride[desc->binding] = desc->stride;
1402
1403 /* Step rate is programmed per vertex element (attribute), not
1404 * binding. Set up a map of which bindings step per instance, for
1405 * reference by vertex element setup. */
1406 switch (desc->inputRate) {
1407 default:
1408 case VK_VERTEX_INPUT_RATE_VERTEX:
1409 pipeline->instancing_enable[desc->binding] = false;
1410 break;
1411 case VK_VERTEX_INPUT_RATE_INSTANCE:
1412 pipeline->instancing_enable[desc->binding] = true;
1413 break;
1414 }
1415 }
1416
1417 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1418 pCreateInfo->pInputAssemblyState;
1419 const VkPipelineTessellationStateCreateInfo *tess_info =
1420 pCreateInfo->pTessellationState;
1421 pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1422
1423 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
1424 pipeline->topology = _3DPRIM_PATCHLIST(tess_info->patchControlPoints);
1425 else
1426 pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1427
1428 return VK_SUCCESS;
1429
1430 compile_fail:
1431 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
1432 if (pipeline->shaders[s])
1433 anv_shader_bin_unref(device, pipeline->shaders[s]);
1434 }
1435
1436 anv_reloc_list_finish(&pipeline->batch_relocs, alloc);
1437
1438 return result;
1439 }