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anv/pipeline: Use a per-VB struct instead of separate arrays
[mesa.git] / src / intel / vulkan / anv_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "util/mesa-sha1.h"
31 #include "common/gen_l3_config.h"
32 #include "anv_private.h"
33 #include "compiler/brw_nir.h"
34 #include "anv_nir.h"
35 #include "spirv/nir_spirv.h"
36
37 /* Needed for SWIZZLE macros */
38 #include "program/prog_instruction.h"
39
40 // Shader functions
41
42 VkResult anv_CreateShaderModule(
43 VkDevice _device,
44 const VkShaderModuleCreateInfo* pCreateInfo,
45 const VkAllocationCallbacks* pAllocator,
46 VkShaderModule* pShaderModule)
47 {
48 ANV_FROM_HANDLE(anv_device, device, _device);
49 struct anv_shader_module *module;
50
51 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
52 assert(pCreateInfo->flags == 0);
53
54 module = vk_alloc2(&device->alloc, pAllocator,
55 sizeof(*module) + pCreateInfo->codeSize, 8,
56 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
57 if (module == NULL)
58 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
59
60 module->size = pCreateInfo->codeSize;
61 memcpy(module->data, pCreateInfo->pCode, module->size);
62
63 _mesa_sha1_compute(module->data, module->size, module->sha1);
64
65 *pShaderModule = anv_shader_module_to_handle(module);
66
67 return VK_SUCCESS;
68 }
69
70 void anv_DestroyShaderModule(
71 VkDevice _device,
72 VkShaderModule _module,
73 const VkAllocationCallbacks* pAllocator)
74 {
75 ANV_FROM_HANDLE(anv_device, device, _device);
76 ANV_FROM_HANDLE(anv_shader_module, module, _module);
77
78 if (!module)
79 return;
80
81 vk_free2(&device->alloc, pAllocator, module);
82 }
83
84 #define SPIR_V_MAGIC_NUMBER 0x07230203
85
86 static const uint64_t stage_to_debug[] = {
87 [MESA_SHADER_VERTEX] = DEBUG_VS,
88 [MESA_SHADER_TESS_CTRL] = DEBUG_TCS,
89 [MESA_SHADER_TESS_EVAL] = DEBUG_TES,
90 [MESA_SHADER_GEOMETRY] = DEBUG_GS,
91 [MESA_SHADER_FRAGMENT] = DEBUG_WM,
92 [MESA_SHADER_COMPUTE] = DEBUG_CS,
93 };
94
95 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
96 * we can't do that yet because we don't have the ability to copy nir.
97 */
98 static nir_shader *
99 anv_shader_compile_to_nir(struct anv_pipeline *pipeline,
100 void *mem_ctx,
101 struct anv_shader_module *module,
102 const char *entrypoint_name,
103 gl_shader_stage stage,
104 const VkSpecializationInfo *spec_info)
105 {
106 const struct anv_device *device = pipeline->device;
107
108 const struct brw_compiler *compiler =
109 device->instance->physicalDevice.compiler;
110 const nir_shader_compiler_options *nir_options =
111 compiler->glsl_compiler_options[stage].NirOptions;
112
113 uint32_t *spirv = (uint32_t *) module->data;
114 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
115 assert(module->size % 4 == 0);
116
117 uint32_t num_spec_entries = 0;
118 struct nir_spirv_specialization *spec_entries = NULL;
119 if (spec_info && spec_info->mapEntryCount > 0) {
120 num_spec_entries = spec_info->mapEntryCount;
121 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
122 for (uint32_t i = 0; i < num_spec_entries; i++) {
123 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
124 const void *data = spec_info->pData + entry.offset;
125 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
126
127 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
128 if (spec_info->dataSize == 8)
129 spec_entries[i].data64 = *(const uint64_t *)data;
130 else
131 spec_entries[i].data32 = *(const uint32_t *)data;
132 }
133 }
134
135 struct spirv_to_nir_options spirv_options = {
136 .lower_workgroup_access_to_offsets = true,
137 .caps = {
138 .float64 = device->instance->physicalDevice.info.gen >= 8,
139 .int64 = device->instance->physicalDevice.info.gen >= 8,
140 .tessellation = true,
141 .device_group = true,
142 .draw_parameters = true,
143 .image_write_without_format = true,
144 .multiview = true,
145 .variable_pointers = true,
146 .storage_16bit = device->instance->physicalDevice.info.gen >= 8,
147 .int16 = device->instance->physicalDevice.info.gen >= 8,
148 .shader_viewport_index_layer = true,
149 .subgroup_arithmetic = true,
150 .subgroup_basic = true,
151 .subgroup_ballot = true,
152 .subgroup_quad = true,
153 .subgroup_shuffle = true,
154 .subgroup_vote = true,
155 .stencil_export = device->instance->physicalDevice.info.gen >= 9,
156 .storage_8bit = device->instance->physicalDevice.info.gen >= 8,
157 },
158 };
159
160 nir_function *entry_point =
161 spirv_to_nir(spirv, module->size / 4,
162 spec_entries, num_spec_entries,
163 stage, entrypoint_name, &spirv_options, nir_options);
164 nir_shader *nir = entry_point->shader;
165 assert(nir->info.stage == stage);
166 nir_validate_shader(nir);
167 ralloc_steal(mem_ctx, nir);
168
169 free(spec_entries);
170
171 if (unlikely(INTEL_DEBUG & stage_to_debug[stage])) {
172 fprintf(stderr, "NIR (from SPIR-V) for %s shader:\n",
173 gl_shader_stage_name(stage));
174 nir_print_shader(nir, stderr);
175 }
176
177 /* We have to lower away local constant initializers right before we
178 * inline functions. That way they get properly initialized at the top
179 * of the function and not at the top of its caller.
180 */
181 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
182 NIR_PASS_V(nir, nir_lower_returns);
183 NIR_PASS_V(nir, nir_inline_functions);
184 NIR_PASS_V(nir, nir_copy_prop);
185
186 /* Pick off the single entrypoint that we want */
187 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
188 if (func != entry_point)
189 exec_node_remove(&func->node);
190 }
191 assert(exec_list_length(&nir->functions) == 1);
192 entry_point->name = ralloc_strdup(entry_point, "main");
193
194 /* Now that we've deleted all but the main function, we can go ahead and
195 * lower the rest of the constant initializers. We do this here so that
196 * nir_remove_dead_variables and split_per_member_structs below see the
197 * corresponding stores.
198 */
199 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
200
201 /* Split member structs. We do this before lower_io_to_temporaries so that
202 * it doesn't lower system values to temporaries by accident.
203 */
204 NIR_PASS_V(nir, nir_split_var_copies);
205 NIR_PASS_V(nir, nir_split_per_member_structs);
206
207 NIR_PASS_V(nir, nir_remove_dead_variables,
208 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
209
210 if (stage == MESA_SHADER_FRAGMENT)
211 NIR_PASS_V(nir, nir_lower_wpos_center, pipeline->sample_shading_enable);
212
213 NIR_PASS_V(nir, nir_propagate_invariant);
214 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
215 entry_point->impl, true, false);
216
217 /* Vulkan uses the separate-shader linking model */
218 nir->info.separate_shader = true;
219
220 nir = brw_preprocess_nir(compiler, nir);
221
222 if (stage == MESA_SHADER_FRAGMENT)
223 NIR_PASS_V(nir, anv_nir_lower_input_attachments);
224
225 return nir;
226 }
227
228 void anv_DestroyPipeline(
229 VkDevice _device,
230 VkPipeline _pipeline,
231 const VkAllocationCallbacks* pAllocator)
232 {
233 ANV_FROM_HANDLE(anv_device, device, _device);
234 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
235
236 if (!pipeline)
237 return;
238
239 anv_reloc_list_finish(&pipeline->batch_relocs,
240 pAllocator ? pAllocator : &device->alloc);
241 if (pipeline->blend_state.map)
242 anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
243
244 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
245 if (pipeline->shaders[s])
246 anv_shader_bin_unref(device, pipeline->shaders[s]);
247 }
248
249 vk_free2(&device->alloc, pAllocator, pipeline);
250 }
251
252 static const uint32_t vk_to_gen_primitive_type[] = {
253 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
254 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
255 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
256 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
257 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
258 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
259 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
260 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
261 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
262 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
263 };
264
265 static void
266 populate_sampler_prog_key(const struct gen_device_info *devinfo,
267 struct brw_sampler_prog_key_data *key)
268 {
269 /* Almost all multisampled textures are compressed. The only time when we
270 * don't compress a multisampled texture is for 16x MSAA with a surface
271 * width greater than 8k which is a bit of an edge case. Since the sampler
272 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
273 * to tell the compiler to always assume compression.
274 */
275 key->compressed_multisample_layout_mask = ~0;
276
277 /* SkyLake added support for 16x MSAA. With this came a new message for
278 * reading from a 16x MSAA surface with compression. The new message was
279 * needed because now the MCS data is 64 bits instead of 32 or lower as is
280 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
281 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
282 * so we can just use it unconditionally. This may not be quite as
283 * efficient but it saves us from recompiling.
284 */
285 if (devinfo->gen >= 9)
286 key->msaa_16 = ~0;
287
288 /* XXX: Handle texture swizzle on HSW- */
289 for (int i = 0; i < MAX_SAMPLERS; i++) {
290 /* Assume color sampler, no swizzling. (Works for BDW+) */
291 key->swizzles[i] = SWIZZLE_XYZW;
292 }
293 }
294
295 static void
296 populate_vs_prog_key(const struct gen_device_info *devinfo,
297 struct brw_vs_prog_key *key)
298 {
299 memset(key, 0, sizeof(*key));
300
301 populate_sampler_prog_key(devinfo, &key->tex);
302
303 /* XXX: Handle vertex input work-arounds */
304
305 /* XXX: Handle sampler_prog_key */
306 }
307
308 static void
309 populate_gs_prog_key(const struct gen_device_info *devinfo,
310 struct brw_gs_prog_key *key)
311 {
312 memset(key, 0, sizeof(*key));
313
314 populate_sampler_prog_key(devinfo, &key->tex);
315 }
316
317 static void
318 populate_wm_prog_key(const struct anv_pipeline *pipeline,
319 const VkGraphicsPipelineCreateInfo *info,
320 struct brw_wm_prog_key *key)
321 {
322 const struct gen_device_info *devinfo = &pipeline->device->info;
323
324 memset(key, 0, sizeof(*key));
325
326 populate_sampler_prog_key(devinfo, &key->tex);
327
328 /* TODO: we could set this to 0 based on the information in nir_shader, but
329 * this function is called before spirv_to_nir. */
330 const struct brw_vue_map *vue_map =
331 &anv_pipeline_get_last_vue_prog_data(pipeline)->vue_map;
332 key->input_slots_valid = vue_map->slots_valid;
333
334 /* Vulkan doesn't specify a default */
335 key->high_quality_derivatives = false;
336
337 /* XXX Vulkan doesn't appear to specify */
338 key->clamp_fragment_color = false;
339
340 key->nr_color_regions = pipeline->subpass->color_count;
341
342 key->replicate_alpha = key->nr_color_regions > 1 &&
343 info->pMultisampleState &&
344 info->pMultisampleState->alphaToCoverageEnable;
345
346 if (info->pMultisampleState) {
347 /* We should probably pull this out of the shader, but it's fairly
348 * harmless to compute it and then let dead-code take care of it.
349 */
350 if (info->pMultisampleState->rasterizationSamples > 1) {
351 key->persample_interp =
352 (info->pMultisampleState->minSampleShading *
353 info->pMultisampleState->rasterizationSamples) > 1;
354 key->multisample_fbo = true;
355 }
356
357 key->frag_coord_adds_sample_pos =
358 info->pMultisampleState->sampleShadingEnable;
359 }
360 }
361
362 static void
363 populate_cs_prog_key(const struct gen_device_info *devinfo,
364 struct brw_cs_prog_key *key)
365 {
366 memset(key, 0, sizeof(*key));
367
368 populate_sampler_prog_key(devinfo, &key->tex);
369 }
370
371 static void
372 anv_pipeline_hash_shader(struct anv_pipeline *pipeline,
373 struct anv_pipeline_layout *layout,
374 struct anv_shader_module *module,
375 const char *entrypoint,
376 gl_shader_stage stage,
377 const VkSpecializationInfo *spec_info,
378 const void *key, size_t key_size,
379 unsigned char *sha1_out)
380 {
381 struct mesa_sha1 ctx;
382
383 _mesa_sha1_init(&ctx);
384 if (stage != MESA_SHADER_COMPUTE) {
385 _mesa_sha1_update(&ctx, &pipeline->subpass->view_mask,
386 sizeof(pipeline->subpass->view_mask));
387 }
388 if (layout)
389 _mesa_sha1_update(&ctx, layout->sha1, sizeof(layout->sha1));
390 _mesa_sha1_update(&ctx, module->sha1, sizeof(module->sha1));
391 _mesa_sha1_update(&ctx, entrypoint, strlen(entrypoint));
392 _mesa_sha1_update(&ctx, &stage, sizeof(stage));
393 if (spec_info) {
394 _mesa_sha1_update(&ctx, spec_info->pMapEntries,
395 spec_info->mapEntryCount * sizeof(*spec_info->pMapEntries));
396 _mesa_sha1_update(&ctx, spec_info->pData, spec_info->dataSize);
397 }
398 _mesa_sha1_update(&ctx, key, key_size);
399 _mesa_sha1_final(&ctx, sha1_out);
400 }
401
402 static nir_shader *
403 anv_pipeline_compile(struct anv_pipeline *pipeline,
404 void *mem_ctx,
405 struct anv_pipeline_layout *layout,
406 struct anv_shader_module *module,
407 const char *entrypoint,
408 gl_shader_stage stage,
409 const VkSpecializationInfo *spec_info,
410 struct brw_stage_prog_data *prog_data,
411 struct anv_pipeline_bind_map *map)
412 {
413 const struct brw_compiler *compiler =
414 pipeline->device->instance->physicalDevice.compiler;
415
416 nir_shader *nir = anv_shader_compile_to_nir(pipeline, mem_ctx,
417 module, entrypoint, stage,
418 spec_info);
419 if (nir == NULL)
420 return NULL;
421
422 NIR_PASS_V(nir, anv_nir_lower_ycbcr_textures, layout);
423
424 NIR_PASS_V(nir, anv_nir_lower_push_constants);
425
426 if (stage != MESA_SHADER_COMPUTE)
427 NIR_PASS_V(nir, anv_nir_lower_multiview, pipeline->subpass->view_mask);
428
429 if (stage == MESA_SHADER_COMPUTE)
430 prog_data->total_shared = nir->num_shared;
431
432 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
433
434 if (nir->num_uniforms > 0) {
435 assert(prog_data->nr_params == 0);
436
437 /* If the shader uses any push constants at all, we'll just give
438 * them the maximum possible number
439 */
440 assert(nir->num_uniforms <= MAX_PUSH_CONSTANTS_SIZE);
441 nir->num_uniforms = MAX_PUSH_CONSTANTS_SIZE;
442 prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
443 prog_data->param = ralloc_array(mem_ctx, uint32_t, prog_data->nr_params);
444
445 /* We now set the param values to be offsets into a
446 * anv_push_constant_data structure. Since the compiler doesn't
447 * actually dereference any of the gl_constant_value pointers in the
448 * params array, it doesn't really matter what we put here.
449 */
450 struct anv_push_constants *null_data = NULL;
451 /* Fill out the push constants section of the param array */
452 for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++) {
453 prog_data->param[i] = ANV_PARAM_PUSH(
454 (uintptr_t)&null_data->client_data[i * sizeof(float)]);
455 }
456 }
457
458 if (nir->info.num_ssbos > 0 || nir->info.num_images > 0)
459 pipeline->needs_data_cache = true;
460
461 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
462 if (layout)
463 anv_nir_apply_pipeline_layout(pipeline, layout, nir, prog_data, map);
464
465 if (stage != MESA_SHADER_COMPUTE)
466 brw_nir_analyze_ubo_ranges(compiler, nir, prog_data->ubo_ranges);
467
468 assert(nir->num_uniforms == prog_data->nr_params * 4);
469
470 return nir;
471 }
472
473 static void
474 anv_fill_binding_table(struct brw_stage_prog_data *prog_data, unsigned bias)
475 {
476 prog_data->binding_table.size_bytes = 0;
477 prog_data->binding_table.texture_start = bias;
478 prog_data->binding_table.gather_texture_start = bias;
479 prog_data->binding_table.ubo_start = bias;
480 prog_data->binding_table.ssbo_start = bias;
481 prog_data->binding_table.image_start = bias;
482 }
483
484 static void
485 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
486 gl_shader_stage stage,
487 struct anv_shader_bin *shader)
488 {
489 pipeline->shaders[stage] = shader;
490 }
491
492 static VkResult
493 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
494 struct anv_pipeline_cache *cache,
495 const VkGraphicsPipelineCreateInfo *info,
496 struct anv_shader_module *module,
497 const char *entrypoint,
498 const VkSpecializationInfo *spec_info)
499 {
500 const struct brw_compiler *compiler =
501 pipeline->device->instance->physicalDevice.compiler;
502 struct brw_vs_prog_key key;
503 struct anv_shader_bin *bin = NULL;
504
505 populate_vs_prog_key(&pipeline->device->info, &key);
506
507 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
508
509 unsigned char sha1[20];
510 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
511 MESA_SHADER_VERTEX, spec_info,
512 &key, sizeof(key), sha1);
513 bin = anv_device_search_for_kernel(pipeline->device, cache, sha1, 20);
514
515 if (bin == NULL) {
516 struct brw_vs_prog_data prog_data = {};
517 struct anv_pipeline_binding surface_to_descriptor[256];
518 struct anv_pipeline_binding sampler_to_descriptor[256];
519
520 struct anv_pipeline_bind_map map = {
521 .surface_to_descriptor = surface_to_descriptor,
522 .sampler_to_descriptor = sampler_to_descriptor
523 };
524
525 void *mem_ctx = ralloc_context(NULL);
526
527 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
528 module, entrypoint,
529 MESA_SHADER_VERTEX, spec_info,
530 &prog_data.base.base, &map);
531 if (nir == NULL) {
532 ralloc_free(mem_ctx);
533 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
534 }
535
536 anv_fill_binding_table(&prog_data.base.base, 0);
537
538 brw_compute_vue_map(&pipeline->device->info,
539 &prog_data.base.vue_map,
540 nir->info.outputs_written,
541 nir->info.separate_shader);
542
543 const unsigned *shader_code =
544 brw_compile_vs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
545 -1, NULL);
546 if (shader_code == NULL) {
547 ralloc_free(mem_ctx);
548 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
549 }
550
551 unsigned code_size = prog_data.base.base.program_size;
552 bin = anv_device_upload_kernel(pipeline->device, cache, sha1, 20,
553 shader_code, code_size,
554 nir->constant_data,
555 nir->constant_data_size,
556 &prog_data.base.base, sizeof(prog_data),
557 &map);
558 if (!bin) {
559 ralloc_free(mem_ctx);
560 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
561 }
562
563 ralloc_free(mem_ctx);
564 }
565
566 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX, bin);
567
568 return VK_SUCCESS;
569 }
570
571 static void
572 merge_tess_info(struct shader_info *tes_info,
573 const struct shader_info *tcs_info)
574 {
575 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
576 *
577 * "PointMode. Controls generation of points rather than triangles
578 * or lines. This functionality defaults to disabled, and is
579 * enabled if either shader stage includes the execution mode.
580 *
581 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
582 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
583 * and OutputVertices, it says:
584 *
585 * "One mode must be set in at least one of the tessellation
586 * shader stages."
587 *
588 * So, the fields can be set in either the TCS or TES, but they must
589 * agree if set in both. Our backend looks at TES, so bitwise-or in
590 * the values from the TCS.
591 */
592 assert(tcs_info->tess.tcs_vertices_out == 0 ||
593 tes_info->tess.tcs_vertices_out == 0 ||
594 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
595 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
596
597 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
598 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
599 tcs_info->tess.spacing == tes_info->tess.spacing);
600 tes_info->tess.spacing |= tcs_info->tess.spacing;
601
602 assert(tcs_info->tess.primitive_mode == 0 ||
603 tes_info->tess.primitive_mode == 0 ||
604 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
605 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
606 tes_info->tess.ccw |= tcs_info->tess.ccw;
607 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
608 }
609
610 static VkResult
611 anv_pipeline_compile_tcs_tes(struct anv_pipeline *pipeline,
612 struct anv_pipeline_cache *cache,
613 const VkGraphicsPipelineCreateInfo *info,
614 struct anv_shader_module *tcs_module,
615 const char *tcs_entrypoint,
616 const VkSpecializationInfo *tcs_spec_info,
617 struct anv_shader_module *tes_module,
618 const char *tes_entrypoint,
619 const VkSpecializationInfo *tes_spec_info)
620 {
621 const struct gen_device_info *devinfo = &pipeline->device->info;
622 const struct brw_compiler *compiler =
623 pipeline->device->instance->physicalDevice.compiler;
624 struct brw_tcs_prog_key tcs_key = {};
625 struct brw_tes_prog_key tes_key = {};
626 struct anv_shader_bin *tcs_bin = NULL;
627 struct anv_shader_bin *tes_bin = NULL;
628
629 populate_sampler_prog_key(&pipeline->device->info, &tcs_key.tex);
630 populate_sampler_prog_key(&pipeline->device->info, &tes_key.tex);
631 tcs_key.input_vertices = info->pTessellationState->patchControlPoints;
632
633 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
634
635 unsigned char tcs_sha1[40];
636 unsigned char tes_sha1[40];
637 anv_pipeline_hash_shader(pipeline, layout, tcs_module, tcs_entrypoint,
638 MESA_SHADER_TESS_CTRL, tcs_spec_info,
639 &tcs_key, sizeof(tcs_key), tcs_sha1);
640 anv_pipeline_hash_shader(pipeline, layout, tes_module, tes_entrypoint,
641 MESA_SHADER_TESS_EVAL, tes_spec_info,
642 &tes_key, sizeof(tes_key), tes_sha1);
643 memcpy(&tcs_sha1[20], tes_sha1, 20);
644 memcpy(&tes_sha1[20], tcs_sha1, 20);
645
646 tcs_bin = anv_device_search_for_kernel(pipeline->device, cache,
647 tcs_sha1, sizeof(tcs_sha1));
648 tes_bin = anv_device_search_for_kernel(pipeline->device, cache,
649 tes_sha1, sizeof(tes_sha1));
650
651 if (tcs_bin == NULL || tes_bin == NULL) {
652 struct brw_tcs_prog_data tcs_prog_data = {};
653 struct brw_tes_prog_data tes_prog_data = {};
654 struct anv_pipeline_binding tcs_surface_to_descriptor[256];
655 struct anv_pipeline_binding tcs_sampler_to_descriptor[256];
656 struct anv_pipeline_binding tes_surface_to_descriptor[256];
657 struct anv_pipeline_binding tes_sampler_to_descriptor[256];
658
659 struct anv_pipeline_bind_map tcs_map = {
660 .surface_to_descriptor = tcs_surface_to_descriptor,
661 .sampler_to_descriptor = tcs_sampler_to_descriptor
662 };
663 struct anv_pipeline_bind_map tes_map = {
664 .surface_to_descriptor = tes_surface_to_descriptor,
665 .sampler_to_descriptor = tes_sampler_to_descriptor
666 };
667
668 void *mem_ctx = ralloc_context(NULL);
669
670 nir_shader *tcs_nir =
671 anv_pipeline_compile(pipeline, mem_ctx, layout,
672 tcs_module, tcs_entrypoint,
673 MESA_SHADER_TESS_CTRL, tcs_spec_info,
674 &tcs_prog_data.base.base, &tcs_map);
675 nir_shader *tes_nir =
676 anv_pipeline_compile(pipeline, mem_ctx, layout,
677 tes_module, tes_entrypoint,
678 MESA_SHADER_TESS_EVAL, tes_spec_info,
679 &tes_prog_data.base.base, &tes_map);
680 if (tcs_nir == NULL || tes_nir == NULL) {
681 ralloc_free(mem_ctx);
682 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
683 }
684
685 nir_lower_tes_patch_vertices(tes_nir,
686 tcs_nir->info.tess.tcs_vertices_out);
687
688 /* Copy TCS info into the TES info */
689 merge_tess_info(&tes_nir->info, &tcs_nir->info);
690
691 anv_fill_binding_table(&tcs_prog_data.base.base, 0);
692 anv_fill_binding_table(&tes_prog_data.base.base, 0);
693
694 /* Whacking the key after cache lookup is a bit sketchy, but all of
695 * this comes from the SPIR-V, which is part of the hash used for the
696 * pipeline cache. So it should be safe.
697 */
698 tcs_key.tes_primitive_mode = tes_nir->info.tess.primitive_mode;
699 tcs_key.outputs_written = tcs_nir->info.outputs_written;
700 tcs_key.patch_outputs_written = tcs_nir->info.patch_outputs_written;
701 tcs_key.quads_workaround =
702 devinfo->gen < 9 &&
703 tes_nir->info.tess.primitive_mode == 7 /* GL_QUADS */ &&
704 tes_nir->info.tess.spacing == TESS_SPACING_EQUAL;
705
706 tes_key.inputs_read = tcs_key.outputs_written;
707 tes_key.patch_inputs_read = tcs_key.patch_outputs_written;
708
709 const int shader_time_index = -1;
710 const unsigned *shader_code;
711
712 shader_code =
713 brw_compile_tcs(compiler, NULL, mem_ctx, &tcs_key, &tcs_prog_data,
714 tcs_nir, shader_time_index, NULL);
715 if (shader_code == NULL) {
716 ralloc_free(mem_ctx);
717 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
718 }
719
720 unsigned code_size = tcs_prog_data.base.base.program_size;
721 tcs_bin = anv_device_upload_kernel(pipeline->device, cache,
722 tcs_sha1, sizeof(tcs_sha1),
723 shader_code, code_size,
724 tcs_nir->constant_data,
725 tcs_nir->constant_data_size,
726 &tcs_prog_data.base.base,
727 sizeof(tcs_prog_data),
728 &tcs_map);
729 if (!tcs_bin) {
730 ralloc_free(mem_ctx);
731 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
732 }
733
734 shader_code =
735 brw_compile_tes(compiler, NULL, mem_ctx, &tes_key,
736 &tcs_prog_data.base.vue_map, &tes_prog_data, tes_nir,
737 NULL, shader_time_index, NULL);
738 if (shader_code == NULL) {
739 ralloc_free(mem_ctx);
740 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
741 }
742
743 code_size = tes_prog_data.base.base.program_size;
744 tes_bin = anv_device_upload_kernel(pipeline->device, cache,
745 tes_sha1, sizeof(tes_sha1),
746 shader_code, code_size,
747 tes_nir->constant_data,
748 tes_nir->constant_data_size,
749 &tes_prog_data.base.base,
750 sizeof(tes_prog_data),
751 &tes_map);
752 if (!tes_bin) {
753 ralloc_free(mem_ctx);
754 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
755 }
756
757 ralloc_free(mem_ctx);
758 }
759
760 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_TESS_CTRL, tcs_bin);
761 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_TESS_EVAL, tes_bin);
762
763 return VK_SUCCESS;
764 }
765
766 static VkResult
767 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
768 struct anv_pipeline_cache *cache,
769 const VkGraphicsPipelineCreateInfo *info,
770 struct anv_shader_module *module,
771 const char *entrypoint,
772 const VkSpecializationInfo *spec_info)
773 {
774 const struct brw_compiler *compiler =
775 pipeline->device->instance->physicalDevice.compiler;
776 struct brw_gs_prog_key key;
777 struct anv_shader_bin *bin = NULL;
778
779 populate_gs_prog_key(&pipeline->device->info, &key);
780
781 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
782
783 unsigned char sha1[20];
784 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
785 MESA_SHADER_GEOMETRY, spec_info,
786 &key, sizeof(key), sha1);
787 bin = anv_device_search_for_kernel(pipeline->device, cache, sha1, 20);
788
789 if (bin == NULL) {
790 struct brw_gs_prog_data prog_data = {};
791 struct anv_pipeline_binding surface_to_descriptor[256];
792 struct anv_pipeline_binding sampler_to_descriptor[256];
793
794 struct anv_pipeline_bind_map map = {
795 .surface_to_descriptor = surface_to_descriptor,
796 .sampler_to_descriptor = sampler_to_descriptor
797 };
798
799 void *mem_ctx = ralloc_context(NULL);
800
801 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
802 module, entrypoint,
803 MESA_SHADER_GEOMETRY, spec_info,
804 &prog_data.base.base, &map);
805 if (nir == NULL) {
806 ralloc_free(mem_ctx);
807 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
808 }
809
810 anv_fill_binding_table(&prog_data.base.base, 0);
811
812 brw_compute_vue_map(&pipeline->device->info,
813 &prog_data.base.vue_map,
814 nir->info.outputs_written,
815 nir->info.separate_shader);
816
817 const unsigned *shader_code =
818 brw_compile_gs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
819 NULL, -1, NULL);
820 if (shader_code == NULL) {
821 ralloc_free(mem_ctx);
822 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
823 }
824
825 /* TODO: SIMD8 GS */
826 const unsigned code_size = prog_data.base.base.program_size;
827 bin = anv_device_upload_kernel(pipeline->device, cache, sha1, 20,
828 shader_code, code_size,
829 nir->constant_data,
830 nir->constant_data_size,
831 &prog_data.base.base, sizeof(prog_data),
832 &map);
833 if (!bin) {
834 ralloc_free(mem_ctx);
835 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
836 }
837
838 ralloc_free(mem_ctx);
839 }
840
841 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY, bin);
842
843 return VK_SUCCESS;
844 }
845
846 static VkResult
847 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
848 struct anv_pipeline_cache *cache,
849 const VkGraphicsPipelineCreateInfo *info,
850 struct anv_shader_module *module,
851 const char *entrypoint,
852 const VkSpecializationInfo *spec_info)
853 {
854 const struct brw_compiler *compiler =
855 pipeline->device->instance->physicalDevice.compiler;
856 struct brw_wm_prog_key key;
857 struct anv_shader_bin *bin = NULL;
858
859 populate_wm_prog_key(pipeline, info, &key);
860
861 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
862
863 unsigned char sha1[20];
864 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
865 MESA_SHADER_FRAGMENT, spec_info,
866 &key, sizeof(key), sha1);
867 bin = anv_device_search_for_kernel(pipeline->device, cache, sha1, 20);
868
869 if (bin == NULL) {
870 struct brw_wm_prog_data prog_data = {};
871 struct anv_pipeline_binding surface_to_descriptor[256];
872 struct anv_pipeline_binding sampler_to_descriptor[256];
873
874 struct anv_pipeline_bind_map map = {
875 .surface_to_descriptor = surface_to_descriptor + 8,
876 .sampler_to_descriptor = sampler_to_descriptor
877 };
878
879 void *mem_ctx = ralloc_context(NULL);
880
881 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
882 module, entrypoint,
883 MESA_SHADER_FRAGMENT, spec_info,
884 &prog_data.base, &map);
885 if (nir == NULL) {
886 ralloc_free(mem_ctx);
887 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
888 }
889
890 unsigned num_rts = 0;
891 const int max_rt = FRAG_RESULT_DATA7 - FRAG_RESULT_DATA0 + 1;
892 struct anv_pipeline_binding rt_bindings[max_rt];
893 nir_function_impl *impl = nir_shader_get_entrypoint(nir);
894 int rt_to_bindings[max_rt];
895 memset(rt_to_bindings, -1, sizeof(rt_to_bindings));
896 bool rt_used[max_rt];
897 memset(rt_used, 0, sizeof(rt_used));
898
899 /* Flag used render targets */
900 nir_foreach_variable_safe(var, &nir->outputs) {
901 if (var->data.location < FRAG_RESULT_DATA0)
902 continue;
903
904 const unsigned rt = var->data.location - FRAG_RESULT_DATA0;
905 /* Out-of-bounds */
906 if (rt >= key.nr_color_regions)
907 continue;
908
909 const unsigned array_len =
910 glsl_type_is_array(var->type) ? glsl_get_length(var->type) : 1;
911 assert(rt + array_len <= max_rt);
912
913 for (unsigned i = 0; i < array_len; i++)
914 rt_used[rt + i] = true;
915 }
916
917 /* Set new, compacted, location */
918 for (unsigned i = 0; i < max_rt; i++) {
919 if (!rt_used[i])
920 continue;
921
922 rt_to_bindings[i] = num_rts;
923 rt_bindings[rt_to_bindings[i]] = (struct anv_pipeline_binding) {
924 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
925 .binding = 0,
926 .index = i,
927 };
928 num_rts++;
929 }
930
931 nir_foreach_variable_safe(var, &nir->outputs) {
932 if (var->data.location < FRAG_RESULT_DATA0)
933 continue;
934
935 const unsigned rt = var->data.location - FRAG_RESULT_DATA0;
936 if (rt >= key.nr_color_regions) {
937 /* Out-of-bounds, throw it away */
938 var->data.mode = nir_var_local;
939 exec_node_remove(&var->node);
940 exec_list_push_tail(&impl->locals, &var->node);
941 continue;
942 }
943
944 /* Give it the new location */
945 assert(rt_to_bindings[rt] != -1);
946 var->data.location = rt_to_bindings[rt] + FRAG_RESULT_DATA0;
947 }
948
949 if (num_rts == 0) {
950 /* If we have no render targets, we need a null render target */
951 rt_bindings[0] = (struct anv_pipeline_binding) {
952 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
953 .binding = 0,
954 .index = UINT32_MAX,
955 };
956 num_rts = 1;
957 }
958
959 assert(num_rts <= max_rt);
960 map.surface_to_descriptor -= num_rts;
961 map.surface_count += num_rts;
962 assert(map.surface_count <= 256);
963 memcpy(map.surface_to_descriptor, rt_bindings,
964 num_rts * sizeof(*rt_bindings));
965
966 anv_fill_binding_table(&prog_data.base, num_rts);
967
968 const unsigned *shader_code =
969 brw_compile_fs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
970 NULL, -1, -1, -1, true, false, NULL, NULL);
971 if (shader_code == NULL) {
972 ralloc_free(mem_ctx);
973 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
974 }
975
976 unsigned code_size = prog_data.base.program_size;
977 bin = anv_device_upload_kernel(pipeline->device, cache, sha1, 20,
978 shader_code, code_size,
979 nir->constant_data,
980 nir->constant_data_size,
981 &prog_data.base, sizeof(prog_data),
982 &map);
983 if (!bin) {
984 ralloc_free(mem_ctx);
985 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
986 }
987
988 ralloc_free(mem_ctx);
989 }
990
991 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT, bin);
992
993 return VK_SUCCESS;
994 }
995
996 VkResult
997 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
998 struct anv_pipeline_cache *cache,
999 const VkComputePipelineCreateInfo *info,
1000 struct anv_shader_module *module,
1001 const char *entrypoint,
1002 const VkSpecializationInfo *spec_info)
1003 {
1004 const struct brw_compiler *compiler =
1005 pipeline->device->instance->physicalDevice.compiler;
1006 struct brw_cs_prog_key key;
1007 struct anv_shader_bin *bin = NULL;
1008
1009 populate_cs_prog_key(&pipeline->device->info, &key);
1010
1011 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
1012
1013 unsigned char sha1[20];
1014 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
1015 MESA_SHADER_COMPUTE, spec_info,
1016 &key, sizeof(key), sha1);
1017 bin = anv_device_search_for_kernel(pipeline->device, cache, sha1, 20);
1018
1019 if (bin == NULL) {
1020 struct brw_cs_prog_data prog_data = {};
1021 struct anv_pipeline_binding surface_to_descriptor[256];
1022 struct anv_pipeline_binding sampler_to_descriptor[256];
1023
1024 struct anv_pipeline_bind_map map = {
1025 .surface_to_descriptor = surface_to_descriptor,
1026 .sampler_to_descriptor = sampler_to_descriptor
1027 };
1028
1029 void *mem_ctx = ralloc_context(NULL);
1030
1031 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
1032 module, entrypoint,
1033 MESA_SHADER_COMPUTE, spec_info,
1034 &prog_data.base, &map);
1035 if (nir == NULL) {
1036 ralloc_free(mem_ctx);
1037 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1038 }
1039
1040 NIR_PASS_V(nir, anv_nir_add_base_work_group_id, &prog_data);
1041
1042 anv_fill_binding_table(&prog_data.base, 1);
1043
1044 const unsigned *shader_code =
1045 brw_compile_cs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
1046 -1, NULL);
1047 if (shader_code == NULL) {
1048 ralloc_free(mem_ctx);
1049 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1050 }
1051
1052 const unsigned code_size = prog_data.base.program_size;
1053 bin = anv_device_upload_kernel(pipeline->device, cache, sha1, 20,
1054 shader_code, code_size,
1055 nir->constant_data,
1056 nir->constant_data_size,
1057 &prog_data.base, sizeof(prog_data),
1058 &map);
1059 if (!bin) {
1060 ralloc_free(mem_ctx);
1061 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1062 }
1063
1064 ralloc_free(mem_ctx);
1065 }
1066
1067 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE, bin);
1068
1069 return VK_SUCCESS;
1070 }
1071
1072 /**
1073 * Copy pipeline state not marked as dynamic.
1074 * Dynamic state is pipeline state which hasn't been provided at pipeline
1075 * creation time, but is dynamically provided afterwards using various
1076 * vkCmdSet* functions.
1077 *
1078 * The set of state considered "non_dynamic" is determined by the pieces of
1079 * state that have their corresponding VkDynamicState enums omitted from
1080 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1081 *
1082 * @param[out] pipeline Destination non_dynamic state.
1083 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1084 */
1085 static void
1086 copy_non_dynamic_state(struct anv_pipeline *pipeline,
1087 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1088 {
1089 anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
1090 struct anv_subpass *subpass = pipeline->subpass;
1091
1092 pipeline->dynamic_state = default_dynamic_state;
1093
1094 if (pCreateInfo->pDynamicState) {
1095 /* Remove all of the states that are marked as dynamic */
1096 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1097 for (uint32_t s = 0; s < count; s++)
1098 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1099 }
1100
1101 struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
1102
1103 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1104 *
1105 * pViewportState is [...] NULL if the pipeline
1106 * has rasterization disabled.
1107 */
1108 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1109 assert(pCreateInfo->pViewportState);
1110
1111 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1112 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1113 typed_memcpy(dynamic->viewport.viewports,
1114 pCreateInfo->pViewportState->pViewports,
1115 pCreateInfo->pViewportState->viewportCount);
1116 }
1117
1118 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1119 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1120 typed_memcpy(dynamic->scissor.scissors,
1121 pCreateInfo->pViewportState->pScissors,
1122 pCreateInfo->pViewportState->scissorCount);
1123 }
1124 }
1125
1126 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1127 assert(pCreateInfo->pRasterizationState);
1128 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1129 }
1130
1131 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1132 assert(pCreateInfo->pRasterizationState);
1133 dynamic->depth_bias.bias =
1134 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1135 dynamic->depth_bias.clamp =
1136 pCreateInfo->pRasterizationState->depthBiasClamp;
1137 dynamic->depth_bias.slope =
1138 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1139 }
1140
1141 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1142 *
1143 * pColorBlendState is [...] NULL if the pipeline has rasterization
1144 * disabled or if the subpass of the render pass the pipeline is
1145 * created against does not use any color attachments.
1146 */
1147 bool uses_color_att = false;
1148 for (unsigned i = 0; i < subpass->color_count; ++i) {
1149 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1150 uses_color_att = true;
1151 break;
1152 }
1153 }
1154
1155 if (uses_color_att &&
1156 !pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1157 assert(pCreateInfo->pColorBlendState);
1158
1159 if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
1160 typed_memcpy(dynamic->blend_constants,
1161 pCreateInfo->pColorBlendState->blendConstants, 4);
1162 }
1163
1164 /* If there is no depthstencil attachment, then don't read
1165 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1166 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1167 * no need to override the depthstencil defaults in
1168 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1169 *
1170 * Section 9.2 of the Vulkan 1.0.15 spec says:
1171 *
1172 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1173 * disabled or if the subpass of the render pass the pipeline is created
1174 * against does not use a depth/stencil attachment.
1175 */
1176 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1177 subpass->depth_stencil_attachment) {
1178 assert(pCreateInfo->pDepthStencilState);
1179
1180 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1181 dynamic->depth_bounds.min =
1182 pCreateInfo->pDepthStencilState->minDepthBounds;
1183 dynamic->depth_bounds.max =
1184 pCreateInfo->pDepthStencilState->maxDepthBounds;
1185 }
1186
1187 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1188 dynamic->stencil_compare_mask.front =
1189 pCreateInfo->pDepthStencilState->front.compareMask;
1190 dynamic->stencil_compare_mask.back =
1191 pCreateInfo->pDepthStencilState->back.compareMask;
1192 }
1193
1194 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1195 dynamic->stencil_write_mask.front =
1196 pCreateInfo->pDepthStencilState->front.writeMask;
1197 dynamic->stencil_write_mask.back =
1198 pCreateInfo->pDepthStencilState->back.writeMask;
1199 }
1200
1201 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1202 dynamic->stencil_reference.front =
1203 pCreateInfo->pDepthStencilState->front.reference;
1204 dynamic->stencil_reference.back =
1205 pCreateInfo->pDepthStencilState->back.reference;
1206 }
1207 }
1208
1209 pipeline->dynamic_state_mask = states;
1210 }
1211
1212 static void
1213 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
1214 {
1215 #ifdef DEBUG
1216 struct anv_render_pass *renderpass = NULL;
1217 struct anv_subpass *subpass = NULL;
1218
1219 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1220 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1221 */
1222 assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
1223
1224 renderpass = anv_render_pass_from_handle(info->renderPass);
1225 assert(renderpass);
1226
1227 assert(info->subpass < renderpass->subpass_count);
1228 subpass = &renderpass->subpasses[info->subpass];
1229
1230 assert(info->stageCount >= 1);
1231 assert(info->pVertexInputState);
1232 assert(info->pInputAssemblyState);
1233 assert(info->pRasterizationState);
1234 if (!info->pRasterizationState->rasterizerDiscardEnable) {
1235 assert(info->pViewportState);
1236 assert(info->pMultisampleState);
1237
1238 if (subpass && subpass->depth_stencil_attachment)
1239 assert(info->pDepthStencilState);
1240
1241 if (subpass && subpass->color_count > 0) {
1242 bool all_color_unused = true;
1243 for (int i = 0; i < subpass->color_count; i++) {
1244 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1245 all_color_unused = false;
1246 }
1247 /* pColorBlendState is ignored if the pipeline has rasterization
1248 * disabled or if the subpass of the render pass the pipeline is
1249 * created against does not use any color attachments.
1250 */
1251 assert(info->pColorBlendState || all_color_unused);
1252 }
1253 }
1254
1255 for (uint32_t i = 0; i < info->stageCount; ++i) {
1256 switch (info->pStages[i].stage) {
1257 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
1258 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
1259 assert(info->pTessellationState);
1260 break;
1261 default:
1262 break;
1263 }
1264 }
1265 #endif
1266 }
1267
1268 /**
1269 * Calculate the desired L3 partitioning based on the current state of the
1270 * pipeline. For now this simply returns the conservative defaults calculated
1271 * by get_default_l3_weights(), but we could probably do better by gathering
1272 * more statistics from the pipeline state (e.g. guess of expected URB usage
1273 * and bound surfaces), or by using feed-back from performance counters.
1274 */
1275 void
1276 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm)
1277 {
1278 const struct gen_device_info *devinfo = &pipeline->device->info;
1279
1280 const struct gen_l3_weights w =
1281 gen_get_default_l3_weights(devinfo, pipeline->needs_data_cache, needs_slm);
1282
1283 pipeline->urb.l3_config = gen_get_l3_config(devinfo, w);
1284 pipeline->urb.total_size =
1285 gen_get_l3_config_urb_size(devinfo, pipeline->urb.l3_config);
1286 }
1287
1288 VkResult
1289 anv_pipeline_init(struct anv_pipeline *pipeline,
1290 struct anv_device *device,
1291 struct anv_pipeline_cache *cache,
1292 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1293 const VkAllocationCallbacks *alloc)
1294 {
1295 VkResult result;
1296
1297 anv_pipeline_validate_create_info(pCreateInfo);
1298
1299 if (alloc == NULL)
1300 alloc = &device->alloc;
1301
1302 pipeline->device = device;
1303
1304 ANV_FROM_HANDLE(anv_render_pass, render_pass, pCreateInfo->renderPass);
1305 assert(pCreateInfo->subpass < render_pass->subpass_count);
1306 pipeline->subpass = &render_pass->subpasses[pCreateInfo->subpass];
1307
1308 result = anv_reloc_list_init(&pipeline->batch_relocs, alloc);
1309 if (result != VK_SUCCESS)
1310 return result;
1311
1312 pipeline->batch.alloc = alloc;
1313 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
1314 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
1315 pipeline->batch.relocs = &pipeline->batch_relocs;
1316 pipeline->batch.status = VK_SUCCESS;
1317
1318 copy_non_dynamic_state(pipeline, pCreateInfo);
1319 pipeline->depth_clamp_enable = pCreateInfo->pRasterizationState &&
1320 pCreateInfo->pRasterizationState->depthClampEnable;
1321
1322 pipeline->sample_shading_enable = pCreateInfo->pMultisampleState &&
1323 pCreateInfo->pMultisampleState->sampleShadingEnable;
1324
1325 pipeline->needs_data_cache = false;
1326
1327 /* When we free the pipeline, we detect stages based on the NULL status
1328 * of various prog_data pointers. Make them NULL by default.
1329 */
1330 memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
1331
1332 pipeline->active_stages = 0;
1333
1334 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = {};
1335 struct anv_shader_module *modules[MESA_SHADER_STAGES] = {};
1336 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1337 VkShaderStageFlagBits vk_stage = pCreateInfo->pStages[i].stage;
1338 gl_shader_stage stage = vk_to_mesa_shader_stage(vk_stage);
1339 pStages[stage] = &pCreateInfo->pStages[i];
1340 modules[stage] = anv_shader_module_from_handle(pStages[stage]->module);
1341 pipeline->active_stages |= vk_stage;
1342 }
1343
1344 if (pipeline->active_stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT)
1345 pipeline->active_stages |= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT;
1346
1347 assert(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT);
1348
1349 if (modules[MESA_SHADER_VERTEX]) {
1350 result = anv_pipeline_compile_vs(pipeline, cache, pCreateInfo,
1351 modules[MESA_SHADER_VERTEX],
1352 pStages[MESA_SHADER_VERTEX]->pName,
1353 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo);
1354 if (result != VK_SUCCESS)
1355 goto compile_fail;
1356 }
1357
1358 if (modules[MESA_SHADER_TESS_EVAL]) {
1359 result = anv_pipeline_compile_tcs_tes(pipeline, cache, pCreateInfo,
1360 modules[MESA_SHADER_TESS_CTRL],
1361 pStages[MESA_SHADER_TESS_CTRL]->pName,
1362 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
1363 modules[MESA_SHADER_TESS_EVAL],
1364 pStages[MESA_SHADER_TESS_EVAL]->pName,
1365 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo);
1366 if (result != VK_SUCCESS)
1367 goto compile_fail;
1368 }
1369
1370 if (modules[MESA_SHADER_GEOMETRY]) {
1371 result = anv_pipeline_compile_gs(pipeline, cache, pCreateInfo,
1372 modules[MESA_SHADER_GEOMETRY],
1373 pStages[MESA_SHADER_GEOMETRY]->pName,
1374 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo);
1375 if (result != VK_SUCCESS)
1376 goto compile_fail;
1377 }
1378
1379 if (modules[MESA_SHADER_FRAGMENT]) {
1380 result = anv_pipeline_compile_fs(pipeline, cache, pCreateInfo,
1381 modules[MESA_SHADER_FRAGMENT],
1382 pStages[MESA_SHADER_FRAGMENT]->pName,
1383 pStages[MESA_SHADER_FRAGMENT]->pSpecializationInfo);
1384 if (result != VK_SUCCESS)
1385 goto compile_fail;
1386 }
1387
1388 assert(pipeline->shaders[MESA_SHADER_VERTEX]);
1389
1390 anv_pipeline_setup_l3_config(pipeline, false);
1391
1392 const VkPipelineVertexInputStateCreateInfo *vi_info =
1393 pCreateInfo->pVertexInputState;
1394
1395 const uint64_t inputs_read = get_vs_prog_data(pipeline)->inputs_read;
1396
1397 pipeline->vb_used = 0;
1398 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1399 const VkVertexInputAttributeDescription *desc =
1400 &vi_info->pVertexAttributeDescriptions[i];
1401
1402 if (inputs_read & (1ull << (VERT_ATTRIB_GENERIC0 + desc->location)))
1403 pipeline->vb_used |= 1 << desc->binding;
1404 }
1405
1406 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1407 const VkVertexInputBindingDescription *desc =
1408 &vi_info->pVertexBindingDescriptions[i];
1409
1410 pipeline->vb[desc->binding].stride = desc->stride;
1411
1412 /* Step rate is programmed per vertex element (attribute), not
1413 * binding. Set up a map of which bindings step per instance, for
1414 * reference by vertex element setup. */
1415 switch (desc->inputRate) {
1416 default:
1417 case VK_VERTEX_INPUT_RATE_VERTEX:
1418 pipeline->vb[desc->binding].instanced = false;
1419 break;
1420 case VK_VERTEX_INPUT_RATE_INSTANCE:
1421 pipeline->vb[desc->binding].instanced = true;
1422 break;
1423 }
1424 }
1425
1426 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1427 pCreateInfo->pInputAssemblyState;
1428 const VkPipelineTessellationStateCreateInfo *tess_info =
1429 pCreateInfo->pTessellationState;
1430 pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1431
1432 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
1433 pipeline->topology = _3DPRIM_PATCHLIST(tess_info->patchControlPoints);
1434 else
1435 pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1436
1437 return VK_SUCCESS;
1438
1439 compile_fail:
1440 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
1441 if (pipeline->shaders[s])
1442 anv_shader_bin_unref(device, pipeline->shaders[s]);
1443 }
1444
1445 anv_reloc_list_finish(&pipeline->batch_relocs, alloc);
1446
1447 return result;
1448 }