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anv: Trivially implement VK_KHR_device_group
[mesa.git] / src / intel / vulkan / anv_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "util/mesa-sha1.h"
31 #include "common/gen_l3_config.h"
32 #include "anv_private.h"
33 #include "compiler/brw_nir.h"
34 #include "anv_nir.h"
35 #include "spirv/nir_spirv.h"
36
37 /* Needed for SWIZZLE macros */
38 #include "program/prog_instruction.h"
39
40 // Shader functions
41
42 VkResult anv_CreateShaderModule(
43 VkDevice _device,
44 const VkShaderModuleCreateInfo* pCreateInfo,
45 const VkAllocationCallbacks* pAllocator,
46 VkShaderModule* pShaderModule)
47 {
48 ANV_FROM_HANDLE(anv_device, device, _device);
49 struct anv_shader_module *module;
50
51 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
52 assert(pCreateInfo->flags == 0);
53
54 module = vk_alloc2(&device->alloc, pAllocator,
55 sizeof(*module) + pCreateInfo->codeSize, 8,
56 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
57 if (module == NULL)
58 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
59
60 module->size = pCreateInfo->codeSize;
61 memcpy(module->data, pCreateInfo->pCode, module->size);
62
63 _mesa_sha1_compute(module->data, module->size, module->sha1);
64
65 *pShaderModule = anv_shader_module_to_handle(module);
66
67 return VK_SUCCESS;
68 }
69
70 void anv_DestroyShaderModule(
71 VkDevice _device,
72 VkShaderModule _module,
73 const VkAllocationCallbacks* pAllocator)
74 {
75 ANV_FROM_HANDLE(anv_device, device, _device);
76 ANV_FROM_HANDLE(anv_shader_module, module, _module);
77
78 if (!module)
79 return;
80
81 vk_free2(&device->alloc, pAllocator, module);
82 }
83
84 #define SPIR_V_MAGIC_NUMBER 0x07230203
85
86 static const uint64_t stage_to_debug[] = {
87 [MESA_SHADER_VERTEX] = DEBUG_VS,
88 [MESA_SHADER_TESS_CTRL] = DEBUG_TCS,
89 [MESA_SHADER_TESS_EVAL] = DEBUG_TES,
90 [MESA_SHADER_GEOMETRY] = DEBUG_GS,
91 [MESA_SHADER_FRAGMENT] = DEBUG_WM,
92 [MESA_SHADER_COMPUTE] = DEBUG_CS,
93 };
94
95 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
96 * we can't do that yet because we don't have the ability to copy nir.
97 */
98 static nir_shader *
99 anv_shader_compile_to_nir(struct anv_pipeline *pipeline,
100 void *mem_ctx,
101 struct anv_shader_module *module,
102 const char *entrypoint_name,
103 gl_shader_stage stage,
104 const VkSpecializationInfo *spec_info)
105 {
106 const struct anv_device *device = pipeline->device;
107
108 const struct brw_compiler *compiler =
109 device->instance->physicalDevice.compiler;
110 const nir_shader_compiler_options *nir_options =
111 compiler->glsl_compiler_options[stage].NirOptions;
112
113 uint32_t *spirv = (uint32_t *) module->data;
114 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
115 assert(module->size % 4 == 0);
116
117 uint32_t num_spec_entries = 0;
118 struct nir_spirv_specialization *spec_entries = NULL;
119 if (spec_info && spec_info->mapEntryCount > 0) {
120 num_spec_entries = spec_info->mapEntryCount;
121 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
122 for (uint32_t i = 0; i < num_spec_entries; i++) {
123 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
124 const void *data = spec_info->pData + entry.offset;
125 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
126
127 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
128 if (spec_info->dataSize == 8)
129 spec_entries[i].data64 = *(const uint64_t *)data;
130 else
131 spec_entries[i].data32 = *(const uint32_t *)data;
132 }
133 }
134
135 struct spirv_to_nir_options spirv_options = {
136 .lower_workgroup_access_to_offsets = true,
137 .caps = {
138 .float64 = device->instance->physicalDevice.info.gen >= 8,
139 .int64 = device->instance->physicalDevice.info.gen >= 8,
140 .tessellation = true,
141 .device_group = true,
142 .draw_parameters = true,
143 .image_write_without_format = true,
144 .multiview = true,
145 .variable_pointers = true,
146 .storage_16bit = device->instance->physicalDevice.info.gen >= 8,
147 },
148 };
149
150 nir_function *entry_point =
151 spirv_to_nir(spirv, module->size / 4,
152 spec_entries, num_spec_entries,
153 stage, entrypoint_name, &spirv_options, nir_options);
154 nir_shader *nir = entry_point->shader;
155 assert(nir->info.stage == stage);
156 nir_validate_shader(nir);
157 ralloc_steal(mem_ctx, nir);
158
159 free(spec_entries);
160
161 if (unlikely(INTEL_DEBUG & stage_to_debug[stage])) {
162 fprintf(stderr, "NIR (from SPIR-V) for %s shader:\n",
163 gl_shader_stage_name(stage));
164 nir_print_shader(nir, stderr);
165 }
166
167 /* We have to lower away local constant initializers right before we
168 * inline functions. That way they get properly initialized at the top
169 * of the function and not at the top of its caller.
170 */
171 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
172 NIR_PASS_V(nir, nir_lower_returns);
173 NIR_PASS_V(nir, nir_inline_functions);
174
175 /* Pick off the single entrypoint that we want */
176 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
177 if (func != entry_point)
178 exec_node_remove(&func->node);
179 }
180 assert(exec_list_length(&nir->functions) == 1);
181 entry_point->name = ralloc_strdup(entry_point, "main");
182
183 /* Make sure we lower constant initializers on output variables so that
184 * nir_remove_dead_variables below sees the corresponding stores
185 */
186 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
187
188 NIR_PASS_V(nir, nir_remove_dead_variables,
189 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
190
191 if (stage == MESA_SHADER_FRAGMENT)
192 NIR_PASS_V(nir, nir_lower_wpos_center, pipeline->sample_shading_enable);
193
194 /* Now that we've deleted all but the main function, we can go ahead and
195 * lower the rest of the constant initializers.
196 */
197 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
198 NIR_PASS_V(nir, nir_propagate_invariant);
199 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
200 entry_point->impl, true, false);
201
202 /* Vulkan uses the separate-shader linking model */
203 nir->info.separate_shader = true;
204
205 nir = brw_preprocess_nir(compiler, nir);
206
207 if (stage == MESA_SHADER_FRAGMENT)
208 NIR_PASS_V(nir, anv_nir_lower_input_attachments);
209
210 return nir;
211 }
212
213 void anv_DestroyPipeline(
214 VkDevice _device,
215 VkPipeline _pipeline,
216 const VkAllocationCallbacks* pAllocator)
217 {
218 ANV_FROM_HANDLE(anv_device, device, _device);
219 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
220
221 if (!pipeline)
222 return;
223
224 anv_reloc_list_finish(&pipeline->batch_relocs,
225 pAllocator ? pAllocator : &device->alloc);
226 if (pipeline->blend_state.map)
227 anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
228
229 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
230 if (pipeline->shaders[s])
231 anv_shader_bin_unref(device, pipeline->shaders[s]);
232 }
233
234 vk_free2(&device->alloc, pAllocator, pipeline);
235 }
236
237 static const uint32_t vk_to_gen_primitive_type[] = {
238 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
239 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
240 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
241 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
242 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
243 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
244 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
245 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
246 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
247 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
248 };
249
250 static void
251 populate_sampler_prog_key(const struct gen_device_info *devinfo,
252 struct brw_sampler_prog_key_data *key)
253 {
254 /* Almost all multisampled textures are compressed. The only time when we
255 * don't compress a multisampled texture is for 16x MSAA with a surface
256 * width greater than 8k which is a bit of an edge case. Since the sampler
257 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
258 * to tell the compiler to always assume compression.
259 */
260 key->compressed_multisample_layout_mask = ~0;
261
262 /* SkyLake added support for 16x MSAA. With this came a new message for
263 * reading from a 16x MSAA surface with compression. The new message was
264 * needed because now the MCS data is 64 bits instead of 32 or lower as is
265 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
266 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
267 * so we can just use it unconditionally. This may not be quite as
268 * efficient but it saves us from recompiling.
269 */
270 if (devinfo->gen >= 9)
271 key->msaa_16 = ~0;
272
273 /* XXX: Handle texture swizzle on HSW- */
274 for (int i = 0; i < MAX_SAMPLERS; i++) {
275 /* Assume color sampler, no swizzling. (Works for BDW+) */
276 key->swizzles[i] = SWIZZLE_XYZW;
277 }
278 }
279
280 static void
281 populate_vs_prog_key(const struct gen_device_info *devinfo,
282 struct brw_vs_prog_key *key)
283 {
284 memset(key, 0, sizeof(*key));
285
286 populate_sampler_prog_key(devinfo, &key->tex);
287
288 /* XXX: Handle vertex input work-arounds */
289
290 /* XXX: Handle sampler_prog_key */
291 }
292
293 static void
294 populate_gs_prog_key(const struct gen_device_info *devinfo,
295 struct brw_gs_prog_key *key)
296 {
297 memset(key, 0, sizeof(*key));
298
299 populate_sampler_prog_key(devinfo, &key->tex);
300 }
301
302 static void
303 populate_wm_prog_key(const struct anv_pipeline *pipeline,
304 const VkGraphicsPipelineCreateInfo *info,
305 struct brw_wm_prog_key *key)
306 {
307 const struct gen_device_info *devinfo = &pipeline->device->info;
308
309 memset(key, 0, sizeof(*key));
310
311 populate_sampler_prog_key(devinfo, &key->tex);
312
313 /* TODO: we could set this to 0 based on the information in nir_shader, but
314 * this function is called before spirv_to_nir. */
315 const struct brw_vue_map *vue_map =
316 &anv_pipeline_get_last_vue_prog_data(pipeline)->vue_map;
317 key->input_slots_valid = vue_map->slots_valid;
318
319 /* Vulkan doesn't specify a default */
320 key->high_quality_derivatives = false;
321
322 /* XXX Vulkan doesn't appear to specify */
323 key->clamp_fragment_color = false;
324
325 key->nr_color_regions = pipeline->subpass->color_count;
326
327 key->replicate_alpha = key->nr_color_regions > 1 &&
328 info->pMultisampleState &&
329 info->pMultisampleState->alphaToCoverageEnable;
330
331 if (info->pMultisampleState) {
332 /* We should probably pull this out of the shader, but it's fairly
333 * harmless to compute it and then let dead-code take care of it.
334 */
335 if (info->pMultisampleState->rasterizationSamples > 1) {
336 key->persample_interp =
337 (info->pMultisampleState->minSampleShading *
338 info->pMultisampleState->rasterizationSamples) > 1;
339 key->multisample_fbo = true;
340 }
341
342 key->frag_coord_adds_sample_pos =
343 info->pMultisampleState->sampleShadingEnable;
344 }
345 }
346
347 static void
348 populate_cs_prog_key(const struct gen_device_info *devinfo,
349 struct brw_cs_prog_key *key)
350 {
351 memset(key, 0, sizeof(*key));
352
353 populate_sampler_prog_key(devinfo, &key->tex);
354 }
355
356 static void
357 anv_pipeline_hash_shader(struct anv_pipeline *pipeline,
358 struct anv_pipeline_layout *layout,
359 struct anv_shader_module *module,
360 const char *entrypoint,
361 gl_shader_stage stage,
362 const VkSpecializationInfo *spec_info,
363 const void *key, size_t key_size,
364 unsigned char *sha1_out)
365 {
366 struct mesa_sha1 ctx;
367
368 _mesa_sha1_init(&ctx);
369 if (stage != MESA_SHADER_COMPUTE) {
370 _mesa_sha1_update(&ctx, &pipeline->subpass->view_mask,
371 sizeof(pipeline->subpass->view_mask));
372 }
373 if (layout)
374 _mesa_sha1_update(&ctx, layout->sha1, sizeof(layout->sha1));
375 _mesa_sha1_update(&ctx, module->sha1, sizeof(module->sha1));
376 _mesa_sha1_update(&ctx, entrypoint, strlen(entrypoint));
377 _mesa_sha1_update(&ctx, &stage, sizeof(stage));
378 if (spec_info) {
379 _mesa_sha1_update(&ctx, spec_info->pMapEntries,
380 spec_info->mapEntryCount * sizeof(*spec_info->pMapEntries));
381 _mesa_sha1_update(&ctx, spec_info->pData, spec_info->dataSize);
382 }
383 _mesa_sha1_update(&ctx, key, key_size);
384 _mesa_sha1_final(&ctx, sha1_out);
385 }
386
387 static nir_shader *
388 anv_pipeline_compile(struct anv_pipeline *pipeline,
389 void *mem_ctx,
390 struct anv_pipeline_layout *layout,
391 struct anv_shader_module *module,
392 const char *entrypoint,
393 gl_shader_stage stage,
394 const VkSpecializationInfo *spec_info,
395 struct brw_stage_prog_data *prog_data,
396 struct anv_pipeline_bind_map *map)
397 {
398 const struct brw_compiler *compiler =
399 pipeline->device->instance->physicalDevice.compiler;
400
401 nir_shader *nir = anv_shader_compile_to_nir(pipeline, mem_ctx,
402 module, entrypoint, stage,
403 spec_info);
404 if (nir == NULL)
405 return NULL;
406
407 NIR_PASS_V(nir, anv_nir_lower_ycbcr_textures, layout);
408
409 NIR_PASS_V(nir, anv_nir_lower_push_constants);
410
411 if (stage != MESA_SHADER_COMPUTE)
412 NIR_PASS_V(nir, anv_nir_lower_multiview, pipeline->subpass->view_mask);
413
414 if (stage == MESA_SHADER_COMPUTE)
415 prog_data->total_shared = nir->num_shared;
416
417 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
418
419 if (nir->num_uniforms > 0) {
420 assert(prog_data->nr_params == 0);
421
422 /* If the shader uses any push constants at all, we'll just give
423 * them the maximum possible number
424 */
425 assert(nir->num_uniforms <= MAX_PUSH_CONSTANTS_SIZE);
426 nir->num_uniforms = MAX_PUSH_CONSTANTS_SIZE;
427 prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
428 prog_data->param = ralloc_array(mem_ctx, uint32_t, prog_data->nr_params);
429
430 /* We now set the param values to be offsets into a
431 * anv_push_constant_data structure. Since the compiler doesn't
432 * actually dereference any of the gl_constant_value pointers in the
433 * params array, it doesn't really matter what we put here.
434 */
435 struct anv_push_constants *null_data = NULL;
436 /* Fill out the push constants section of the param array */
437 for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++) {
438 prog_data->param[i] = ANV_PARAM_PUSH(
439 (uintptr_t)&null_data->client_data[i * sizeof(float)]);
440 }
441 }
442
443 if (nir->info.num_ssbos > 0 || nir->info.num_images > 0)
444 pipeline->needs_data_cache = true;
445
446 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
447 if (layout)
448 anv_nir_apply_pipeline_layout(pipeline, layout, nir, prog_data, map);
449
450 if (stage != MESA_SHADER_COMPUTE)
451 brw_nir_analyze_ubo_ranges(compiler, nir, prog_data->ubo_ranges);
452
453 assert(nir->num_uniforms == prog_data->nr_params * 4);
454
455 return nir;
456 }
457
458 static void
459 anv_fill_binding_table(struct brw_stage_prog_data *prog_data, unsigned bias)
460 {
461 prog_data->binding_table.size_bytes = 0;
462 prog_data->binding_table.texture_start = bias;
463 prog_data->binding_table.gather_texture_start = bias;
464 prog_data->binding_table.ubo_start = bias;
465 prog_data->binding_table.ssbo_start = bias;
466 prog_data->binding_table.image_start = bias;
467 }
468
469 static struct anv_shader_bin *
470 anv_pipeline_upload_kernel(struct anv_pipeline *pipeline,
471 struct anv_pipeline_cache *cache,
472 const void *key_data, uint32_t key_size,
473 const void *kernel_data, uint32_t kernel_size,
474 const struct brw_stage_prog_data *prog_data,
475 uint32_t prog_data_size,
476 const struct anv_pipeline_bind_map *bind_map)
477 {
478 if (cache) {
479 return anv_pipeline_cache_upload_kernel(cache, key_data, key_size,
480 kernel_data, kernel_size,
481 prog_data, prog_data_size,
482 bind_map);
483 } else {
484 return anv_shader_bin_create(pipeline->device, key_data, key_size,
485 kernel_data, kernel_size,
486 prog_data, prog_data_size,
487 prog_data->param, bind_map);
488 }
489 }
490
491
492 static void
493 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
494 gl_shader_stage stage,
495 struct anv_shader_bin *shader)
496 {
497 pipeline->shaders[stage] = shader;
498 pipeline->active_stages |= mesa_to_vk_shader_stage(stage);
499 }
500
501 static VkResult
502 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
503 struct anv_pipeline_cache *cache,
504 const VkGraphicsPipelineCreateInfo *info,
505 struct anv_shader_module *module,
506 const char *entrypoint,
507 const VkSpecializationInfo *spec_info)
508 {
509 const struct brw_compiler *compiler =
510 pipeline->device->instance->physicalDevice.compiler;
511 struct brw_vs_prog_key key;
512 struct anv_shader_bin *bin = NULL;
513 unsigned char sha1[20];
514
515 populate_vs_prog_key(&pipeline->device->info, &key);
516
517 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
518
519 if (cache) {
520 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
521 MESA_SHADER_VERTEX, spec_info,
522 &key, sizeof(key), sha1);
523 bin = anv_pipeline_cache_search(cache, sha1, 20);
524 }
525
526 if (bin == NULL) {
527 struct brw_vs_prog_data prog_data = {};
528 struct anv_pipeline_binding surface_to_descriptor[256];
529 struct anv_pipeline_binding sampler_to_descriptor[256];
530
531 struct anv_pipeline_bind_map map = {
532 .surface_to_descriptor = surface_to_descriptor,
533 .sampler_to_descriptor = sampler_to_descriptor
534 };
535
536 void *mem_ctx = ralloc_context(NULL);
537
538 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
539 module, entrypoint,
540 MESA_SHADER_VERTEX, spec_info,
541 &prog_data.base.base, &map);
542 if (nir == NULL) {
543 ralloc_free(mem_ctx);
544 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
545 }
546
547 anv_fill_binding_table(&prog_data.base.base, 0);
548
549 brw_compute_vue_map(&pipeline->device->info,
550 &prog_data.base.vue_map,
551 nir->info.outputs_written,
552 nir->info.separate_shader);
553
554 const unsigned *shader_code =
555 brw_compile_vs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
556 -1, NULL);
557 if (shader_code == NULL) {
558 ralloc_free(mem_ctx);
559 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
560 }
561
562 unsigned code_size = prog_data.base.base.program_size;
563 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
564 shader_code, code_size,
565 &prog_data.base.base, sizeof(prog_data),
566 &map);
567 if (!bin) {
568 ralloc_free(mem_ctx);
569 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
570 }
571
572 ralloc_free(mem_ctx);
573 }
574
575 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX, bin);
576
577 return VK_SUCCESS;
578 }
579
580 static void
581 merge_tess_info(struct shader_info *tes_info,
582 const struct shader_info *tcs_info)
583 {
584 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
585 *
586 * "PointMode. Controls generation of points rather than triangles
587 * or lines. This functionality defaults to disabled, and is
588 * enabled if either shader stage includes the execution mode.
589 *
590 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
591 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
592 * and OutputVertices, it says:
593 *
594 * "One mode must be set in at least one of the tessellation
595 * shader stages."
596 *
597 * So, the fields can be set in either the TCS or TES, but they must
598 * agree if set in both. Our backend looks at TES, so bitwise-or in
599 * the values from the TCS.
600 */
601 assert(tcs_info->tess.tcs_vertices_out == 0 ||
602 tes_info->tess.tcs_vertices_out == 0 ||
603 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
604 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
605
606 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
607 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
608 tcs_info->tess.spacing == tes_info->tess.spacing);
609 tes_info->tess.spacing |= tcs_info->tess.spacing;
610
611 assert(tcs_info->tess.primitive_mode == 0 ||
612 tes_info->tess.primitive_mode == 0 ||
613 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
614 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
615 tes_info->tess.ccw |= tcs_info->tess.ccw;
616 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
617 }
618
619 static VkResult
620 anv_pipeline_compile_tcs_tes(struct anv_pipeline *pipeline,
621 struct anv_pipeline_cache *cache,
622 const VkGraphicsPipelineCreateInfo *info,
623 struct anv_shader_module *tcs_module,
624 const char *tcs_entrypoint,
625 const VkSpecializationInfo *tcs_spec_info,
626 struct anv_shader_module *tes_module,
627 const char *tes_entrypoint,
628 const VkSpecializationInfo *tes_spec_info)
629 {
630 const struct gen_device_info *devinfo = &pipeline->device->info;
631 const struct brw_compiler *compiler =
632 pipeline->device->instance->physicalDevice.compiler;
633 struct brw_tcs_prog_key tcs_key = {};
634 struct brw_tes_prog_key tes_key = {};
635 struct anv_shader_bin *tcs_bin = NULL;
636 struct anv_shader_bin *tes_bin = NULL;
637 unsigned char tcs_sha1[40];
638 unsigned char tes_sha1[40];
639
640 populate_sampler_prog_key(&pipeline->device->info, &tcs_key.tex);
641 populate_sampler_prog_key(&pipeline->device->info, &tes_key.tex);
642 tcs_key.input_vertices = info->pTessellationState->patchControlPoints;
643
644 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
645
646 if (cache) {
647 anv_pipeline_hash_shader(pipeline, layout, tcs_module, tcs_entrypoint,
648 MESA_SHADER_TESS_CTRL, tcs_spec_info,
649 &tcs_key, sizeof(tcs_key), tcs_sha1);
650 anv_pipeline_hash_shader(pipeline, layout, tes_module, tes_entrypoint,
651 MESA_SHADER_TESS_EVAL, tes_spec_info,
652 &tes_key, sizeof(tes_key), tes_sha1);
653 memcpy(&tcs_sha1[20], tes_sha1, 20);
654 memcpy(&tes_sha1[20], tcs_sha1, 20);
655 tcs_bin = anv_pipeline_cache_search(cache, tcs_sha1, sizeof(tcs_sha1));
656 tes_bin = anv_pipeline_cache_search(cache, tes_sha1, sizeof(tes_sha1));
657 }
658
659 if (tcs_bin == NULL || tes_bin == NULL) {
660 struct brw_tcs_prog_data tcs_prog_data = {};
661 struct brw_tes_prog_data tes_prog_data = {};
662 struct anv_pipeline_binding tcs_surface_to_descriptor[256];
663 struct anv_pipeline_binding tcs_sampler_to_descriptor[256];
664 struct anv_pipeline_binding tes_surface_to_descriptor[256];
665 struct anv_pipeline_binding tes_sampler_to_descriptor[256];
666
667 struct anv_pipeline_bind_map tcs_map = {
668 .surface_to_descriptor = tcs_surface_to_descriptor,
669 .sampler_to_descriptor = tcs_sampler_to_descriptor
670 };
671 struct anv_pipeline_bind_map tes_map = {
672 .surface_to_descriptor = tes_surface_to_descriptor,
673 .sampler_to_descriptor = tes_sampler_to_descriptor
674 };
675
676 void *mem_ctx = ralloc_context(NULL);
677
678 nir_shader *tcs_nir =
679 anv_pipeline_compile(pipeline, mem_ctx, layout,
680 tcs_module, tcs_entrypoint,
681 MESA_SHADER_TESS_CTRL, tcs_spec_info,
682 &tcs_prog_data.base.base, &tcs_map);
683 nir_shader *tes_nir =
684 anv_pipeline_compile(pipeline, mem_ctx, layout,
685 tes_module, tes_entrypoint,
686 MESA_SHADER_TESS_EVAL, tes_spec_info,
687 &tes_prog_data.base.base, &tes_map);
688 if (tcs_nir == NULL || tes_nir == NULL) {
689 ralloc_free(mem_ctx);
690 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
691 }
692
693 nir_lower_tes_patch_vertices(tes_nir,
694 tcs_nir->info.tess.tcs_vertices_out);
695
696 /* Copy TCS info into the TES info */
697 merge_tess_info(&tes_nir->info, &tcs_nir->info);
698
699 anv_fill_binding_table(&tcs_prog_data.base.base, 0);
700 anv_fill_binding_table(&tes_prog_data.base.base, 0);
701
702 /* Whacking the key after cache lookup is a bit sketchy, but all of
703 * this comes from the SPIR-V, which is part of the hash used for the
704 * pipeline cache. So it should be safe.
705 */
706 tcs_key.tes_primitive_mode = tes_nir->info.tess.primitive_mode;
707 tcs_key.outputs_written = tcs_nir->info.outputs_written;
708 tcs_key.patch_outputs_written = tcs_nir->info.patch_outputs_written;
709 tcs_key.quads_workaround =
710 devinfo->gen < 9 &&
711 tes_nir->info.tess.primitive_mode == 7 /* GL_QUADS */ &&
712 tes_nir->info.tess.spacing == TESS_SPACING_EQUAL;
713
714 tes_key.inputs_read = tcs_key.outputs_written;
715 tes_key.patch_inputs_read = tcs_key.patch_outputs_written;
716
717 const int shader_time_index = -1;
718 const unsigned *shader_code;
719
720 shader_code =
721 brw_compile_tcs(compiler, NULL, mem_ctx, &tcs_key, &tcs_prog_data,
722 tcs_nir, shader_time_index, NULL);
723 if (shader_code == NULL) {
724 ralloc_free(mem_ctx);
725 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
726 }
727
728 unsigned code_size = tcs_prog_data.base.base.program_size;
729 tcs_bin = anv_pipeline_upload_kernel(pipeline, cache,
730 tcs_sha1, sizeof(tcs_sha1),
731 shader_code, code_size,
732 &tcs_prog_data.base.base,
733 sizeof(tcs_prog_data),
734 &tcs_map);
735 if (!tcs_bin) {
736 ralloc_free(mem_ctx);
737 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
738 }
739
740 shader_code =
741 brw_compile_tes(compiler, NULL, mem_ctx, &tes_key,
742 &tcs_prog_data.base.vue_map, &tes_prog_data, tes_nir,
743 NULL, shader_time_index, NULL);
744 if (shader_code == NULL) {
745 ralloc_free(mem_ctx);
746 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
747 }
748
749 code_size = tes_prog_data.base.base.program_size;
750 tes_bin = anv_pipeline_upload_kernel(pipeline, cache,
751 tes_sha1, sizeof(tes_sha1),
752 shader_code, code_size,
753 &tes_prog_data.base.base,
754 sizeof(tes_prog_data),
755 &tes_map);
756 if (!tes_bin) {
757 ralloc_free(mem_ctx);
758 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
759 }
760
761 ralloc_free(mem_ctx);
762 }
763
764 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_TESS_CTRL, tcs_bin);
765 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_TESS_EVAL, tes_bin);
766
767 return VK_SUCCESS;
768 }
769
770 static VkResult
771 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
772 struct anv_pipeline_cache *cache,
773 const VkGraphicsPipelineCreateInfo *info,
774 struct anv_shader_module *module,
775 const char *entrypoint,
776 const VkSpecializationInfo *spec_info)
777 {
778 const struct brw_compiler *compiler =
779 pipeline->device->instance->physicalDevice.compiler;
780 struct brw_gs_prog_key key;
781 struct anv_shader_bin *bin = NULL;
782 unsigned char sha1[20];
783
784 populate_gs_prog_key(&pipeline->device->info, &key);
785
786 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
787
788 if (cache) {
789 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
790 MESA_SHADER_GEOMETRY, spec_info,
791 &key, sizeof(key), sha1);
792 bin = anv_pipeline_cache_search(cache, sha1, 20);
793 }
794
795 if (bin == NULL) {
796 struct brw_gs_prog_data prog_data = {};
797 struct anv_pipeline_binding surface_to_descriptor[256];
798 struct anv_pipeline_binding sampler_to_descriptor[256];
799
800 struct anv_pipeline_bind_map map = {
801 .surface_to_descriptor = surface_to_descriptor,
802 .sampler_to_descriptor = sampler_to_descriptor
803 };
804
805 void *mem_ctx = ralloc_context(NULL);
806
807 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
808 module, entrypoint,
809 MESA_SHADER_GEOMETRY, spec_info,
810 &prog_data.base.base, &map);
811 if (nir == NULL) {
812 ralloc_free(mem_ctx);
813 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
814 }
815
816 anv_fill_binding_table(&prog_data.base.base, 0);
817
818 brw_compute_vue_map(&pipeline->device->info,
819 &prog_data.base.vue_map,
820 nir->info.outputs_written,
821 nir->info.separate_shader);
822
823 const unsigned *shader_code =
824 brw_compile_gs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
825 NULL, -1, NULL);
826 if (shader_code == NULL) {
827 ralloc_free(mem_ctx);
828 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
829 }
830
831 /* TODO: SIMD8 GS */
832 const unsigned code_size = prog_data.base.base.program_size;
833 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
834 shader_code, code_size,
835 &prog_data.base.base, sizeof(prog_data),
836 &map);
837 if (!bin) {
838 ralloc_free(mem_ctx);
839 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
840 }
841
842 ralloc_free(mem_ctx);
843 }
844
845 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY, bin);
846
847 return VK_SUCCESS;
848 }
849
850 static VkResult
851 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
852 struct anv_pipeline_cache *cache,
853 const VkGraphicsPipelineCreateInfo *info,
854 struct anv_shader_module *module,
855 const char *entrypoint,
856 const VkSpecializationInfo *spec_info)
857 {
858 const struct brw_compiler *compiler =
859 pipeline->device->instance->physicalDevice.compiler;
860 struct brw_wm_prog_key key;
861 struct anv_shader_bin *bin = NULL;
862 unsigned char sha1[20];
863
864 populate_wm_prog_key(pipeline, info, &key);
865
866 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
867
868 if (cache) {
869 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
870 MESA_SHADER_FRAGMENT, spec_info,
871 &key, sizeof(key), sha1);
872 bin = anv_pipeline_cache_search(cache, sha1, 20);
873 }
874
875 if (bin == NULL) {
876 struct brw_wm_prog_data prog_data = {};
877 struct anv_pipeline_binding surface_to_descriptor[256];
878 struct anv_pipeline_binding sampler_to_descriptor[256];
879
880 struct anv_pipeline_bind_map map = {
881 .surface_to_descriptor = surface_to_descriptor + 8,
882 .sampler_to_descriptor = sampler_to_descriptor
883 };
884
885 void *mem_ctx = ralloc_context(NULL);
886
887 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
888 module, entrypoint,
889 MESA_SHADER_FRAGMENT, spec_info,
890 &prog_data.base, &map);
891 if (nir == NULL) {
892 ralloc_free(mem_ctx);
893 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
894 }
895
896 unsigned num_rts = 0;
897 const int max_rt = FRAG_RESULT_DATA7 - FRAG_RESULT_DATA0 + 1;
898 struct anv_pipeline_binding rt_bindings[max_rt];
899 nir_function_impl *impl = nir_shader_get_entrypoint(nir);
900 int rt_to_bindings[max_rt];
901 memset(rt_to_bindings, -1, sizeof(rt_to_bindings));
902 bool rt_used[max_rt];
903 memset(rt_used, 0, sizeof(rt_used));
904
905 /* Flag used render targets */
906 nir_foreach_variable_safe(var, &nir->outputs) {
907 if (var->data.location < FRAG_RESULT_DATA0)
908 continue;
909
910 const unsigned rt = var->data.location - FRAG_RESULT_DATA0;
911 /* Out-of-bounds */
912 if (rt >= key.nr_color_regions)
913 continue;
914
915 const unsigned array_len =
916 glsl_type_is_array(var->type) ? glsl_get_length(var->type) : 1;
917 assert(rt + array_len <= max_rt);
918
919 for (unsigned i = 0; i < array_len; i++)
920 rt_used[rt + i] = true;
921 }
922
923 /* Set new, compacted, location */
924 for (unsigned i = 0; i < max_rt; i++) {
925 if (!rt_used[i])
926 continue;
927
928 rt_to_bindings[i] = num_rts;
929 rt_bindings[rt_to_bindings[i]] = (struct anv_pipeline_binding) {
930 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
931 .binding = 0,
932 .index = i,
933 };
934 num_rts++;
935 }
936
937 nir_foreach_variable_safe(var, &nir->outputs) {
938 if (var->data.location < FRAG_RESULT_DATA0)
939 continue;
940
941 const unsigned rt = var->data.location - FRAG_RESULT_DATA0;
942 if (rt >= key.nr_color_regions) {
943 /* Out-of-bounds, throw it away */
944 var->data.mode = nir_var_local;
945 exec_node_remove(&var->node);
946 exec_list_push_tail(&impl->locals, &var->node);
947 continue;
948 }
949
950 /* Give it the new location */
951 assert(rt_to_bindings[rt] != -1);
952 var->data.location = rt_to_bindings[rt] + FRAG_RESULT_DATA0;
953 }
954
955 if (num_rts == 0) {
956 /* If we have no render targets, we need a null render target */
957 rt_bindings[0] = (struct anv_pipeline_binding) {
958 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
959 .binding = 0,
960 .index = UINT32_MAX,
961 };
962 num_rts = 1;
963 }
964
965 assert(num_rts <= max_rt);
966 map.surface_to_descriptor -= num_rts;
967 map.surface_count += num_rts;
968 assert(map.surface_count <= 256);
969 memcpy(map.surface_to_descriptor, rt_bindings,
970 num_rts * sizeof(*rt_bindings));
971
972 anv_fill_binding_table(&prog_data.base, num_rts);
973
974 const unsigned *shader_code =
975 brw_compile_fs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
976 NULL, -1, -1, true, false, NULL, NULL);
977 if (shader_code == NULL) {
978 ralloc_free(mem_ctx);
979 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
980 }
981
982 unsigned code_size = prog_data.base.program_size;
983 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
984 shader_code, code_size,
985 &prog_data.base, sizeof(prog_data),
986 &map);
987 if (!bin) {
988 ralloc_free(mem_ctx);
989 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
990 }
991
992 ralloc_free(mem_ctx);
993 }
994
995 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT, bin);
996
997 return VK_SUCCESS;
998 }
999
1000 VkResult
1001 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
1002 struct anv_pipeline_cache *cache,
1003 const VkComputePipelineCreateInfo *info,
1004 struct anv_shader_module *module,
1005 const char *entrypoint,
1006 const VkSpecializationInfo *spec_info)
1007 {
1008 const struct brw_compiler *compiler =
1009 pipeline->device->instance->physicalDevice.compiler;
1010 struct brw_cs_prog_key key;
1011 struct anv_shader_bin *bin = NULL;
1012 unsigned char sha1[20];
1013
1014 populate_cs_prog_key(&pipeline->device->info, &key);
1015
1016 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
1017
1018 if (cache) {
1019 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
1020 MESA_SHADER_COMPUTE, spec_info,
1021 &key, sizeof(key), sha1);
1022 bin = anv_pipeline_cache_search(cache, sha1, 20);
1023 }
1024
1025 if (bin == NULL) {
1026 struct brw_cs_prog_data prog_data = {};
1027 struct anv_pipeline_binding surface_to_descriptor[256];
1028 struct anv_pipeline_binding sampler_to_descriptor[256];
1029
1030 struct anv_pipeline_bind_map map = {
1031 .surface_to_descriptor = surface_to_descriptor,
1032 .sampler_to_descriptor = sampler_to_descriptor
1033 };
1034
1035 void *mem_ctx = ralloc_context(NULL);
1036
1037 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
1038 module, entrypoint,
1039 MESA_SHADER_COMPUTE, spec_info,
1040 &prog_data.base, &map);
1041 if (nir == NULL) {
1042 ralloc_free(mem_ctx);
1043 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1044 }
1045
1046 NIR_PASS_V(nir, anv_nir_add_base_work_group_id, &prog_data);
1047
1048 anv_fill_binding_table(&prog_data.base, 1);
1049
1050 const unsigned *shader_code =
1051 brw_compile_cs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
1052 -1, NULL);
1053 if (shader_code == NULL) {
1054 ralloc_free(mem_ctx);
1055 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1056 }
1057
1058 const unsigned code_size = prog_data.base.program_size;
1059 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
1060 shader_code, code_size,
1061 &prog_data.base, sizeof(prog_data),
1062 &map);
1063 if (!bin) {
1064 ralloc_free(mem_ctx);
1065 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1066 }
1067
1068 ralloc_free(mem_ctx);
1069 }
1070
1071 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE, bin);
1072
1073 return VK_SUCCESS;
1074 }
1075
1076 /**
1077 * Copy pipeline state not marked as dynamic.
1078 * Dynamic state is pipeline state which hasn't been provided at pipeline
1079 * creation time, but is dynamically provided afterwards using various
1080 * vkCmdSet* functions.
1081 *
1082 * The set of state considered "non_dynamic" is determined by the pieces of
1083 * state that have their corresponding VkDynamicState enums omitted from
1084 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1085 *
1086 * @param[out] pipeline Destination non_dynamic state.
1087 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1088 */
1089 static void
1090 copy_non_dynamic_state(struct anv_pipeline *pipeline,
1091 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1092 {
1093 anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
1094 struct anv_subpass *subpass = pipeline->subpass;
1095
1096 pipeline->dynamic_state = default_dynamic_state;
1097
1098 if (pCreateInfo->pDynamicState) {
1099 /* Remove all of the states that are marked as dynamic */
1100 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1101 for (uint32_t s = 0; s < count; s++)
1102 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1103 }
1104
1105 struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
1106
1107 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1108 *
1109 * pViewportState is [...] NULL if the pipeline
1110 * has rasterization disabled.
1111 */
1112 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1113 assert(pCreateInfo->pViewportState);
1114
1115 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1116 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1117 typed_memcpy(dynamic->viewport.viewports,
1118 pCreateInfo->pViewportState->pViewports,
1119 pCreateInfo->pViewportState->viewportCount);
1120 }
1121
1122 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1123 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1124 typed_memcpy(dynamic->scissor.scissors,
1125 pCreateInfo->pViewportState->pScissors,
1126 pCreateInfo->pViewportState->scissorCount);
1127 }
1128 }
1129
1130 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1131 assert(pCreateInfo->pRasterizationState);
1132 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1133 }
1134
1135 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1136 assert(pCreateInfo->pRasterizationState);
1137 dynamic->depth_bias.bias =
1138 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1139 dynamic->depth_bias.clamp =
1140 pCreateInfo->pRasterizationState->depthBiasClamp;
1141 dynamic->depth_bias.slope =
1142 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1143 }
1144
1145 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1146 *
1147 * pColorBlendState is [...] NULL if the pipeline has rasterization
1148 * disabled or if the subpass of the render pass the pipeline is
1149 * created against does not use any color attachments.
1150 */
1151 bool uses_color_att = false;
1152 for (unsigned i = 0; i < subpass->color_count; ++i) {
1153 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1154 uses_color_att = true;
1155 break;
1156 }
1157 }
1158
1159 if (uses_color_att &&
1160 !pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1161 assert(pCreateInfo->pColorBlendState);
1162
1163 if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
1164 typed_memcpy(dynamic->blend_constants,
1165 pCreateInfo->pColorBlendState->blendConstants, 4);
1166 }
1167
1168 /* If there is no depthstencil attachment, then don't read
1169 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1170 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1171 * no need to override the depthstencil defaults in
1172 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1173 *
1174 * Section 9.2 of the Vulkan 1.0.15 spec says:
1175 *
1176 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1177 * disabled or if the subpass of the render pass the pipeline is created
1178 * against does not use a depth/stencil attachment.
1179 */
1180 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1181 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1182 assert(pCreateInfo->pDepthStencilState);
1183
1184 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1185 dynamic->depth_bounds.min =
1186 pCreateInfo->pDepthStencilState->minDepthBounds;
1187 dynamic->depth_bounds.max =
1188 pCreateInfo->pDepthStencilState->maxDepthBounds;
1189 }
1190
1191 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1192 dynamic->stencil_compare_mask.front =
1193 pCreateInfo->pDepthStencilState->front.compareMask;
1194 dynamic->stencil_compare_mask.back =
1195 pCreateInfo->pDepthStencilState->back.compareMask;
1196 }
1197
1198 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1199 dynamic->stencil_write_mask.front =
1200 pCreateInfo->pDepthStencilState->front.writeMask;
1201 dynamic->stencil_write_mask.back =
1202 pCreateInfo->pDepthStencilState->back.writeMask;
1203 }
1204
1205 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1206 dynamic->stencil_reference.front =
1207 pCreateInfo->pDepthStencilState->front.reference;
1208 dynamic->stencil_reference.back =
1209 pCreateInfo->pDepthStencilState->back.reference;
1210 }
1211 }
1212
1213 pipeline->dynamic_state_mask = states;
1214 }
1215
1216 static void
1217 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
1218 {
1219 #ifdef DEBUG
1220 struct anv_render_pass *renderpass = NULL;
1221 struct anv_subpass *subpass = NULL;
1222
1223 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1224 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1225 */
1226 assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
1227
1228 renderpass = anv_render_pass_from_handle(info->renderPass);
1229 assert(renderpass);
1230
1231 assert(info->subpass < renderpass->subpass_count);
1232 subpass = &renderpass->subpasses[info->subpass];
1233
1234 assert(info->stageCount >= 1);
1235 assert(info->pVertexInputState);
1236 assert(info->pInputAssemblyState);
1237 assert(info->pRasterizationState);
1238 if (!info->pRasterizationState->rasterizerDiscardEnable) {
1239 assert(info->pViewportState);
1240 assert(info->pMultisampleState);
1241
1242 if (subpass && subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
1243 assert(info->pDepthStencilState);
1244
1245 if (subpass && subpass->color_count > 0)
1246 assert(info->pColorBlendState);
1247 }
1248
1249 for (uint32_t i = 0; i < info->stageCount; ++i) {
1250 switch (info->pStages[i].stage) {
1251 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
1252 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
1253 assert(info->pTessellationState);
1254 break;
1255 default:
1256 break;
1257 }
1258 }
1259 #endif
1260 }
1261
1262 /**
1263 * Calculate the desired L3 partitioning based on the current state of the
1264 * pipeline. For now this simply returns the conservative defaults calculated
1265 * by get_default_l3_weights(), but we could probably do better by gathering
1266 * more statistics from the pipeline state (e.g. guess of expected URB usage
1267 * and bound surfaces), or by using feed-back from performance counters.
1268 */
1269 void
1270 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm)
1271 {
1272 const struct gen_device_info *devinfo = &pipeline->device->info;
1273
1274 const struct gen_l3_weights w =
1275 gen_get_default_l3_weights(devinfo, pipeline->needs_data_cache, needs_slm);
1276
1277 pipeline->urb.l3_config = gen_get_l3_config(devinfo, w);
1278 pipeline->urb.total_size =
1279 gen_get_l3_config_urb_size(devinfo, pipeline->urb.l3_config);
1280 }
1281
1282 VkResult
1283 anv_pipeline_init(struct anv_pipeline *pipeline,
1284 struct anv_device *device,
1285 struct anv_pipeline_cache *cache,
1286 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1287 const VkAllocationCallbacks *alloc)
1288 {
1289 VkResult result;
1290
1291 anv_pipeline_validate_create_info(pCreateInfo);
1292
1293 if (alloc == NULL)
1294 alloc = &device->alloc;
1295
1296 pipeline->device = device;
1297
1298 ANV_FROM_HANDLE(anv_render_pass, render_pass, pCreateInfo->renderPass);
1299 assert(pCreateInfo->subpass < render_pass->subpass_count);
1300 pipeline->subpass = &render_pass->subpasses[pCreateInfo->subpass];
1301
1302 result = anv_reloc_list_init(&pipeline->batch_relocs, alloc);
1303 if (result != VK_SUCCESS)
1304 return result;
1305
1306 pipeline->batch.alloc = alloc;
1307 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
1308 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
1309 pipeline->batch.relocs = &pipeline->batch_relocs;
1310 pipeline->batch.status = VK_SUCCESS;
1311
1312 copy_non_dynamic_state(pipeline, pCreateInfo);
1313 pipeline->depth_clamp_enable = pCreateInfo->pRasterizationState &&
1314 pCreateInfo->pRasterizationState->depthClampEnable;
1315
1316 pipeline->sample_shading_enable = pCreateInfo->pMultisampleState &&
1317 pCreateInfo->pMultisampleState->sampleShadingEnable;
1318
1319 pipeline->needs_data_cache = false;
1320
1321 /* When we free the pipeline, we detect stages based on the NULL status
1322 * of various prog_data pointers. Make them NULL by default.
1323 */
1324 memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
1325
1326 pipeline->active_stages = 0;
1327
1328 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = {};
1329 struct anv_shader_module *modules[MESA_SHADER_STAGES] = {};
1330 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1331 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1332 pStages[stage] = &pCreateInfo->pStages[i];
1333 modules[stage] = anv_shader_module_from_handle(pStages[stage]->module);
1334 }
1335
1336 if (modules[MESA_SHADER_VERTEX]) {
1337 result = anv_pipeline_compile_vs(pipeline, cache, pCreateInfo,
1338 modules[MESA_SHADER_VERTEX],
1339 pStages[MESA_SHADER_VERTEX]->pName,
1340 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo);
1341 if (result != VK_SUCCESS)
1342 goto compile_fail;
1343 }
1344
1345 if (modules[MESA_SHADER_TESS_EVAL]) {
1346 anv_pipeline_compile_tcs_tes(pipeline, cache, pCreateInfo,
1347 modules[MESA_SHADER_TESS_CTRL],
1348 pStages[MESA_SHADER_TESS_CTRL]->pName,
1349 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
1350 modules[MESA_SHADER_TESS_EVAL],
1351 pStages[MESA_SHADER_TESS_EVAL]->pName,
1352 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo);
1353 }
1354
1355 if (modules[MESA_SHADER_GEOMETRY]) {
1356 result = anv_pipeline_compile_gs(pipeline, cache, pCreateInfo,
1357 modules[MESA_SHADER_GEOMETRY],
1358 pStages[MESA_SHADER_GEOMETRY]->pName,
1359 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo);
1360 if (result != VK_SUCCESS)
1361 goto compile_fail;
1362 }
1363
1364 if (modules[MESA_SHADER_FRAGMENT]) {
1365 result = anv_pipeline_compile_fs(pipeline, cache, pCreateInfo,
1366 modules[MESA_SHADER_FRAGMENT],
1367 pStages[MESA_SHADER_FRAGMENT]->pName,
1368 pStages[MESA_SHADER_FRAGMENT]->pSpecializationInfo);
1369 if (result != VK_SUCCESS)
1370 goto compile_fail;
1371 }
1372
1373 assert(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT);
1374
1375 anv_pipeline_setup_l3_config(pipeline, false);
1376
1377 const VkPipelineVertexInputStateCreateInfo *vi_info =
1378 pCreateInfo->pVertexInputState;
1379
1380 const uint64_t inputs_read = get_vs_prog_data(pipeline)->inputs_read;
1381
1382 pipeline->vb_used = 0;
1383 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1384 const VkVertexInputAttributeDescription *desc =
1385 &vi_info->pVertexAttributeDescriptions[i];
1386
1387 if (inputs_read & (1ull << (VERT_ATTRIB_GENERIC0 + desc->location)))
1388 pipeline->vb_used |= 1 << desc->binding;
1389 }
1390
1391 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1392 const VkVertexInputBindingDescription *desc =
1393 &vi_info->pVertexBindingDescriptions[i];
1394
1395 pipeline->binding_stride[desc->binding] = desc->stride;
1396
1397 /* Step rate is programmed per vertex element (attribute), not
1398 * binding. Set up a map of which bindings step per instance, for
1399 * reference by vertex element setup. */
1400 switch (desc->inputRate) {
1401 default:
1402 case VK_VERTEX_INPUT_RATE_VERTEX:
1403 pipeline->instancing_enable[desc->binding] = false;
1404 break;
1405 case VK_VERTEX_INPUT_RATE_INSTANCE:
1406 pipeline->instancing_enable[desc->binding] = true;
1407 break;
1408 }
1409 }
1410
1411 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1412 pCreateInfo->pInputAssemblyState;
1413 const VkPipelineTessellationStateCreateInfo *tess_info =
1414 pCreateInfo->pTessellationState;
1415 pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1416
1417 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
1418 pipeline->topology = _3DPRIM_PATCHLIST(tess_info->patchControlPoints);
1419 else
1420 pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1421
1422 return VK_SUCCESS;
1423
1424 compile_fail:
1425 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
1426 if (pipeline->shaders[s])
1427 anv_shader_bin_unref(device, pipeline->shaders[s]);
1428 }
1429
1430 anv_reloc_list_finish(&pipeline->batch_relocs, alloc);
1431
1432 return result;
1433 }