2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "common/gen_l3_config.h"
32 #include "anv_private.h"
33 #include "compiler/brw_nir.h"
35 #include "spirv/nir_spirv.h"
38 /* Needed for SWIZZLE macros */
39 #include "program/prog_instruction.h"
43 VkResult
anv_CreateShaderModule(
45 const VkShaderModuleCreateInfo
* pCreateInfo
,
46 const VkAllocationCallbacks
* pAllocator
,
47 VkShaderModule
* pShaderModule
)
49 ANV_FROM_HANDLE(anv_device
, device
, _device
);
50 struct anv_shader_module
*module
;
52 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
53 assert(pCreateInfo
->flags
== 0);
55 module
= vk_alloc2(&device
->alloc
, pAllocator
,
56 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
57 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
59 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
61 module
->size
= pCreateInfo
->codeSize
;
62 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
64 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
66 *pShaderModule
= anv_shader_module_to_handle(module
);
71 void anv_DestroyShaderModule(
73 VkShaderModule _module
,
74 const VkAllocationCallbacks
* pAllocator
)
76 ANV_FROM_HANDLE(anv_device
, device
, _device
);
77 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
82 vk_free2(&device
->alloc
, pAllocator
, module
);
85 #define SPIR_V_MAGIC_NUMBER 0x07230203
87 static const uint64_t stage_to_debug
[] = {
88 [MESA_SHADER_VERTEX
] = DEBUG_VS
,
89 [MESA_SHADER_TESS_CTRL
] = DEBUG_TCS
,
90 [MESA_SHADER_TESS_EVAL
] = DEBUG_TES
,
91 [MESA_SHADER_GEOMETRY
] = DEBUG_GS
,
92 [MESA_SHADER_FRAGMENT
] = DEBUG_WM
,
93 [MESA_SHADER_COMPUTE
] = DEBUG_CS
,
96 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
97 * we can't do that yet because we don't have the ability to copy nir.
100 anv_shader_compile_to_nir(struct anv_pipeline
*pipeline
,
102 struct anv_shader_module
*module
,
103 const char *entrypoint_name
,
104 gl_shader_stage stage
,
105 const VkSpecializationInfo
*spec_info
)
107 const struct anv_device
*device
= pipeline
->device
;
109 const struct brw_compiler
*compiler
=
110 device
->instance
->physicalDevice
.compiler
;
111 const nir_shader_compiler_options
*nir_options
=
112 compiler
->glsl_compiler_options
[stage
].NirOptions
;
114 uint32_t *spirv
= (uint32_t *) module
->data
;
115 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
116 assert(module
->size
% 4 == 0);
118 uint32_t num_spec_entries
= 0;
119 struct nir_spirv_specialization
*spec_entries
= NULL
;
120 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
121 num_spec_entries
= spec_info
->mapEntryCount
;
122 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
123 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
124 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
125 const void *data
= spec_info
->pData
+ entry
.offset
;
126 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
128 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
129 if (spec_info
->dataSize
== 8)
130 spec_entries
[i
].data64
= *(const uint64_t *)data
;
132 spec_entries
[i
].data32
= *(const uint32_t *)data
;
136 struct spirv_to_nir_options spirv_options
= {
137 .lower_workgroup_access_to_offsets
= true,
139 .float64
= device
->instance
->physicalDevice
.info
.gen
>= 8,
140 .int64
= device
->instance
->physicalDevice
.info
.gen
>= 8,
141 .tessellation
= true,
142 .device_group
= true,
143 .draw_parameters
= true,
144 .image_write_without_format
= true,
146 .variable_pointers
= true,
147 .storage_16bit
= device
->instance
->physicalDevice
.info
.gen
>= 8,
148 .int16
= device
->instance
->physicalDevice
.info
.gen
>= 8,
149 .shader_viewport_index_layer
= true,
150 .subgroup_arithmetic
= true,
151 .subgroup_basic
= true,
152 .subgroup_ballot
= true,
153 .subgroup_quad
= true,
154 .subgroup_shuffle
= true,
155 .subgroup_vote
= true,
156 .stencil_export
= device
->instance
->physicalDevice
.info
.gen
>= 9,
157 .storage_8bit
= device
->instance
->physicalDevice
.info
.gen
>= 8,
158 .post_depth_coverage
= device
->instance
->physicalDevice
.info
.gen
>= 9,
162 nir_function
*entry_point
=
163 spirv_to_nir(spirv
, module
->size
/ 4,
164 spec_entries
, num_spec_entries
,
165 stage
, entrypoint_name
, &spirv_options
, nir_options
);
166 nir_shader
*nir
= entry_point
->shader
;
167 assert(nir
->info
.stage
== stage
);
168 nir_validate_shader(nir
);
169 ralloc_steal(mem_ctx
, nir
);
173 if (unlikely(INTEL_DEBUG
& stage_to_debug
[stage
])) {
174 fprintf(stderr
, "NIR (from SPIR-V) for %s shader:\n",
175 gl_shader_stage_name(stage
));
176 nir_print_shader(nir
, stderr
);
179 /* We have to lower away local constant initializers right before we
180 * inline functions. That way they get properly initialized at the top
181 * of the function and not at the top of its caller.
183 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_local
);
184 NIR_PASS_V(nir
, nir_lower_returns
);
185 NIR_PASS_V(nir
, nir_inline_functions
);
186 NIR_PASS_V(nir
, nir_copy_prop
);
188 /* Pick off the single entrypoint that we want */
189 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
190 if (func
!= entry_point
)
191 exec_node_remove(&func
->node
);
193 assert(exec_list_length(&nir
->functions
) == 1);
194 entry_point
->name
= ralloc_strdup(entry_point
, "main");
196 /* Now that we've deleted all but the main function, we can go ahead and
197 * lower the rest of the constant initializers. We do this here so that
198 * nir_remove_dead_variables and split_per_member_structs below see the
199 * corresponding stores.
201 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
203 /* Split member structs. We do this before lower_io_to_temporaries so that
204 * it doesn't lower system values to temporaries by accident.
206 NIR_PASS_V(nir
, nir_split_var_copies
);
207 NIR_PASS_V(nir
, nir_split_per_member_structs
);
209 NIR_PASS_V(nir
, nir_remove_dead_variables
,
210 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
212 if (stage
== MESA_SHADER_FRAGMENT
)
213 NIR_PASS_V(nir
, nir_lower_wpos_center
, pipeline
->sample_shading_enable
);
215 NIR_PASS_V(nir
, nir_propagate_invariant
);
216 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
217 entry_point
->impl
, true, false);
219 /* Vulkan uses the separate-shader linking model */
220 nir
->info
.separate_shader
= true;
222 nir
= brw_preprocess_nir(compiler
, nir
);
224 if (stage
== MESA_SHADER_FRAGMENT
)
225 NIR_PASS_V(nir
, anv_nir_lower_input_attachments
);
230 void anv_DestroyPipeline(
232 VkPipeline _pipeline
,
233 const VkAllocationCallbacks
* pAllocator
)
235 ANV_FROM_HANDLE(anv_device
, device
, _device
);
236 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
241 anv_reloc_list_finish(&pipeline
->batch_relocs
,
242 pAllocator
? pAllocator
: &device
->alloc
);
243 if (pipeline
->blend_state
.map
)
244 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
246 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
247 if (pipeline
->shaders
[s
])
248 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
251 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
254 static const uint32_t vk_to_gen_primitive_type
[] = {
255 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
256 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
257 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
258 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
259 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
260 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
261 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
262 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
263 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
264 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
268 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
269 struct brw_sampler_prog_key_data
*key
)
271 /* Almost all multisampled textures are compressed. The only time when we
272 * don't compress a multisampled texture is for 16x MSAA with a surface
273 * width greater than 8k which is a bit of an edge case. Since the sampler
274 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
275 * to tell the compiler to always assume compression.
277 key
->compressed_multisample_layout_mask
= ~0;
279 /* SkyLake added support for 16x MSAA. With this came a new message for
280 * reading from a 16x MSAA surface with compression. The new message was
281 * needed because now the MCS data is 64 bits instead of 32 or lower as is
282 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
283 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
284 * so we can just use it unconditionally. This may not be quite as
285 * efficient but it saves us from recompiling.
287 if (devinfo
->gen
>= 9)
290 /* XXX: Handle texture swizzle on HSW- */
291 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
292 /* Assume color sampler, no swizzling. (Works for BDW+) */
293 key
->swizzles
[i
] = SWIZZLE_XYZW
;
298 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
299 struct brw_vs_prog_key
*key
)
301 memset(key
, 0, sizeof(*key
));
303 populate_sampler_prog_key(devinfo
, &key
->tex
);
305 /* XXX: Handle vertex input work-arounds */
307 /* XXX: Handle sampler_prog_key */
311 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
312 struct brw_gs_prog_key
*key
)
314 memset(key
, 0, sizeof(*key
));
316 populate_sampler_prog_key(devinfo
, &key
->tex
);
320 populate_wm_prog_key(const struct anv_pipeline
*pipeline
,
321 const VkGraphicsPipelineCreateInfo
*info
,
322 struct brw_wm_prog_key
*key
)
324 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
326 memset(key
, 0, sizeof(*key
));
328 populate_sampler_prog_key(devinfo
, &key
->tex
);
330 /* TODO: we could set this to 0 based on the information in nir_shader, but
331 * this function is called before spirv_to_nir. */
332 const struct brw_vue_map
*vue_map
=
333 &anv_pipeline_get_last_vue_prog_data(pipeline
)->vue_map
;
334 key
->input_slots_valid
= vue_map
->slots_valid
;
336 /* Vulkan doesn't specify a default */
337 key
->high_quality_derivatives
= false;
339 /* XXX Vulkan doesn't appear to specify */
340 key
->clamp_fragment_color
= false;
342 key
->nr_color_regions
= pipeline
->subpass
->color_count
;
344 key
->replicate_alpha
= key
->nr_color_regions
> 1 &&
345 info
->pMultisampleState
&&
346 info
->pMultisampleState
->alphaToCoverageEnable
;
348 if (info
->pMultisampleState
) {
349 /* We should probably pull this out of the shader, but it's fairly
350 * harmless to compute it and then let dead-code take care of it.
352 if (info
->pMultisampleState
->rasterizationSamples
> 1) {
353 key
->persample_interp
=
354 (info
->pMultisampleState
->minSampleShading
*
355 info
->pMultisampleState
->rasterizationSamples
) > 1;
356 key
->multisample_fbo
= true;
359 key
->frag_coord_adds_sample_pos
=
360 info
->pMultisampleState
->sampleShadingEnable
;
365 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
366 struct brw_cs_prog_key
*key
)
368 memset(key
, 0, sizeof(*key
));
370 populate_sampler_prog_key(devinfo
, &key
->tex
);
374 anv_pipeline_hash_shader(struct anv_pipeline
*pipeline
,
375 struct anv_pipeline_layout
*layout
,
376 struct anv_shader_module
*module
,
377 const char *entrypoint
,
378 gl_shader_stage stage
,
379 const VkSpecializationInfo
*spec_info
,
380 const void *key
, size_t key_size
,
381 unsigned char *sha1_out
)
383 struct mesa_sha1 ctx
;
385 _mesa_sha1_init(&ctx
);
386 if (stage
!= MESA_SHADER_COMPUTE
) {
387 _mesa_sha1_update(&ctx
, &pipeline
->subpass
->view_mask
,
388 sizeof(pipeline
->subpass
->view_mask
));
391 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
392 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
393 _mesa_sha1_update(&ctx
, entrypoint
, strlen(entrypoint
));
394 _mesa_sha1_update(&ctx
, &stage
, sizeof(stage
));
396 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
397 spec_info
->mapEntryCount
* sizeof(*spec_info
->pMapEntries
));
398 _mesa_sha1_update(&ctx
, spec_info
->pData
, spec_info
->dataSize
);
400 _mesa_sha1_update(&ctx
, key
, key_size
);
401 _mesa_sha1_final(&ctx
, sha1_out
);
405 anv_pipeline_compile(struct anv_pipeline
*pipeline
,
407 struct anv_pipeline_layout
*layout
,
408 struct anv_shader_module
*module
,
409 const char *entrypoint
,
410 gl_shader_stage stage
,
411 const VkSpecializationInfo
*spec_info
,
412 struct brw_stage_prog_data
*prog_data
,
413 struct anv_pipeline_bind_map
*map
)
415 const struct brw_compiler
*compiler
=
416 pipeline
->device
->instance
->physicalDevice
.compiler
;
418 nir_shader
*nir
= anv_shader_compile_to_nir(pipeline
, mem_ctx
,
419 module
, entrypoint
, stage
,
424 NIR_PASS_V(nir
, anv_nir_lower_ycbcr_textures
, layout
);
426 NIR_PASS_V(nir
, anv_nir_lower_push_constants
);
428 if (stage
!= MESA_SHADER_COMPUTE
)
429 NIR_PASS_V(nir
, anv_nir_lower_multiview
, pipeline
->subpass
->view_mask
);
431 if (stage
== MESA_SHADER_COMPUTE
)
432 prog_data
->total_shared
= nir
->num_shared
;
434 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
436 if (nir
->num_uniforms
> 0) {
437 assert(prog_data
->nr_params
== 0);
439 /* If the shader uses any push constants at all, we'll just give
440 * them the maximum possible number
442 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
443 nir
->num_uniforms
= MAX_PUSH_CONSTANTS_SIZE
;
444 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
445 prog_data
->param
= ralloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
447 /* We now set the param values to be offsets into a
448 * anv_push_constant_data structure. Since the compiler doesn't
449 * actually dereference any of the gl_constant_value pointers in the
450 * params array, it doesn't really matter what we put here.
452 struct anv_push_constants
*null_data
= NULL
;
453 /* Fill out the push constants section of the param array */
454 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++) {
455 prog_data
->param
[i
] = ANV_PARAM_PUSH(
456 (uintptr_t)&null_data
->client_data
[i
* sizeof(float)]);
460 if (nir
->info
.num_ssbos
> 0 || nir
->info
.num_images
> 0)
461 pipeline
->needs_data_cache
= true;
463 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
465 anv_nir_apply_pipeline_layout(pipeline
, layout
, nir
, prog_data
, map
);
467 if (stage
!= MESA_SHADER_COMPUTE
)
468 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
470 assert(nir
->num_uniforms
== prog_data
->nr_params
* 4);
476 anv_fill_binding_table(struct brw_stage_prog_data
*prog_data
, unsigned bias
)
478 prog_data
->binding_table
.size_bytes
= 0;
479 prog_data
->binding_table
.texture_start
= bias
;
480 prog_data
->binding_table
.gather_texture_start
= bias
;
481 prog_data
->binding_table
.ubo_start
= bias
;
482 prog_data
->binding_table
.ssbo_start
= bias
;
483 prog_data
->binding_table
.image_start
= bias
;
487 anv_pipeline_add_compiled_stage(struct anv_pipeline
*pipeline
,
488 gl_shader_stage stage
,
489 struct anv_shader_bin
*shader
)
491 pipeline
->shaders
[stage
] = shader
;
495 anv_pipeline_compile_vs(struct anv_pipeline
*pipeline
,
496 struct anv_pipeline_cache
*cache
,
497 const VkGraphicsPipelineCreateInfo
*info
,
498 struct anv_shader_module
*module
,
499 const char *entrypoint
,
500 const VkSpecializationInfo
*spec_info
)
502 const struct brw_compiler
*compiler
=
503 pipeline
->device
->instance
->physicalDevice
.compiler
;
504 struct brw_vs_prog_key key
;
505 struct anv_shader_bin
*bin
= NULL
;
507 populate_vs_prog_key(&pipeline
->device
->info
, &key
);
509 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
511 unsigned char sha1
[20];
512 anv_pipeline_hash_shader(pipeline
, layout
, module
, entrypoint
,
513 MESA_SHADER_VERTEX
, spec_info
,
514 &key
, sizeof(key
), sha1
);
515 bin
= anv_device_search_for_kernel(pipeline
->device
, cache
, sha1
, 20);
518 struct brw_vs_prog_data prog_data
= {};
519 struct anv_pipeline_binding surface_to_descriptor
[256];
520 struct anv_pipeline_binding sampler_to_descriptor
[256];
522 struct anv_pipeline_bind_map map
= {
523 .surface_to_descriptor
= surface_to_descriptor
,
524 .sampler_to_descriptor
= sampler_to_descriptor
527 void *mem_ctx
= ralloc_context(NULL
);
529 nir_shader
*nir
= anv_pipeline_compile(pipeline
, mem_ctx
, layout
,
531 MESA_SHADER_VERTEX
, spec_info
,
532 &prog_data
.base
.base
, &map
);
534 ralloc_free(mem_ctx
);
535 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
538 anv_fill_binding_table(&prog_data
.base
.base
, 0);
540 brw_compute_vue_map(&pipeline
->device
->info
,
541 &prog_data
.base
.vue_map
,
542 nir
->info
.outputs_written
,
543 nir
->info
.separate_shader
);
545 const unsigned *shader_code
=
546 brw_compile_vs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
548 if (shader_code
== NULL
) {
549 ralloc_free(mem_ctx
);
550 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
553 unsigned code_size
= prog_data
.base
.base
.program_size
;
554 bin
= anv_device_upload_kernel(pipeline
->device
, cache
, sha1
, 20,
555 shader_code
, code_size
,
557 nir
->constant_data_size
,
558 &prog_data
.base
.base
, sizeof(prog_data
),
561 ralloc_free(mem_ctx
);
562 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
565 ralloc_free(mem_ctx
);
568 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_VERTEX
, bin
);
574 merge_tess_info(struct shader_info
*tes_info
,
575 const struct shader_info
*tcs_info
)
577 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
579 * "PointMode. Controls generation of points rather than triangles
580 * or lines. This functionality defaults to disabled, and is
581 * enabled if either shader stage includes the execution mode.
583 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
584 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
585 * and OutputVertices, it says:
587 * "One mode must be set in at least one of the tessellation
590 * So, the fields can be set in either the TCS or TES, but they must
591 * agree if set in both. Our backend looks at TES, so bitwise-or in
592 * the values from the TCS.
594 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
595 tes_info
->tess
.tcs_vertices_out
== 0 ||
596 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
597 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
599 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
600 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
601 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
602 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
604 assert(tcs_info
->tess
.primitive_mode
== 0 ||
605 tes_info
->tess
.primitive_mode
== 0 ||
606 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
607 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
608 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
609 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
613 anv_pipeline_compile_tcs_tes(struct anv_pipeline
*pipeline
,
614 struct anv_pipeline_cache
*cache
,
615 const VkGraphicsPipelineCreateInfo
*info
,
616 struct anv_shader_module
*tcs_module
,
617 const char *tcs_entrypoint
,
618 const VkSpecializationInfo
*tcs_spec_info
,
619 struct anv_shader_module
*tes_module
,
620 const char *tes_entrypoint
,
621 const VkSpecializationInfo
*tes_spec_info
)
623 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
624 const struct brw_compiler
*compiler
=
625 pipeline
->device
->instance
->physicalDevice
.compiler
;
626 struct brw_tcs_prog_key tcs_key
= {};
627 struct brw_tes_prog_key tes_key
= {};
628 struct anv_shader_bin
*tcs_bin
= NULL
;
629 struct anv_shader_bin
*tes_bin
= NULL
;
631 populate_sampler_prog_key(&pipeline
->device
->info
, &tcs_key
.tex
);
632 populate_sampler_prog_key(&pipeline
->device
->info
, &tes_key
.tex
);
633 tcs_key
.input_vertices
= info
->pTessellationState
->patchControlPoints
;
635 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
637 unsigned char tcs_sha1
[40];
638 unsigned char tes_sha1
[40];
639 anv_pipeline_hash_shader(pipeline
, layout
, tcs_module
, tcs_entrypoint
,
640 MESA_SHADER_TESS_CTRL
, tcs_spec_info
,
641 &tcs_key
, sizeof(tcs_key
), tcs_sha1
);
642 anv_pipeline_hash_shader(pipeline
, layout
, tes_module
, tes_entrypoint
,
643 MESA_SHADER_TESS_EVAL
, tes_spec_info
,
644 &tes_key
, sizeof(tes_key
), tes_sha1
);
645 memcpy(&tcs_sha1
[20], tes_sha1
, 20);
646 memcpy(&tes_sha1
[20], tcs_sha1
, 20);
648 tcs_bin
= anv_device_search_for_kernel(pipeline
->device
, cache
,
649 tcs_sha1
, sizeof(tcs_sha1
));
650 tes_bin
= anv_device_search_for_kernel(pipeline
->device
, cache
,
651 tes_sha1
, sizeof(tes_sha1
));
653 if (tcs_bin
== NULL
|| tes_bin
== NULL
) {
654 struct brw_tcs_prog_data tcs_prog_data
= {};
655 struct brw_tes_prog_data tes_prog_data
= {};
656 struct anv_pipeline_binding tcs_surface_to_descriptor
[256];
657 struct anv_pipeline_binding tcs_sampler_to_descriptor
[256];
658 struct anv_pipeline_binding tes_surface_to_descriptor
[256];
659 struct anv_pipeline_binding tes_sampler_to_descriptor
[256];
661 struct anv_pipeline_bind_map tcs_map
= {
662 .surface_to_descriptor
= tcs_surface_to_descriptor
,
663 .sampler_to_descriptor
= tcs_sampler_to_descriptor
665 struct anv_pipeline_bind_map tes_map
= {
666 .surface_to_descriptor
= tes_surface_to_descriptor
,
667 .sampler_to_descriptor
= tes_sampler_to_descriptor
670 void *mem_ctx
= ralloc_context(NULL
);
672 nir_shader
*tcs_nir
=
673 anv_pipeline_compile(pipeline
, mem_ctx
, layout
,
674 tcs_module
, tcs_entrypoint
,
675 MESA_SHADER_TESS_CTRL
, tcs_spec_info
,
676 &tcs_prog_data
.base
.base
, &tcs_map
);
677 nir_shader
*tes_nir
=
678 anv_pipeline_compile(pipeline
, mem_ctx
, layout
,
679 tes_module
, tes_entrypoint
,
680 MESA_SHADER_TESS_EVAL
, tes_spec_info
,
681 &tes_prog_data
.base
.base
, &tes_map
);
682 if (tcs_nir
== NULL
|| tes_nir
== NULL
) {
683 ralloc_free(mem_ctx
);
684 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
687 nir_lower_tes_patch_vertices(tes_nir
,
688 tcs_nir
->info
.tess
.tcs_vertices_out
);
690 /* Copy TCS info into the TES info */
691 merge_tess_info(&tes_nir
->info
, &tcs_nir
->info
);
693 anv_fill_binding_table(&tcs_prog_data
.base
.base
, 0);
694 anv_fill_binding_table(&tes_prog_data
.base
.base
, 0);
696 /* Whacking the key after cache lookup is a bit sketchy, but all of
697 * this comes from the SPIR-V, which is part of the hash used for the
698 * pipeline cache. So it should be safe.
700 tcs_key
.tes_primitive_mode
= tes_nir
->info
.tess
.primitive_mode
;
701 tcs_key
.outputs_written
= tcs_nir
->info
.outputs_written
;
702 tcs_key
.patch_outputs_written
= tcs_nir
->info
.patch_outputs_written
;
703 tcs_key
.quads_workaround
=
705 tes_nir
->info
.tess
.primitive_mode
== 7 /* GL_QUADS */ &&
706 tes_nir
->info
.tess
.spacing
== TESS_SPACING_EQUAL
;
708 tes_key
.inputs_read
= tcs_key
.outputs_written
;
709 tes_key
.patch_inputs_read
= tcs_key
.patch_outputs_written
;
711 const int shader_time_index
= -1;
712 const unsigned *shader_code
;
715 brw_compile_tcs(compiler
, NULL
, mem_ctx
, &tcs_key
, &tcs_prog_data
,
716 tcs_nir
, shader_time_index
, NULL
);
717 if (shader_code
== NULL
) {
718 ralloc_free(mem_ctx
);
719 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
722 unsigned code_size
= tcs_prog_data
.base
.base
.program_size
;
723 tcs_bin
= anv_device_upload_kernel(pipeline
->device
, cache
,
724 tcs_sha1
, sizeof(tcs_sha1
),
725 shader_code
, code_size
,
726 tcs_nir
->constant_data
,
727 tcs_nir
->constant_data_size
,
728 &tcs_prog_data
.base
.base
,
729 sizeof(tcs_prog_data
),
732 ralloc_free(mem_ctx
);
733 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
737 brw_compile_tes(compiler
, NULL
, mem_ctx
, &tes_key
,
738 &tcs_prog_data
.base
.vue_map
, &tes_prog_data
, tes_nir
,
739 NULL
, shader_time_index
, NULL
);
740 if (shader_code
== NULL
) {
741 ralloc_free(mem_ctx
);
742 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
745 code_size
= tes_prog_data
.base
.base
.program_size
;
746 tes_bin
= anv_device_upload_kernel(pipeline
->device
, cache
,
747 tes_sha1
, sizeof(tes_sha1
),
748 shader_code
, code_size
,
749 tes_nir
->constant_data
,
750 tes_nir
->constant_data_size
,
751 &tes_prog_data
.base
.base
,
752 sizeof(tes_prog_data
),
755 ralloc_free(mem_ctx
);
756 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
759 ralloc_free(mem_ctx
);
762 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_TESS_CTRL
, tcs_bin
);
763 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_TESS_EVAL
, tes_bin
);
769 anv_pipeline_compile_gs(struct anv_pipeline
*pipeline
,
770 struct anv_pipeline_cache
*cache
,
771 const VkGraphicsPipelineCreateInfo
*info
,
772 struct anv_shader_module
*module
,
773 const char *entrypoint
,
774 const VkSpecializationInfo
*spec_info
)
776 const struct brw_compiler
*compiler
=
777 pipeline
->device
->instance
->physicalDevice
.compiler
;
778 struct brw_gs_prog_key key
;
779 struct anv_shader_bin
*bin
= NULL
;
781 populate_gs_prog_key(&pipeline
->device
->info
, &key
);
783 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
785 unsigned char sha1
[20];
786 anv_pipeline_hash_shader(pipeline
, layout
, module
, entrypoint
,
787 MESA_SHADER_GEOMETRY
, spec_info
,
788 &key
, sizeof(key
), sha1
);
789 bin
= anv_device_search_for_kernel(pipeline
->device
, cache
, sha1
, 20);
792 struct brw_gs_prog_data prog_data
= {};
793 struct anv_pipeline_binding surface_to_descriptor
[256];
794 struct anv_pipeline_binding sampler_to_descriptor
[256];
796 struct anv_pipeline_bind_map map
= {
797 .surface_to_descriptor
= surface_to_descriptor
,
798 .sampler_to_descriptor
= sampler_to_descriptor
801 void *mem_ctx
= ralloc_context(NULL
);
803 nir_shader
*nir
= anv_pipeline_compile(pipeline
, mem_ctx
, layout
,
805 MESA_SHADER_GEOMETRY
, spec_info
,
806 &prog_data
.base
.base
, &map
);
808 ralloc_free(mem_ctx
);
809 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
812 anv_fill_binding_table(&prog_data
.base
.base
, 0);
814 brw_compute_vue_map(&pipeline
->device
->info
,
815 &prog_data
.base
.vue_map
,
816 nir
->info
.outputs_written
,
817 nir
->info
.separate_shader
);
819 const unsigned *shader_code
=
820 brw_compile_gs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
822 if (shader_code
== NULL
) {
823 ralloc_free(mem_ctx
);
824 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
828 const unsigned code_size
= prog_data
.base
.base
.program_size
;
829 bin
= anv_device_upload_kernel(pipeline
->device
, cache
, sha1
, 20,
830 shader_code
, code_size
,
832 nir
->constant_data_size
,
833 &prog_data
.base
.base
, sizeof(prog_data
),
836 ralloc_free(mem_ctx
);
837 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
840 ralloc_free(mem_ctx
);
843 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_GEOMETRY
, bin
);
849 anv_pipeline_compile_fs(struct anv_pipeline
*pipeline
,
850 struct anv_pipeline_cache
*cache
,
851 const VkGraphicsPipelineCreateInfo
*info
,
852 struct anv_shader_module
*module
,
853 const char *entrypoint
,
854 const VkSpecializationInfo
*spec_info
)
856 const struct brw_compiler
*compiler
=
857 pipeline
->device
->instance
->physicalDevice
.compiler
;
858 struct brw_wm_prog_key key
;
859 struct anv_shader_bin
*bin
= NULL
;
861 populate_wm_prog_key(pipeline
, info
, &key
);
863 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
865 unsigned char sha1
[20];
866 anv_pipeline_hash_shader(pipeline
, layout
, module
, entrypoint
,
867 MESA_SHADER_FRAGMENT
, spec_info
,
868 &key
, sizeof(key
), sha1
);
869 bin
= anv_device_search_for_kernel(pipeline
->device
, cache
, sha1
, 20);
872 struct brw_wm_prog_data prog_data
= {};
873 struct anv_pipeline_binding surface_to_descriptor
[256];
874 struct anv_pipeline_binding sampler_to_descriptor
[256];
876 struct anv_pipeline_bind_map map
= {
877 .surface_to_descriptor
= surface_to_descriptor
+ 8,
878 .sampler_to_descriptor
= sampler_to_descriptor
881 void *mem_ctx
= ralloc_context(NULL
);
883 nir_shader
*nir
= anv_pipeline_compile(pipeline
, mem_ctx
, layout
,
885 MESA_SHADER_FRAGMENT
, spec_info
,
886 &prog_data
.base
, &map
);
888 ralloc_free(mem_ctx
);
889 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
892 unsigned num_rts
= 0;
893 const int max_rt
= FRAG_RESULT_DATA7
- FRAG_RESULT_DATA0
+ 1;
894 struct anv_pipeline_binding rt_bindings
[max_rt
];
895 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
896 int rt_to_bindings
[max_rt
];
897 memset(rt_to_bindings
, -1, sizeof(rt_to_bindings
));
898 bool rt_used
[max_rt
];
899 memset(rt_used
, 0, sizeof(rt_used
));
901 /* Flag used render targets */
902 nir_foreach_variable_safe(var
, &nir
->outputs
) {
903 if (var
->data
.location
< FRAG_RESULT_DATA0
)
906 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
908 if (rt
>= key
.nr_color_regions
)
911 const unsigned array_len
=
912 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
913 assert(rt
+ array_len
<= max_rt
);
915 for (unsigned i
= 0; i
< array_len
; i
++)
916 rt_used
[rt
+ i
] = true;
919 /* Set new, compacted, location */
920 for (unsigned i
= 0; i
< max_rt
; i
++) {
924 rt_to_bindings
[i
] = num_rts
;
925 rt_bindings
[rt_to_bindings
[i
]] = (struct anv_pipeline_binding
) {
926 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
933 nir_foreach_variable_safe(var
, &nir
->outputs
) {
934 if (var
->data
.location
< FRAG_RESULT_DATA0
)
937 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
938 if (rt
>= key
.nr_color_regions
) {
939 /* Out-of-bounds, throw it away */
940 var
->data
.mode
= nir_var_local
;
941 exec_node_remove(&var
->node
);
942 exec_list_push_tail(&impl
->locals
, &var
->node
);
946 /* Give it the new location */
947 assert(rt_to_bindings
[rt
] != -1);
948 var
->data
.location
= rt_to_bindings
[rt
] + FRAG_RESULT_DATA0
;
952 /* If we have no render targets, we need a null render target */
953 rt_bindings
[0] = (struct anv_pipeline_binding
) {
954 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
961 assert(num_rts
<= max_rt
);
962 map
.surface_to_descriptor
-= num_rts
;
963 map
.surface_count
+= num_rts
;
964 assert(map
.surface_count
<= 256);
965 memcpy(map
.surface_to_descriptor
, rt_bindings
,
966 num_rts
* sizeof(*rt_bindings
));
968 anv_fill_binding_table(&prog_data
.base
, num_rts
);
970 const unsigned *shader_code
=
971 brw_compile_fs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
972 NULL
, -1, -1, -1, true, false, NULL
, NULL
);
973 if (shader_code
== NULL
) {
974 ralloc_free(mem_ctx
);
975 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
978 unsigned code_size
= prog_data
.base
.program_size
;
979 bin
= anv_device_upload_kernel(pipeline
->device
, cache
, sha1
, 20,
980 shader_code
, code_size
,
982 nir
->constant_data_size
,
983 &prog_data
.base
, sizeof(prog_data
),
986 ralloc_free(mem_ctx
);
987 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
990 ralloc_free(mem_ctx
);
993 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_FRAGMENT
, bin
);
999 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1000 struct anv_pipeline_cache
*cache
,
1001 const VkComputePipelineCreateInfo
*info
,
1002 struct anv_shader_module
*module
,
1003 const char *entrypoint
,
1004 const VkSpecializationInfo
*spec_info
)
1006 const struct brw_compiler
*compiler
=
1007 pipeline
->device
->instance
->physicalDevice
.compiler
;
1008 struct brw_cs_prog_key key
;
1009 struct anv_shader_bin
*bin
= NULL
;
1011 populate_cs_prog_key(&pipeline
->device
->info
, &key
);
1013 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1015 unsigned char sha1
[20];
1016 anv_pipeline_hash_shader(pipeline
, layout
, module
, entrypoint
,
1017 MESA_SHADER_COMPUTE
, spec_info
,
1018 &key
, sizeof(key
), sha1
);
1019 bin
= anv_device_search_for_kernel(pipeline
->device
, cache
, sha1
, 20);
1022 struct brw_cs_prog_data prog_data
= {};
1023 struct anv_pipeline_binding surface_to_descriptor
[256];
1024 struct anv_pipeline_binding sampler_to_descriptor
[256];
1026 struct anv_pipeline_bind_map map
= {
1027 .surface_to_descriptor
= surface_to_descriptor
,
1028 .sampler_to_descriptor
= sampler_to_descriptor
1031 void *mem_ctx
= ralloc_context(NULL
);
1033 nir_shader
*nir
= anv_pipeline_compile(pipeline
, mem_ctx
, layout
,
1035 MESA_SHADER_COMPUTE
, spec_info
,
1036 &prog_data
.base
, &map
);
1038 ralloc_free(mem_ctx
);
1039 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1042 NIR_PASS_V(nir
, anv_nir_add_base_work_group_id
, &prog_data
);
1044 anv_fill_binding_table(&prog_data
.base
, 1);
1046 const unsigned *shader_code
=
1047 brw_compile_cs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
1049 if (shader_code
== NULL
) {
1050 ralloc_free(mem_ctx
);
1051 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1054 const unsigned code_size
= prog_data
.base
.program_size
;
1055 bin
= anv_device_upload_kernel(pipeline
->device
, cache
, sha1
, 20,
1056 shader_code
, code_size
,
1058 nir
->constant_data_size
,
1059 &prog_data
.base
, sizeof(prog_data
),
1062 ralloc_free(mem_ctx
);
1063 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1066 ralloc_free(mem_ctx
);
1069 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_COMPUTE
, bin
);
1075 * Copy pipeline state not marked as dynamic.
1076 * Dynamic state is pipeline state which hasn't been provided at pipeline
1077 * creation time, but is dynamically provided afterwards using various
1078 * vkCmdSet* functions.
1080 * The set of state considered "non_dynamic" is determined by the pieces of
1081 * state that have their corresponding VkDynamicState enums omitted from
1082 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1084 * @param[out] pipeline Destination non_dynamic state.
1085 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1088 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
1089 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1091 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
1092 struct anv_subpass
*subpass
= pipeline
->subpass
;
1094 pipeline
->dynamic_state
= default_dynamic_state
;
1096 if (pCreateInfo
->pDynamicState
) {
1097 /* Remove all of the states that are marked as dynamic */
1098 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1099 for (uint32_t s
= 0; s
< count
; s
++)
1100 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1103 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1105 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1107 * pViewportState is [...] NULL if the pipeline
1108 * has rasterization disabled.
1110 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1111 assert(pCreateInfo
->pViewportState
);
1113 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1114 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
1115 typed_memcpy(dynamic
->viewport
.viewports
,
1116 pCreateInfo
->pViewportState
->pViewports
,
1117 pCreateInfo
->pViewportState
->viewportCount
);
1120 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1121 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
1122 typed_memcpy(dynamic
->scissor
.scissors
,
1123 pCreateInfo
->pViewportState
->pScissors
,
1124 pCreateInfo
->pViewportState
->scissorCount
);
1128 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1129 assert(pCreateInfo
->pRasterizationState
);
1130 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1133 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1134 assert(pCreateInfo
->pRasterizationState
);
1135 dynamic
->depth_bias
.bias
=
1136 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1137 dynamic
->depth_bias
.clamp
=
1138 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1139 dynamic
->depth_bias
.slope
=
1140 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1143 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1145 * pColorBlendState is [...] NULL if the pipeline has rasterization
1146 * disabled or if the subpass of the render pass the pipeline is
1147 * created against does not use any color attachments.
1149 bool uses_color_att
= false;
1150 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1151 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1152 uses_color_att
= true;
1157 if (uses_color_att
&&
1158 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1159 assert(pCreateInfo
->pColorBlendState
);
1161 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
1162 typed_memcpy(dynamic
->blend_constants
,
1163 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1166 /* If there is no depthstencil attachment, then don't read
1167 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1168 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1169 * no need to override the depthstencil defaults in
1170 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1172 * Section 9.2 of the Vulkan 1.0.15 spec says:
1174 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1175 * disabled or if the subpass of the render pass the pipeline is created
1176 * against does not use a depth/stencil attachment.
1178 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1179 subpass
->depth_stencil_attachment
) {
1180 assert(pCreateInfo
->pDepthStencilState
);
1182 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1183 dynamic
->depth_bounds
.min
=
1184 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1185 dynamic
->depth_bounds
.max
=
1186 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1189 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1190 dynamic
->stencil_compare_mask
.front
=
1191 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1192 dynamic
->stencil_compare_mask
.back
=
1193 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1196 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1197 dynamic
->stencil_write_mask
.front
=
1198 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1199 dynamic
->stencil_write_mask
.back
=
1200 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1203 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1204 dynamic
->stencil_reference
.front
=
1205 pCreateInfo
->pDepthStencilState
->front
.reference
;
1206 dynamic
->stencil_reference
.back
=
1207 pCreateInfo
->pDepthStencilState
->back
.reference
;
1211 pipeline
->dynamic_state_mask
= states
;
1215 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1218 struct anv_render_pass
*renderpass
= NULL
;
1219 struct anv_subpass
*subpass
= NULL
;
1221 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1222 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1224 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1226 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1229 assert(info
->subpass
< renderpass
->subpass_count
);
1230 subpass
= &renderpass
->subpasses
[info
->subpass
];
1232 assert(info
->stageCount
>= 1);
1233 assert(info
->pVertexInputState
);
1234 assert(info
->pInputAssemblyState
);
1235 assert(info
->pRasterizationState
);
1236 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1237 assert(info
->pViewportState
);
1238 assert(info
->pMultisampleState
);
1240 if (subpass
&& subpass
->depth_stencil_attachment
)
1241 assert(info
->pDepthStencilState
);
1243 if (subpass
&& subpass
->color_count
> 0) {
1244 bool all_color_unused
= true;
1245 for (int i
= 0; i
< subpass
->color_count
; i
++) {
1246 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
1247 all_color_unused
= false;
1249 /* pColorBlendState is ignored if the pipeline has rasterization
1250 * disabled or if the subpass of the render pass the pipeline is
1251 * created against does not use any color attachments.
1253 assert(info
->pColorBlendState
|| all_color_unused
);
1257 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1258 switch (info
->pStages
[i
].stage
) {
1259 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1260 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1261 assert(info
->pTessellationState
);
1271 * Calculate the desired L3 partitioning based on the current state of the
1272 * pipeline. For now this simply returns the conservative defaults calculated
1273 * by get_default_l3_weights(), but we could probably do better by gathering
1274 * more statistics from the pipeline state (e.g. guess of expected URB usage
1275 * and bound surfaces), or by using feed-back from performance counters.
1278 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1280 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1282 const struct gen_l3_weights w
=
1283 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
1285 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
1286 pipeline
->urb
.total_size
=
1287 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
1291 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1292 struct anv_device
*device
,
1293 struct anv_pipeline_cache
*cache
,
1294 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1295 const VkAllocationCallbacks
*alloc
)
1299 anv_pipeline_validate_create_info(pCreateInfo
);
1302 alloc
= &device
->alloc
;
1304 pipeline
->device
= device
;
1306 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, pCreateInfo
->renderPass
);
1307 assert(pCreateInfo
->subpass
< render_pass
->subpass_count
);
1308 pipeline
->subpass
= &render_pass
->subpasses
[pCreateInfo
->subpass
];
1310 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1311 if (result
!= VK_SUCCESS
)
1314 pipeline
->batch
.alloc
= alloc
;
1315 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1316 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1317 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1318 pipeline
->batch
.status
= VK_SUCCESS
;
1320 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1321 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1322 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1324 pipeline
->sample_shading_enable
= pCreateInfo
->pMultisampleState
&&
1325 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
1327 pipeline
->needs_data_cache
= false;
1329 /* When we free the pipeline, we detect stages based on the NULL status
1330 * of various prog_data pointers. Make them NULL by default.
1332 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1334 pipeline
->active_stages
= 0;
1336 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = {};
1337 struct anv_shader_module
*modules
[MESA_SHADER_STAGES
] = {};
1338 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
1339 VkShaderStageFlagBits vk_stage
= pCreateInfo
->pStages
[i
].stage
;
1340 gl_shader_stage stage
= vk_to_mesa_shader_stage(vk_stage
);
1341 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
1342 modules
[stage
] = anv_shader_module_from_handle(pStages
[stage
]->module
);
1343 pipeline
->active_stages
|= vk_stage
;
1346 if (pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
)
1347 pipeline
->active_stages
|= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
1349 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1351 if (modules
[MESA_SHADER_VERTEX
]) {
1352 result
= anv_pipeline_compile_vs(pipeline
, cache
, pCreateInfo
,
1353 modules
[MESA_SHADER_VERTEX
],
1354 pStages
[MESA_SHADER_VERTEX
]->pName
,
1355 pStages
[MESA_SHADER_VERTEX
]->pSpecializationInfo
);
1356 if (result
!= VK_SUCCESS
)
1360 if (modules
[MESA_SHADER_TESS_EVAL
]) {
1361 result
= anv_pipeline_compile_tcs_tes(pipeline
, cache
, pCreateInfo
,
1362 modules
[MESA_SHADER_TESS_CTRL
],
1363 pStages
[MESA_SHADER_TESS_CTRL
]->pName
,
1364 pStages
[MESA_SHADER_TESS_CTRL
]->pSpecializationInfo
,
1365 modules
[MESA_SHADER_TESS_EVAL
],
1366 pStages
[MESA_SHADER_TESS_EVAL
]->pName
,
1367 pStages
[MESA_SHADER_TESS_EVAL
]->pSpecializationInfo
);
1368 if (result
!= VK_SUCCESS
)
1372 if (modules
[MESA_SHADER_GEOMETRY
]) {
1373 result
= anv_pipeline_compile_gs(pipeline
, cache
, pCreateInfo
,
1374 modules
[MESA_SHADER_GEOMETRY
],
1375 pStages
[MESA_SHADER_GEOMETRY
]->pName
,
1376 pStages
[MESA_SHADER_GEOMETRY
]->pSpecializationInfo
);
1377 if (result
!= VK_SUCCESS
)
1381 if (modules
[MESA_SHADER_FRAGMENT
]) {
1382 result
= anv_pipeline_compile_fs(pipeline
, cache
, pCreateInfo
,
1383 modules
[MESA_SHADER_FRAGMENT
],
1384 pStages
[MESA_SHADER_FRAGMENT
]->pName
,
1385 pStages
[MESA_SHADER_FRAGMENT
]->pSpecializationInfo
);
1386 if (result
!= VK_SUCCESS
)
1390 assert(pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1392 anv_pipeline_setup_l3_config(pipeline
, false);
1394 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1395 pCreateInfo
->pVertexInputState
;
1397 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1399 pipeline
->vb_used
= 0;
1400 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1401 const VkVertexInputAttributeDescription
*desc
=
1402 &vi_info
->pVertexAttributeDescriptions
[i
];
1404 if (inputs_read
& (1ull << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1405 pipeline
->vb_used
|= 1 << desc
->binding
;
1408 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1409 const VkVertexInputBindingDescription
*desc
=
1410 &vi_info
->pVertexBindingDescriptions
[i
];
1412 pipeline
->vb
[desc
->binding
].stride
= desc
->stride
;
1414 /* Step rate is programmed per vertex element (attribute), not
1415 * binding. Set up a map of which bindings step per instance, for
1416 * reference by vertex element setup. */
1417 switch (desc
->inputRate
) {
1419 case VK_VERTEX_INPUT_RATE_VERTEX
:
1420 pipeline
->vb
[desc
->binding
].instanced
= false;
1422 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1423 pipeline
->vb
[desc
->binding
].instanced
= true;
1427 pipeline
->vb
[desc
->binding
].instance_divisor
= 1;
1430 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*vi_div_state
=
1431 vk_find_struct_const(vi_info
->pNext
,
1432 PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
1434 for (uint32_t i
= 0; i
< vi_div_state
->vertexBindingDivisorCount
; i
++) {
1435 const VkVertexInputBindingDivisorDescriptionEXT
*desc
=
1436 &vi_div_state
->pVertexBindingDivisors
[i
];
1438 pipeline
->vb
[desc
->binding
].instance_divisor
= desc
->divisor
;
1442 /* Our implementation of VK_KHR_multiview uses instancing to draw the
1443 * different views. If the client asks for instancing, we need to multiply
1444 * the instance divisor by the number of views ensure that we repeat the
1445 * client's per-instance data once for each view.
1447 if (pipeline
->subpass
->view_mask
) {
1448 const uint32_t view_count
= anv_subpass_view_count(pipeline
->subpass
);
1449 for (uint32_t vb
= 0; vb
< MAX_VBS
; vb
++) {
1450 if (pipeline
->vb
[vb
].instanced
)
1451 pipeline
->vb
[vb
].instance_divisor
*= view_count
;
1455 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1456 pCreateInfo
->pInputAssemblyState
;
1457 const VkPipelineTessellationStateCreateInfo
*tess_info
=
1458 pCreateInfo
->pTessellationState
;
1459 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1461 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1462 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
1464 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];
1469 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1470 if (pipeline
->shaders
[s
])
1471 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
1474 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);