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anv: Remove left-over bits of sparse-descriptor code
[mesa.git] / src / intel / vulkan / anv_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "util/mesa-sha1.h"
31 #include "anv_private.h"
32 #include "brw_nir.h"
33 #include "anv_nir.h"
34 #include "nir/spirv/nir_spirv.h"
35
36 /* Needed for SWIZZLE macros */
37 #include "program/prog_instruction.h"
38
39 // Shader functions
40
41 VkResult anv_CreateShaderModule(
42 VkDevice _device,
43 const VkShaderModuleCreateInfo* pCreateInfo,
44 const VkAllocationCallbacks* pAllocator,
45 VkShaderModule* pShaderModule)
46 {
47 ANV_FROM_HANDLE(anv_device, device, _device);
48 struct anv_shader_module *module;
49
50 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
51 assert(pCreateInfo->flags == 0);
52
53 module = anv_alloc2(&device->alloc, pAllocator,
54 sizeof(*module) + pCreateInfo->codeSize, 8,
55 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
56 if (module == NULL)
57 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
58
59 module->nir = NULL;
60 module->size = pCreateInfo->codeSize;
61 memcpy(module->data, pCreateInfo->pCode, module->size);
62
63 _mesa_sha1_compute(module->data, module->size, module->sha1);
64
65 *pShaderModule = anv_shader_module_to_handle(module);
66
67 return VK_SUCCESS;
68 }
69
70 void anv_DestroyShaderModule(
71 VkDevice _device,
72 VkShaderModule _module,
73 const VkAllocationCallbacks* pAllocator)
74 {
75 ANV_FROM_HANDLE(anv_device, device, _device);
76 ANV_FROM_HANDLE(anv_shader_module, module, _module);
77
78 anv_free2(&device->alloc, pAllocator, module);
79 }
80
81 #define SPIR_V_MAGIC_NUMBER 0x07230203
82
83 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
84 * we can't do that yet because we don't have the ability to copy nir.
85 */
86 static nir_shader *
87 anv_shader_compile_to_nir(struct anv_device *device,
88 struct anv_shader_module *module,
89 const char *entrypoint_name,
90 gl_shader_stage stage,
91 const VkSpecializationInfo *spec_info)
92 {
93 if (strcmp(entrypoint_name, "main") != 0) {
94 anv_finishme("Multiple shaders per module not really supported");
95 }
96
97 const struct brw_compiler *compiler =
98 device->instance->physicalDevice.compiler;
99 const nir_shader_compiler_options *nir_options =
100 compiler->glsl_compiler_options[stage].NirOptions;
101
102 nir_shader *nir;
103 nir_function *entry_point;
104 if (module->nir) {
105 /* Some things such as our meta clear/blit code will give us a NIR
106 * shader directly. In that case, we just ignore the SPIR-V entirely
107 * and just use the NIR shader */
108 nir = module->nir;
109 nir->options = nir_options;
110 nir_validate_shader(nir);
111
112 assert(exec_list_length(&nir->functions) == 1);
113 struct exec_node *node = exec_list_get_head(&nir->functions);
114 entry_point = exec_node_data(nir_function, node, node);
115 } else {
116 uint32_t *spirv = (uint32_t *) module->data;
117 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
118 assert(module->size % 4 == 0);
119
120 uint32_t num_spec_entries = 0;
121 struct nir_spirv_specialization *spec_entries = NULL;
122 if (spec_info && spec_info->mapEntryCount > 0) {
123 num_spec_entries = spec_info->mapEntryCount;
124 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
125 for (uint32_t i = 0; i < num_spec_entries; i++) {
126 const uint32_t *data =
127 spec_info->pData + spec_info->pMapEntries[i].offset;
128 assert((const void *)(data + 1) <=
129 spec_info->pData + spec_info->dataSize);
130
131 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
132 spec_entries[i].data = *data;
133 }
134 }
135
136 entry_point = spirv_to_nir(spirv, module->size / 4,
137 spec_entries, num_spec_entries,
138 stage, entrypoint_name, nir_options);
139 nir = entry_point->shader;
140 assert(nir->stage == stage);
141 nir_validate_shader(nir);
142
143 free(spec_entries);
144
145 nir_lower_returns(nir);
146 nir_validate_shader(nir);
147
148 nir_inline_functions(nir);
149 nir_validate_shader(nir);
150
151 /* Pick off the single entrypoint that we want */
152 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
153 if (func != entry_point)
154 exec_node_remove(&func->node);
155 }
156 assert(exec_list_length(&nir->functions) == 1);
157 entry_point->name = ralloc_strdup(entry_point, "main");
158
159 nir_remove_dead_variables(nir, nir_var_shader_in);
160 nir_remove_dead_variables(nir, nir_var_shader_out);
161 nir_remove_dead_variables(nir, nir_var_system_value);
162 nir_validate_shader(nir);
163
164 nir_lower_outputs_to_temporaries(entry_point->shader, entry_point);
165
166 nir_lower_system_values(nir);
167 nir_validate_shader(nir);
168 }
169
170 /* Vulkan uses the separate-shader linking model */
171 nir->info.separate_shader = true;
172
173 nir = brw_preprocess_nir(nir, compiler->scalar_stage[stage]);
174
175 nir_shader_gather_info(nir, entry_point->impl);
176
177 uint32_t indirect_mask = 0;
178 if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput)
179 indirect_mask |= (1 << nir_var_shader_in);
180 if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
181 indirect_mask |= 1 << nir_var_local;
182
183 nir_lower_indirect_derefs(nir, indirect_mask);
184
185 return nir;
186 }
187
188 void anv_DestroyPipeline(
189 VkDevice _device,
190 VkPipeline _pipeline,
191 const VkAllocationCallbacks* pAllocator)
192 {
193 ANV_FROM_HANDLE(anv_device, device, _device);
194 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
195
196 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
197 free(pipeline->bindings[s].surface_to_descriptor);
198 free(pipeline->bindings[s].sampler_to_descriptor);
199 }
200
201 anv_reloc_list_finish(&pipeline->batch_relocs,
202 pAllocator ? pAllocator : &device->alloc);
203 if (pipeline->blend_state.map)
204 anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
205 anv_free2(&device->alloc, pAllocator, pipeline);
206 }
207
208 static const uint32_t vk_to_gen_primitive_type[] = {
209 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
210 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
211 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
212 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
213 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
214 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
215 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
216 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
217 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
218 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
219 /* [VK_PRIMITIVE_TOPOLOGY_PATCH_LIST] = _3DPRIM_PATCHLIST_1 */
220 };
221
222 static void
223 populate_sampler_prog_key(const struct brw_device_info *devinfo,
224 struct brw_sampler_prog_key_data *key)
225 {
226 /* XXX: Handle texture swizzle on HSW- */
227 for (int i = 0; i < MAX_SAMPLERS; i++) {
228 /* Assume color sampler, no swizzling. (Works for BDW+) */
229 key->swizzles[i] = SWIZZLE_XYZW;
230 }
231 }
232
233 static void
234 populate_vs_prog_key(const struct brw_device_info *devinfo,
235 struct brw_vs_prog_key *key)
236 {
237 memset(key, 0, sizeof(*key));
238
239 populate_sampler_prog_key(devinfo, &key->tex);
240
241 /* XXX: Handle vertex input work-arounds */
242
243 /* XXX: Handle sampler_prog_key */
244 }
245
246 static void
247 populate_gs_prog_key(const struct brw_device_info *devinfo,
248 struct brw_gs_prog_key *key)
249 {
250 memset(key, 0, sizeof(*key));
251
252 populate_sampler_prog_key(devinfo, &key->tex);
253 }
254
255 static void
256 populate_wm_prog_key(const struct brw_device_info *devinfo,
257 const VkGraphicsPipelineCreateInfo *info,
258 const struct anv_graphics_pipeline_create_info *extra,
259 struct brw_wm_prog_key *key)
260 {
261 ANV_FROM_HANDLE(anv_render_pass, render_pass, info->renderPass);
262
263 memset(key, 0, sizeof(*key));
264
265 populate_sampler_prog_key(devinfo, &key->tex);
266
267 /* TODO: Fill out key->input_slots_valid */
268
269 /* Vulkan doesn't specify a default */
270 key->high_quality_derivatives = false;
271
272 /* XXX Vulkan doesn't appear to specify */
273 key->clamp_fragment_color = false;
274
275 /* Vulkan always specifies upper-left coordinates */
276 key->drawable_height = 0;
277 key->render_to_fbo = false;
278
279 if (extra && extra->color_attachment_count >= 0) {
280 key->nr_color_regions = extra->color_attachment_count;
281 } else {
282 key->nr_color_regions =
283 render_pass->subpasses[info->subpass].color_count;
284 }
285
286 key->replicate_alpha = key->nr_color_regions > 1 &&
287 info->pMultisampleState &&
288 info->pMultisampleState->alphaToCoverageEnable;
289
290 if (info->pMultisampleState && info->pMultisampleState->rasterizationSamples > 1) {
291 /* We should probably pull this out of the shader, but it's fairly
292 * harmless to compute it and then let dead-code take care of it.
293 */
294 key->persample_shading = info->pMultisampleState->sampleShadingEnable;
295 if (key->persample_shading)
296 key->persample_2x = info->pMultisampleState->rasterizationSamples == 2;
297
298 key->compute_pos_offset = info->pMultisampleState->sampleShadingEnable;
299 key->compute_sample_id = info->pMultisampleState->sampleShadingEnable;
300 }
301 }
302
303 static void
304 populate_cs_prog_key(const struct brw_device_info *devinfo,
305 struct brw_cs_prog_key *key)
306 {
307 memset(key, 0, sizeof(*key));
308
309 populate_sampler_prog_key(devinfo, &key->tex);
310 }
311
312 static nir_shader *
313 anv_pipeline_compile(struct anv_pipeline *pipeline,
314 struct anv_shader_module *module,
315 const char *entrypoint,
316 gl_shader_stage stage,
317 const VkSpecializationInfo *spec_info,
318 struct brw_stage_prog_data *prog_data)
319 {
320 const struct brw_compiler *compiler =
321 pipeline->device->instance->physicalDevice.compiler;
322
323 nir_shader *nir = anv_shader_compile_to_nir(pipeline->device,
324 module, entrypoint, stage,
325 spec_info);
326 if (nir == NULL)
327 return NULL;
328
329 anv_nir_lower_push_constants(nir, compiler->scalar_stage[stage]);
330
331 /* Figure out the number of parameters */
332 prog_data->nr_params = 0;
333
334 if (nir->num_uniforms > 0) {
335 /* If the shader uses any push constants at all, we'll just give
336 * them the maximum possible number
337 */
338 prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
339 }
340
341 if (pipeline->layout && pipeline->layout->stage[stage].has_dynamic_offsets)
342 prog_data->nr_params += MAX_DYNAMIC_BUFFERS * 2;
343
344 if (nir->info.num_images > 0)
345 prog_data->nr_params += nir->info.num_images * BRW_IMAGE_PARAM_SIZE;
346
347 if (prog_data->nr_params > 0) {
348 /* XXX: I think we're leaking this */
349 prog_data->param = (const union gl_constant_value **)
350 malloc(prog_data->nr_params * sizeof(union gl_constant_value *));
351
352 /* We now set the param values to be offsets into a
353 * anv_push_constant_data structure. Since the compiler doesn't
354 * actually dereference any of the gl_constant_value pointers in the
355 * params array, it doesn't really matter what we put here.
356 */
357 struct anv_push_constants *null_data = NULL;
358 if (nir->num_uniforms > 0) {
359 /* Fill out the push constants section of the param array */
360 for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++)
361 prog_data->param[i] = (const union gl_constant_value *)
362 &null_data->client_data[i * sizeof(float)];
363 }
364 }
365
366 /* Set up dynamic offsets */
367 anv_nir_apply_dynamic_offsets(pipeline, nir, prog_data);
368
369 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
370 if (pipeline->layout)
371 anv_nir_apply_pipeline_layout(pipeline, nir, prog_data);
372
373 /* All binding table offsets provided by apply_pipeline_layout() are
374 * relative to the start of the bindint table (plus MAX_RTS for VS).
375 */
376 unsigned bias;
377 switch (stage) {
378 case MESA_SHADER_FRAGMENT:
379 bias = MAX_RTS;
380 break;
381 case MESA_SHADER_COMPUTE:
382 bias = 1;
383 break;
384 default:
385 bias = 0;
386 break;
387 }
388 prog_data->binding_table.size_bytes = 0;
389 prog_data->binding_table.texture_start = bias;
390 prog_data->binding_table.ubo_start = bias;
391 prog_data->binding_table.ssbo_start = bias;
392 prog_data->binding_table.image_start = bias;
393
394 /* Finish the optimization and compilation process */
395 if (nir->stage == MESA_SHADER_COMPUTE)
396 brw_nir_lower_shared(nir);
397
398 /* nir_lower_io will only handle the push constants; we need to set this
399 * to the full number of possible uniforms.
400 */
401 nir->num_uniforms = prog_data->nr_params * 4;
402
403 return nir;
404 }
405
406 static void
407 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
408 gl_shader_stage stage,
409 struct brw_stage_prog_data *prog_data)
410 {
411 struct brw_device_info *devinfo = &pipeline->device->info;
412 uint32_t max_threads[] = {
413 [MESA_SHADER_VERTEX] = devinfo->max_vs_threads,
414 [MESA_SHADER_TESS_CTRL] = devinfo->max_hs_threads,
415 [MESA_SHADER_TESS_EVAL] = devinfo->max_ds_threads,
416 [MESA_SHADER_GEOMETRY] = devinfo->max_gs_threads,
417 [MESA_SHADER_FRAGMENT] = devinfo->max_wm_threads,
418 [MESA_SHADER_COMPUTE] = devinfo->max_cs_threads,
419 };
420
421 pipeline->prog_data[stage] = prog_data;
422 pipeline->active_stages |= mesa_to_vk_shader_stage(stage);
423 pipeline->scratch_start[stage] = pipeline->total_scratch;
424 pipeline->total_scratch =
425 align_u32(pipeline->total_scratch, 1024) +
426 prog_data->total_scratch * max_threads[stage];
427 }
428
429 static VkResult
430 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
431 struct anv_pipeline_cache *cache,
432 const VkGraphicsPipelineCreateInfo *info,
433 struct anv_shader_module *module,
434 const char *entrypoint,
435 const VkSpecializationInfo *spec_info)
436 {
437 const struct brw_compiler *compiler =
438 pipeline->device->instance->physicalDevice.compiler;
439 struct brw_vs_prog_data *prog_data = &pipeline->vs_prog_data;
440 struct brw_vs_prog_key key;
441 uint32_t kernel;
442 unsigned char sha1[20], *hash;
443
444 populate_vs_prog_key(&pipeline->device->info, &key);
445
446 if (module->size > 0) {
447 hash = sha1;
448 anv_hash_shader(hash, &key, sizeof(key), module, entrypoint, spec_info);
449 kernel = anv_pipeline_cache_search(cache, hash, prog_data);
450 } else {
451 hash = NULL;
452 }
453
454 if (module->size == 0 || kernel == NO_KERNEL) {
455 memset(prog_data, 0, sizeof(*prog_data));
456
457 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
458 MESA_SHADER_VERTEX, spec_info,
459 &prog_data->base.base);
460 if (nir == NULL)
461 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
462
463 void *mem_ctx = ralloc_context(NULL);
464
465 if (module->nir == NULL)
466 ralloc_steal(mem_ctx, nir);
467
468 prog_data->inputs_read = nir->info.inputs_read;
469 if (nir->info.outputs_written & (1ull << VARYING_SLOT_PSIZ))
470 pipeline->writes_point_size = true;
471
472 brw_compute_vue_map(&pipeline->device->info,
473 &prog_data->base.vue_map,
474 nir->info.outputs_written,
475 nir->info.separate_shader);
476
477 unsigned code_size;
478 const unsigned *shader_code =
479 brw_compile_vs(compiler, NULL, mem_ctx, &key, prog_data, nir,
480 NULL, false, -1, &code_size, NULL);
481 if (shader_code == NULL) {
482 ralloc_free(mem_ctx);
483 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
484 }
485
486 kernel = anv_pipeline_cache_upload_kernel(cache, hash,
487 shader_code, code_size,
488 prog_data, sizeof(*prog_data));
489 ralloc_free(mem_ctx);
490 }
491
492 if (prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8) {
493 pipeline->vs_simd8 = kernel;
494 pipeline->vs_vec4 = NO_KERNEL;
495 } else {
496 pipeline->vs_simd8 = NO_KERNEL;
497 pipeline->vs_vec4 = kernel;
498 }
499
500 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX,
501 &prog_data->base.base);
502
503 return VK_SUCCESS;
504 }
505
506 static VkResult
507 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
508 struct anv_pipeline_cache *cache,
509 const VkGraphicsPipelineCreateInfo *info,
510 struct anv_shader_module *module,
511 const char *entrypoint,
512 const VkSpecializationInfo *spec_info)
513 {
514 const struct brw_compiler *compiler =
515 pipeline->device->instance->physicalDevice.compiler;
516 struct brw_gs_prog_data *prog_data = &pipeline->gs_prog_data;
517 struct brw_gs_prog_key key;
518 uint32_t kernel;
519 unsigned char sha1[20], *hash;
520
521 populate_gs_prog_key(&pipeline->device->info, &key);
522
523 if (module->size > 0) {
524 hash = sha1;
525 anv_hash_shader(hash, &key, sizeof(key), module, entrypoint, spec_info);
526 kernel = anv_pipeline_cache_search(cache, hash, prog_data);
527 } else {
528 hash = NULL;
529 }
530
531 if (module->size == 0 || kernel == NO_KERNEL) {
532 memset(prog_data, 0, sizeof(*prog_data));
533
534 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
535 MESA_SHADER_GEOMETRY, spec_info,
536 &prog_data->base.base);
537 if (nir == NULL)
538 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
539
540 void *mem_ctx = ralloc_context(NULL);
541
542 if (module->nir == NULL)
543 ralloc_steal(mem_ctx, nir);
544
545 if (nir->info.outputs_written & (1ull << VARYING_SLOT_PSIZ))
546 pipeline->writes_point_size = true;
547
548 brw_compute_vue_map(&pipeline->device->info,
549 &prog_data->base.vue_map,
550 nir->info.outputs_written,
551 nir->info.separate_shader);
552
553 unsigned code_size;
554 const unsigned *shader_code =
555 brw_compile_gs(compiler, NULL, mem_ctx, &key, prog_data, nir,
556 NULL, -1, &code_size, NULL);
557 if (shader_code == NULL) {
558 ralloc_free(mem_ctx);
559 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
560 }
561
562 /* TODO: SIMD8 GS */
563 kernel = anv_pipeline_cache_upload_kernel(cache, hash,
564 shader_code, code_size,
565 prog_data, sizeof(*prog_data));
566
567 ralloc_free(mem_ctx);
568 }
569
570 pipeline->gs_kernel = kernel;
571
572 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY,
573 &prog_data->base.base);
574
575 return VK_SUCCESS;
576 }
577
578 static VkResult
579 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
580 struct anv_pipeline_cache *cache,
581 const VkGraphicsPipelineCreateInfo *info,
582 const struct anv_graphics_pipeline_create_info *extra,
583 struct anv_shader_module *module,
584 const char *entrypoint,
585 const VkSpecializationInfo *spec_info)
586 {
587 const struct brw_compiler *compiler =
588 pipeline->device->instance->physicalDevice.compiler;
589 struct brw_wm_prog_data *prog_data = &pipeline->wm_prog_data;
590 struct brw_wm_prog_key key;
591 uint32_t kernel;
592 unsigned char sha1[20], *hash;
593
594 populate_wm_prog_key(&pipeline->device->info, info, extra, &key);
595
596 if (pipeline->use_repclear)
597 key.nr_color_regions = 1;
598
599 if (module->size > 0) {
600 hash = sha1;
601 anv_hash_shader(hash, &key, sizeof(key), module, entrypoint, spec_info);
602 kernel = anv_pipeline_cache_search(cache, hash, prog_data);
603 } else {
604 hash = NULL;
605 }
606
607 if (module->size == 0 || kernel == NO_KERNEL) {
608 memset(prog_data, 0, sizeof(*prog_data));
609
610 prog_data->binding_table.render_target_start = 0;
611
612 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
613 MESA_SHADER_FRAGMENT, spec_info,
614 &prog_data->base);
615 if (nir == NULL)
616 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
617
618 nir_function_impl *impl = nir_shader_get_entrypoint(nir)->impl;
619 nir_foreach_variable_safe(var, &nir->outputs) {
620 if (var->data.location < FRAG_RESULT_DATA0)
621 continue;
622
623 unsigned rt = var->data.location - FRAG_RESULT_DATA0;
624 if (rt >= key.nr_color_regions) {
625 var->data.mode = nir_var_local;
626 exec_node_remove(&var->node);
627 exec_list_push_tail(&impl->locals, &var->node);
628 }
629 }
630
631 void *mem_ctx = ralloc_context(NULL);
632
633 if (module->nir == NULL)
634 ralloc_steal(mem_ctx, nir);
635
636 unsigned code_size;
637 const unsigned *shader_code =
638 brw_compile_fs(compiler, NULL, mem_ctx, &key, prog_data, nir,
639 NULL, -1, -1, pipeline->use_repclear, &code_size, NULL);
640 if (shader_code == NULL) {
641 ralloc_free(mem_ctx);
642 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
643 }
644
645 kernel = anv_pipeline_cache_upload_kernel(cache, hash,
646 shader_code, code_size,
647 prog_data, sizeof(*prog_data));
648
649 ralloc_free(mem_ctx);
650 }
651
652 if (prog_data->no_8)
653 pipeline->ps_simd8 = NO_KERNEL;
654 else
655 pipeline->ps_simd8 = kernel;
656
657 if (prog_data->no_8 || prog_data->prog_offset_16) {
658 pipeline->ps_simd16 = kernel + prog_data->prog_offset_16;
659 } else {
660 pipeline->ps_simd16 = NO_KERNEL;
661 }
662
663 pipeline->ps_ksp2 = 0;
664 pipeline->ps_grf_start2 = 0;
665 if (pipeline->ps_simd8 != NO_KERNEL) {
666 pipeline->ps_ksp0 = pipeline->ps_simd8;
667 pipeline->ps_grf_start0 = prog_data->base.dispatch_grf_start_reg;
668 if (pipeline->ps_simd16 != NO_KERNEL) {
669 pipeline->ps_ksp2 = pipeline->ps_simd16;
670 pipeline->ps_grf_start2 = prog_data->dispatch_grf_start_reg_16;
671 }
672 } else if (pipeline->ps_simd16 != NO_KERNEL) {
673 pipeline->ps_ksp0 = pipeline->ps_simd16;
674 pipeline->ps_grf_start0 = prog_data->dispatch_grf_start_reg_16;
675 }
676
677 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT,
678 &prog_data->base);
679
680 return VK_SUCCESS;
681 }
682
683 VkResult
684 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
685 struct anv_pipeline_cache *cache,
686 const VkComputePipelineCreateInfo *info,
687 struct anv_shader_module *module,
688 const char *entrypoint,
689 const VkSpecializationInfo *spec_info)
690 {
691 const struct brw_compiler *compiler =
692 pipeline->device->instance->physicalDevice.compiler;
693 struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
694 struct brw_cs_prog_key key;
695 uint32_t kernel;
696 unsigned char sha1[20], *hash;
697
698 populate_cs_prog_key(&pipeline->device->info, &key);
699
700 if (module->size > 0) {
701 hash = sha1;
702 anv_hash_shader(hash, &key, sizeof(key), module, entrypoint, spec_info);
703 kernel = anv_pipeline_cache_search(cache, hash, prog_data);
704 } else {
705 hash = NULL;
706 }
707
708 if (module->size == 0 || kernel == NO_KERNEL) {
709 memset(prog_data, 0, sizeof(*prog_data));
710
711 prog_data->binding_table.work_groups_start = 0;
712
713 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
714 MESA_SHADER_COMPUTE, spec_info,
715 &prog_data->base);
716 if (nir == NULL)
717 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
718
719 prog_data->base.total_shared = nir->num_shared;
720
721 void *mem_ctx = ralloc_context(NULL);
722
723 if (module->nir == NULL)
724 ralloc_steal(mem_ctx, nir);
725
726 unsigned code_size;
727 const unsigned *shader_code =
728 brw_compile_cs(compiler, NULL, mem_ctx, &key, prog_data, nir,
729 -1, &code_size, NULL);
730 if (shader_code == NULL) {
731 ralloc_free(mem_ctx);
732 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
733 }
734
735 kernel = anv_pipeline_cache_upload_kernel(cache, hash,
736 shader_code, code_size,
737 prog_data, sizeof(*prog_data));
738 ralloc_free(mem_ctx);
739 }
740
741 pipeline->cs_simd = kernel;
742
743 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE,
744 &prog_data->base);
745
746 return VK_SUCCESS;
747 }
748
749 static void
750 gen7_compute_urb_partition(struct anv_pipeline *pipeline)
751 {
752 const struct brw_device_info *devinfo = &pipeline->device->info;
753 bool vs_present = pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT;
754 unsigned vs_size = vs_present ? pipeline->vs_prog_data.base.urb_entry_size : 1;
755 unsigned vs_entry_size_bytes = vs_size * 64;
756 bool gs_present = pipeline->active_stages & VK_SHADER_STAGE_GEOMETRY_BIT;
757 unsigned gs_size = gs_present ? pipeline->gs_prog_data.base.urb_entry_size : 1;
758 unsigned gs_entry_size_bytes = gs_size * 64;
759
760 /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
761 *
762 * VS Number of URB Entries must be divisible by 8 if the VS URB Entry
763 * Allocation Size is less than 9 512-bit URB entries.
764 *
765 * Similar text exists for GS.
766 */
767 unsigned vs_granularity = (vs_size < 9) ? 8 : 1;
768 unsigned gs_granularity = (gs_size < 9) ? 8 : 1;
769
770 /* URB allocations must be done in 8k chunks. */
771 unsigned chunk_size_bytes = 8192;
772
773 /* Determine the size of the URB in chunks. */
774 unsigned urb_chunks = devinfo->urb.size * 1024 / chunk_size_bytes;
775
776 /* Reserve space for push constants */
777 unsigned push_constant_kb;
778 if (pipeline->device->info.gen >= 8)
779 push_constant_kb = 32;
780 else if (pipeline->device->info.is_haswell)
781 push_constant_kb = pipeline->device->info.gt == 3 ? 32 : 16;
782 else
783 push_constant_kb = 16;
784
785 unsigned push_constant_bytes = push_constant_kb * 1024;
786 unsigned push_constant_chunks =
787 push_constant_bytes / chunk_size_bytes;
788
789 /* Initially, assign each stage the minimum amount of URB space it needs,
790 * and make a note of how much additional space it "wants" (the amount of
791 * additional space it could actually make use of).
792 */
793
794 /* VS has a lower limit on the number of URB entries */
795 unsigned vs_chunks =
796 ALIGN(devinfo->urb.min_vs_entries * vs_entry_size_bytes,
797 chunk_size_bytes) / chunk_size_bytes;
798 unsigned vs_wants =
799 ALIGN(devinfo->urb.max_vs_entries * vs_entry_size_bytes,
800 chunk_size_bytes) / chunk_size_bytes - vs_chunks;
801
802 unsigned gs_chunks = 0;
803 unsigned gs_wants = 0;
804 if (gs_present) {
805 /* There are two constraints on the minimum amount of URB space we can
806 * allocate:
807 *
808 * (1) We need room for at least 2 URB entries, since we always operate
809 * the GS in DUAL_OBJECT mode.
810 *
811 * (2) We can't allocate less than nr_gs_entries_granularity.
812 */
813 gs_chunks = ALIGN(MAX2(gs_granularity, 2) * gs_entry_size_bytes,
814 chunk_size_bytes) / chunk_size_bytes;
815 gs_wants =
816 ALIGN(devinfo->urb.max_gs_entries * gs_entry_size_bytes,
817 chunk_size_bytes) / chunk_size_bytes - gs_chunks;
818 }
819
820 /* There should always be enough URB space to satisfy the minimum
821 * requirements of each stage.
822 */
823 unsigned total_needs = push_constant_chunks + vs_chunks + gs_chunks;
824 assert(total_needs <= urb_chunks);
825
826 /* Mete out remaining space (if any) in proportion to "wants". */
827 unsigned total_wants = vs_wants + gs_wants;
828 unsigned remaining_space = urb_chunks - total_needs;
829 if (remaining_space > total_wants)
830 remaining_space = total_wants;
831 if (remaining_space > 0) {
832 unsigned vs_additional = (unsigned)
833 round(vs_wants * (((double) remaining_space) / total_wants));
834 vs_chunks += vs_additional;
835 remaining_space -= vs_additional;
836 gs_chunks += remaining_space;
837 }
838
839 /* Sanity check that we haven't over-allocated. */
840 assert(push_constant_chunks + vs_chunks + gs_chunks <= urb_chunks);
841
842 /* Finally, compute the number of entries that can fit in the space
843 * allocated to each stage.
844 */
845 unsigned nr_vs_entries = vs_chunks * chunk_size_bytes / vs_entry_size_bytes;
846 unsigned nr_gs_entries = gs_chunks * chunk_size_bytes / gs_entry_size_bytes;
847
848 /* Since we rounded up when computing *_wants, this may be slightly more
849 * than the maximum allowed amount, so correct for that.
850 */
851 nr_vs_entries = MIN2(nr_vs_entries, devinfo->urb.max_vs_entries);
852 nr_gs_entries = MIN2(nr_gs_entries, devinfo->urb.max_gs_entries);
853
854 /* Ensure that we program a multiple of the granularity. */
855 nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, vs_granularity);
856 nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, gs_granularity);
857
858 /* Finally, sanity check to make sure we have at least the minimum number
859 * of entries needed for each stage.
860 */
861 assert(nr_vs_entries >= devinfo->urb.min_vs_entries);
862 if (gs_present)
863 assert(nr_gs_entries >= 2);
864
865 /* Lay out the URB in the following order:
866 * - push constants
867 * - VS
868 * - GS
869 */
870 pipeline->urb.start[MESA_SHADER_VERTEX] = push_constant_chunks;
871 pipeline->urb.size[MESA_SHADER_VERTEX] = vs_size;
872 pipeline->urb.entries[MESA_SHADER_VERTEX] = nr_vs_entries;
873
874 pipeline->urb.start[MESA_SHADER_GEOMETRY] = push_constant_chunks + vs_chunks;
875 pipeline->urb.size[MESA_SHADER_GEOMETRY] = gs_size;
876 pipeline->urb.entries[MESA_SHADER_GEOMETRY] = nr_gs_entries;
877
878 pipeline->urb.start[MESA_SHADER_TESS_CTRL] = push_constant_chunks;
879 pipeline->urb.size[MESA_SHADER_TESS_CTRL] = 1;
880 pipeline->urb.entries[MESA_SHADER_TESS_CTRL] = 0;
881
882 pipeline->urb.start[MESA_SHADER_TESS_EVAL] = push_constant_chunks;
883 pipeline->urb.size[MESA_SHADER_TESS_EVAL] = 1;
884 pipeline->urb.entries[MESA_SHADER_TESS_EVAL] = 0;
885
886 const unsigned stages =
887 _mesa_bitcount(pipeline->active_stages & VK_SHADER_STAGE_ALL_GRAPHICS);
888 unsigned size_per_stage = stages ? (push_constant_kb / stages) : 0;
889 unsigned used_kb = 0;
890
891 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
892 * units of 2KB. Incidentally, these are the same platforms that have
893 * 32KB worth of push constant space.
894 */
895 if (push_constant_kb == 32)
896 size_per_stage &= ~1u;
897
898 for (int i = MESA_SHADER_VERTEX; i < MESA_SHADER_FRAGMENT; i++) {
899 pipeline->urb.push_size[i] =
900 (pipeline->active_stages & (1 << i)) ? size_per_stage : 0;
901 used_kb += pipeline->urb.push_size[i];
902 assert(used_kb <= push_constant_kb);
903 }
904
905 pipeline->urb.push_size[MESA_SHADER_FRAGMENT] =
906 push_constant_kb - used_kb;
907 }
908
909 static void
910 anv_pipeline_init_dynamic_state(struct anv_pipeline *pipeline,
911 const VkGraphicsPipelineCreateInfo *pCreateInfo)
912 {
913 anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
914 ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
915 struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
916
917 pipeline->dynamic_state = default_dynamic_state;
918
919 if (pCreateInfo->pDynamicState) {
920 /* Remove all of the states that are marked as dynamic */
921 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
922 for (uint32_t s = 0; s < count; s++)
923 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
924 }
925
926 struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
927
928 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
929 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
930 typed_memcpy(dynamic->viewport.viewports,
931 pCreateInfo->pViewportState->pViewports,
932 pCreateInfo->pViewportState->viewportCount);
933 }
934
935 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
936 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
937 typed_memcpy(dynamic->scissor.scissors,
938 pCreateInfo->pViewportState->pScissors,
939 pCreateInfo->pViewportState->scissorCount);
940 }
941
942 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
943 assert(pCreateInfo->pRasterizationState);
944 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
945 }
946
947 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
948 assert(pCreateInfo->pRasterizationState);
949 dynamic->depth_bias.bias =
950 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
951 dynamic->depth_bias.clamp =
952 pCreateInfo->pRasterizationState->depthBiasClamp;
953 dynamic->depth_bias.slope =
954 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
955 }
956
957 if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
958 assert(pCreateInfo->pColorBlendState);
959 typed_memcpy(dynamic->blend_constants,
960 pCreateInfo->pColorBlendState->blendConstants, 4);
961 }
962
963 /* If there is no depthstencil attachment, then don't read
964 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
965 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
966 * no need to override the depthstencil defaults in
967 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
968 *
969 * From the Vulkan spec (20 Oct 2015, git-aa308cb):
970 *
971 * pDepthStencilState [...] may only be NULL if renderPass and subpass
972 * specify a subpass that has no depth/stencil attachment.
973 */
974 if (subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
975 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
976 assert(pCreateInfo->pDepthStencilState);
977 dynamic->depth_bounds.min =
978 pCreateInfo->pDepthStencilState->minDepthBounds;
979 dynamic->depth_bounds.max =
980 pCreateInfo->pDepthStencilState->maxDepthBounds;
981 }
982
983 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
984 assert(pCreateInfo->pDepthStencilState);
985 dynamic->stencil_compare_mask.front =
986 pCreateInfo->pDepthStencilState->front.compareMask;
987 dynamic->stencil_compare_mask.back =
988 pCreateInfo->pDepthStencilState->back.compareMask;
989 }
990
991 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
992 assert(pCreateInfo->pDepthStencilState);
993 dynamic->stencil_write_mask.front =
994 pCreateInfo->pDepthStencilState->front.writeMask;
995 dynamic->stencil_write_mask.back =
996 pCreateInfo->pDepthStencilState->back.writeMask;
997 }
998
999 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1000 assert(pCreateInfo->pDepthStencilState);
1001 dynamic->stencil_reference.front =
1002 pCreateInfo->pDepthStencilState->front.reference;
1003 dynamic->stencil_reference.back =
1004 pCreateInfo->pDepthStencilState->back.reference;
1005 }
1006 }
1007
1008 pipeline->dynamic_state_mask = states;
1009 }
1010
1011 static void
1012 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
1013 {
1014 struct anv_render_pass *renderpass = NULL;
1015 struct anv_subpass *subpass = NULL;
1016
1017 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1018 * present, as explained by the Vulkan (20 Oct 2015, git-aa308cb), Section
1019 * 4.2 Graphics Pipeline.
1020 */
1021 assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
1022
1023 renderpass = anv_render_pass_from_handle(info->renderPass);
1024 assert(renderpass);
1025
1026 if (renderpass != &anv_meta_dummy_renderpass) {
1027 assert(info->subpass < renderpass->subpass_count);
1028 subpass = &renderpass->subpasses[info->subpass];
1029 }
1030
1031 assert(info->stageCount >= 1);
1032 assert(info->pVertexInputState);
1033 assert(info->pInputAssemblyState);
1034 assert(info->pViewportState);
1035 assert(info->pRasterizationState);
1036
1037 if (subpass && subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED)
1038 assert(info->pDepthStencilState);
1039
1040 if (subpass && subpass->color_count > 0)
1041 assert(info->pColorBlendState);
1042
1043 for (uint32_t i = 0; i < info->stageCount; ++i) {
1044 switch (info->pStages[i].stage) {
1045 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
1046 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
1047 assert(info->pTessellationState);
1048 break;
1049 default:
1050 break;
1051 }
1052 }
1053 }
1054
1055 VkResult
1056 anv_pipeline_init(struct anv_pipeline *pipeline,
1057 struct anv_device *device,
1058 struct anv_pipeline_cache *cache,
1059 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1060 const struct anv_graphics_pipeline_create_info *extra,
1061 const VkAllocationCallbacks *alloc)
1062 {
1063 VkResult result;
1064
1065 anv_validate {
1066 anv_pipeline_validate_create_info(pCreateInfo);
1067 }
1068
1069 if (alloc == NULL)
1070 alloc = &device->alloc;
1071
1072 pipeline->device = device;
1073 pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
1074
1075 result = anv_reloc_list_init(&pipeline->batch_relocs, alloc);
1076 if (result != VK_SUCCESS)
1077 return result;
1078
1079 pipeline->batch.alloc = alloc;
1080 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
1081 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
1082 pipeline->batch.relocs = &pipeline->batch_relocs;
1083
1084 anv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1085
1086 if (pCreateInfo->pTessellationState)
1087 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_TESSELLATION_STATE_CREATE_INFO");
1088
1089 pipeline->use_repclear = extra && extra->use_repclear;
1090 pipeline->writes_point_size = false;
1091
1092 /* When we free the pipeline, we detect stages based on the NULL status
1093 * of various prog_data pointers. Make them NULL by default.
1094 */
1095 memset(pipeline->prog_data, 0, sizeof(pipeline->prog_data));
1096 memset(pipeline->scratch_start, 0, sizeof(pipeline->scratch_start));
1097 memset(pipeline->bindings, 0, sizeof(pipeline->bindings));
1098
1099 pipeline->vs_simd8 = NO_KERNEL;
1100 pipeline->vs_vec4 = NO_KERNEL;
1101 pipeline->gs_kernel = NO_KERNEL;
1102 pipeline->ps_ksp0 = NO_KERNEL;
1103
1104 pipeline->active_stages = 0;
1105 pipeline->total_scratch = 0;
1106
1107 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1108 struct anv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1109 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1110 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1111 pStages[stage] = &pCreateInfo->pStages[i];
1112 modules[stage] = anv_shader_module_from_handle(pStages[stage]->module);
1113 }
1114
1115 if (modules[MESA_SHADER_VERTEX]) {
1116 anv_pipeline_compile_vs(pipeline, cache, pCreateInfo,
1117 modules[MESA_SHADER_VERTEX],
1118 pStages[MESA_SHADER_VERTEX]->pName,
1119 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo);
1120 }
1121
1122 if (modules[MESA_SHADER_GEOMETRY]) {
1123 anv_pipeline_compile_gs(pipeline, cache, pCreateInfo,
1124 modules[MESA_SHADER_GEOMETRY],
1125 pStages[MESA_SHADER_GEOMETRY]->pName,
1126 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo);
1127 }
1128
1129 if (modules[MESA_SHADER_FRAGMENT]) {
1130 anv_pipeline_compile_fs(pipeline, cache, pCreateInfo, extra,
1131 modules[MESA_SHADER_FRAGMENT],
1132 pStages[MESA_SHADER_FRAGMENT]->pName,
1133 pStages[MESA_SHADER_FRAGMENT]->pSpecializationInfo);
1134 }
1135
1136 if (!(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT)) {
1137 /* Vertex is only optional if disable_vs is set */
1138 assert(extra->disable_vs);
1139 memset(&pipeline->vs_prog_data, 0, sizeof(pipeline->vs_prog_data));
1140 }
1141
1142 gen7_compute_urb_partition(pipeline);
1143
1144 const VkPipelineVertexInputStateCreateInfo *vi_info =
1145 pCreateInfo->pVertexInputState;
1146
1147 uint64_t inputs_read;
1148 if (extra && extra->disable_vs) {
1149 /* If the VS is disabled, just assume the user knows what they're
1150 * doing and apply the layout blindly. This can only come from
1151 * meta, so this *should* be safe.
1152 */
1153 inputs_read = ~0ull;
1154 } else {
1155 inputs_read = pipeline->vs_prog_data.inputs_read;
1156 }
1157
1158 pipeline->vb_used = 0;
1159 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1160 const VkVertexInputAttributeDescription *desc =
1161 &vi_info->pVertexAttributeDescriptions[i];
1162
1163 if (inputs_read & (1 << (VERT_ATTRIB_GENERIC0 + desc->location)))
1164 pipeline->vb_used |= 1 << desc->binding;
1165 }
1166
1167 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1168 const VkVertexInputBindingDescription *desc =
1169 &vi_info->pVertexBindingDescriptions[i];
1170
1171 pipeline->binding_stride[desc->binding] = desc->stride;
1172
1173 /* Step rate is programmed per vertex element (attribute), not
1174 * binding. Set up a map of which bindings step per instance, for
1175 * reference by vertex element setup. */
1176 switch (desc->inputRate) {
1177 default:
1178 case VK_VERTEX_INPUT_RATE_VERTEX:
1179 pipeline->instancing_enable[desc->binding] = false;
1180 break;
1181 case VK_VERTEX_INPUT_RATE_INSTANCE:
1182 pipeline->instancing_enable[desc->binding] = true;
1183 break;
1184 }
1185 }
1186
1187 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1188 pCreateInfo->pInputAssemblyState;
1189 pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1190 pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1191
1192 if (extra && extra->use_rectlist)
1193 pipeline->topology = _3DPRIM_RECTLIST;
1194
1195 while (anv_block_pool_size(&device->scratch_block_pool) <
1196 pipeline->total_scratch)
1197 anv_block_pool_alloc(&device->scratch_block_pool);
1198
1199 return VK_SUCCESS;
1200 }
1201
1202 VkResult
1203 anv_graphics_pipeline_create(
1204 VkDevice _device,
1205 VkPipelineCache _cache,
1206 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1207 const struct anv_graphics_pipeline_create_info *extra,
1208 const VkAllocationCallbacks *pAllocator,
1209 VkPipeline *pPipeline)
1210 {
1211 ANV_FROM_HANDLE(anv_device, device, _device);
1212 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
1213
1214 if (cache == NULL)
1215 cache = &device->default_pipeline_cache;
1216
1217 switch (device->info.gen) {
1218 case 7:
1219 if (device->info.is_haswell)
1220 return gen75_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1221 else
1222 return gen7_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1223 case 8:
1224 return gen8_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1225 case 9:
1226 return gen9_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1227 default:
1228 unreachable("unsupported gen\n");
1229 }
1230 }
1231
1232 VkResult anv_CreateGraphicsPipelines(
1233 VkDevice _device,
1234 VkPipelineCache pipelineCache,
1235 uint32_t count,
1236 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1237 const VkAllocationCallbacks* pAllocator,
1238 VkPipeline* pPipelines)
1239 {
1240 VkResult result = VK_SUCCESS;
1241
1242 unsigned i = 0;
1243 for (; i < count; i++) {
1244 result = anv_graphics_pipeline_create(_device,
1245 pipelineCache,
1246 &pCreateInfos[i],
1247 NULL, pAllocator, &pPipelines[i]);
1248 if (result != VK_SUCCESS) {
1249 for (unsigned j = 0; j < i; j++) {
1250 anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1251 }
1252
1253 return result;
1254 }
1255 }
1256
1257 return VK_SUCCESS;
1258 }
1259
1260 static VkResult anv_compute_pipeline_create(
1261 VkDevice _device,
1262 VkPipelineCache _cache,
1263 const VkComputePipelineCreateInfo* pCreateInfo,
1264 const VkAllocationCallbacks* pAllocator,
1265 VkPipeline* pPipeline)
1266 {
1267 ANV_FROM_HANDLE(anv_device, device, _device);
1268 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
1269
1270 if (cache == NULL)
1271 cache = &device->default_pipeline_cache;
1272
1273 switch (device->info.gen) {
1274 case 7:
1275 if (device->info.is_haswell)
1276 return gen75_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1277 else
1278 return gen7_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1279 case 8:
1280 return gen8_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1281 case 9:
1282 return gen9_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1283 default:
1284 unreachable("unsupported gen\n");
1285 }
1286 }
1287
1288 VkResult anv_CreateComputePipelines(
1289 VkDevice _device,
1290 VkPipelineCache pipelineCache,
1291 uint32_t count,
1292 const VkComputePipelineCreateInfo* pCreateInfos,
1293 const VkAllocationCallbacks* pAllocator,
1294 VkPipeline* pPipelines)
1295 {
1296 VkResult result = VK_SUCCESS;
1297
1298 unsigned i = 0;
1299 for (; i < count; i++) {
1300 result = anv_compute_pipeline_create(_device, pipelineCache,
1301 &pCreateInfos[i],
1302 pAllocator, &pPipelines[i]);
1303 if (result != VK_SUCCESS) {
1304 for (unsigned j = 0; j < i; j++) {
1305 anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1306 }
1307
1308 return result;
1309 }
1310 }
1311
1312 return VK_SUCCESS;
1313 }