2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "common/gen_l3_config.h"
32 #include "anv_private.h"
33 #include "compiler/brw_nir.h"
35 #include "spirv/nir_spirv.h"
37 /* Needed for SWIZZLE macros */
38 #include "program/prog_instruction.h"
42 VkResult
anv_CreateShaderModule(
44 const VkShaderModuleCreateInfo
* pCreateInfo
,
45 const VkAllocationCallbacks
* pAllocator
,
46 VkShaderModule
* pShaderModule
)
48 ANV_FROM_HANDLE(anv_device
, device
, _device
);
49 struct anv_shader_module
*module
;
51 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
52 assert(pCreateInfo
->flags
== 0);
54 module
= vk_alloc2(&device
->alloc
, pAllocator
,
55 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
56 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
58 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
60 module
->size
= pCreateInfo
->codeSize
;
61 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
63 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
65 *pShaderModule
= anv_shader_module_to_handle(module
);
70 void anv_DestroyShaderModule(
72 VkShaderModule _module
,
73 const VkAllocationCallbacks
* pAllocator
)
75 ANV_FROM_HANDLE(anv_device
, device
, _device
);
76 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
81 vk_free2(&device
->alloc
, pAllocator
, module
);
84 #define SPIR_V_MAGIC_NUMBER 0x07230203
86 static const uint64_t stage_to_debug
[] = {
87 [MESA_SHADER_VERTEX
] = DEBUG_VS
,
88 [MESA_SHADER_TESS_CTRL
] = DEBUG_TCS
,
89 [MESA_SHADER_TESS_EVAL
] = DEBUG_TES
,
90 [MESA_SHADER_GEOMETRY
] = DEBUG_GS
,
91 [MESA_SHADER_FRAGMENT
] = DEBUG_WM
,
92 [MESA_SHADER_COMPUTE
] = DEBUG_CS
,
95 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
96 * we can't do that yet because we don't have the ability to copy nir.
99 anv_shader_compile_to_nir(struct anv_pipeline
*pipeline
,
101 struct anv_shader_module
*module
,
102 const char *entrypoint_name
,
103 gl_shader_stage stage
,
104 const VkSpecializationInfo
*spec_info
)
106 const struct anv_device
*device
= pipeline
->device
;
108 const struct brw_compiler
*compiler
=
109 device
->instance
->physicalDevice
.compiler
;
110 const nir_shader_compiler_options
*nir_options
=
111 compiler
->glsl_compiler_options
[stage
].NirOptions
;
113 uint32_t *spirv
= (uint32_t *) module
->data
;
114 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
115 assert(module
->size
% 4 == 0);
117 uint32_t num_spec_entries
= 0;
118 struct nir_spirv_specialization
*spec_entries
= NULL
;
119 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
120 num_spec_entries
= spec_info
->mapEntryCount
;
121 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
122 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
123 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
124 const void *data
= spec_info
->pData
+ entry
.offset
;
125 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
127 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
128 if (spec_info
->dataSize
== 8)
129 spec_entries
[i
].data64
= *(const uint64_t *)data
;
131 spec_entries
[i
].data32
= *(const uint32_t *)data
;
135 const struct nir_spirv_supported_extensions supported_ext
= {
136 .float64
= device
->instance
->physicalDevice
.info
.gen
>= 8,
137 .int64
= device
->instance
->physicalDevice
.info
.gen
>= 8,
138 .tessellation
= true,
139 .draw_parameters
= true,
140 .image_write_without_format
= true,
142 .variable_pointers
= true,
145 nir_function
*entry_point
=
146 spirv_to_nir(spirv
, module
->size
/ 4,
147 spec_entries
, num_spec_entries
,
148 stage
, entrypoint_name
, &supported_ext
, nir_options
);
149 nir_shader
*nir
= entry_point
->shader
;
150 assert(nir
->info
.stage
== stage
);
151 nir_validate_shader(nir
);
152 ralloc_steal(mem_ctx
, nir
);
156 if (unlikely(INTEL_DEBUG
& stage_to_debug
[stage
])) {
157 fprintf(stderr
, "NIR (from SPIR-V) for %s shader:\n",
158 gl_shader_stage_name(stage
));
159 nir_print_shader(nir
, stderr
);
162 /* We have to lower away local constant initializers right before we
163 * inline functions. That way they get properly initialized at the top
164 * of the function and not at the top of its caller.
166 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_local
);
167 NIR_PASS_V(nir
, nir_lower_returns
);
168 NIR_PASS_V(nir
, nir_inline_functions
);
170 /* Pick off the single entrypoint that we want */
171 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
172 if (func
!= entry_point
)
173 exec_node_remove(&func
->node
);
175 assert(exec_list_length(&nir
->functions
) == 1);
176 entry_point
->name
= ralloc_strdup(entry_point
, "main");
178 NIR_PASS_V(nir
, nir_remove_dead_variables
,
179 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
181 if (stage
== MESA_SHADER_FRAGMENT
)
182 NIR_PASS_V(nir
, nir_lower_wpos_center
, pipeline
->sample_shading_enable
);
184 /* Now that we've deleted all but the main function, we can go ahead and
185 * lower the rest of the constant initializers.
187 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
188 NIR_PASS_V(nir
, nir_propagate_invariant
);
189 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
190 entry_point
->impl
, true, false);
191 NIR_PASS_V(nir
, nir_lower_system_values
);
193 /* Vulkan uses the separate-shader linking model */
194 nir
->info
.separate_shader
= true;
196 nir
= brw_preprocess_nir(compiler
, nir
);
198 if (stage
== MESA_SHADER_FRAGMENT
)
199 NIR_PASS_V(nir
, anv_nir_lower_input_attachments
);
204 void anv_DestroyPipeline(
206 VkPipeline _pipeline
,
207 const VkAllocationCallbacks
* pAllocator
)
209 ANV_FROM_HANDLE(anv_device
, device
, _device
);
210 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
215 anv_reloc_list_finish(&pipeline
->batch_relocs
,
216 pAllocator
? pAllocator
: &device
->alloc
);
217 if (pipeline
->blend_state
.map
)
218 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
220 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
221 if (pipeline
->shaders
[s
])
222 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
225 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
228 static const uint32_t vk_to_gen_primitive_type
[] = {
229 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
230 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
231 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
232 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
233 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
234 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
235 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
236 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
237 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
238 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
242 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
243 struct brw_sampler_prog_key_data
*key
)
245 /* Almost all multisampled textures are compressed. The only time when we
246 * don't compress a multisampled texture is for 16x MSAA with a surface
247 * width greater than 8k which is a bit of an edge case. Since the sampler
248 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
249 * to tell the compiler to always assume compression.
251 key
->compressed_multisample_layout_mask
= ~0;
253 /* SkyLake added support for 16x MSAA. With this came a new message for
254 * reading from a 16x MSAA surface with compression. The new message was
255 * needed because now the MCS data is 64 bits instead of 32 or lower as is
256 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
257 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
258 * so we can just use it unconditionally. This may not be quite as
259 * efficient but it saves us from recompiling.
261 if (devinfo
->gen
>= 9)
264 /* XXX: Handle texture swizzle on HSW- */
265 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
266 /* Assume color sampler, no swizzling. (Works for BDW+) */
267 key
->swizzles
[i
] = SWIZZLE_XYZW
;
272 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
273 struct brw_vs_prog_key
*key
)
275 memset(key
, 0, sizeof(*key
));
277 populate_sampler_prog_key(devinfo
, &key
->tex
);
279 /* XXX: Handle vertex input work-arounds */
281 /* XXX: Handle sampler_prog_key */
285 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
286 struct brw_gs_prog_key
*key
)
288 memset(key
, 0, sizeof(*key
));
290 populate_sampler_prog_key(devinfo
, &key
->tex
);
294 populate_wm_prog_key(const struct anv_pipeline
*pipeline
,
295 const VkGraphicsPipelineCreateInfo
*info
,
296 struct brw_wm_prog_key
*key
)
298 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
300 memset(key
, 0, sizeof(*key
));
302 populate_sampler_prog_key(devinfo
, &key
->tex
);
304 /* TODO: we could set this to 0 based on the information in nir_shader, but
305 * this function is called before spirv_to_nir. */
306 const struct brw_vue_map
*vue_map
=
307 &anv_pipeline_get_last_vue_prog_data(pipeline
)->vue_map
;
308 key
->input_slots_valid
= vue_map
->slots_valid
;
310 /* Vulkan doesn't specify a default */
311 key
->high_quality_derivatives
= false;
313 /* XXX Vulkan doesn't appear to specify */
314 key
->clamp_fragment_color
= false;
316 key
->nr_color_regions
= pipeline
->subpass
->color_count
;
318 key
->replicate_alpha
= key
->nr_color_regions
> 1 &&
319 info
->pMultisampleState
&&
320 info
->pMultisampleState
->alphaToCoverageEnable
;
322 if (info
->pMultisampleState
) {
323 /* We should probably pull this out of the shader, but it's fairly
324 * harmless to compute it and then let dead-code take care of it.
326 if (info
->pMultisampleState
->rasterizationSamples
> 1) {
327 key
->persample_interp
=
328 (info
->pMultisampleState
->minSampleShading
*
329 info
->pMultisampleState
->rasterizationSamples
) > 1;
330 key
->multisample_fbo
= true;
333 key
->frag_coord_adds_sample_pos
=
334 info
->pMultisampleState
->sampleShadingEnable
;
339 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
340 struct brw_cs_prog_key
*key
)
342 memset(key
, 0, sizeof(*key
));
344 populate_sampler_prog_key(devinfo
, &key
->tex
);
348 anv_pipeline_hash_shader(struct anv_pipeline
*pipeline
,
349 struct anv_shader_module
*module
,
350 const char *entrypoint
,
351 gl_shader_stage stage
,
352 const VkSpecializationInfo
*spec_info
,
353 const void *key
, size_t key_size
,
354 unsigned char *sha1_out
)
356 struct mesa_sha1 ctx
;
358 _mesa_sha1_init(&ctx
);
359 if (stage
!= MESA_SHADER_COMPUTE
) {
360 _mesa_sha1_update(&ctx
, &pipeline
->subpass
->view_mask
,
361 sizeof(pipeline
->subpass
->view_mask
));
363 if (pipeline
->layout
) {
364 _mesa_sha1_update(&ctx
, pipeline
->layout
->sha1
,
365 sizeof(pipeline
->layout
->sha1
));
367 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
368 _mesa_sha1_update(&ctx
, entrypoint
, strlen(entrypoint
));
369 _mesa_sha1_update(&ctx
, &stage
, sizeof(stage
));
371 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
372 spec_info
->mapEntryCount
* sizeof(*spec_info
->pMapEntries
));
373 _mesa_sha1_update(&ctx
, spec_info
->pData
, spec_info
->dataSize
);
375 _mesa_sha1_update(&ctx
, key
, key_size
);
376 _mesa_sha1_final(&ctx
, sha1_out
);
380 anv_pipeline_compile(struct anv_pipeline
*pipeline
,
382 struct anv_shader_module
*module
,
383 const char *entrypoint
,
384 gl_shader_stage stage
,
385 const VkSpecializationInfo
*spec_info
,
386 struct brw_stage_prog_data
*prog_data
,
387 struct anv_pipeline_bind_map
*map
)
389 nir_shader
*nir
= anv_shader_compile_to_nir(pipeline
, mem_ctx
,
390 module
, entrypoint
, stage
,
395 NIR_PASS_V(nir
, anv_nir_lower_ycbcr_textures
, pipeline
);
397 NIR_PASS_V(nir
, anv_nir_lower_push_constants
);
399 if (stage
!= MESA_SHADER_COMPUTE
)
400 NIR_PASS_V(nir
, anv_nir_lower_multiview
, pipeline
->subpass
->view_mask
);
402 if (stage
== MESA_SHADER_COMPUTE
) {
403 NIR_PASS_V(nir
, brw_nir_lower_cs_shared
);
404 prog_data
->total_shared
= nir
->num_shared
;
407 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
409 if (nir
->num_uniforms
> 0) {
410 assert(prog_data
->nr_params
== 0);
412 /* If the shader uses any push constants at all, we'll just give
413 * them the maximum possible number
415 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
416 nir
->num_uniforms
= MAX_PUSH_CONSTANTS_SIZE
;
417 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
418 prog_data
->param
= ralloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
420 /* We now set the param values to be offsets into a
421 * anv_push_constant_data structure. Since the compiler doesn't
422 * actually dereference any of the gl_constant_value pointers in the
423 * params array, it doesn't really matter what we put here.
425 struct anv_push_constants
*null_data
= NULL
;
426 /* Fill out the push constants section of the param array */
427 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++) {
428 prog_data
->param
[i
] = ANV_PARAM_PUSH(
429 (uintptr_t)&null_data
->client_data
[i
* sizeof(float)]);
433 if (nir
->info
.num_ssbos
> 0 || nir
->info
.num_images
> 0)
434 pipeline
->needs_data_cache
= true;
436 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
437 if (pipeline
->layout
)
438 anv_nir_apply_pipeline_layout(pipeline
, nir
, prog_data
, map
);
440 assert(nir
->num_uniforms
== prog_data
->nr_params
* 4);
446 anv_fill_binding_table(struct brw_stage_prog_data
*prog_data
, unsigned bias
)
448 prog_data
->binding_table
.size_bytes
= 0;
449 prog_data
->binding_table
.texture_start
= bias
;
450 prog_data
->binding_table
.gather_texture_start
= bias
;
451 prog_data
->binding_table
.ubo_start
= bias
;
452 prog_data
->binding_table
.ssbo_start
= bias
;
453 prog_data
->binding_table
.image_start
= bias
;
456 static struct anv_shader_bin
*
457 anv_pipeline_upload_kernel(struct anv_pipeline
*pipeline
,
458 struct anv_pipeline_cache
*cache
,
459 const void *key_data
, uint32_t key_size
,
460 const void *kernel_data
, uint32_t kernel_size
,
461 const struct brw_stage_prog_data
*prog_data
,
462 uint32_t prog_data_size
,
463 const struct anv_pipeline_bind_map
*bind_map
)
466 return anv_pipeline_cache_upload_kernel(cache
, key_data
, key_size
,
467 kernel_data
, kernel_size
,
468 prog_data
, prog_data_size
,
471 return anv_shader_bin_create(pipeline
->device
, key_data
, key_size
,
472 kernel_data
, kernel_size
,
473 prog_data
, prog_data_size
,
474 prog_data
->param
, bind_map
);
480 anv_pipeline_add_compiled_stage(struct anv_pipeline
*pipeline
,
481 gl_shader_stage stage
,
482 struct anv_shader_bin
*shader
)
484 pipeline
->shaders
[stage
] = shader
;
485 pipeline
->active_stages
|= mesa_to_vk_shader_stage(stage
);
489 anv_pipeline_compile_vs(struct anv_pipeline
*pipeline
,
490 struct anv_pipeline_cache
*cache
,
491 const VkGraphicsPipelineCreateInfo
*info
,
492 struct anv_shader_module
*module
,
493 const char *entrypoint
,
494 const VkSpecializationInfo
*spec_info
)
496 const struct brw_compiler
*compiler
=
497 pipeline
->device
->instance
->physicalDevice
.compiler
;
498 struct brw_vs_prog_key key
;
499 struct anv_shader_bin
*bin
= NULL
;
500 unsigned char sha1
[20];
502 populate_vs_prog_key(&pipeline
->device
->info
, &key
);
505 anv_pipeline_hash_shader(pipeline
, module
, entrypoint
,
506 MESA_SHADER_VERTEX
, spec_info
,
507 &key
, sizeof(key
), sha1
);
508 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
512 struct brw_vs_prog_data prog_data
= {};
513 struct anv_pipeline_binding surface_to_descriptor
[256];
514 struct anv_pipeline_binding sampler_to_descriptor
[256];
516 struct anv_pipeline_bind_map map
= {
517 .surface_to_descriptor
= surface_to_descriptor
,
518 .sampler_to_descriptor
= sampler_to_descriptor
521 void *mem_ctx
= ralloc_context(NULL
);
523 nir_shader
*nir
= anv_pipeline_compile(pipeline
, mem_ctx
,
525 MESA_SHADER_VERTEX
, spec_info
,
526 &prog_data
.base
.base
, &map
);
528 ralloc_free(mem_ctx
);
529 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
532 anv_fill_binding_table(&prog_data
.base
.base
, 0);
534 brw_compute_vue_map(&pipeline
->device
->info
,
535 &prog_data
.base
.vue_map
,
536 nir
->info
.outputs_written
,
537 nir
->info
.separate_shader
);
540 const unsigned *shader_code
=
541 brw_compile_vs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
542 false, -1, &code_size
, NULL
);
543 if (shader_code
== NULL
) {
544 ralloc_free(mem_ctx
);
545 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
548 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
549 shader_code
, code_size
,
550 &prog_data
.base
.base
, sizeof(prog_data
),
553 ralloc_free(mem_ctx
);
554 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
557 ralloc_free(mem_ctx
);
560 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_VERTEX
, bin
);
566 merge_tess_info(struct shader_info
*tes_info
,
567 const struct shader_info
*tcs_info
)
569 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
571 * "PointMode. Controls generation of points rather than triangles
572 * or lines. This functionality defaults to disabled, and is
573 * enabled if either shader stage includes the execution mode.
575 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
576 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
577 * and OutputVertices, it says:
579 * "One mode must be set in at least one of the tessellation
582 * So, the fields can be set in either the TCS or TES, but they must
583 * agree if set in both. Our backend looks at TES, so bitwise-or in
584 * the values from the TCS.
586 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
587 tes_info
->tess
.tcs_vertices_out
== 0 ||
588 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
589 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
591 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
592 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
593 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
594 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
596 assert(tcs_info
->tess
.primitive_mode
== 0 ||
597 tes_info
->tess
.primitive_mode
== 0 ||
598 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
599 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
600 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
601 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
605 anv_pipeline_compile_tcs_tes(struct anv_pipeline
*pipeline
,
606 struct anv_pipeline_cache
*cache
,
607 const VkGraphicsPipelineCreateInfo
*info
,
608 struct anv_shader_module
*tcs_module
,
609 const char *tcs_entrypoint
,
610 const VkSpecializationInfo
*tcs_spec_info
,
611 struct anv_shader_module
*tes_module
,
612 const char *tes_entrypoint
,
613 const VkSpecializationInfo
*tes_spec_info
)
615 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
616 const struct brw_compiler
*compiler
=
617 pipeline
->device
->instance
->physicalDevice
.compiler
;
618 struct brw_tcs_prog_key tcs_key
= {};
619 struct brw_tes_prog_key tes_key
= {};
620 struct anv_shader_bin
*tcs_bin
= NULL
;
621 struct anv_shader_bin
*tes_bin
= NULL
;
622 unsigned char tcs_sha1
[40];
623 unsigned char tes_sha1
[40];
625 populate_sampler_prog_key(&pipeline
->device
->info
, &tcs_key
.tex
);
626 populate_sampler_prog_key(&pipeline
->device
->info
, &tes_key
.tex
);
627 tcs_key
.input_vertices
= info
->pTessellationState
->patchControlPoints
;
630 anv_pipeline_hash_shader(pipeline
, tcs_module
, tcs_entrypoint
,
631 MESA_SHADER_TESS_CTRL
, tcs_spec_info
,
632 &tcs_key
, sizeof(tcs_key
), tcs_sha1
);
633 anv_pipeline_hash_shader(pipeline
, tes_module
, tes_entrypoint
,
634 MESA_SHADER_TESS_EVAL
, tes_spec_info
,
635 &tes_key
, sizeof(tes_key
), tes_sha1
);
636 memcpy(&tcs_sha1
[20], tes_sha1
, 20);
637 memcpy(&tes_sha1
[20], tcs_sha1
, 20);
638 tcs_bin
= anv_pipeline_cache_search(cache
, tcs_sha1
, sizeof(tcs_sha1
));
639 tes_bin
= anv_pipeline_cache_search(cache
, tes_sha1
, sizeof(tes_sha1
));
642 if (tcs_bin
== NULL
|| tes_bin
== NULL
) {
643 struct brw_tcs_prog_data tcs_prog_data
= {};
644 struct brw_tes_prog_data tes_prog_data
= {};
645 struct anv_pipeline_binding tcs_surface_to_descriptor
[256];
646 struct anv_pipeline_binding tcs_sampler_to_descriptor
[256];
647 struct anv_pipeline_binding tes_surface_to_descriptor
[256];
648 struct anv_pipeline_binding tes_sampler_to_descriptor
[256];
650 struct anv_pipeline_bind_map tcs_map
= {
651 .surface_to_descriptor
= tcs_surface_to_descriptor
,
652 .sampler_to_descriptor
= tcs_sampler_to_descriptor
654 struct anv_pipeline_bind_map tes_map
= {
655 .surface_to_descriptor
= tes_surface_to_descriptor
,
656 .sampler_to_descriptor
= tes_sampler_to_descriptor
659 void *mem_ctx
= ralloc_context(NULL
);
661 nir_shader
*tcs_nir
=
662 anv_pipeline_compile(pipeline
, mem_ctx
, tcs_module
, tcs_entrypoint
,
663 MESA_SHADER_TESS_CTRL
, tcs_spec_info
,
664 &tcs_prog_data
.base
.base
, &tcs_map
);
665 nir_shader
*tes_nir
=
666 anv_pipeline_compile(pipeline
, mem_ctx
, tes_module
, tes_entrypoint
,
667 MESA_SHADER_TESS_EVAL
, tes_spec_info
,
668 &tes_prog_data
.base
.base
, &tes_map
);
669 if (tcs_nir
== NULL
|| tes_nir
== NULL
) {
670 ralloc_free(mem_ctx
);
671 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
674 nir_lower_tes_patch_vertices(tes_nir
,
675 tcs_nir
->info
.tess
.tcs_vertices_out
);
677 /* Copy TCS info into the TES info */
678 merge_tess_info(&tes_nir
->info
, &tcs_nir
->info
);
680 anv_fill_binding_table(&tcs_prog_data
.base
.base
, 0);
681 anv_fill_binding_table(&tes_prog_data
.base
.base
, 0);
683 /* Whacking the key after cache lookup is a bit sketchy, but all of
684 * this comes from the SPIR-V, which is part of the hash used for the
685 * pipeline cache. So it should be safe.
687 tcs_key
.tes_primitive_mode
= tes_nir
->info
.tess
.primitive_mode
;
688 tcs_key
.outputs_written
= tcs_nir
->info
.outputs_written
;
689 tcs_key
.patch_outputs_written
= tcs_nir
->info
.patch_outputs_written
;
690 tcs_key
.quads_workaround
=
692 tes_nir
->info
.tess
.primitive_mode
== 7 /* GL_QUADS */ &&
693 tes_nir
->info
.tess
.spacing
== TESS_SPACING_EQUAL
;
695 tes_key
.inputs_read
= tcs_key
.outputs_written
;
696 tes_key
.patch_inputs_read
= tcs_key
.patch_outputs_written
;
699 const int shader_time_index
= -1;
700 const unsigned *shader_code
;
703 brw_compile_tcs(compiler
, NULL
, mem_ctx
, &tcs_key
, &tcs_prog_data
,
704 tcs_nir
, shader_time_index
, &code_size
, NULL
);
705 if (shader_code
== NULL
) {
706 ralloc_free(mem_ctx
);
707 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
710 tcs_bin
= anv_pipeline_upload_kernel(pipeline
, cache
,
711 tcs_sha1
, sizeof(tcs_sha1
),
712 shader_code
, code_size
,
713 &tcs_prog_data
.base
.base
,
714 sizeof(tcs_prog_data
),
717 ralloc_free(mem_ctx
);
718 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
722 brw_compile_tes(compiler
, NULL
, mem_ctx
, &tes_key
,
723 &tcs_prog_data
.base
.vue_map
, &tes_prog_data
, tes_nir
,
724 NULL
, shader_time_index
, &code_size
, NULL
);
725 if (shader_code
== NULL
) {
726 ralloc_free(mem_ctx
);
727 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
730 tes_bin
= anv_pipeline_upload_kernel(pipeline
, cache
,
731 tes_sha1
, sizeof(tes_sha1
),
732 shader_code
, code_size
,
733 &tes_prog_data
.base
.base
,
734 sizeof(tes_prog_data
),
737 ralloc_free(mem_ctx
);
738 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
741 ralloc_free(mem_ctx
);
744 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_TESS_CTRL
, tcs_bin
);
745 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_TESS_EVAL
, tes_bin
);
751 anv_pipeline_compile_gs(struct anv_pipeline
*pipeline
,
752 struct anv_pipeline_cache
*cache
,
753 const VkGraphicsPipelineCreateInfo
*info
,
754 struct anv_shader_module
*module
,
755 const char *entrypoint
,
756 const VkSpecializationInfo
*spec_info
)
758 const struct brw_compiler
*compiler
=
759 pipeline
->device
->instance
->physicalDevice
.compiler
;
760 struct brw_gs_prog_key key
;
761 struct anv_shader_bin
*bin
= NULL
;
762 unsigned char sha1
[20];
764 populate_gs_prog_key(&pipeline
->device
->info
, &key
);
767 anv_pipeline_hash_shader(pipeline
, module
, entrypoint
,
768 MESA_SHADER_GEOMETRY
, spec_info
,
769 &key
, sizeof(key
), sha1
);
770 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
774 struct brw_gs_prog_data prog_data
= {};
775 struct anv_pipeline_binding surface_to_descriptor
[256];
776 struct anv_pipeline_binding sampler_to_descriptor
[256];
778 struct anv_pipeline_bind_map map
= {
779 .surface_to_descriptor
= surface_to_descriptor
,
780 .sampler_to_descriptor
= sampler_to_descriptor
783 void *mem_ctx
= ralloc_context(NULL
);
785 nir_shader
*nir
= anv_pipeline_compile(pipeline
, mem_ctx
,
787 MESA_SHADER_GEOMETRY
, spec_info
,
788 &prog_data
.base
.base
, &map
);
790 ralloc_free(mem_ctx
);
791 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
794 anv_fill_binding_table(&prog_data
.base
.base
, 0);
796 brw_compute_vue_map(&pipeline
->device
->info
,
797 &prog_data
.base
.vue_map
,
798 nir
->info
.outputs_written
,
799 nir
->info
.separate_shader
);
802 const unsigned *shader_code
=
803 brw_compile_gs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
804 NULL
, -1, &code_size
, NULL
);
805 if (shader_code
== NULL
) {
806 ralloc_free(mem_ctx
);
807 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
811 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
812 shader_code
, code_size
,
813 &prog_data
.base
.base
, sizeof(prog_data
),
816 ralloc_free(mem_ctx
);
817 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
820 ralloc_free(mem_ctx
);
823 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_GEOMETRY
, bin
);
829 anv_pipeline_compile_fs(struct anv_pipeline
*pipeline
,
830 struct anv_pipeline_cache
*cache
,
831 const VkGraphicsPipelineCreateInfo
*info
,
832 struct anv_shader_module
*module
,
833 const char *entrypoint
,
834 const VkSpecializationInfo
*spec_info
)
836 const struct brw_compiler
*compiler
=
837 pipeline
->device
->instance
->physicalDevice
.compiler
;
838 struct brw_wm_prog_key key
;
839 struct anv_shader_bin
*bin
= NULL
;
840 unsigned char sha1
[20];
842 populate_wm_prog_key(pipeline
, info
, &key
);
845 anv_pipeline_hash_shader(pipeline
, module
, entrypoint
,
846 MESA_SHADER_FRAGMENT
, spec_info
,
847 &key
, sizeof(key
), sha1
);
848 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
852 struct brw_wm_prog_data prog_data
= {};
853 struct anv_pipeline_binding surface_to_descriptor
[256];
854 struct anv_pipeline_binding sampler_to_descriptor
[256];
856 struct anv_pipeline_bind_map map
= {
857 .surface_to_descriptor
= surface_to_descriptor
+ 8,
858 .sampler_to_descriptor
= sampler_to_descriptor
861 void *mem_ctx
= ralloc_context(NULL
);
863 nir_shader
*nir
= anv_pipeline_compile(pipeline
, mem_ctx
,
865 MESA_SHADER_FRAGMENT
, spec_info
,
866 &prog_data
.base
, &map
);
868 ralloc_free(mem_ctx
);
869 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
872 unsigned num_rts
= 0;
873 struct anv_pipeline_binding rt_bindings
[8];
874 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
875 nir_foreach_variable_safe(var
, &nir
->outputs
) {
876 if (var
->data
.location
< FRAG_RESULT_DATA0
)
879 unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
880 if (rt
>= key
.nr_color_regions
) {
881 /* Out-of-bounds, throw it away */
882 var
->data
.mode
= nir_var_local
;
883 exec_node_remove(&var
->node
);
884 exec_list_push_tail(&impl
->locals
, &var
->node
);
888 /* Give it a new, compacted, location */
889 var
->data
.location
= FRAG_RESULT_DATA0
+ num_rts
;
892 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
893 assert(num_rts
+ array_len
<= 8);
895 for (unsigned i
= 0; i
< array_len
; i
++) {
896 rt_bindings
[num_rts
+ i
] = (struct anv_pipeline_binding
) {
897 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
903 num_rts
+= array_len
;
907 /* If we have no render targets, we need a null render target */
908 rt_bindings
[0] = (struct anv_pipeline_binding
) {
909 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
916 assert(num_rts
<= 8);
917 map
.surface_to_descriptor
-= num_rts
;
918 map
.surface_count
+= num_rts
;
919 assert(map
.surface_count
<= 256);
920 memcpy(map
.surface_to_descriptor
, rt_bindings
,
921 num_rts
* sizeof(*rt_bindings
));
923 anv_fill_binding_table(&prog_data
.base
, num_rts
);
926 const unsigned *shader_code
=
927 brw_compile_fs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
928 NULL
, -1, -1, true, false, NULL
, &code_size
, NULL
);
929 if (shader_code
== NULL
) {
930 ralloc_free(mem_ctx
);
931 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
934 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
935 shader_code
, code_size
,
936 &prog_data
.base
, sizeof(prog_data
),
939 ralloc_free(mem_ctx
);
940 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
943 ralloc_free(mem_ctx
);
946 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_FRAGMENT
, bin
);
952 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
953 struct anv_pipeline_cache
*cache
,
954 const VkComputePipelineCreateInfo
*info
,
955 struct anv_shader_module
*module
,
956 const char *entrypoint
,
957 const VkSpecializationInfo
*spec_info
)
959 const struct brw_compiler
*compiler
=
960 pipeline
->device
->instance
->physicalDevice
.compiler
;
961 struct brw_cs_prog_key key
;
962 struct anv_shader_bin
*bin
= NULL
;
963 unsigned char sha1
[20];
965 populate_cs_prog_key(&pipeline
->device
->info
, &key
);
968 anv_pipeline_hash_shader(pipeline
, module
, entrypoint
,
969 MESA_SHADER_COMPUTE
, spec_info
,
970 &key
, sizeof(key
), sha1
);
971 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
975 struct brw_cs_prog_data prog_data
= {};
976 struct anv_pipeline_binding surface_to_descriptor
[256];
977 struct anv_pipeline_binding sampler_to_descriptor
[256];
979 struct anv_pipeline_bind_map map
= {
980 .surface_to_descriptor
= surface_to_descriptor
,
981 .sampler_to_descriptor
= sampler_to_descriptor
984 void *mem_ctx
= ralloc_context(NULL
);
986 nir_shader
*nir
= anv_pipeline_compile(pipeline
, mem_ctx
,
988 MESA_SHADER_COMPUTE
, spec_info
,
989 &prog_data
.base
, &map
);
991 ralloc_free(mem_ctx
);
992 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
995 anv_fill_binding_table(&prog_data
.base
, 1);
998 const unsigned *shader_code
=
999 brw_compile_cs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
1000 -1, &code_size
, NULL
);
1001 if (shader_code
== NULL
) {
1002 ralloc_free(mem_ctx
);
1003 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1006 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
1007 shader_code
, code_size
,
1008 &prog_data
.base
, sizeof(prog_data
),
1011 ralloc_free(mem_ctx
);
1012 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1015 ralloc_free(mem_ctx
);
1018 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_COMPUTE
, bin
);
1024 * Copy pipeline state not marked as dynamic.
1025 * Dynamic state is pipeline state which hasn't been provided at pipeline
1026 * creation time, but is dynamically provided afterwards using various
1027 * vkCmdSet* functions.
1029 * The set of state considered "non_dynamic" is determined by the pieces of
1030 * state that have their corresponding VkDynamicState enums omitted from
1031 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1033 * @param[out] pipeline Destination non_dynamic state.
1034 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1037 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
1038 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1040 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
1041 struct anv_subpass
*subpass
= pipeline
->subpass
;
1043 pipeline
->dynamic_state
= default_dynamic_state
;
1045 if (pCreateInfo
->pDynamicState
) {
1046 /* Remove all of the states that are marked as dynamic */
1047 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1048 for (uint32_t s
= 0; s
< count
; s
++)
1049 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1052 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1054 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1056 * pViewportState is [...] NULL if the pipeline
1057 * has rasterization disabled.
1059 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1060 assert(pCreateInfo
->pViewportState
);
1062 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1063 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
1064 typed_memcpy(dynamic
->viewport
.viewports
,
1065 pCreateInfo
->pViewportState
->pViewports
,
1066 pCreateInfo
->pViewportState
->viewportCount
);
1069 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1070 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
1071 typed_memcpy(dynamic
->scissor
.scissors
,
1072 pCreateInfo
->pViewportState
->pScissors
,
1073 pCreateInfo
->pViewportState
->scissorCount
);
1077 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1078 assert(pCreateInfo
->pRasterizationState
);
1079 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1082 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1083 assert(pCreateInfo
->pRasterizationState
);
1084 dynamic
->depth_bias
.bias
=
1085 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1086 dynamic
->depth_bias
.clamp
=
1087 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1088 dynamic
->depth_bias
.slope
=
1089 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1092 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1094 * pColorBlendState is [...] NULL if the pipeline has rasterization
1095 * disabled or if the subpass of the render pass the pipeline is
1096 * created against does not use any color attachments.
1098 bool uses_color_att
= false;
1099 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1100 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1101 uses_color_att
= true;
1106 if (uses_color_att
&&
1107 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1108 assert(pCreateInfo
->pColorBlendState
);
1110 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
1111 typed_memcpy(dynamic
->blend_constants
,
1112 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1115 /* If there is no depthstencil attachment, then don't read
1116 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1117 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1118 * no need to override the depthstencil defaults in
1119 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1121 * Section 9.2 of the Vulkan 1.0.15 spec says:
1123 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1124 * disabled or if the subpass of the render pass the pipeline is created
1125 * against does not use a depth/stencil attachment.
1127 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1128 subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1129 assert(pCreateInfo
->pDepthStencilState
);
1131 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1132 dynamic
->depth_bounds
.min
=
1133 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1134 dynamic
->depth_bounds
.max
=
1135 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1138 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1139 dynamic
->stencil_compare_mask
.front
=
1140 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1141 dynamic
->stencil_compare_mask
.back
=
1142 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1145 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1146 dynamic
->stencil_write_mask
.front
=
1147 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1148 dynamic
->stencil_write_mask
.back
=
1149 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1152 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1153 dynamic
->stencil_reference
.front
=
1154 pCreateInfo
->pDepthStencilState
->front
.reference
;
1155 dynamic
->stencil_reference
.back
=
1156 pCreateInfo
->pDepthStencilState
->back
.reference
;
1160 pipeline
->dynamic_state_mask
= states
;
1164 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1167 struct anv_render_pass
*renderpass
= NULL
;
1168 struct anv_subpass
*subpass
= NULL
;
1170 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1171 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1173 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1175 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1178 assert(info
->subpass
< renderpass
->subpass_count
);
1179 subpass
= &renderpass
->subpasses
[info
->subpass
];
1181 assert(info
->stageCount
>= 1);
1182 assert(info
->pVertexInputState
);
1183 assert(info
->pInputAssemblyState
);
1184 assert(info
->pRasterizationState
);
1185 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1186 assert(info
->pViewportState
);
1187 assert(info
->pMultisampleState
);
1189 if (subpass
&& subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
)
1190 assert(info
->pDepthStencilState
);
1192 if (subpass
&& subpass
->color_count
> 0)
1193 assert(info
->pColorBlendState
);
1196 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1197 switch (info
->pStages
[i
].stage
) {
1198 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1199 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1200 assert(info
->pTessellationState
);
1210 * Calculate the desired L3 partitioning based on the current state of the
1211 * pipeline. For now this simply returns the conservative defaults calculated
1212 * by get_default_l3_weights(), but we could probably do better by gathering
1213 * more statistics from the pipeline state (e.g. guess of expected URB usage
1214 * and bound surfaces), or by using feed-back from performance counters.
1217 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1219 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1221 const struct gen_l3_weights w
=
1222 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
1224 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
1225 pipeline
->urb
.total_size
=
1226 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
1230 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1231 struct anv_device
*device
,
1232 struct anv_pipeline_cache
*cache
,
1233 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1234 const VkAllocationCallbacks
*alloc
)
1238 anv_pipeline_validate_create_info(pCreateInfo
);
1241 alloc
= &device
->alloc
;
1243 pipeline
->device
= device
;
1245 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, pCreateInfo
->renderPass
);
1246 assert(pCreateInfo
->subpass
< render_pass
->subpass_count
);
1247 pipeline
->subpass
= &render_pass
->subpasses
[pCreateInfo
->subpass
];
1249 pipeline
->layout
= anv_pipeline_layout_from_handle(pCreateInfo
->layout
);
1251 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1252 if (result
!= VK_SUCCESS
)
1255 pipeline
->batch
.alloc
= alloc
;
1256 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1257 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1258 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1259 pipeline
->batch
.status
= VK_SUCCESS
;
1261 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1262 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1263 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1265 pipeline
->sample_shading_enable
= pCreateInfo
->pMultisampleState
&&
1266 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
1268 pipeline
->needs_data_cache
= false;
1270 /* When we free the pipeline, we detect stages based on the NULL status
1271 * of various prog_data pointers. Make them NULL by default.
1273 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1275 pipeline
->active_stages
= 0;
1277 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = {};
1278 struct anv_shader_module
*modules
[MESA_SHADER_STAGES
] = {};
1279 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
1280 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
1281 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
1282 modules
[stage
] = anv_shader_module_from_handle(pStages
[stage
]->module
);
1285 if (modules
[MESA_SHADER_VERTEX
]) {
1286 result
= anv_pipeline_compile_vs(pipeline
, cache
, pCreateInfo
,
1287 modules
[MESA_SHADER_VERTEX
],
1288 pStages
[MESA_SHADER_VERTEX
]->pName
,
1289 pStages
[MESA_SHADER_VERTEX
]->pSpecializationInfo
);
1290 if (result
!= VK_SUCCESS
)
1294 if (modules
[MESA_SHADER_TESS_EVAL
]) {
1295 anv_pipeline_compile_tcs_tes(pipeline
, cache
, pCreateInfo
,
1296 modules
[MESA_SHADER_TESS_CTRL
],
1297 pStages
[MESA_SHADER_TESS_CTRL
]->pName
,
1298 pStages
[MESA_SHADER_TESS_CTRL
]->pSpecializationInfo
,
1299 modules
[MESA_SHADER_TESS_EVAL
],
1300 pStages
[MESA_SHADER_TESS_EVAL
]->pName
,
1301 pStages
[MESA_SHADER_TESS_EVAL
]->pSpecializationInfo
);
1304 if (modules
[MESA_SHADER_GEOMETRY
]) {
1305 result
= anv_pipeline_compile_gs(pipeline
, cache
, pCreateInfo
,
1306 modules
[MESA_SHADER_GEOMETRY
],
1307 pStages
[MESA_SHADER_GEOMETRY
]->pName
,
1308 pStages
[MESA_SHADER_GEOMETRY
]->pSpecializationInfo
);
1309 if (result
!= VK_SUCCESS
)
1313 if (modules
[MESA_SHADER_FRAGMENT
]) {
1314 result
= anv_pipeline_compile_fs(pipeline
, cache
, pCreateInfo
,
1315 modules
[MESA_SHADER_FRAGMENT
],
1316 pStages
[MESA_SHADER_FRAGMENT
]->pName
,
1317 pStages
[MESA_SHADER_FRAGMENT
]->pSpecializationInfo
);
1318 if (result
!= VK_SUCCESS
)
1322 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1324 anv_pipeline_setup_l3_config(pipeline
, false);
1326 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1327 pCreateInfo
->pVertexInputState
;
1329 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1331 pipeline
->vb_used
= 0;
1332 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1333 const VkVertexInputAttributeDescription
*desc
=
1334 &vi_info
->pVertexAttributeDescriptions
[i
];
1336 if (inputs_read
& (1ull << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1337 pipeline
->vb_used
|= 1 << desc
->binding
;
1340 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1341 const VkVertexInputBindingDescription
*desc
=
1342 &vi_info
->pVertexBindingDescriptions
[i
];
1344 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
1346 /* Step rate is programmed per vertex element (attribute), not
1347 * binding. Set up a map of which bindings step per instance, for
1348 * reference by vertex element setup. */
1349 switch (desc
->inputRate
) {
1351 case VK_VERTEX_INPUT_RATE_VERTEX
:
1352 pipeline
->instancing_enable
[desc
->binding
] = false;
1354 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1355 pipeline
->instancing_enable
[desc
->binding
] = true;
1360 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1361 pCreateInfo
->pInputAssemblyState
;
1362 const VkPipelineTessellationStateCreateInfo
*tess_info
=
1363 pCreateInfo
->pTessellationState
;
1364 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1366 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1367 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
1369 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];
1374 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1375 if (pipeline
->shaders
[s
])
1376 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
1379 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);