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anv/pipeline: Lower more constant initializers earlier
[mesa.git] / src / intel / vulkan / anv_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "util/mesa-sha1.h"
31 #include "common/gen_l3_config.h"
32 #include "anv_private.h"
33 #include "compiler/brw_nir.h"
34 #include "anv_nir.h"
35 #include "spirv/nir_spirv.h"
36
37 /* Needed for SWIZZLE macros */
38 #include "program/prog_instruction.h"
39
40 // Shader functions
41
42 VkResult anv_CreateShaderModule(
43 VkDevice _device,
44 const VkShaderModuleCreateInfo* pCreateInfo,
45 const VkAllocationCallbacks* pAllocator,
46 VkShaderModule* pShaderModule)
47 {
48 ANV_FROM_HANDLE(anv_device, device, _device);
49 struct anv_shader_module *module;
50
51 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
52 assert(pCreateInfo->flags == 0);
53
54 module = vk_alloc2(&device->alloc, pAllocator,
55 sizeof(*module) + pCreateInfo->codeSize, 8,
56 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
57 if (module == NULL)
58 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
59
60 module->size = pCreateInfo->codeSize;
61 memcpy(module->data, pCreateInfo->pCode, module->size);
62
63 _mesa_sha1_compute(module->data, module->size, module->sha1);
64
65 *pShaderModule = anv_shader_module_to_handle(module);
66
67 return VK_SUCCESS;
68 }
69
70 void anv_DestroyShaderModule(
71 VkDevice _device,
72 VkShaderModule _module,
73 const VkAllocationCallbacks* pAllocator)
74 {
75 ANV_FROM_HANDLE(anv_device, device, _device);
76 ANV_FROM_HANDLE(anv_shader_module, module, _module);
77
78 if (!module)
79 return;
80
81 vk_free2(&device->alloc, pAllocator, module);
82 }
83
84 #define SPIR_V_MAGIC_NUMBER 0x07230203
85
86 static const uint64_t stage_to_debug[] = {
87 [MESA_SHADER_VERTEX] = DEBUG_VS,
88 [MESA_SHADER_TESS_CTRL] = DEBUG_TCS,
89 [MESA_SHADER_TESS_EVAL] = DEBUG_TES,
90 [MESA_SHADER_GEOMETRY] = DEBUG_GS,
91 [MESA_SHADER_FRAGMENT] = DEBUG_WM,
92 [MESA_SHADER_COMPUTE] = DEBUG_CS,
93 };
94
95 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
96 * we can't do that yet because we don't have the ability to copy nir.
97 */
98 static nir_shader *
99 anv_shader_compile_to_nir(struct anv_pipeline *pipeline,
100 void *mem_ctx,
101 struct anv_shader_module *module,
102 const char *entrypoint_name,
103 gl_shader_stage stage,
104 const VkSpecializationInfo *spec_info)
105 {
106 const struct anv_device *device = pipeline->device;
107
108 const struct brw_compiler *compiler =
109 device->instance->physicalDevice.compiler;
110 const nir_shader_compiler_options *nir_options =
111 compiler->glsl_compiler_options[stage].NirOptions;
112
113 uint32_t *spirv = (uint32_t *) module->data;
114 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
115 assert(module->size % 4 == 0);
116
117 uint32_t num_spec_entries = 0;
118 struct nir_spirv_specialization *spec_entries = NULL;
119 if (spec_info && spec_info->mapEntryCount > 0) {
120 num_spec_entries = spec_info->mapEntryCount;
121 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
122 for (uint32_t i = 0; i < num_spec_entries; i++) {
123 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
124 const void *data = spec_info->pData + entry.offset;
125 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
126
127 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
128 if (spec_info->dataSize == 8)
129 spec_entries[i].data64 = *(const uint64_t *)data;
130 else
131 spec_entries[i].data32 = *(const uint32_t *)data;
132 }
133 }
134
135 struct spirv_to_nir_options spirv_options = {
136 .lower_workgroup_access_to_offsets = true,
137 .caps = {
138 .float64 = device->instance->physicalDevice.info.gen >= 8,
139 .int64 = device->instance->physicalDevice.info.gen >= 8,
140 .tessellation = true,
141 .device_group = true,
142 .draw_parameters = true,
143 .image_write_without_format = true,
144 .multiview = true,
145 .variable_pointers = true,
146 .storage_16bit = device->instance->physicalDevice.info.gen >= 8,
147 .subgroup_arithmetic = true,
148 .subgroup_basic = true,
149 .subgroup_ballot = true,
150 .subgroup_quad = true,
151 .subgroup_shuffle = true,
152 .subgroup_vote = true,
153 },
154 };
155
156 nir_function *entry_point =
157 spirv_to_nir(spirv, module->size / 4,
158 spec_entries, num_spec_entries,
159 stage, entrypoint_name, &spirv_options, nir_options);
160 nir_shader *nir = entry_point->shader;
161 assert(nir->info.stage == stage);
162 nir_validate_shader(nir);
163 ralloc_steal(mem_ctx, nir);
164
165 free(spec_entries);
166
167 if (unlikely(INTEL_DEBUG & stage_to_debug[stage])) {
168 fprintf(stderr, "NIR (from SPIR-V) for %s shader:\n",
169 gl_shader_stage_name(stage));
170 nir_print_shader(nir, stderr);
171 }
172
173 /* We have to lower away local constant initializers right before we
174 * inline functions. That way they get properly initialized at the top
175 * of the function and not at the top of its caller.
176 */
177 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
178 NIR_PASS_V(nir, nir_lower_returns);
179 NIR_PASS_V(nir, nir_inline_functions);
180
181 /* Pick off the single entrypoint that we want */
182 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
183 if (func != entry_point)
184 exec_node_remove(&func->node);
185 }
186 assert(exec_list_length(&nir->functions) == 1);
187 entry_point->name = ralloc_strdup(entry_point, "main");
188
189 /* Now that we've deleted all but the main function, we can go ahead and
190 * lower the rest of the constant initializers. We do this here so that
191 * nir_remove_dead_variables and split_per_member_structs below see the
192 * corresponding stores.
193 */
194 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
195
196 NIR_PASS_V(nir, nir_remove_dead_variables,
197 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
198
199 if (stage == MESA_SHADER_FRAGMENT)
200 NIR_PASS_V(nir, nir_lower_wpos_center, pipeline->sample_shading_enable);
201
202 NIR_PASS_V(nir, nir_propagate_invariant);
203 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
204 entry_point->impl, true, false);
205
206 /* Vulkan uses the separate-shader linking model */
207 nir->info.separate_shader = true;
208
209 nir = brw_preprocess_nir(compiler, nir);
210
211 if (stage == MESA_SHADER_FRAGMENT)
212 NIR_PASS_V(nir, anv_nir_lower_input_attachments);
213
214 return nir;
215 }
216
217 void anv_DestroyPipeline(
218 VkDevice _device,
219 VkPipeline _pipeline,
220 const VkAllocationCallbacks* pAllocator)
221 {
222 ANV_FROM_HANDLE(anv_device, device, _device);
223 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
224
225 if (!pipeline)
226 return;
227
228 anv_reloc_list_finish(&pipeline->batch_relocs,
229 pAllocator ? pAllocator : &device->alloc);
230 if (pipeline->blend_state.map)
231 anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
232
233 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
234 if (pipeline->shaders[s])
235 anv_shader_bin_unref(device, pipeline->shaders[s]);
236 }
237
238 vk_free2(&device->alloc, pAllocator, pipeline);
239 }
240
241 static const uint32_t vk_to_gen_primitive_type[] = {
242 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
243 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
244 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
245 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
246 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
247 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
248 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
249 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
250 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
251 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
252 };
253
254 static void
255 populate_sampler_prog_key(const struct gen_device_info *devinfo,
256 struct brw_sampler_prog_key_data *key)
257 {
258 /* Almost all multisampled textures are compressed. The only time when we
259 * don't compress a multisampled texture is for 16x MSAA with a surface
260 * width greater than 8k which is a bit of an edge case. Since the sampler
261 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
262 * to tell the compiler to always assume compression.
263 */
264 key->compressed_multisample_layout_mask = ~0;
265
266 /* SkyLake added support for 16x MSAA. With this came a new message for
267 * reading from a 16x MSAA surface with compression. The new message was
268 * needed because now the MCS data is 64 bits instead of 32 or lower as is
269 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
270 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
271 * so we can just use it unconditionally. This may not be quite as
272 * efficient but it saves us from recompiling.
273 */
274 if (devinfo->gen >= 9)
275 key->msaa_16 = ~0;
276
277 /* XXX: Handle texture swizzle on HSW- */
278 for (int i = 0; i < MAX_SAMPLERS; i++) {
279 /* Assume color sampler, no swizzling. (Works for BDW+) */
280 key->swizzles[i] = SWIZZLE_XYZW;
281 }
282 }
283
284 static void
285 populate_vs_prog_key(const struct gen_device_info *devinfo,
286 struct brw_vs_prog_key *key)
287 {
288 memset(key, 0, sizeof(*key));
289
290 populate_sampler_prog_key(devinfo, &key->tex);
291
292 /* XXX: Handle vertex input work-arounds */
293
294 /* XXX: Handle sampler_prog_key */
295 }
296
297 static void
298 populate_gs_prog_key(const struct gen_device_info *devinfo,
299 struct brw_gs_prog_key *key)
300 {
301 memset(key, 0, sizeof(*key));
302
303 populate_sampler_prog_key(devinfo, &key->tex);
304 }
305
306 static void
307 populate_wm_prog_key(const struct anv_pipeline *pipeline,
308 const VkGraphicsPipelineCreateInfo *info,
309 struct brw_wm_prog_key *key)
310 {
311 const struct gen_device_info *devinfo = &pipeline->device->info;
312
313 memset(key, 0, sizeof(*key));
314
315 populate_sampler_prog_key(devinfo, &key->tex);
316
317 /* TODO: we could set this to 0 based on the information in nir_shader, but
318 * this function is called before spirv_to_nir. */
319 const struct brw_vue_map *vue_map =
320 &anv_pipeline_get_last_vue_prog_data(pipeline)->vue_map;
321 key->input_slots_valid = vue_map->slots_valid;
322
323 /* Vulkan doesn't specify a default */
324 key->high_quality_derivatives = false;
325
326 /* XXX Vulkan doesn't appear to specify */
327 key->clamp_fragment_color = false;
328
329 key->nr_color_regions = pipeline->subpass->color_count;
330
331 key->replicate_alpha = key->nr_color_regions > 1 &&
332 info->pMultisampleState &&
333 info->pMultisampleState->alphaToCoverageEnable;
334
335 if (info->pMultisampleState) {
336 /* We should probably pull this out of the shader, but it's fairly
337 * harmless to compute it and then let dead-code take care of it.
338 */
339 if (info->pMultisampleState->rasterizationSamples > 1) {
340 key->persample_interp =
341 (info->pMultisampleState->minSampleShading *
342 info->pMultisampleState->rasterizationSamples) > 1;
343 key->multisample_fbo = true;
344 }
345
346 key->frag_coord_adds_sample_pos =
347 info->pMultisampleState->sampleShadingEnable;
348 }
349 }
350
351 static void
352 populate_cs_prog_key(const struct gen_device_info *devinfo,
353 struct brw_cs_prog_key *key)
354 {
355 memset(key, 0, sizeof(*key));
356
357 populate_sampler_prog_key(devinfo, &key->tex);
358 }
359
360 static void
361 anv_pipeline_hash_shader(struct anv_pipeline *pipeline,
362 struct anv_pipeline_layout *layout,
363 struct anv_shader_module *module,
364 const char *entrypoint,
365 gl_shader_stage stage,
366 const VkSpecializationInfo *spec_info,
367 const void *key, size_t key_size,
368 unsigned char *sha1_out)
369 {
370 struct mesa_sha1 ctx;
371
372 _mesa_sha1_init(&ctx);
373 if (stage != MESA_SHADER_COMPUTE) {
374 _mesa_sha1_update(&ctx, &pipeline->subpass->view_mask,
375 sizeof(pipeline->subpass->view_mask));
376 }
377 if (layout)
378 _mesa_sha1_update(&ctx, layout->sha1, sizeof(layout->sha1));
379 _mesa_sha1_update(&ctx, module->sha1, sizeof(module->sha1));
380 _mesa_sha1_update(&ctx, entrypoint, strlen(entrypoint));
381 _mesa_sha1_update(&ctx, &stage, sizeof(stage));
382 if (spec_info) {
383 _mesa_sha1_update(&ctx, spec_info->pMapEntries,
384 spec_info->mapEntryCount * sizeof(*spec_info->pMapEntries));
385 _mesa_sha1_update(&ctx, spec_info->pData, spec_info->dataSize);
386 }
387 _mesa_sha1_update(&ctx, key, key_size);
388 _mesa_sha1_final(&ctx, sha1_out);
389 }
390
391 static nir_shader *
392 anv_pipeline_compile(struct anv_pipeline *pipeline,
393 void *mem_ctx,
394 struct anv_pipeline_layout *layout,
395 struct anv_shader_module *module,
396 const char *entrypoint,
397 gl_shader_stage stage,
398 const VkSpecializationInfo *spec_info,
399 struct brw_stage_prog_data *prog_data,
400 struct anv_pipeline_bind_map *map)
401 {
402 const struct brw_compiler *compiler =
403 pipeline->device->instance->physicalDevice.compiler;
404
405 nir_shader *nir = anv_shader_compile_to_nir(pipeline, mem_ctx,
406 module, entrypoint, stage,
407 spec_info);
408 if (nir == NULL)
409 return NULL;
410
411 NIR_PASS_V(nir, anv_nir_lower_ycbcr_textures, layout);
412
413 NIR_PASS_V(nir, anv_nir_lower_push_constants);
414
415 if (stage != MESA_SHADER_COMPUTE)
416 NIR_PASS_V(nir, anv_nir_lower_multiview, pipeline->subpass->view_mask);
417
418 if (stage == MESA_SHADER_COMPUTE)
419 prog_data->total_shared = nir->num_shared;
420
421 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
422
423 if (nir->num_uniforms > 0) {
424 assert(prog_data->nr_params == 0);
425
426 /* If the shader uses any push constants at all, we'll just give
427 * them the maximum possible number
428 */
429 assert(nir->num_uniforms <= MAX_PUSH_CONSTANTS_SIZE);
430 nir->num_uniforms = MAX_PUSH_CONSTANTS_SIZE;
431 prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
432 prog_data->param = ralloc_array(mem_ctx, uint32_t, prog_data->nr_params);
433
434 /* We now set the param values to be offsets into a
435 * anv_push_constant_data structure. Since the compiler doesn't
436 * actually dereference any of the gl_constant_value pointers in the
437 * params array, it doesn't really matter what we put here.
438 */
439 struct anv_push_constants *null_data = NULL;
440 /* Fill out the push constants section of the param array */
441 for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++) {
442 prog_data->param[i] = ANV_PARAM_PUSH(
443 (uintptr_t)&null_data->client_data[i * sizeof(float)]);
444 }
445 }
446
447 if (nir->info.num_ssbos > 0 || nir->info.num_images > 0)
448 pipeline->needs_data_cache = true;
449
450 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
451 if (layout)
452 anv_nir_apply_pipeline_layout(pipeline, layout, nir, prog_data, map);
453
454 if (stage != MESA_SHADER_COMPUTE)
455 brw_nir_analyze_ubo_ranges(compiler, nir, prog_data->ubo_ranges);
456
457 assert(nir->num_uniforms == prog_data->nr_params * 4);
458
459 return nir;
460 }
461
462 static void
463 anv_fill_binding_table(struct brw_stage_prog_data *prog_data, unsigned bias)
464 {
465 prog_data->binding_table.size_bytes = 0;
466 prog_data->binding_table.texture_start = bias;
467 prog_data->binding_table.gather_texture_start = bias;
468 prog_data->binding_table.ubo_start = bias;
469 prog_data->binding_table.ssbo_start = bias;
470 prog_data->binding_table.image_start = bias;
471 }
472
473 static struct anv_shader_bin *
474 anv_pipeline_upload_kernel(struct anv_pipeline *pipeline,
475 struct anv_pipeline_cache *cache,
476 const void *key_data, uint32_t key_size,
477 const void *kernel_data, uint32_t kernel_size,
478 const struct brw_stage_prog_data *prog_data,
479 uint32_t prog_data_size,
480 const struct anv_pipeline_bind_map *bind_map)
481 {
482 if (cache) {
483 return anv_pipeline_cache_upload_kernel(cache, key_data, key_size,
484 kernel_data, kernel_size,
485 prog_data, prog_data_size,
486 bind_map);
487 } else {
488 return anv_shader_bin_create(pipeline->device, key_data, key_size,
489 kernel_data, kernel_size,
490 prog_data, prog_data_size,
491 prog_data->param, bind_map);
492 }
493 }
494
495
496 static void
497 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
498 gl_shader_stage stage,
499 struct anv_shader_bin *shader)
500 {
501 pipeline->shaders[stage] = shader;
502 }
503
504 static VkResult
505 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
506 struct anv_pipeline_cache *cache,
507 const VkGraphicsPipelineCreateInfo *info,
508 struct anv_shader_module *module,
509 const char *entrypoint,
510 const VkSpecializationInfo *spec_info)
511 {
512 const struct brw_compiler *compiler =
513 pipeline->device->instance->physicalDevice.compiler;
514 struct brw_vs_prog_key key;
515 struct anv_shader_bin *bin = NULL;
516 unsigned char sha1[20];
517
518 populate_vs_prog_key(&pipeline->device->info, &key);
519
520 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
521
522 if (cache) {
523 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
524 MESA_SHADER_VERTEX, spec_info,
525 &key, sizeof(key), sha1);
526 bin = anv_pipeline_cache_search(cache, sha1, 20);
527 }
528
529 if (bin == NULL) {
530 struct brw_vs_prog_data prog_data = {};
531 struct anv_pipeline_binding surface_to_descriptor[256];
532 struct anv_pipeline_binding sampler_to_descriptor[256];
533
534 struct anv_pipeline_bind_map map = {
535 .surface_to_descriptor = surface_to_descriptor,
536 .sampler_to_descriptor = sampler_to_descriptor
537 };
538
539 void *mem_ctx = ralloc_context(NULL);
540
541 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
542 module, entrypoint,
543 MESA_SHADER_VERTEX, spec_info,
544 &prog_data.base.base, &map);
545 if (nir == NULL) {
546 ralloc_free(mem_ctx);
547 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
548 }
549
550 anv_fill_binding_table(&prog_data.base.base, 0);
551
552 brw_compute_vue_map(&pipeline->device->info,
553 &prog_data.base.vue_map,
554 nir->info.outputs_written,
555 nir->info.separate_shader);
556
557 const unsigned *shader_code =
558 brw_compile_vs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
559 -1, NULL);
560 if (shader_code == NULL) {
561 ralloc_free(mem_ctx);
562 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
563 }
564
565 unsigned code_size = prog_data.base.base.program_size;
566 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
567 shader_code, code_size,
568 &prog_data.base.base, sizeof(prog_data),
569 &map);
570 if (!bin) {
571 ralloc_free(mem_ctx);
572 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
573 }
574
575 ralloc_free(mem_ctx);
576 }
577
578 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX, bin);
579
580 return VK_SUCCESS;
581 }
582
583 static void
584 merge_tess_info(struct shader_info *tes_info,
585 const struct shader_info *tcs_info)
586 {
587 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
588 *
589 * "PointMode. Controls generation of points rather than triangles
590 * or lines. This functionality defaults to disabled, and is
591 * enabled if either shader stage includes the execution mode.
592 *
593 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
594 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
595 * and OutputVertices, it says:
596 *
597 * "One mode must be set in at least one of the tessellation
598 * shader stages."
599 *
600 * So, the fields can be set in either the TCS or TES, but they must
601 * agree if set in both. Our backend looks at TES, so bitwise-or in
602 * the values from the TCS.
603 */
604 assert(tcs_info->tess.tcs_vertices_out == 0 ||
605 tes_info->tess.tcs_vertices_out == 0 ||
606 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
607 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
608
609 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
610 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
611 tcs_info->tess.spacing == tes_info->tess.spacing);
612 tes_info->tess.spacing |= tcs_info->tess.spacing;
613
614 assert(tcs_info->tess.primitive_mode == 0 ||
615 tes_info->tess.primitive_mode == 0 ||
616 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
617 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
618 tes_info->tess.ccw |= tcs_info->tess.ccw;
619 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
620 }
621
622 static VkResult
623 anv_pipeline_compile_tcs_tes(struct anv_pipeline *pipeline,
624 struct anv_pipeline_cache *cache,
625 const VkGraphicsPipelineCreateInfo *info,
626 struct anv_shader_module *tcs_module,
627 const char *tcs_entrypoint,
628 const VkSpecializationInfo *tcs_spec_info,
629 struct anv_shader_module *tes_module,
630 const char *tes_entrypoint,
631 const VkSpecializationInfo *tes_spec_info)
632 {
633 const struct gen_device_info *devinfo = &pipeline->device->info;
634 const struct brw_compiler *compiler =
635 pipeline->device->instance->physicalDevice.compiler;
636 struct brw_tcs_prog_key tcs_key = {};
637 struct brw_tes_prog_key tes_key = {};
638 struct anv_shader_bin *tcs_bin = NULL;
639 struct anv_shader_bin *tes_bin = NULL;
640 unsigned char tcs_sha1[40];
641 unsigned char tes_sha1[40];
642
643 populate_sampler_prog_key(&pipeline->device->info, &tcs_key.tex);
644 populate_sampler_prog_key(&pipeline->device->info, &tes_key.tex);
645 tcs_key.input_vertices = info->pTessellationState->patchControlPoints;
646
647 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
648
649 if (cache) {
650 anv_pipeline_hash_shader(pipeline, layout, tcs_module, tcs_entrypoint,
651 MESA_SHADER_TESS_CTRL, tcs_spec_info,
652 &tcs_key, sizeof(tcs_key), tcs_sha1);
653 anv_pipeline_hash_shader(pipeline, layout, tes_module, tes_entrypoint,
654 MESA_SHADER_TESS_EVAL, tes_spec_info,
655 &tes_key, sizeof(tes_key), tes_sha1);
656 memcpy(&tcs_sha1[20], tes_sha1, 20);
657 memcpy(&tes_sha1[20], tcs_sha1, 20);
658 tcs_bin = anv_pipeline_cache_search(cache, tcs_sha1, sizeof(tcs_sha1));
659 tes_bin = anv_pipeline_cache_search(cache, tes_sha1, sizeof(tes_sha1));
660 }
661
662 if (tcs_bin == NULL || tes_bin == NULL) {
663 struct brw_tcs_prog_data tcs_prog_data = {};
664 struct brw_tes_prog_data tes_prog_data = {};
665 struct anv_pipeline_binding tcs_surface_to_descriptor[256];
666 struct anv_pipeline_binding tcs_sampler_to_descriptor[256];
667 struct anv_pipeline_binding tes_surface_to_descriptor[256];
668 struct anv_pipeline_binding tes_sampler_to_descriptor[256];
669
670 struct anv_pipeline_bind_map tcs_map = {
671 .surface_to_descriptor = tcs_surface_to_descriptor,
672 .sampler_to_descriptor = tcs_sampler_to_descriptor
673 };
674 struct anv_pipeline_bind_map tes_map = {
675 .surface_to_descriptor = tes_surface_to_descriptor,
676 .sampler_to_descriptor = tes_sampler_to_descriptor
677 };
678
679 void *mem_ctx = ralloc_context(NULL);
680
681 nir_shader *tcs_nir =
682 anv_pipeline_compile(pipeline, mem_ctx, layout,
683 tcs_module, tcs_entrypoint,
684 MESA_SHADER_TESS_CTRL, tcs_spec_info,
685 &tcs_prog_data.base.base, &tcs_map);
686 nir_shader *tes_nir =
687 anv_pipeline_compile(pipeline, mem_ctx, layout,
688 tes_module, tes_entrypoint,
689 MESA_SHADER_TESS_EVAL, tes_spec_info,
690 &tes_prog_data.base.base, &tes_map);
691 if (tcs_nir == NULL || tes_nir == NULL) {
692 ralloc_free(mem_ctx);
693 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
694 }
695
696 nir_lower_tes_patch_vertices(tes_nir,
697 tcs_nir->info.tess.tcs_vertices_out);
698
699 /* Copy TCS info into the TES info */
700 merge_tess_info(&tes_nir->info, &tcs_nir->info);
701
702 anv_fill_binding_table(&tcs_prog_data.base.base, 0);
703 anv_fill_binding_table(&tes_prog_data.base.base, 0);
704
705 /* Whacking the key after cache lookup is a bit sketchy, but all of
706 * this comes from the SPIR-V, which is part of the hash used for the
707 * pipeline cache. So it should be safe.
708 */
709 tcs_key.tes_primitive_mode = tes_nir->info.tess.primitive_mode;
710 tcs_key.outputs_written = tcs_nir->info.outputs_written;
711 tcs_key.patch_outputs_written = tcs_nir->info.patch_outputs_written;
712 tcs_key.quads_workaround =
713 devinfo->gen < 9 &&
714 tes_nir->info.tess.primitive_mode == 7 /* GL_QUADS */ &&
715 tes_nir->info.tess.spacing == TESS_SPACING_EQUAL;
716
717 tes_key.inputs_read = tcs_key.outputs_written;
718 tes_key.patch_inputs_read = tcs_key.patch_outputs_written;
719
720 const int shader_time_index = -1;
721 const unsigned *shader_code;
722
723 shader_code =
724 brw_compile_tcs(compiler, NULL, mem_ctx, &tcs_key, &tcs_prog_data,
725 tcs_nir, shader_time_index, NULL);
726 if (shader_code == NULL) {
727 ralloc_free(mem_ctx);
728 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
729 }
730
731 unsigned code_size = tcs_prog_data.base.base.program_size;
732 tcs_bin = anv_pipeline_upload_kernel(pipeline, cache,
733 tcs_sha1, sizeof(tcs_sha1),
734 shader_code, code_size,
735 &tcs_prog_data.base.base,
736 sizeof(tcs_prog_data),
737 &tcs_map);
738 if (!tcs_bin) {
739 ralloc_free(mem_ctx);
740 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
741 }
742
743 shader_code =
744 brw_compile_tes(compiler, NULL, mem_ctx, &tes_key,
745 &tcs_prog_data.base.vue_map, &tes_prog_data, tes_nir,
746 NULL, shader_time_index, NULL);
747 if (shader_code == NULL) {
748 ralloc_free(mem_ctx);
749 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
750 }
751
752 code_size = tes_prog_data.base.base.program_size;
753 tes_bin = anv_pipeline_upload_kernel(pipeline, cache,
754 tes_sha1, sizeof(tes_sha1),
755 shader_code, code_size,
756 &tes_prog_data.base.base,
757 sizeof(tes_prog_data),
758 &tes_map);
759 if (!tes_bin) {
760 ralloc_free(mem_ctx);
761 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
762 }
763
764 ralloc_free(mem_ctx);
765 }
766
767 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_TESS_CTRL, tcs_bin);
768 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_TESS_EVAL, tes_bin);
769
770 return VK_SUCCESS;
771 }
772
773 static VkResult
774 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
775 struct anv_pipeline_cache *cache,
776 const VkGraphicsPipelineCreateInfo *info,
777 struct anv_shader_module *module,
778 const char *entrypoint,
779 const VkSpecializationInfo *spec_info)
780 {
781 const struct brw_compiler *compiler =
782 pipeline->device->instance->physicalDevice.compiler;
783 struct brw_gs_prog_key key;
784 struct anv_shader_bin *bin = NULL;
785 unsigned char sha1[20];
786
787 populate_gs_prog_key(&pipeline->device->info, &key);
788
789 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
790
791 if (cache) {
792 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
793 MESA_SHADER_GEOMETRY, spec_info,
794 &key, sizeof(key), sha1);
795 bin = anv_pipeline_cache_search(cache, sha1, 20);
796 }
797
798 if (bin == NULL) {
799 struct brw_gs_prog_data prog_data = {};
800 struct anv_pipeline_binding surface_to_descriptor[256];
801 struct anv_pipeline_binding sampler_to_descriptor[256];
802
803 struct anv_pipeline_bind_map map = {
804 .surface_to_descriptor = surface_to_descriptor,
805 .sampler_to_descriptor = sampler_to_descriptor
806 };
807
808 void *mem_ctx = ralloc_context(NULL);
809
810 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
811 module, entrypoint,
812 MESA_SHADER_GEOMETRY, spec_info,
813 &prog_data.base.base, &map);
814 if (nir == NULL) {
815 ralloc_free(mem_ctx);
816 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
817 }
818
819 anv_fill_binding_table(&prog_data.base.base, 0);
820
821 brw_compute_vue_map(&pipeline->device->info,
822 &prog_data.base.vue_map,
823 nir->info.outputs_written,
824 nir->info.separate_shader);
825
826 const unsigned *shader_code =
827 brw_compile_gs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
828 NULL, -1, NULL);
829 if (shader_code == NULL) {
830 ralloc_free(mem_ctx);
831 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
832 }
833
834 /* TODO: SIMD8 GS */
835 const unsigned code_size = prog_data.base.base.program_size;
836 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
837 shader_code, code_size,
838 &prog_data.base.base, sizeof(prog_data),
839 &map);
840 if (!bin) {
841 ralloc_free(mem_ctx);
842 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
843 }
844
845 ralloc_free(mem_ctx);
846 }
847
848 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY, bin);
849
850 return VK_SUCCESS;
851 }
852
853 static VkResult
854 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
855 struct anv_pipeline_cache *cache,
856 const VkGraphicsPipelineCreateInfo *info,
857 struct anv_shader_module *module,
858 const char *entrypoint,
859 const VkSpecializationInfo *spec_info)
860 {
861 const struct brw_compiler *compiler =
862 pipeline->device->instance->physicalDevice.compiler;
863 struct brw_wm_prog_key key;
864 struct anv_shader_bin *bin = NULL;
865 unsigned char sha1[20];
866
867 populate_wm_prog_key(pipeline, info, &key);
868
869 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
870
871 if (cache) {
872 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
873 MESA_SHADER_FRAGMENT, spec_info,
874 &key, sizeof(key), sha1);
875 bin = anv_pipeline_cache_search(cache, sha1, 20);
876 }
877
878 if (bin == NULL) {
879 struct brw_wm_prog_data prog_data = {};
880 struct anv_pipeline_binding surface_to_descriptor[256];
881 struct anv_pipeline_binding sampler_to_descriptor[256];
882
883 struct anv_pipeline_bind_map map = {
884 .surface_to_descriptor = surface_to_descriptor + 8,
885 .sampler_to_descriptor = sampler_to_descriptor
886 };
887
888 void *mem_ctx = ralloc_context(NULL);
889
890 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
891 module, entrypoint,
892 MESA_SHADER_FRAGMENT, spec_info,
893 &prog_data.base, &map);
894 if (nir == NULL) {
895 ralloc_free(mem_ctx);
896 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
897 }
898
899 unsigned num_rts = 0;
900 const int max_rt = FRAG_RESULT_DATA7 - FRAG_RESULT_DATA0 + 1;
901 struct anv_pipeline_binding rt_bindings[max_rt];
902 nir_function_impl *impl = nir_shader_get_entrypoint(nir);
903 int rt_to_bindings[max_rt];
904 memset(rt_to_bindings, -1, sizeof(rt_to_bindings));
905 bool rt_used[max_rt];
906 memset(rt_used, 0, sizeof(rt_used));
907
908 /* Flag used render targets */
909 nir_foreach_variable_safe(var, &nir->outputs) {
910 if (var->data.location < FRAG_RESULT_DATA0)
911 continue;
912
913 const unsigned rt = var->data.location - FRAG_RESULT_DATA0;
914 /* Out-of-bounds */
915 if (rt >= key.nr_color_regions)
916 continue;
917
918 const unsigned array_len =
919 glsl_type_is_array(var->type) ? glsl_get_length(var->type) : 1;
920 assert(rt + array_len <= max_rt);
921
922 for (unsigned i = 0; i < array_len; i++)
923 rt_used[rt + i] = true;
924 }
925
926 /* Set new, compacted, location */
927 for (unsigned i = 0; i < max_rt; i++) {
928 if (!rt_used[i])
929 continue;
930
931 rt_to_bindings[i] = num_rts;
932 rt_bindings[rt_to_bindings[i]] = (struct anv_pipeline_binding) {
933 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
934 .binding = 0,
935 .index = i,
936 };
937 num_rts++;
938 }
939
940 nir_foreach_variable_safe(var, &nir->outputs) {
941 if (var->data.location < FRAG_RESULT_DATA0)
942 continue;
943
944 const unsigned rt = var->data.location - FRAG_RESULT_DATA0;
945 if (rt >= key.nr_color_regions) {
946 /* Out-of-bounds, throw it away */
947 var->data.mode = nir_var_local;
948 exec_node_remove(&var->node);
949 exec_list_push_tail(&impl->locals, &var->node);
950 continue;
951 }
952
953 /* Give it the new location */
954 assert(rt_to_bindings[rt] != -1);
955 var->data.location = rt_to_bindings[rt] + FRAG_RESULT_DATA0;
956 }
957
958 if (num_rts == 0) {
959 /* If we have no render targets, we need a null render target */
960 rt_bindings[0] = (struct anv_pipeline_binding) {
961 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
962 .binding = 0,
963 .index = UINT32_MAX,
964 };
965 num_rts = 1;
966 }
967
968 assert(num_rts <= max_rt);
969 map.surface_to_descriptor -= num_rts;
970 map.surface_count += num_rts;
971 assert(map.surface_count <= 256);
972 memcpy(map.surface_to_descriptor, rt_bindings,
973 num_rts * sizeof(*rt_bindings));
974
975 anv_fill_binding_table(&prog_data.base, num_rts);
976
977 const unsigned *shader_code =
978 brw_compile_fs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
979 NULL, -1, -1, true, false, NULL, NULL);
980 if (shader_code == NULL) {
981 ralloc_free(mem_ctx);
982 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
983 }
984
985 unsigned code_size = prog_data.base.program_size;
986 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
987 shader_code, code_size,
988 &prog_data.base, sizeof(prog_data),
989 &map);
990 if (!bin) {
991 ralloc_free(mem_ctx);
992 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
993 }
994
995 ralloc_free(mem_ctx);
996 }
997
998 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT, bin);
999
1000 return VK_SUCCESS;
1001 }
1002
1003 VkResult
1004 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
1005 struct anv_pipeline_cache *cache,
1006 const VkComputePipelineCreateInfo *info,
1007 struct anv_shader_module *module,
1008 const char *entrypoint,
1009 const VkSpecializationInfo *spec_info)
1010 {
1011 const struct brw_compiler *compiler =
1012 pipeline->device->instance->physicalDevice.compiler;
1013 struct brw_cs_prog_key key;
1014 struct anv_shader_bin *bin = NULL;
1015 unsigned char sha1[20];
1016
1017 populate_cs_prog_key(&pipeline->device->info, &key);
1018
1019 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
1020
1021 if (cache) {
1022 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
1023 MESA_SHADER_COMPUTE, spec_info,
1024 &key, sizeof(key), sha1);
1025 bin = anv_pipeline_cache_search(cache, sha1, 20);
1026 }
1027
1028 if (bin == NULL) {
1029 struct brw_cs_prog_data prog_data = {};
1030 struct anv_pipeline_binding surface_to_descriptor[256];
1031 struct anv_pipeline_binding sampler_to_descriptor[256];
1032
1033 struct anv_pipeline_bind_map map = {
1034 .surface_to_descriptor = surface_to_descriptor,
1035 .sampler_to_descriptor = sampler_to_descriptor
1036 };
1037
1038 void *mem_ctx = ralloc_context(NULL);
1039
1040 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
1041 module, entrypoint,
1042 MESA_SHADER_COMPUTE, spec_info,
1043 &prog_data.base, &map);
1044 if (nir == NULL) {
1045 ralloc_free(mem_ctx);
1046 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1047 }
1048
1049 NIR_PASS_V(nir, anv_nir_add_base_work_group_id, &prog_data);
1050
1051 anv_fill_binding_table(&prog_data.base, 1);
1052
1053 const unsigned *shader_code =
1054 brw_compile_cs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
1055 -1, NULL);
1056 if (shader_code == NULL) {
1057 ralloc_free(mem_ctx);
1058 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1059 }
1060
1061 const unsigned code_size = prog_data.base.program_size;
1062 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
1063 shader_code, code_size,
1064 &prog_data.base, sizeof(prog_data),
1065 &map);
1066 if (!bin) {
1067 ralloc_free(mem_ctx);
1068 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1069 }
1070
1071 ralloc_free(mem_ctx);
1072 }
1073
1074 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE, bin);
1075
1076 return VK_SUCCESS;
1077 }
1078
1079 /**
1080 * Copy pipeline state not marked as dynamic.
1081 * Dynamic state is pipeline state which hasn't been provided at pipeline
1082 * creation time, but is dynamically provided afterwards using various
1083 * vkCmdSet* functions.
1084 *
1085 * The set of state considered "non_dynamic" is determined by the pieces of
1086 * state that have their corresponding VkDynamicState enums omitted from
1087 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1088 *
1089 * @param[out] pipeline Destination non_dynamic state.
1090 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1091 */
1092 static void
1093 copy_non_dynamic_state(struct anv_pipeline *pipeline,
1094 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1095 {
1096 anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
1097 struct anv_subpass *subpass = pipeline->subpass;
1098
1099 pipeline->dynamic_state = default_dynamic_state;
1100
1101 if (pCreateInfo->pDynamicState) {
1102 /* Remove all of the states that are marked as dynamic */
1103 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1104 for (uint32_t s = 0; s < count; s++)
1105 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1106 }
1107
1108 struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
1109
1110 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1111 *
1112 * pViewportState is [...] NULL if the pipeline
1113 * has rasterization disabled.
1114 */
1115 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1116 assert(pCreateInfo->pViewportState);
1117
1118 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1119 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1120 typed_memcpy(dynamic->viewport.viewports,
1121 pCreateInfo->pViewportState->pViewports,
1122 pCreateInfo->pViewportState->viewportCount);
1123 }
1124
1125 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1126 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1127 typed_memcpy(dynamic->scissor.scissors,
1128 pCreateInfo->pViewportState->pScissors,
1129 pCreateInfo->pViewportState->scissorCount);
1130 }
1131 }
1132
1133 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1134 assert(pCreateInfo->pRasterizationState);
1135 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1136 }
1137
1138 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1139 assert(pCreateInfo->pRasterizationState);
1140 dynamic->depth_bias.bias =
1141 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1142 dynamic->depth_bias.clamp =
1143 pCreateInfo->pRasterizationState->depthBiasClamp;
1144 dynamic->depth_bias.slope =
1145 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1146 }
1147
1148 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1149 *
1150 * pColorBlendState is [...] NULL if the pipeline has rasterization
1151 * disabled or if the subpass of the render pass the pipeline is
1152 * created against does not use any color attachments.
1153 */
1154 bool uses_color_att = false;
1155 for (unsigned i = 0; i < subpass->color_count; ++i) {
1156 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1157 uses_color_att = true;
1158 break;
1159 }
1160 }
1161
1162 if (uses_color_att &&
1163 !pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1164 assert(pCreateInfo->pColorBlendState);
1165
1166 if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
1167 typed_memcpy(dynamic->blend_constants,
1168 pCreateInfo->pColorBlendState->blendConstants, 4);
1169 }
1170
1171 /* If there is no depthstencil attachment, then don't read
1172 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1173 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1174 * no need to override the depthstencil defaults in
1175 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1176 *
1177 * Section 9.2 of the Vulkan 1.0.15 spec says:
1178 *
1179 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1180 * disabled or if the subpass of the render pass the pipeline is created
1181 * against does not use a depth/stencil attachment.
1182 */
1183 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1184 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1185 assert(pCreateInfo->pDepthStencilState);
1186
1187 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1188 dynamic->depth_bounds.min =
1189 pCreateInfo->pDepthStencilState->minDepthBounds;
1190 dynamic->depth_bounds.max =
1191 pCreateInfo->pDepthStencilState->maxDepthBounds;
1192 }
1193
1194 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1195 dynamic->stencil_compare_mask.front =
1196 pCreateInfo->pDepthStencilState->front.compareMask;
1197 dynamic->stencil_compare_mask.back =
1198 pCreateInfo->pDepthStencilState->back.compareMask;
1199 }
1200
1201 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1202 dynamic->stencil_write_mask.front =
1203 pCreateInfo->pDepthStencilState->front.writeMask;
1204 dynamic->stencil_write_mask.back =
1205 pCreateInfo->pDepthStencilState->back.writeMask;
1206 }
1207
1208 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1209 dynamic->stencil_reference.front =
1210 pCreateInfo->pDepthStencilState->front.reference;
1211 dynamic->stencil_reference.back =
1212 pCreateInfo->pDepthStencilState->back.reference;
1213 }
1214 }
1215
1216 pipeline->dynamic_state_mask = states;
1217 }
1218
1219 static void
1220 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
1221 {
1222 #ifdef DEBUG
1223 struct anv_render_pass *renderpass = NULL;
1224 struct anv_subpass *subpass = NULL;
1225
1226 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1227 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1228 */
1229 assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
1230
1231 renderpass = anv_render_pass_from_handle(info->renderPass);
1232 assert(renderpass);
1233
1234 assert(info->subpass < renderpass->subpass_count);
1235 subpass = &renderpass->subpasses[info->subpass];
1236
1237 assert(info->stageCount >= 1);
1238 assert(info->pVertexInputState);
1239 assert(info->pInputAssemblyState);
1240 assert(info->pRasterizationState);
1241 if (!info->pRasterizationState->rasterizerDiscardEnable) {
1242 assert(info->pViewportState);
1243 assert(info->pMultisampleState);
1244
1245 if (subpass && subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
1246 assert(info->pDepthStencilState);
1247
1248 if (subpass && subpass->color_count > 0)
1249 assert(info->pColorBlendState);
1250 }
1251
1252 for (uint32_t i = 0; i < info->stageCount; ++i) {
1253 switch (info->pStages[i].stage) {
1254 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
1255 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
1256 assert(info->pTessellationState);
1257 break;
1258 default:
1259 break;
1260 }
1261 }
1262 #endif
1263 }
1264
1265 /**
1266 * Calculate the desired L3 partitioning based on the current state of the
1267 * pipeline. For now this simply returns the conservative defaults calculated
1268 * by get_default_l3_weights(), but we could probably do better by gathering
1269 * more statistics from the pipeline state (e.g. guess of expected URB usage
1270 * and bound surfaces), or by using feed-back from performance counters.
1271 */
1272 void
1273 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm)
1274 {
1275 const struct gen_device_info *devinfo = &pipeline->device->info;
1276
1277 const struct gen_l3_weights w =
1278 gen_get_default_l3_weights(devinfo, pipeline->needs_data_cache, needs_slm);
1279
1280 pipeline->urb.l3_config = gen_get_l3_config(devinfo, w);
1281 pipeline->urb.total_size =
1282 gen_get_l3_config_urb_size(devinfo, pipeline->urb.l3_config);
1283 }
1284
1285 VkResult
1286 anv_pipeline_init(struct anv_pipeline *pipeline,
1287 struct anv_device *device,
1288 struct anv_pipeline_cache *cache,
1289 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1290 const VkAllocationCallbacks *alloc)
1291 {
1292 VkResult result;
1293
1294 anv_pipeline_validate_create_info(pCreateInfo);
1295
1296 if (alloc == NULL)
1297 alloc = &device->alloc;
1298
1299 pipeline->device = device;
1300
1301 ANV_FROM_HANDLE(anv_render_pass, render_pass, pCreateInfo->renderPass);
1302 assert(pCreateInfo->subpass < render_pass->subpass_count);
1303 pipeline->subpass = &render_pass->subpasses[pCreateInfo->subpass];
1304
1305 result = anv_reloc_list_init(&pipeline->batch_relocs, alloc);
1306 if (result != VK_SUCCESS)
1307 return result;
1308
1309 pipeline->batch.alloc = alloc;
1310 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
1311 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
1312 pipeline->batch.relocs = &pipeline->batch_relocs;
1313 pipeline->batch.status = VK_SUCCESS;
1314
1315 copy_non_dynamic_state(pipeline, pCreateInfo);
1316 pipeline->depth_clamp_enable = pCreateInfo->pRasterizationState &&
1317 pCreateInfo->pRasterizationState->depthClampEnable;
1318
1319 pipeline->sample_shading_enable = pCreateInfo->pMultisampleState &&
1320 pCreateInfo->pMultisampleState->sampleShadingEnable;
1321
1322 pipeline->needs_data_cache = false;
1323
1324 /* When we free the pipeline, we detect stages based on the NULL status
1325 * of various prog_data pointers. Make them NULL by default.
1326 */
1327 memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
1328
1329 pipeline->active_stages = 0;
1330
1331 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = {};
1332 struct anv_shader_module *modules[MESA_SHADER_STAGES] = {};
1333 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1334 VkShaderStageFlagBits vk_stage = pCreateInfo->pStages[i].stage;
1335 gl_shader_stage stage = vk_to_mesa_shader_stage(vk_stage);
1336 pStages[stage] = &pCreateInfo->pStages[i];
1337 modules[stage] = anv_shader_module_from_handle(pStages[stage]->module);
1338 pipeline->active_stages |= vk_stage;
1339 }
1340
1341 if (pipeline->active_stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT)
1342 pipeline->active_stages |= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT;
1343
1344 assert(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT);
1345
1346 if (modules[MESA_SHADER_VERTEX]) {
1347 result = anv_pipeline_compile_vs(pipeline, cache, pCreateInfo,
1348 modules[MESA_SHADER_VERTEX],
1349 pStages[MESA_SHADER_VERTEX]->pName,
1350 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo);
1351 if (result != VK_SUCCESS)
1352 goto compile_fail;
1353 }
1354
1355 if (modules[MESA_SHADER_TESS_EVAL]) {
1356 result = anv_pipeline_compile_tcs_tes(pipeline, cache, pCreateInfo,
1357 modules[MESA_SHADER_TESS_CTRL],
1358 pStages[MESA_SHADER_TESS_CTRL]->pName,
1359 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
1360 modules[MESA_SHADER_TESS_EVAL],
1361 pStages[MESA_SHADER_TESS_EVAL]->pName,
1362 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo);
1363 if (result != VK_SUCCESS)
1364 goto compile_fail;
1365 }
1366
1367 if (modules[MESA_SHADER_GEOMETRY]) {
1368 result = anv_pipeline_compile_gs(pipeline, cache, pCreateInfo,
1369 modules[MESA_SHADER_GEOMETRY],
1370 pStages[MESA_SHADER_GEOMETRY]->pName,
1371 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo);
1372 if (result != VK_SUCCESS)
1373 goto compile_fail;
1374 }
1375
1376 if (modules[MESA_SHADER_FRAGMENT]) {
1377 result = anv_pipeline_compile_fs(pipeline, cache, pCreateInfo,
1378 modules[MESA_SHADER_FRAGMENT],
1379 pStages[MESA_SHADER_FRAGMENT]->pName,
1380 pStages[MESA_SHADER_FRAGMENT]->pSpecializationInfo);
1381 if (result != VK_SUCCESS)
1382 goto compile_fail;
1383 }
1384
1385 assert(pipeline->shaders[MESA_SHADER_VERTEX]);
1386
1387 anv_pipeline_setup_l3_config(pipeline, false);
1388
1389 const VkPipelineVertexInputStateCreateInfo *vi_info =
1390 pCreateInfo->pVertexInputState;
1391
1392 const uint64_t inputs_read = get_vs_prog_data(pipeline)->inputs_read;
1393
1394 pipeline->vb_used = 0;
1395 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1396 const VkVertexInputAttributeDescription *desc =
1397 &vi_info->pVertexAttributeDescriptions[i];
1398
1399 if (inputs_read & (1ull << (VERT_ATTRIB_GENERIC0 + desc->location)))
1400 pipeline->vb_used |= 1 << desc->binding;
1401 }
1402
1403 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1404 const VkVertexInputBindingDescription *desc =
1405 &vi_info->pVertexBindingDescriptions[i];
1406
1407 pipeline->binding_stride[desc->binding] = desc->stride;
1408
1409 /* Step rate is programmed per vertex element (attribute), not
1410 * binding. Set up a map of which bindings step per instance, for
1411 * reference by vertex element setup. */
1412 switch (desc->inputRate) {
1413 default:
1414 case VK_VERTEX_INPUT_RATE_VERTEX:
1415 pipeline->instancing_enable[desc->binding] = false;
1416 break;
1417 case VK_VERTEX_INPUT_RATE_INSTANCE:
1418 pipeline->instancing_enable[desc->binding] = true;
1419 break;
1420 }
1421 }
1422
1423 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1424 pCreateInfo->pInputAssemblyState;
1425 const VkPipelineTessellationStateCreateInfo *tess_info =
1426 pCreateInfo->pTessellationState;
1427 pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1428
1429 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
1430 pipeline->topology = _3DPRIM_PATCHLIST(tess_info->patchControlPoints);
1431 else
1432 pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1433
1434 return VK_SUCCESS;
1435
1436 compile_fail:
1437 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
1438 if (pipeline->shaders[s])
1439 anv_shader_bin_unref(device, pipeline->shaders[s]);
1440 }
1441
1442 anv_reloc_list_finish(&pipeline->batch_relocs, alloc);
1443
1444 return result;
1445 }