2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "util/os_time.h"
32 #include "common/gen_l3_config.h"
33 #include "anv_private.h"
34 #include "compiler/brw_nir.h"
36 #include "nir/nir_xfb_info.h"
37 #include "spirv/nir_spirv.h"
40 /* Needed for SWIZZLE macros */
41 #include "program/prog_instruction.h"
45 VkResult
anv_CreateShaderModule(
47 const VkShaderModuleCreateInfo
* pCreateInfo
,
48 const VkAllocationCallbacks
* pAllocator
,
49 VkShaderModule
* pShaderModule
)
51 ANV_FROM_HANDLE(anv_device
, device
, _device
);
52 struct anv_shader_module
*module
;
54 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
55 assert(pCreateInfo
->flags
== 0);
57 module
= vk_alloc2(&device
->alloc
, pAllocator
,
58 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
59 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
61 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
63 module
->size
= pCreateInfo
->codeSize
;
64 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
66 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
68 *pShaderModule
= anv_shader_module_to_handle(module
);
73 void anv_DestroyShaderModule(
75 VkShaderModule _module
,
76 const VkAllocationCallbacks
* pAllocator
)
78 ANV_FROM_HANDLE(anv_device
, device
, _device
);
79 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
84 vk_free2(&device
->alloc
, pAllocator
, module
);
87 #define SPIR_V_MAGIC_NUMBER 0x07230203
89 static const uint64_t stage_to_debug
[] = {
90 [MESA_SHADER_VERTEX
] = DEBUG_VS
,
91 [MESA_SHADER_TESS_CTRL
] = DEBUG_TCS
,
92 [MESA_SHADER_TESS_EVAL
] = DEBUG_TES
,
93 [MESA_SHADER_GEOMETRY
] = DEBUG_GS
,
94 [MESA_SHADER_FRAGMENT
] = DEBUG_WM
,
95 [MESA_SHADER_COMPUTE
] = DEBUG_CS
,
98 struct anv_spirv_debug_data
{
99 struct anv_device
*device
;
100 const struct anv_shader_module
*module
;
103 static void anv_spirv_nir_debug(void *private_data
,
104 enum nir_spirv_debug_level level
,
108 struct anv_spirv_debug_data
*debug_data
= private_data
;
109 static const VkDebugReportFlagsEXT vk_flags
[] = {
110 [NIR_SPIRV_DEBUG_LEVEL_INFO
] = VK_DEBUG_REPORT_INFORMATION_BIT_EXT
,
111 [NIR_SPIRV_DEBUG_LEVEL_WARNING
] = VK_DEBUG_REPORT_WARNING_BIT_EXT
,
112 [NIR_SPIRV_DEBUG_LEVEL_ERROR
] = VK_DEBUG_REPORT_ERROR_BIT_EXT
,
116 snprintf(buffer
, sizeof(buffer
), "SPIR-V offset %lu: %s", (unsigned long) spirv_offset
, message
);
118 vk_debug_report(&debug_data
->device
->instance
->debug_report_callbacks
,
120 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT
,
121 (uint64_t) (uintptr_t) debug_data
->module
,
122 0, 0, "anv", buffer
);
125 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
126 * we can't do that yet because we don't have the ability to copy nir.
129 anv_shader_compile_to_nir(struct anv_device
*device
,
131 const struct anv_shader_module
*module
,
132 const char *entrypoint_name
,
133 gl_shader_stage stage
,
134 const VkSpecializationInfo
*spec_info
)
136 const struct anv_physical_device
*pdevice
=
137 &device
->instance
->physicalDevice
;
138 const struct brw_compiler
*compiler
= pdevice
->compiler
;
139 const nir_shader_compiler_options
*nir_options
=
140 compiler
->glsl_compiler_options
[stage
].NirOptions
;
142 uint32_t *spirv
= (uint32_t *) module
->data
;
143 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
144 assert(module
->size
% 4 == 0);
146 uint32_t num_spec_entries
= 0;
147 struct nir_spirv_specialization
*spec_entries
= NULL
;
148 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
149 num_spec_entries
= spec_info
->mapEntryCount
;
150 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
151 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
152 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
153 const void *data
= spec_info
->pData
+ entry
.offset
;
154 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
156 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
157 if (spec_info
->dataSize
== 8)
158 spec_entries
[i
].data64
= *(const uint64_t *)data
;
160 spec_entries
[i
].data32
= *(const uint32_t *)data
;
164 struct anv_spirv_debug_data spirv_debug_data
= {
168 struct spirv_to_nir_options spirv_options
= {
169 .lower_workgroup_access_to_offsets
= true,
171 .demote_to_helper_invocation
= true,
172 .derivative_group
= true,
173 .descriptor_array_dynamic_indexing
= true,
174 .descriptor_array_non_uniform_indexing
= true,
175 .descriptor_indexing
= true,
176 .device_group
= true,
177 .draw_parameters
= true,
178 .float16
= pdevice
->info
.gen
>= 8,
179 .float64
= pdevice
->info
.gen
>= 8,
180 .fragment_shader_sample_interlock
= pdevice
->info
.gen
>= 9,
181 .fragment_shader_pixel_interlock
= pdevice
->info
.gen
>= 9,
182 .geometry_streams
= true,
183 .image_write_without_format
= true,
184 .int8
= pdevice
->info
.gen
>= 8,
185 .int16
= pdevice
->info
.gen
>= 8,
186 .int64
= pdevice
->info
.gen
>= 8,
187 .int64_atomics
= pdevice
->info
.gen
>= 9 && pdevice
->use_softpin
,
190 .physical_storage_buffer_address
= pdevice
->has_a64_buffer_access
,
191 .post_depth_coverage
= pdevice
->info
.gen
>= 9,
192 .runtime_descriptor_array
= true,
193 .shader_viewport_index_layer
= true,
194 .stencil_export
= pdevice
->info
.gen
>= 9,
195 .storage_8bit
= pdevice
->info
.gen
>= 8,
196 .storage_16bit
= pdevice
->info
.gen
>= 8,
197 .subgroup_arithmetic
= true,
198 .subgroup_basic
= true,
199 .subgroup_ballot
= true,
200 .subgroup_quad
= true,
201 .subgroup_shuffle
= true,
202 .subgroup_vote
= true,
203 .tessellation
= true,
204 .transform_feedback
= pdevice
->info
.gen
>= 8,
205 .variable_pointers
= true,
207 .ubo_addr_format
= nir_address_format_32bit_index_offset
,
209 anv_nir_ssbo_addr_format(pdevice
, device
->robust_buffer_access
),
210 .phys_ssbo_addr_format
= nir_address_format_64bit_global
,
211 .push_const_addr_format
= nir_address_format_logical
,
213 /* TODO: Consider changing this to an address format that has the NULL
214 * pointer equals to 0. That might be a better format to play nice
215 * with certain code / code generators.
217 .shared_addr_format
= nir_address_format_32bit_offset
,
219 .func
= anv_spirv_nir_debug
,
220 .private_data
= &spirv_debug_data
,
226 spirv_to_nir(spirv
, module
->size
/ 4,
227 spec_entries
, num_spec_entries
,
228 stage
, entrypoint_name
, &spirv_options
, nir_options
);
229 assert(nir
->info
.stage
== stage
);
230 nir_validate_shader(nir
, "after spirv_to_nir");
231 ralloc_steal(mem_ctx
, nir
);
235 if (unlikely(INTEL_DEBUG
& stage_to_debug
[stage
])) {
236 fprintf(stderr
, "NIR (from SPIR-V) for %s shader:\n",
237 gl_shader_stage_name(stage
));
238 nir_print_shader(nir
, stderr
);
241 /* We have to lower away local constant initializers right before we
242 * inline functions. That way they get properly initialized at the top
243 * of the function and not at the top of its caller.
245 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_function_temp
);
246 NIR_PASS_V(nir
, nir_lower_returns
);
247 NIR_PASS_V(nir
, nir_inline_functions
);
248 NIR_PASS_V(nir
, nir_opt_deref
);
250 /* Pick off the single entrypoint that we want */
251 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
252 if (!func
->is_entrypoint
)
253 exec_node_remove(&func
->node
);
255 assert(exec_list_length(&nir
->functions
) == 1);
257 /* Now that we've deleted all but the main function, we can go ahead and
258 * lower the rest of the constant initializers. We do this here so that
259 * nir_remove_dead_variables and split_per_member_structs below see the
260 * corresponding stores.
262 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
264 /* Split member structs. We do this before lower_io_to_temporaries so that
265 * it doesn't lower system values to temporaries by accident.
267 NIR_PASS_V(nir
, nir_split_var_copies
);
268 NIR_PASS_V(nir
, nir_split_per_member_structs
);
270 NIR_PASS_V(nir
, nir_remove_dead_variables
,
271 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
273 NIR_PASS_V(nir
, nir_propagate_invariant
);
274 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
275 nir_shader_get_entrypoint(nir
), true, false);
277 NIR_PASS_V(nir
, nir_lower_frexp
);
279 /* Vulkan uses the separate-shader linking model */
280 nir
->info
.separate_shader
= true;
282 brw_preprocess_nir(compiler
, nir
, NULL
);
287 void anv_DestroyPipeline(
289 VkPipeline _pipeline
,
290 const VkAllocationCallbacks
* pAllocator
)
292 ANV_FROM_HANDLE(anv_device
, device
, _device
);
293 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
298 anv_reloc_list_finish(&pipeline
->batch_relocs
,
299 pAllocator
? pAllocator
: &device
->alloc
);
300 if (pipeline
->blend_state
.map
)
301 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
303 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
304 if (pipeline
->shaders
[s
])
305 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
308 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
311 static const uint32_t vk_to_gen_primitive_type
[] = {
312 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
313 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
314 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
315 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
316 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
317 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
318 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
319 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
320 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
321 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
325 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
326 struct brw_sampler_prog_key_data
*key
)
328 /* Almost all multisampled textures are compressed. The only time when we
329 * don't compress a multisampled texture is for 16x MSAA with a surface
330 * width greater than 8k which is a bit of an edge case. Since the sampler
331 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
332 * to tell the compiler to always assume compression.
334 key
->compressed_multisample_layout_mask
= ~0;
336 /* SkyLake added support for 16x MSAA. With this came a new message for
337 * reading from a 16x MSAA surface with compression. The new message was
338 * needed because now the MCS data is 64 bits instead of 32 or lower as is
339 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
340 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
341 * so we can just use it unconditionally. This may not be quite as
342 * efficient but it saves us from recompiling.
344 if (devinfo
->gen
>= 9)
347 /* XXX: Handle texture swizzle on HSW- */
348 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
349 /* Assume color sampler, no swizzling. (Works for BDW+) */
350 key
->swizzles
[i
] = SWIZZLE_XYZW
;
355 populate_base_prog_key(const struct gen_device_info
*devinfo
,
356 struct brw_base_prog_key
*key
)
358 key
->subgroup_size_type
= BRW_SUBGROUP_SIZE_API_CONSTANT
;
360 populate_sampler_prog_key(devinfo
, &key
->tex
);
364 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
365 struct brw_vs_prog_key
*key
)
367 memset(key
, 0, sizeof(*key
));
369 populate_base_prog_key(devinfo
, &key
->base
);
371 /* XXX: Handle vertex input work-arounds */
373 /* XXX: Handle sampler_prog_key */
377 populate_tcs_prog_key(const struct gen_device_info
*devinfo
,
378 unsigned input_vertices
,
379 struct brw_tcs_prog_key
*key
)
381 memset(key
, 0, sizeof(*key
));
383 populate_base_prog_key(devinfo
, &key
->base
);
385 key
->input_vertices
= input_vertices
;
389 populate_tes_prog_key(const struct gen_device_info
*devinfo
,
390 struct brw_tes_prog_key
*key
)
392 memset(key
, 0, sizeof(*key
));
394 populate_base_prog_key(devinfo
, &key
->base
);
398 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
399 struct brw_gs_prog_key
*key
)
401 memset(key
, 0, sizeof(*key
));
403 populate_base_prog_key(devinfo
, &key
->base
);
407 populate_wm_prog_key(const struct gen_device_info
*devinfo
,
408 const struct anv_subpass
*subpass
,
409 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
410 struct brw_wm_prog_key
*key
)
412 memset(key
, 0, sizeof(*key
));
414 populate_base_prog_key(devinfo
, &key
->base
);
416 /* We set this to 0 here and set to the actual value before we call
419 key
->input_slots_valid
= 0;
421 /* Vulkan doesn't specify a default */
422 key
->high_quality_derivatives
= false;
424 /* XXX Vulkan doesn't appear to specify */
425 key
->clamp_fragment_color
= false;
427 assert(subpass
->color_count
<= MAX_RTS
);
428 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
429 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
430 key
->color_outputs_valid
|= (1 << i
);
433 key
->nr_color_regions
= util_bitcount(key
->color_outputs_valid
);
435 /* To reduce possible shader recompilations we would need to know if
436 * there is a SampleMask output variable to compute if we should emit
437 * code to workaround the issue that hardware disables alpha to coverage
438 * when there is SampleMask output.
440 key
->alpha_to_coverage
= ms_info
&& ms_info
->alphaToCoverageEnable
;
442 /* Vulkan doesn't support fixed-function alpha test */
443 key
->alpha_test_replicate_alpha
= false;
446 /* We should probably pull this out of the shader, but it's fairly
447 * harmless to compute it and then let dead-code take care of it.
449 if (ms_info
->rasterizationSamples
> 1) {
450 key
->persample_interp
= ms_info
->sampleShadingEnable
&&
451 (ms_info
->minSampleShading
* ms_info
->rasterizationSamples
) > 1;
452 key
->multisample_fbo
= true;
455 key
->frag_coord_adds_sample_pos
= key
->persample_interp
;
460 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
461 struct brw_cs_prog_key
*key
)
463 memset(key
, 0, sizeof(*key
));
465 populate_base_prog_key(devinfo
, &key
->base
);
468 struct anv_pipeline_stage
{
469 gl_shader_stage stage
;
471 const struct anv_shader_module
*module
;
472 const char *entrypoint
;
473 const VkSpecializationInfo
*spec_info
;
475 unsigned char shader_sha1
[20];
477 union brw_any_prog_key key
;
480 gl_shader_stage stage
;
481 unsigned char sha1
[20];
486 struct anv_pipeline_binding surface_to_descriptor
[256];
487 struct anv_pipeline_binding sampler_to_descriptor
[256];
488 struct anv_pipeline_bind_map bind_map
;
490 union brw_any_prog_data prog_data
;
492 VkPipelineCreationFeedbackEXT feedback
;
496 anv_pipeline_hash_shader(const struct anv_shader_module
*module
,
497 const char *entrypoint
,
498 gl_shader_stage stage
,
499 const VkSpecializationInfo
*spec_info
,
500 unsigned char *sha1_out
)
502 struct mesa_sha1 ctx
;
503 _mesa_sha1_init(&ctx
);
505 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
506 _mesa_sha1_update(&ctx
, entrypoint
, strlen(entrypoint
));
507 _mesa_sha1_update(&ctx
, &stage
, sizeof(stage
));
509 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
510 spec_info
->mapEntryCount
*
511 sizeof(*spec_info
->pMapEntries
));
512 _mesa_sha1_update(&ctx
, spec_info
->pData
,
513 spec_info
->dataSize
);
516 _mesa_sha1_final(&ctx
, sha1_out
);
520 anv_pipeline_hash_graphics(struct anv_pipeline
*pipeline
,
521 struct anv_pipeline_layout
*layout
,
522 struct anv_pipeline_stage
*stages
,
523 unsigned char *sha1_out
)
525 struct mesa_sha1 ctx
;
526 _mesa_sha1_init(&ctx
);
528 _mesa_sha1_update(&ctx
, &pipeline
->subpass
->view_mask
,
529 sizeof(pipeline
->subpass
->view_mask
));
532 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
534 const bool rba
= pipeline
->device
->robust_buffer_access
;
535 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
537 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
538 if (stages
[s
].entrypoint
) {
539 _mesa_sha1_update(&ctx
, stages
[s
].shader_sha1
,
540 sizeof(stages
[s
].shader_sha1
));
541 _mesa_sha1_update(&ctx
, &stages
[s
].key
, brw_prog_key_size(s
));
545 _mesa_sha1_final(&ctx
, sha1_out
);
549 anv_pipeline_hash_compute(struct anv_pipeline
*pipeline
,
550 struct anv_pipeline_layout
*layout
,
551 struct anv_pipeline_stage
*stage
,
552 unsigned char *sha1_out
)
554 struct mesa_sha1 ctx
;
555 _mesa_sha1_init(&ctx
);
558 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
560 const bool rba
= pipeline
->device
->robust_buffer_access
;
561 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
563 _mesa_sha1_update(&ctx
, stage
->shader_sha1
,
564 sizeof(stage
->shader_sha1
));
565 _mesa_sha1_update(&ctx
, &stage
->key
.cs
, sizeof(stage
->key
.cs
));
567 _mesa_sha1_final(&ctx
, sha1_out
);
571 anv_pipeline_stage_get_nir(struct anv_pipeline
*pipeline
,
572 struct anv_pipeline_cache
*cache
,
574 struct anv_pipeline_stage
*stage
)
576 const struct brw_compiler
*compiler
=
577 pipeline
->device
->instance
->physicalDevice
.compiler
;
578 const nir_shader_compiler_options
*nir_options
=
579 compiler
->glsl_compiler_options
[stage
->stage
].NirOptions
;
582 nir
= anv_device_search_for_nir(pipeline
->device
, cache
,
587 assert(nir
->info
.stage
== stage
->stage
);
591 nir
= anv_shader_compile_to_nir(pipeline
->device
,
598 anv_device_upload_nir(pipeline
->device
, cache
, nir
, stage
->shader_sha1
);
606 anv_pipeline_lower_nir(struct anv_pipeline
*pipeline
,
608 struct anv_pipeline_stage
*stage
,
609 struct anv_pipeline_layout
*layout
)
611 const struct anv_physical_device
*pdevice
=
612 &pipeline
->device
->instance
->physicalDevice
;
613 const struct brw_compiler
*compiler
= pdevice
->compiler
;
615 struct brw_stage_prog_data
*prog_data
= &stage
->prog_data
.base
;
616 nir_shader
*nir
= stage
->nir
;
618 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
619 NIR_PASS_V(nir
, nir_lower_wpos_center
, pipeline
->sample_shading_enable
);
620 NIR_PASS_V(nir
, nir_lower_input_attachments
, false);
623 NIR_PASS_V(nir
, anv_nir_lower_ycbcr_textures
, layout
);
625 NIR_PASS_V(nir
, anv_nir_lower_push_constants
);
627 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
628 NIR_PASS_V(nir
, anv_nir_lower_multiview
, pipeline
->subpass
->view_mask
);
630 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
631 prog_data
->total_shared
= nir
->num_shared
;
633 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
635 if (nir
->num_uniforms
> 0) {
636 assert(prog_data
->nr_params
== 0);
638 /* If the shader uses any push constants at all, we'll just give
639 * them the maximum possible number
641 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
642 nir
->num_uniforms
= MAX_PUSH_CONSTANTS_SIZE
;
643 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
644 prog_data
->param
= ralloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
646 /* We now set the param values to be offsets into a
647 * anv_push_constant_data structure. Since the compiler doesn't
648 * actually dereference any of the gl_constant_value pointers in the
649 * params array, it doesn't really matter what we put here.
651 struct anv_push_constants
*null_data
= NULL
;
652 /* Fill out the push constants section of the param array */
653 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++) {
654 prog_data
->param
[i
] = ANV_PARAM_PUSH(
655 (uintptr_t)&null_data
->client_data
[i
* sizeof(float)]);
659 if (nir
->info
.num_ssbos
> 0 || nir
->info
.num_images
> 0)
660 pipeline
->needs_data_cache
= true;
662 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, compiler
->devinfo
);
664 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_global
,
665 nir_address_format_64bit_global
);
667 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
669 anv_nir_apply_pipeline_layout(pdevice
,
670 pipeline
->device
->robust_buffer_access
,
671 layout
, nir
, prog_data
,
674 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ubo
,
675 nir_address_format_32bit_index_offset
);
676 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ssbo
,
677 anv_nir_ssbo_addr_format(pdevice
,
678 pipeline
->device
->robust_buffer_access
));
680 NIR_PASS_V(nir
, nir_opt_constant_folding
);
682 /* We don't support non-uniform UBOs and non-uniform SSBO access is
683 * handled naturally by falling back to A64 messages.
685 NIR_PASS_V(nir
, nir_lower_non_uniform_access
,
686 nir_lower_non_uniform_texture_access
|
687 nir_lower_non_uniform_image_access
);
690 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
691 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
693 assert(nir
->num_uniforms
== prog_data
->nr_params
* 4);
699 anv_pipeline_link_vs(const struct brw_compiler
*compiler
,
700 struct anv_pipeline_stage
*vs_stage
,
701 struct anv_pipeline_stage
*next_stage
)
704 brw_nir_link_shaders(compiler
, vs_stage
->nir
, next_stage
->nir
);
707 static const unsigned *
708 anv_pipeline_compile_vs(const struct brw_compiler
*compiler
,
710 struct anv_device
*device
,
711 struct anv_pipeline_stage
*vs_stage
)
713 brw_compute_vue_map(compiler
->devinfo
,
714 &vs_stage
->prog_data
.vs
.base
.vue_map
,
715 vs_stage
->nir
->info
.outputs_written
,
716 vs_stage
->nir
->info
.separate_shader
);
718 return brw_compile_vs(compiler
, device
, mem_ctx
, &vs_stage
->key
.vs
,
719 &vs_stage
->prog_data
.vs
, vs_stage
->nir
, -1, NULL
);
723 merge_tess_info(struct shader_info
*tes_info
,
724 const struct shader_info
*tcs_info
)
726 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
728 * "PointMode. Controls generation of points rather than triangles
729 * or lines. This functionality defaults to disabled, and is
730 * enabled if either shader stage includes the execution mode.
732 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
733 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
734 * and OutputVertices, it says:
736 * "One mode must be set in at least one of the tessellation
739 * So, the fields can be set in either the TCS or TES, but they must
740 * agree if set in both. Our backend looks at TES, so bitwise-or in
741 * the values from the TCS.
743 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
744 tes_info
->tess
.tcs_vertices_out
== 0 ||
745 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
746 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
748 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
749 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
750 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
751 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
753 assert(tcs_info
->tess
.primitive_mode
== 0 ||
754 tes_info
->tess
.primitive_mode
== 0 ||
755 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
756 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
757 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
758 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
762 anv_pipeline_link_tcs(const struct brw_compiler
*compiler
,
763 struct anv_pipeline_stage
*tcs_stage
,
764 struct anv_pipeline_stage
*tes_stage
)
766 assert(tes_stage
&& tes_stage
->stage
== MESA_SHADER_TESS_EVAL
);
768 brw_nir_link_shaders(compiler
, tcs_stage
->nir
, tes_stage
->nir
);
770 nir_lower_patch_vertices(tes_stage
->nir
,
771 tcs_stage
->nir
->info
.tess
.tcs_vertices_out
,
774 /* Copy TCS info into the TES info */
775 merge_tess_info(&tes_stage
->nir
->info
, &tcs_stage
->nir
->info
);
777 /* Whacking the key after cache lookup is a bit sketchy, but all of
778 * this comes from the SPIR-V, which is part of the hash used for the
779 * pipeline cache. So it should be safe.
781 tcs_stage
->key
.tcs
.tes_primitive_mode
=
782 tes_stage
->nir
->info
.tess
.primitive_mode
;
783 tcs_stage
->key
.tcs
.quads_workaround
=
784 compiler
->devinfo
->gen
< 9 &&
785 tes_stage
->nir
->info
.tess
.primitive_mode
== 7 /* GL_QUADS */ &&
786 tes_stage
->nir
->info
.tess
.spacing
== TESS_SPACING_EQUAL
;
789 static const unsigned *
790 anv_pipeline_compile_tcs(const struct brw_compiler
*compiler
,
792 struct anv_device
*device
,
793 struct anv_pipeline_stage
*tcs_stage
,
794 struct anv_pipeline_stage
*prev_stage
)
796 tcs_stage
->key
.tcs
.outputs_written
=
797 tcs_stage
->nir
->info
.outputs_written
;
798 tcs_stage
->key
.tcs
.patch_outputs_written
=
799 tcs_stage
->nir
->info
.patch_outputs_written
;
801 return brw_compile_tcs(compiler
, device
, mem_ctx
, &tcs_stage
->key
.tcs
,
802 &tcs_stage
->prog_data
.tcs
, tcs_stage
->nir
,
807 anv_pipeline_link_tes(const struct brw_compiler
*compiler
,
808 struct anv_pipeline_stage
*tes_stage
,
809 struct anv_pipeline_stage
*next_stage
)
812 brw_nir_link_shaders(compiler
, tes_stage
->nir
, next_stage
->nir
);
815 static const unsigned *
816 anv_pipeline_compile_tes(const struct brw_compiler
*compiler
,
818 struct anv_device
*device
,
819 struct anv_pipeline_stage
*tes_stage
,
820 struct anv_pipeline_stage
*tcs_stage
)
822 tes_stage
->key
.tes
.inputs_read
=
823 tcs_stage
->nir
->info
.outputs_written
;
824 tes_stage
->key
.tes
.patch_inputs_read
=
825 tcs_stage
->nir
->info
.patch_outputs_written
;
827 return brw_compile_tes(compiler
, device
, mem_ctx
, &tes_stage
->key
.tes
,
828 &tcs_stage
->prog_data
.tcs
.base
.vue_map
,
829 &tes_stage
->prog_data
.tes
, tes_stage
->nir
,
834 anv_pipeline_link_gs(const struct brw_compiler
*compiler
,
835 struct anv_pipeline_stage
*gs_stage
,
836 struct anv_pipeline_stage
*next_stage
)
839 brw_nir_link_shaders(compiler
, gs_stage
->nir
, next_stage
->nir
);
842 static const unsigned *
843 anv_pipeline_compile_gs(const struct brw_compiler
*compiler
,
845 struct anv_device
*device
,
846 struct anv_pipeline_stage
*gs_stage
,
847 struct anv_pipeline_stage
*prev_stage
)
849 brw_compute_vue_map(compiler
->devinfo
,
850 &gs_stage
->prog_data
.gs
.base
.vue_map
,
851 gs_stage
->nir
->info
.outputs_written
,
852 gs_stage
->nir
->info
.separate_shader
);
854 return brw_compile_gs(compiler
, device
, mem_ctx
, &gs_stage
->key
.gs
,
855 &gs_stage
->prog_data
.gs
, gs_stage
->nir
,
860 anv_pipeline_link_fs(const struct brw_compiler
*compiler
,
861 struct anv_pipeline_stage
*stage
)
863 unsigned num_rts
= 0;
864 const int max_rt
= FRAG_RESULT_DATA7
- FRAG_RESULT_DATA0
+ 1;
865 struct anv_pipeline_binding rt_bindings
[max_rt
];
866 nir_function_impl
*impl
= nir_shader_get_entrypoint(stage
->nir
);
867 int rt_to_bindings
[max_rt
];
868 memset(rt_to_bindings
, -1, sizeof(rt_to_bindings
));
869 bool rt_used
[max_rt
];
870 memset(rt_used
, 0, sizeof(rt_used
));
872 /* Flag used render targets */
873 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
874 if (var
->data
.location
< FRAG_RESULT_DATA0
)
877 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
882 const unsigned array_len
=
883 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
884 assert(rt
+ array_len
<= max_rt
);
887 if (!(stage
->key
.wm
.color_outputs_valid
& BITFIELD_RANGE(rt
, array_len
))) {
888 /* If this is the RT at location 0 and we have alpha to coverage
889 * enabled we will have to create a null RT for it, so mark it as
892 if (rt
> 0 || !stage
->key
.wm
.alpha_to_coverage
)
896 for (unsigned i
= 0; i
< array_len
; i
++)
897 rt_used
[rt
+ i
] = true;
900 /* Set new, compacted, location */
901 for (unsigned i
= 0; i
< max_rt
; i
++) {
905 rt_to_bindings
[i
] = num_rts
;
907 if (stage
->key
.wm
.color_outputs_valid
& (1 << i
)) {
908 rt_bindings
[rt_to_bindings
[i
]] = (struct anv_pipeline_binding
) {
909 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
914 /* Setup a null render target */
915 rt_bindings
[rt_to_bindings
[i
]] = (struct anv_pipeline_binding
) {
916 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
925 bool deleted_output
= false;
926 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
927 if (var
->data
.location
< FRAG_RESULT_DATA0
)
930 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
932 if (rt
>= MAX_RTS
|| !rt_used
[rt
]) {
933 /* Unused or out-of-bounds, throw it away, unless it is the first
934 * RT and we have alpha to coverage enabled.
936 deleted_output
= true;
937 var
->data
.mode
= nir_var_function_temp
;
938 exec_node_remove(&var
->node
);
939 exec_list_push_tail(&impl
->locals
, &var
->node
);
943 /* Give it the new location */
944 assert(rt_to_bindings
[rt
] != -1);
945 var
->data
.location
= rt_to_bindings
[rt
] + FRAG_RESULT_DATA0
;
949 nir_fixup_deref_modes(stage
->nir
);
952 /* If we have no render targets, we need a null render target */
953 rt_bindings
[0] = (struct anv_pipeline_binding
) {
954 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
961 /* Now that we've determined the actual number of render targets, adjust
962 * the key accordingly.
964 stage
->key
.wm
.nr_color_regions
= num_rts
;
965 stage
->key
.wm
.color_outputs_valid
= (1 << num_rts
) - 1;
967 assert(num_rts
<= max_rt
);
968 assert(stage
->bind_map
.surface_count
== 0);
969 typed_memcpy(stage
->bind_map
.surface_to_descriptor
,
970 rt_bindings
, num_rts
);
971 stage
->bind_map
.surface_count
+= num_rts
;
974 static const unsigned *
975 anv_pipeline_compile_fs(const struct brw_compiler
*compiler
,
977 struct anv_device
*device
,
978 struct anv_pipeline_stage
*fs_stage
,
979 struct anv_pipeline_stage
*prev_stage
)
981 /* TODO: we could set this to 0 based on the information in nir_shader, but
982 * we need this before we call spirv_to_nir.
985 fs_stage
->key
.wm
.input_slots_valid
=
986 prev_stage
->prog_data
.vue
.vue_map
.slots_valid
;
988 const unsigned *code
=
989 brw_compile_fs(compiler
, device
, mem_ctx
, &fs_stage
->key
.wm
,
990 &fs_stage
->prog_data
.wm
, fs_stage
->nir
,
991 NULL
, -1, -1, -1, true, false, NULL
, NULL
);
993 if (fs_stage
->key
.wm
.nr_color_regions
== 0 &&
994 !fs_stage
->prog_data
.wm
.has_side_effects
&&
995 !fs_stage
->prog_data
.wm
.uses_kill
&&
996 fs_stage
->prog_data
.wm
.computed_depth_mode
== BRW_PSCDEPTH_OFF
&&
997 !fs_stage
->prog_data
.wm
.computed_stencil
) {
998 /* This fragment shader has no outputs and no side effects. Go ahead
999 * and return the code pointer so we don't accidentally think the
1000 * compile failed but zero out prog_data which will set program_size to
1001 * zero and disable the stage.
1003 memset(&fs_stage
->prog_data
, 0, sizeof(fs_stage
->prog_data
));
1010 anv_pipeline_compile_graphics(struct anv_pipeline
*pipeline
,
1011 struct anv_pipeline_cache
*cache
,
1012 const VkGraphicsPipelineCreateInfo
*info
)
1014 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1015 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1017 int64_t pipeline_start
= os_time_get_nano();
1019 const struct brw_compiler
*compiler
=
1020 pipeline
->device
->instance
->physicalDevice
.compiler
;
1021 struct anv_pipeline_stage stages
[MESA_SHADER_STAGES
] = {};
1023 pipeline
->active_stages
= 0;
1026 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1027 const VkPipelineShaderStageCreateInfo
*sinfo
= &info
->pStages
[i
];
1028 gl_shader_stage stage
= vk_to_mesa_shader_stage(sinfo
->stage
);
1030 pipeline
->active_stages
|= sinfo
->stage
;
1032 int64_t stage_start
= os_time_get_nano();
1034 stages
[stage
].stage
= stage
;
1035 stages
[stage
].module
= anv_shader_module_from_handle(sinfo
->module
);
1036 stages
[stage
].entrypoint
= sinfo
->pName
;
1037 stages
[stage
].spec_info
= sinfo
->pSpecializationInfo
;
1038 anv_pipeline_hash_shader(stages
[stage
].module
,
1039 stages
[stage
].entrypoint
,
1041 stages
[stage
].spec_info
,
1042 stages
[stage
].shader_sha1
);
1044 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1046 case MESA_SHADER_VERTEX
:
1047 populate_vs_prog_key(devinfo
, &stages
[stage
].key
.vs
);
1049 case MESA_SHADER_TESS_CTRL
:
1050 populate_tcs_prog_key(devinfo
,
1051 info
->pTessellationState
->patchControlPoints
,
1052 &stages
[stage
].key
.tcs
);
1054 case MESA_SHADER_TESS_EVAL
:
1055 populate_tes_prog_key(devinfo
, &stages
[stage
].key
.tes
);
1057 case MESA_SHADER_GEOMETRY
:
1058 populate_gs_prog_key(devinfo
, &stages
[stage
].key
.gs
);
1060 case MESA_SHADER_FRAGMENT
:
1061 populate_wm_prog_key(devinfo
, pipeline
->subpass
,
1062 info
->pMultisampleState
,
1063 &stages
[stage
].key
.wm
);
1066 unreachable("Invalid graphics shader stage");
1069 stages
[stage
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1070 stages
[stage
].feedback
.flags
|= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
1073 if (pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
)
1074 pipeline
->active_stages
|= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
1076 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1078 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1080 unsigned char sha1
[20];
1081 anv_pipeline_hash_graphics(pipeline
, layout
, stages
, sha1
);
1084 unsigned cache_hits
= 0;
1085 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1086 if (!stages
[s
].entrypoint
)
1089 int64_t stage_start
= os_time_get_nano();
1091 stages
[s
].cache_key
.stage
= s
;
1092 memcpy(stages
[s
].cache_key
.sha1
, sha1
, sizeof(sha1
));
1095 struct anv_shader_bin
*bin
=
1096 anv_device_search_for_kernel(pipeline
->device
, cache
,
1097 &stages
[s
].cache_key
,
1098 sizeof(stages
[s
].cache_key
), &cache_hit
);
1101 pipeline
->shaders
[s
] = bin
;
1106 stages
[s
].feedback
.flags
|=
1107 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1109 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1112 if (found
== __builtin_popcount(pipeline
->active_stages
)) {
1113 if (cache_hits
== found
) {
1114 pipeline_feedback
.flags
|=
1115 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1117 /* We found all our shaders in the cache. We're done. */
1119 } else if (found
> 0) {
1120 /* We found some but not all of our shaders. This shouldn't happen
1121 * most of the time but it can if we have a partially populated
1124 assert(found
< __builtin_popcount(pipeline
->active_stages
));
1126 vk_debug_report(&pipeline
->device
->instance
->debug_report_callbacks
,
1127 VK_DEBUG_REPORT_WARNING_BIT_EXT
|
1128 VK_DEBUG_REPORT_PERFORMANCE_WARNING_BIT_EXT
,
1129 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT
,
1130 (uint64_t)(uintptr_t)cache
,
1132 "Found a partial pipeline in the cache. This is "
1133 "most likely caused by an incomplete pipeline cache "
1134 "import or export");
1136 /* We're going to have to recompile anyway, so just throw away our
1137 * references to the shaders in the cache. We'll get them out of the
1138 * cache again as part of the compilation process.
1140 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1141 stages
[s
].feedback
.flags
= 0;
1142 if (pipeline
->shaders
[s
]) {
1143 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1144 pipeline
->shaders
[s
] = NULL
;
1149 void *pipeline_ctx
= ralloc_context(NULL
);
1151 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1152 if (!stages
[s
].entrypoint
)
1155 int64_t stage_start
= os_time_get_nano();
1157 assert(stages
[s
].stage
== s
);
1158 assert(pipeline
->shaders
[s
] == NULL
);
1160 stages
[s
].bind_map
= (struct anv_pipeline_bind_map
) {
1161 .surface_to_descriptor
= stages
[s
].surface_to_descriptor
,
1162 .sampler_to_descriptor
= stages
[s
].sampler_to_descriptor
1165 stages
[s
].nir
= anv_pipeline_stage_get_nir(pipeline
, cache
,
1168 if (stages
[s
].nir
== NULL
) {
1169 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1173 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1176 /* Walk backwards to link */
1177 struct anv_pipeline_stage
*next_stage
= NULL
;
1178 for (int s
= MESA_SHADER_STAGES
- 1; s
>= 0; s
--) {
1179 if (!stages
[s
].entrypoint
)
1183 case MESA_SHADER_VERTEX
:
1184 anv_pipeline_link_vs(compiler
, &stages
[s
], next_stage
);
1186 case MESA_SHADER_TESS_CTRL
:
1187 anv_pipeline_link_tcs(compiler
, &stages
[s
], next_stage
);
1189 case MESA_SHADER_TESS_EVAL
:
1190 anv_pipeline_link_tes(compiler
, &stages
[s
], next_stage
);
1192 case MESA_SHADER_GEOMETRY
:
1193 anv_pipeline_link_gs(compiler
, &stages
[s
], next_stage
);
1195 case MESA_SHADER_FRAGMENT
:
1196 anv_pipeline_link_fs(compiler
, &stages
[s
]);
1199 unreachable("Invalid graphics shader stage");
1202 next_stage
= &stages
[s
];
1205 struct anv_pipeline_stage
*prev_stage
= NULL
;
1206 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1207 if (!stages
[s
].entrypoint
)
1210 int64_t stage_start
= os_time_get_nano();
1212 void *stage_ctx
= ralloc_context(NULL
);
1214 nir_xfb_info
*xfb_info
= NULL
;
1215 if (s
== MESA_SHADER_VERTEX
||
1216 s
== MESA_SHADER_TESS_EVAL
||
1217 s
== MESA_SHADER_GEOMETRY
)
1218 xfb_info
= nir_gather_xfb_info(stages
[s
].nir
, stage_ctx
);
1220 anv_pipeline_lower_nir(pipeline
, stage_ctx
, &stages
[s
], layout
);
1222 const unsigned *code
;
1224 case MESA_SHADER_VERTEX
:
1225 code
= anv_pipeline_compile_vs(compiler
, stage_ctx
, pipeline
->device
,
1228 case MESA_SHADER_TESS_CTRL
:
1229 code
= anv_pipeline_compile_tcs(compiler
, stage_ctx
, pipeline
->device
,
1230 &stages
[s
], prev_stage
);
1232 case MESA_SHADER_TESS_EVAL
:
1233 code
= anv_pipeline_compile_tes(compiler
, stage_ctx
, pipeline
->device
,
1234 &stages
[s
], prev_stage
);
1236 case MESA_SHADER_GEOMETRY
:
1237 code
= anv_pipeline_compile_gs(compiler
, stage_ctx
, pipeline
->device
,
1238 &stages
[s
], prev_stage
);
1240 case MESA_SHADER_FRAGMENT
:
1241 code
= anv_pipeline_compile_fs(compiler
, stage_ctx
, pipeline
->device
,
1242 &stages
[s
], prev_stage
);
1245 unreachable("Invalid graphics shader stage");
1248 ralloc_free(stage_ctx
);
1249 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1253 struct anv_shader_bin
*bin
=
1254 anv_device_upload_kernel(pipeline
->device
, cache
,
1255 &stages
[s
].cache_key
,
1256 sizeof(stages
[s
].cache_key
),
1257 code
, stages
[s
].prog_data
.base
.program_size
,
1258 stages
[s
].nir
->constant_data
,
1259 stages
[s
].nir
->constant_data_size
,
1260 &stages
[s
].prog_data
.base
,
1261 brw_prog_data_size(s
),
1262 xfb_info
, &stages
[s
].bind_map
);
1264 ralloc_free(stage_ctx
);
1265 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1269 pipeline
->shaders
[s
] = bin
;
1270 ralloc_free(stage_ctx
);
1272 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1274 prev_stage
= &stages
[s
];
1277 ralloc_free(pipeline_ctx
);
1281 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
] &&
1282 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->prog_data
->program_size
== 0) {
1283 /* This can happen if we decided to implicitly disable the fragment
1284 * shader. See anv_pipeline_compile_fs().
1286 anv_shader_bin_unref(pipeline
->device
,
1287 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
1288 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] = NULL
;
1289 pipeline
->active_stages
&= ~VK_SHADER_STAGE_FRAGMENT_BIT
;
1292 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1294 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1295 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1296 if (create_feedback
) {
1297 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1299 assert(info
->stageCount
== create_feedback
->pipelineStageCreationFeedbackCount
);
1300 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1301 gl_shader_stage s
= vk_to_mesa_shader_stage(info
->pStages
[i
].stage
);
1302 create_feedback
->pPipelineStageCreationFeedbacks
[i
] = stages
[s
].feedback
;
1309 ralloc_free(pipeline_ctx
);
1311 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1312 if (pipeline
->shaders
[s
])
1313 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1320 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1321 struct anv_pipeline_cache
*cache
,
1322 const VkComputePipelineCreateInfo
*info
,
1323 const struct anv_shader_module
*module
,
1324 const char *entrypoint
,
1325 const VkSpecializationInfo
*spec_info
)
1327 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1328 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1330 int64_t pipeline_start
= os_time_get_nano();
1332 const struct brw_compiler
*compiler
=
1333 pipeline
->device
->instance
->physicalDevice
.compiler
;
1335 struct anv_pipeline_stage stage
= {
1336 .stage
= MESA_SHADER_COMPUTE
,
1338 .entrypoint
= entrypoint
,
1339 .spec_info
= spec_info
,
1341 .stage
= MESA_SHADER_COMPUTE
,
1344 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1347 anv_pipeline_hash_shader(stage
.module
,
1349 MESA_SHADER_COMPUTE
,
1353 struct anv_shader_bin
*bin
= NULL
;
1355 populate_cs_prog_key(&pipeline
->device
->info
, &stage
.key
.cs
);
1357 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1359 anv_pipeline_hash_compute(pipeline
, layout
, &stage
, stage
.cache_key
.sha1
);
1361 bin
= anv_device_search_for_kernel(pipeline
->device
, cache
, &stage
.cache_key
,
1362 sizeof(stage
.cache_key
), &cache_hit
);
1365 int64_t stage_start
= os_time_get_nano();
1367 stage
.bind_map
= (struct anv_pipeline_bind_map
) {
1368 .surface_to_descriptor
= stage
.surface_to_descriptor
,
1369 .sampler_to_descriptor
= stage
.sampler_to_descriptor
1372 /* Set up a binding for the gl_NumWorkGroups */
1373 stage
.bind_map
.surface_count
= 1;
1374 stage
.bind_map
.surface_to_descriptor
[0] = (struct anv_pipeline_binding
) {
1375 .set
= ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
,
1378 void *mem_ctx
= ralloc_context(NULL
);
1380 stage
.nir
= anv_pipeline_stage_get_nir(pipeline
, cache
, mem_ctx
, &stage
);
1381 if (stage
.nir
== NULL
) {
1382 ralloc_free(mem_ctx
);
1383 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1386 anv_pipeline_lower_nir(pipeline
, mem_ctx
, &stage
, layout
);
1388 NIR_PASS_V(stage
.nir
, anv_nir_add_base_work_group_id
,
1389 &stage
.prog_data
.cs
);
1391 const unsigned *shader_code
=
1392 brw_compile_cs(compiler
, pipeline
->device
, mem_ctx
, &stage
.key
.cs
,
1393 &stage
.prog_data
.cs
, stage
.nir
, -1, NULL
);
1394 if (shader_code
== NULL
) {
1395 ralloc_free(mem_ctx
);
1396 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1399 const unsigned code_size
= stage
.prog_data
.base
.program_size
;
1400 bin
= anv_device_upload_kernel(pipeline
->device
, cache
,
1401 &stage
.cache_key
, sizeof(stage
.cache_key
),
1402 shader_code
, code_size
,
1403 stage
.nir
->constant_data
,
1404 stage
.nir
->constant_data_size
,
1405 &stage
.prog_data
.base
,
1406 sizeof(stage
.prog_data
.cs
),
1407 NULL
, &stage
.bind_map
);
1409 ralloc_free(mem_ctx
);
1410 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1413 ralloc_free(mem_ctx
);
1415 stage
.feedback
.duration
= os_time_get_nano() - stage_start
;
1419 stage
.feedback
.flags
|=
1420 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1421 pipeline_feedback
.flags
|=
1422 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1424 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1426 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1427 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1428 if (create_feedback
) {
1429 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1431 assert(create_feedback
->pipelineStageCreationFeedbackCount
== 1);
1432 create_feedback
->pPipelineStageCreationFeedbacks
[0] = stage
.feedback
;
1435 pipeline
->active_stages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1436 pipeline
->shaders
[MESA_SHADER_COMPUTE
] = bin
;
1442 * Copy pipeline state not marked as dynamic.
1443 * Dynamic state is pipeline state which hasn't been provided at pipeline
1444 * creation time, but is dynamically provided afterwards using various
1445 * vkCmdSet* functions.
1447 * The set of state considered "non_dynamic" is determined by the pieces of
1448 * state that have their corresponding VkDynamicState enums omitted from
1449 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1451 * @param[out] pipeline Destination non_dynamic state.
1452 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1455 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
1456 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1458 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
1459 struct anv_subpass
*subpass
= pipeline
->subpass
;
1461 pipeline
->dynamic_state
= default_dynamic_state
;
1463 if (pCreateInfo
->pDynamicState
) {
1464 /* Remove all of the states that are marked as dynamic */
1465 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1466 for (uint32_t s
= 0; s
< count
; s
++)
1467 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1470 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1472 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1474 * pViewportState is [...] NULL if the pipeline
1475 * has rasterization disabled.
1477 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1478 assert(pCreateInfo
->pViewportState
);
1480 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1481 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
1482 typed_memcpy(dynamic
->viewport
.viewports
,
1483 pCreateInfo
->pViewportState
->pViewports
,
1484 pCreateInfo
->pViewportState
->viewportCount
);
1487 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1488 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
1489 typed_memcpy(dynamic
->scissor
.scissors
,
1490 pCreateInfo
->pViewportState
->pScissors
,
1491 pCreateInfo
->pViewportState
->scissorCount
);
1495 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1496 assert(pCreateInfo
->pRasterizationState
);
1497 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1500 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1501 assert(pCreateInfo
->pRasterizationState
);
1502 dynamic
->depth_bias
.bias
=
1503 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1504 dynamic
->depth_bias
.clamp
=
1505 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1506 dynamic
->depth_bias
.slope
=
1507 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1510 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1512 * pColorBlendState is [...] NULL if the pipeline has rasterization
1513 * disabled or if the subpass of the render pass the pipeline is
1514 * created against does not use any color attachments.
1516 bool uses_color_att
= false;
1517 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1518 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1519 uses_color_att
= true;
1524 if (uses_color_att
&&
1525 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1526 assert(pCreateInfo
->pColorBlendState
);
1528 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
1529 typed_memcpy(dynamic
->blend_constants
,
1530 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1533 /* If there is no depthstencil attachment, then don't read
1534 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1535 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1536 * no need to override the depthstencil defaults in
1537 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1539 * Section 9.2 of the Vulkan 1.0.15 spec says:
1541 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1542 * disabled or if the subpass of the render pass the pipeline is created
1543 * against does not use a depth/stencil attachment.
1545 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1546 subpass
->depth_stencil_attachment
) {
1547 assert(pCreateInfo
->pDepthStencilState
);
1549 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1550 dynamic
->depth_bounds
.min
=
1551 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1552 dynamic
->depth_bounds
.max
=
1553 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1556 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1557 dynamic
->stencil_compare_mask
.front
=
1558 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1559 dynamic
->stencil_compare_mask
.back
=
1560 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1563 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1564 dynamic
->stencil_write_mask
.front
=
1565 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1566 dynamic
->stencil_write_mask
.back
=
1567 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1570 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1571 dynamic
->stencil_reference
.front
=
1572 pCreateInfo
->pDepthStencilState
->front
.reference
;
1573 dynamic
->stencil_reference
.back
=
1574 pCreateInfo
->pDepthStencilState
->back
.reference
;
1578 pipeline
->dynamic_state_mask
= states
;
1582 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1585 struct anv_render_pass
*renderpass
= NULL
;
1586 struct anv_subpass
*subpass
= NULL
;
1588 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1589 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1591 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1593 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1596 assert(info
->subpass
< renderpass
->subpass_count
);
1597 subpass
= &renderpass
->subpasses
[info
->subpass
];
1599 assert(info
->stageCount
>= 1);
1600 assert(info
->pVertexInputState
);
1601 assert(info
->pInputAssemblyState
);
1602 assert(info
->pRasterizationState
);
1603 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1604 assert(info
->pViewportState
);
1605 assert(info
->pMultisampleState
);
1607 if (subpass
&& subpass
->depth_stencil_attachment
)
1608 assert(info
->pDepthStencilState
);
1610 if (subpass
&& subpass
->color_count
> 0) {
1611 bool all_color_unused
= true;
1612 for (int i
= 0; i
< subpass
->color_count
; i
++) {
1613 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
1614 all_color_unused
= false;
1616 /* pColorBlendState is ignored if the pipeline has rasterization
1617 * disabled or if the subpass of the render pass the pipeline is
1618 * created against does not use any color attachments.
1620 assert(info
->pColorBlendState
|| all_color_unused
);
1624 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1625 switch (info
->pStages
[i
].stage
) {
1626 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1627 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1628 assert(info
->pTessellationState
);
1638 * Calculate the desired L3 partitioning based on the current state of the
1639 * pipeline. For now this simply returns the conservative defaults calculated
1640 * by get_default_l3_weights(), but we could probably do better by gathering
1641 * more statistics from the pipeline state (e.g. guess of expected URB usage
1642 * and bound surfaces), or by using feed-back from performance counters.
1645 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1647 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1649 const struct gen_l3_weights w
=
1650 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
1652 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
1653 pipeline
->urb
.total_size
=
1654 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
1658 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1659 struct anv_device
*device
,
1660 struct anv_pipeline_cache
*cache
,
1661 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1662 const VkAllocationCallbacks
*alloc
)
1666 anv_pipeline_validate_create_info(pCreateInfo
);
1669 alloc
= &device
->alloc
;
1671 pipeline
->device
= device
;
1673 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, pCreateInfo
->renderPass
);
1674 assert(pCreateInfo
->subpass
< render_pass
->subpass_count
);
1675 pipeline
->subpass
= &render_pass
->subpasses
[pCreateInfo
->subpass
];
1677 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1678 if (result
!= VK_SUCCESS
)
1681 pipeline
->batch
.alloc
= alloc
;
1682 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1683 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1684 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1685 pipeline
->batch
.status
= VK_SUCCESS
;
1687 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1688 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1689 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1691 /* Previously we enabled depth clipping when !depthClampEnable.
1692 * DepthClipStateCreateInfo now makes depth clipping explicit so if the
1693 * clipping info is available, use its enable value to determine clipping,
1694 * otherwise fallback to the previous !depthClampEnable logic.
1696 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*clip_info
=
1697 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1698 PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
1699 pipeline
->depth_clip_enable
= clip_info
? clip_info
->depthClipEnable
: !pipeline
->depth_clamp_enable
;
1701 pipeline
->sample_shading_enable
= pCreateInfo
->pMultisampleState
&&
1702 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
1704 pipeline
->needs_data_cache
= false;
1706 /* When we free the pipeline, we detect stages based on the NULL status
1707 * of various prog_data pointers. Make them NULL by default.
1709 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1711 result
= anv_pipeline_compile_graphics(pipeline
, cache
, pCreateInfo
);
1712 if (result
!= VK_SUCCESS
) {
1713 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);
1717 assert(pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1719 anv_pipeline_setup_l3_config(pipeline
, false);
1721 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1722 pCreateInfo
->pVertexInputState
;
1724 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1726 pipeline
->vb_used
= 0;
1727 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1728 const VkVertexInputAttributeDescription
*desc
=
1729 &vi_info
->pVertexAttributeDescriptions
[i
];
1731 if (inputs_read
& (1ull << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1732 pipeline
->vb_used
|= 1 << desc
->binding
;
1735 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1736 const VkVertexInputBindingDescription
*desc
=
1737 &vi_info
->pVertexBindingDescriptions
[i
];
1739 pipeline
->vb
[desc
->binding
].stride
= desc
->stride
;
1741 /* Step rate is programmed per vertex element (attribute), not
1742 * binding. Set up a map of which bindings step per instance, for
1743 * reference by vertex element setup. */
1744 switch (desc
->inputRate
) {
1746 case VK_VERTEX_INPUT_RATE_VERTEX
:
1747 pipeline
->vb
[desc
->binding
].instanced
= false;
1749 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1750 pipeline
->vb
[desc
->binding
].instanced
= true;
1754 pipeline
->vb
[desc
->binding
].instance_divisor
= 1;
1757 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*vi_div_state
=
1758 vk_find_struct_const(vi_info
->pNext
,
1759 PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
1761 for (uint32_t i
= 0; i
< vi_div_state
->vertexBindingDivisorCount
; i
++) {
1762 const VkVertexInputBindingDivisorDescriptionEXT
*desc
=
1763 &vi_div_state
->pVertexBindingDivisors
[i
];
1765 pipeline
->vb
[desc
->binding
].instance_divisor
= desc
->divisor
;
1769 /* Our implementation of VK_KHR_multiview uses instancing to draw the
1770 * different views. If the client asks for instancing, we need to multiply
1771 * the instance divisor by the number of views ensure that we repeat the
1772 * client's per-instance data once for each view.
1774 if (pipeline
->subpass
->view_mask
) {
1775 const uint32_t view_count
= anv_subpass_view_count(pipeline
->subpass
);
1776 for (uint32_t vb
= 0; vb
< MAX_VBS
; vb
++) {
1777 if (pipeline
->vb
[vb
].instanced
)
1778 pipeline
->vb
[vb
].instance_divisor
*= view_count
;
1782 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1783 pCreateInfo
->pInputAssemblyState
;
1784 const VkPipelineTessellationStateCreateInfo
*tess_info
=
1785 pCreateInfo
->pTessellationState
;
1786 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1788 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1789 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
1791 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];