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anv/pipeline: remove the pipeline layout field from anv_pipeline
[mesa.git] / src / intel / vulkan / anv_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "util/mesa-sha1.h"
31 #include "common/gen_l3_config.h"
32 #include "anv_private.h"
33 #include "compiler/brw_nir.h"
34 #include "anv_nir.h"
35 #include "spirv/nir_spirv.h"
36
37 /* Needed for SWIZZLE macros */
38 #include "program/prog_instruction.h"
39
40 // Shader functions
41
42 VkResult anv_CreateShaderModule(
43 VkDevice _device,
44 const VkShaderModuleCreateInfo* pCreateInfo,
45 const VkAllocationCallbacks* pAllocator,
46 VkShaderModule* pShaderModule)
47 {
48 ANV_FROM_HANDLE(anv_device, device, _device);
49 struct anv_shader_module *module;
50
51 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
52 assert(pCreateInfo->flags == 0);
53
54 module = vk_alloc2(&device->alloc, pAllocator,
55 sizeof(*module) + pCreateInfo->codeSize, 8,
56 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
57 if (module == NULL)
58 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
59
60 module->size = pCreateInfo->codeSize;
61 memcpy(module->data, pCreateInfo->pCode, module->size);
62
63 _mesa_sha1_compute(module->data, module->size, module->sha1);
64
65 *pShaderModule = anv_shader_module_to_handle(module);
66
67 return VK_SUCCESS;
68 }
69
70 void anv_DestroyShaderModule(
71 VkDevice _device,
72 VkShaderModule _module,
73 const VkAllocationCallbacks* pAllocator)
74 {
75 ANV_FROM_HANDLE(anv_device, device, _device);
76 ANV_FROM_HANDLE(anv_shader_module, module, _module);
77
78 if (!module)
79 return;
80
81 vk_free2(&device->alloc, pAllocator, module);
82 }
83
84 #define SPIR_V_MAGIC_NUMBER 0x07230203
85
86 static const uint64_t stage_to_debug[] = {
87 [MESA_SHADER_VERTEX] = DEBUG_VS,
88 [MESA_SHADER_TESS_CTRL] = DEBUG_TCS,
89 [MESA_SHADER_TESS_EVAL] = DEBUG_TES,
90 [MESA_SHADER_GEOMETRY] = DEBUG_GS,
91 [MESA_SHADER_FRAGMENT] = DEBUG_WM,
92 [MESA_SHADER_COMPUTE] = DEBUG_CS,
93 };
94
95 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
96 * we can't do that yet because we don't have the ability to copy nir.
97 */
98 static nir_shader *
99 anv_shader_compile_to_nir(struct anv_pipeline *pipeline,
100 void *mem_ctx,
101 struct anv_shader_module *module,
102 const char *entrypoint_name,
103 gl_shader_stage stage,
104 const VkSpecializationInfo *spec_info)
105 {
106 const struct anv_device *device = pipeline->device;
107
108 const struct brw_compiler *compiler =
109 device->instance->physicalDevice.compiler;
110 const nir_shader_compiler_options *nir_options =
111 compiler->glsl_compiler_options[stage].NirOptions;
112
113 uint32_t *spirv = (uint32_t *) module->data;
114 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
115 assert(module->size % 4 == 0);
116
117 uint32_t num_spec_entries = 0;
118 struct nir_spirv_specialization *spec_entries = NULL;
119 if (spec_info && spec_info->mapEntryCount > 0) {
120 num_spec_entries = spec_info->mapEntryCount;
121 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
122 for (uint32_t i = 0; i < num_spec_entries; i++) {
123 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
124 const void *data = spec_info->pData + entry.offset;
125 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
126
127 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
128 if (spec_info->dataSize == 8)
129 spec_entries[i].data64 = *(const uint64_t *)data;
130 else
131 spec_entries[i].data32 = *(const uint32_t *)data;
132 }
133 }
134
135 struct spirv_to_nir_options spirv_options = {
136 .lower_workgroup_access_to_offsets = true,
137 .caps = {
138 .float64 = device->instance->physicalDevice.info.gen >= 8,
139 .int64 = device->instance->physicalDevice.info.gen >= 8,
140 .tessellation = true,
141 .draw_parameters = true,
142 .image_write_without_format = true,
143 .multiview = true,
144 .variable_pointers = true,
145 .storage_16bit = device->instance->physicalDevice.info.gen >= 8,
146 },
147 };
148
149 nir_function *entry_point =
150 spirv_to_nir(spirv, module->size / 4,
151 spec_entries, num_spec_entries,
152 stage, entrypoint_name, &spirv_options, nir_options);
153 nir_shader *nir = entry_point->shader;
154 assert(nir->info.stage == stage);
155 nir_validate_shader(nir);
156 ralloc_steal(mem_ctx, nir);
157
158 free(spec_entries);
159
160 if (unlikely(INTEL_DEBUG & stage_to_debug[stage])) {
161 fprintf(stderr, "NIR (from SPIR-V) for %s shader:\n",
162 gl_shader_stage_name(stage));
163 nir_print_shader(nir, stderr);
164 }
165
166 /* We have to lower away local constant initializers right before we
167 * inline functions. That way they get properly initialized at the top
168 * of the function and not at the top of its caller.
169 */
170 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
171 NIR_PASS_V(nir, nir_lower_returns);
172 NIR_PASS_V(nir, nir_inline_functions);
173
174 /* Pick off the single entrypoint that we want */
175 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
176 if (func != entry_point)
177 exec_node_remove(&func->node);
178 }
179 assert(exec_list_length(&nir->functions) == 1);
180 entry_point->name = ralloc_strdup(entry_point, "main");
181
182 NIR_PASS_V(nir, nir_remove_dead_variables,
183 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
184
185 if (stage == MESA_SHADER_FRAGMENT)
186 NIR_PASS_V(nir, nir_lower_wpos_center, pipeline->sample_shading_enable);
187
188 /* Now that we've deleted all but the main function, we can go ahead and
189 * lower the rest of the constant initializers.
190 */
191 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
192 NIR_PASS_V(nir, nir_propagate_invariant);
193 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
194 entry_point->impl, true, false);
195
196 /* Vulkan uses the separate-shader linking model */
197 nir->info.separate_shader = true;
198
199 nir = brw_preprocess_nir(compiler, nir);
200
201 if (stage == MESA_SHADER_FRAGMENT)
202 NIR_PASS_V(nir, anv_nir_lower_input_attachments);
203
204 return nir;
205 }
206
207 void anv_DestroyPipeline(
208 VkDevice _device,
209 VkPipeline _pipeline,
210 const VkAllocationCallbacks* pAllocator)
211 {
212 ANV_FROM_HANDLE(anv_device, device, _device);
213 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
214
215 if (!pipeline)
216 return;
217
218 anv_reloc_list_finish(&pipeline->batch_relocs,
219 pAllocator ? pAllocator : &device->alloc);
220 if (pipeline->blend_state.map)
221 anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
222
223 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
224 if (pipeline->shaders[s])
225 anv_shader_bin_unref(device, pipeline->shaders[s]);
226 }
227
228 vk_free2(&device->alloc, pAllocator, pipeline);
229 }
230
231 static const uint32_t vk_to_gen_primitive_type[] = {
232 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
233 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
234 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
235 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
236 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
237 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
238 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
239 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
240 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
241 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
242 };
243
244 static void
245 populate_sampler_prog_key(const struct gen_device_info *devinfo,
246 struct brw_sampler_prog_key_data *key)
247 {
248 /* Almost all multisampled textures are compressed. The only time when we
249 * don't compress a multisampled texture is for 16x MSAA with a surface
250 * width greater than 8k which is a bit of an edge case. Since the sampler
251 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
252 * to tell the compiler to always assume compression.
253 */
254 key->compressed_multisample_layout_mask = ~0;
255
256 /* SkyLake added support for 16x MSAA. With this came a new message for
257 * reading from a 16x MSAA surface with compression. The new message was
258 * needed because now the MCS data is 64 bits instead of 32 or lower as is
259 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
260 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
261 * so we can just use it unconditionally. This may not be quite as
262 * efficient but it saves us from recompiling.
263 */
264 if (devinfo->gen >= 9)
265 key->msaa_16 = ~0;
266
267 /* XXX: Handle texture swizzle on HSW- */
268 for (int i = 0; i < MAX_SAMPLERS; i++) {
269 /* Assume color sampler, no swizzling. (Works for BDW+) */
270 key->swizzles[i] = SWIZZLE_XYZW;
271 }
272 }
273
274 static void
275 populate_vs_prog_key(const struct gen_device_info *devinfo,
276 struct brw_vs_prog_key *key)
277 {
278 memset(key, 0, sizeof(*key));
279
280 populate_sampler_prog_key(devinfo, &key->tex);
281
282 /* XXX: Handle vertex input work-arounds */
283
284 /* XXX: Handle sampler_prog_key */
285 }
286
287 static void
288 populate_gs_prog_key(const struct gen_device_info *devinfo,
289 struct brw_gs_prog_key *key)
290 {
291 memset(key, 0, sizeof(*key));
292
293 populate_sampler_prog_key(devinfo, &key->tex);
294 }
295
296 static void
297 populate_wm_prog_key(const struct anv_pipeline *pipeline,
298 const VkGraphicsPipelineCreateInfo *info,
299 struct brw_wm_prog_key *key)
300 {
301 const struct gen_device_info *devinfo = &pipeline->device->info;
302
303 memset(key, 0, sizeof(*key));
304
305 populate_sampler_prog_key(devinfo, &key->tex);
306
307 /* TODO: we could set this to 0 based on the information in nir_shader, but
308 * this function is called before spirv_to_nir. */
309 const struct brw_vue_map *vue_map =
310 &anv_pipeline_get_last_vue_prog_data(pipeline)->vue_map;
311 key->input_slots_valid = vue_map->slots_valid;
312
313 /* Vulkan doesn't specify a default */
314 key->high_quality_derivatives = false;
315
316 /* XXX Vulkan doesn't appear to specify */
317 key->clamp_fragment_color = false;
318
319 key->nr_color_regions = pipeline->subpass->color_count;
320
321 key->replicate_alpha = key->nr_color_regions > 1 &&
322 info->pMultisampleState &&
323 info->pMultisampleState->alphaToCoverageEnable;
324
325 if (info->pMultisampleState) {
326 /* We should probably pull this out of the shader, but it's fairly
327 * harmless to compute it and then let dead-code take care of it.
328 */
329 if (info->pMultisampleState->rasterizationSamples > 1) {
330 key->persample_interp =
331 (info->pMultisampleState->minSampleShading *
332 info->pMultisampleState->rasterizationSamples) > 1;
333 key->multisample_fbo = true;
334 }
335
336 key->frag_coord_adds_sample_pos =
337 info->pMultisampleState->sampleShadingEnable;
338 }
339 }
340
341 static void
342 populate_cs_prog_key(const struct gen_device_info *devinfo,
343 struct brw_cs_prog_key *key)
344 {
345 memset(key, 0, sizeof(*key));
346
347 populate_sampler_prog_key(devinfo, &key->tex);
348 }
349
350 static void
351 anv_pipeline_hash_shader(struct anv_pipeline *pipeline,
352 struct anv_pipeline_layout *layout,
353 struct anv_shader_module *module,
354 const char *entrypoint,
355 gl_shader_stage stage,
356 const VkSpecializationInfo *spec_info,
357 const void *key, size_t key_size,
358 unsigned char *sha1_out)
359 {
360 struct mesa_sha1 ctx;
361
362 _mesa_sha1_init(&ctx);
363 if (stage != MESA_SHADER_COMPUTE) {
364 _mesa_sha1_update(&ctx, &pipeline->subpass->view_mask,
365 sizeof(pipeline->subpass->view_mask));
366 }
367 if (layout)
368 _mesa_sha1_update(&ctx, layout->sha1, sizeof(layout->sha1));
369 _mesa_sha1_update(&ctx, module->sha1, sizeof(module->sha1));
370 _mesa_sha1_update(&ctx, entrypoint, strlen(entrypoint));
371 _mesa_sha1_update(&ctx, &stage, sizeof(stage));
372 if (spec_info) {
373 _mesa_sha1_update(&ctx, spec_info->pMapEntries,
374 spec_info->mapEntryCount * sizeof(*spec_info->pMapEntries));
375 _mesa_sha1_update(&ctx, spec_info->pData, spec_info->dataSize);
376 }
377 _mesa_sha1_update(&ctx, key, key_size);
378 _mesa_sha1_final(&ctx, sha1_out);
379 }
380
381 static nir_shader *
382 anv_pipeline_compile(struct anv_pipeline *pipeline,
383 void *mem_ctx,
384 struct anv_pipeline_layout *layout,
385 struct anv_shader_module *module,
386 const char *entrypoint,
387 gl_shader_stage stage,
388 const VkSpecializationInfo *spec_info,
389 struct brw_stage_prog_data *prog_data,
390 struct anv_pipeline_bind_map *map)
391 {
392 const struct brw_compiler *compiler =
393 pipeline->device->instance->physicalDevice.compiler;
394
395 nir_shader *nir = anv_shader_compile_to_nir(pipeline, mem_ctx,
396 module, entrypoint, stage,
397 spec_info);
398 if (nir == NULL)
399 return NULL;
400
401 NIR_PASS_V(nir, anv_nir_lower_ycbcr_textures, layout);
402
403 NIR_PASS_V(nir, anv_nir_lower_push_constants);
404
405 if (stage != MESA_SHADER_COMPUTE)
406 NIR_PASS_V(nir, anv_nir_lower_multiview, pipeline->subpass->view_mask);
407
408 if (stage == MESA_SHADER_COMPUTE)
409 prog_data->total_shared = nir->num_shared;
410
411 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
412
413 if (nir->num_uniforms > 0) {
414 assert(prog_data->nr_params == 0);
415
416 /* If the shader uses any push constants at all, we'll just give
417 * them the maximum possible number
418 */
419 assert(nir->num_uniforms <= MAX_PUSH_CONSTANTS_SIZE);
420 nir->num_uniforms = MAX_PUSH_CONSTANTS_SIZE;
421 prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
422 prog_data->param = ralloc_array(mem_ctx, uint32_t, prog_data->nr_params);
423
424 /* We now set the param values to be offsets into a
425 * anv_push_constant_data structure. Since the compiler doesn't
426 * actually dereference any of the gl_constant_value pointers in the
427 * params array, it doesn't really matter what we put here.
428 */
429 struct anv_push_constants *null_data = NULL;
430 /* Fill out the push constants section of the param array */
431 for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++) {
432 prog_data->param[i] = ANV_PARAM_PUSH(
433 (uintptr_t)&null_data->client_data[i * sizeof(float)]);
434 }
435 }
436
437 if (nir->info.num_ssbos > 0 || nir->info.num_images > 0)
438 pipeline->needs_data_cache = true;
439
440 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
441 if (layout)
442 anv_nir_apply_pipeline_layout(pipeline, layout, nir, prog_data, map);
443
444 if (stage != MESA_SHADER_COMPUTE)
445 brw_nir_analyze_ubo_ranges(compiler, nir, prog_data->ubo_ranges);
446
447 assert(nir->num_uniforms == prog_data->nr_params * 4);
448
449 return nir;
450 }
451
452 static void
453 anv_fill_binding_table(struct brw_stage_prog_data *prog_data, unsigned bias)
454 {
455 prog_data->binding_table.size_bytes = 0;
456 prog_data->binding_table.texture_start = bias;
457 prog_data->binding_table.gather_texture_start = bias;
458 prog_data->binding_table.ubo_start = bias;
459 prog_data->binding_table.ssbo_start = bias;
460 prog_data->binding_table.image_start = bias;
461 }
462
463 static struct anv_shader_bin *
464 anv_pipeline_upload_kernel(struct anv_pipeline *pipeline,
465 struct anv_pipeline_cache *cache,
466 const void *key_data, uint32_t key_size,
467 const void *kernel_data, uint32_t kernel_size,
468 const struct brw_stage_prog_data *prog_data,
469 uint32_t prog_data_size,
470 const struct anv_pipeline_bind_map *bind_map)
471 {
472 if (cache) {
473 return anv_pipeline_cache_upload_kernel(cache, key_data, key_size,
474 kernel_data, kernel_size,
475 prog_data, prog_data_size,
476 bind_map);
477 } else {
478 return anv_shader_bin_create(pipeline->device, key_data, key_size,
479 kernel_data, kernel_size,
480 prog_data, prog_data_size,
481 prog_data->param, bind_map);
482 }
483 }
484
485
486 static void
487 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
488 gl_shader_stage stage,
489 struct anv_shader_bin *shader)
490 {
491 pipeline->shaders[stage] = shader;
492 pipeline->active_stages |= mesa_to_vk_shader_stage(stage);
493 }
494
495 static VkResult
496 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
497 struct anv_pipeline_cache *cache,
498 const VkGraphicsPipelineCreateInfo *info,
499 struct anv_shader_module *module,
500 const char *entrypoint,
501 const VkSpecializationInfo *spec_info)
502 {
503 const struct brw_compiler *compiler =
504 pipeline->device->instance->physicalDevice.compiler;
505 struct brw_vs_prog_key key;
506 struct anv_shader_bin *bin = NULL;
507 unsigned char sha1[20];
508
509 populate_vs_prog_key(&pipeline->device->info, &key);
510
511 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
512
513 if (cache) {
514 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
515 MESA_SHADER_VERTEX, spec_info,
516 &key, sizeof(key), sha1);
517 bin = anv_pipeline_cache_search(cache, sha1, 20);
518 }
519
520 if (bin == NULL) {
521 struct brw_vs_prog_data prog_data = {};
522 struct anv_pipeline_binding surface_to_descriptor[256];
523 struct anv_pipeline_binding sampler_to_descriptor[256];
524
525 struct anv_pipeline_bind_map map = {
526 .surface_to_descriptor = surface_to_descriptor,
527 .sampler_to_descriptor = sampler_to_descriptor
528 };
529
530 void *mem_ctx = ralloc_context(NULL);
531
532 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
533 module, entrypoint,
534 MESA_SHADER_VERTEX, spec_info,
535 &prog_data.base.base, &map);
536 if (nir == NULL) {
537 ralloc_free(mem_ctx);
538 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
539 }
540
541 anv_fill_binding_table(&prog_data.base.base, 0);
542
543 brw_compute_vue_map(&pipeline->device->info,
544 &prog_data.base.vue_map,
545 nir->info.outputs_written,
546 nir->info.separate_shader);
547
548 const unsigned *shader_code =
549 brw_compile_vs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
550 -1, NULL);
551 if (shader_code == NULL) {
552 ralloc_free(mem_ctx);
553 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
554 }
555
556 unsigned code_size = prog_data.base.base.program_size;
557 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
558 shader_code, code_size,
559 &prog_data.base.base, sizeof(prog_data),
560 &map);
561 if (!bin) {
562 ralloc_free(mem_ctx);
563 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
564 }
565
566 ralloc_free(mem_ctx);
567 }
568
569 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX, bin);
570
571 return VK_SUCCESS;
572 }
573
574 static void
575 merge_tess_info(struct shader_info *tes_info,
576 const struct shader_info *tcs_info)
577 {
578 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
579 *
580 * "PointMode. Controls generation of points rather than triangles
581 * or lines. This functionality defaults to disabled, and is
582 * enabled if either shader stage includes the execution mode.
583 *
584 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
585 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
586 * and OutputVertices, it says:
587 *
588 * "One mode must be set in at least one of the tessellation
589 * shader stages."
590 *
591 * So, the fields can be set in either the TCS or TES, but they must
592 * agree if set in both. Our backend looks at TES, so bitwise-or in
593 * the values from the TCS.
594 */
595 assert(tcs_info->tess.tcs_vertices_out == 0 ||
596 tes_info->tess.tcs_vertices_out == 0 ||
597 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
598 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
599
600 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
601 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
602 tcs_info->tess.spacing == tes_info->tess.spacing);
603 tes_info->tess.spacing |= tcs_info->tess.spacing;
604
605 assert(tcs_info->tess.primitive_mode == 0 ||
606 tes_info->tess.primitive_mode == 0 ||
607 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
608 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
609 tes_info->tess.ccw |= tcs_info->tess.ccw;
610 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
611 }
612
613 static VkResult
614 anv_pipeline_compile_tcs_tes(struct anv_pipeline *pipeline,
615 struct anv_pipeline_cache *cache,
616 const VkGraphicsPipelineCreateInfo *info,
617 struct anv_shader_module *tcs_module,
618 const char *tcs_entrypoint,
619 const VkSpecializationInfo *tcs_spec_info,
620 struct anv_shader_module *tes_module,
621 const char *tes_entrypoint,
622 const VkSpecializationInfo *tes_spec_info)
623 {
624 const struct gen_device_info *devinfo = &pipeline->device->info;
625 const struct brw_compiler *compiler =
626 pipeline->device->instance->physicalDevice.compiler;
627 struct brw_tcs_prog_key tcs_key = {};
628 struct brw_tes_prog_key tes_key = {};
629 struct anv_shader_bin *tcs_bin = NULL;
630 struct anv_shader_bin *tes_bin = NULL;
631 unsigned char tcs_sha1[40];
632 unsigned char tes_sha1[40];
633
634 populate_sampler_prog_key(&pipeline->device->info, &tcs_key.tex);
635 populate_sampler_prog_key(&pipeline->device->info, &tes_key.tex);
636 tcs_key.input_vertices = info->pTessellationState->patchControlPoints;
637
638 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
639
640 if (cache) {
641 anv_pipeline_hash_shader(pipeline, layout, tcs_module, tcs_entrypoint,
642 MESA_SHADER_TESS_CTRL, tcs_spec_info,
643 &tcs_key, sizeof(tcs_key), tcs_sha1);
644 anv_pipeline_hash_shader(pipeline, layout, tes_module, tes_entrypoint,
645 MESA_SHADER_TESS_EVAL, tes_spec_info,
646 &tes_key, sizeof(tes_key), tes_sha1);
647 memcpy(&tcs_sha1[20], tes_sha1, 20);
648 memcpy(&tes_sha1[20], tcs_sha1, 20);
649 tcs_bin = anv_pipeline_cache_search(cache, tcs_sha1, sizeof(tcs_sha1));
650 tes_bin = anv_pipeline_cache_search(cache, tes_sha1, sizeof(tes_sha1));
651 }
652
653 if (tcs_bin == NULL || tes_bin == NULL) {
654 struct brw_tcs_prog_data tcs_prog_data = {};
655 struct brw_tes_prog_data tes_prog_data = {};
656 struct anv_pipeline_binding tcs_surface_to_descriptor[256];
657 struct anv_pipeline_binding tcs_sampler_to_descriptor[256];
658 struct anv_pipeline_binding tes_surface_to_descriptor[256];
659 struct anv_pipeline_binding tes_sampler_to_descriptor[256];
660
661 struct anv_pipeline_bind_map tcs_map = {
662 .surface_to_descriptor = tcs_surface_to_descriptor,
663 .sampler_to_descriptor = tcs_sampler_to_descriptor
664 };
665 struct anv_pipeline_bind_map tes_map = {
666 .surface_to_descriptor = tes_surface_to_descriptor,
667 .sampler_to_descriptor = tes_sampler_to_descriptor
668 };
669
670 void *mem_ctx = ralloc_context(NULL);
671
672 nir_shader *tcs_nir =
673 anv_pipeline_compile(pipeline, mem_ctx, layout,
674 tcs_module, tcs_entrypoint,
675 MESA_SHADER_TESS_CTRL, tcs_spec_info,
676 &tcs_prog_data.base.base, &tcs_map);
677 nir_shader *tes_nir =
678 anv_pipeline_compile(pipeline, mem_ctx, layout,
679 tes_module, tes_entrypoint,
680 MESA_SHADER_TESS_EVAL, tes_spec_info,
681 &tes_prog_data.base.base, &tes_map);
682 if (tcs_nir == NULL || tes_nir == NULL) {
683 ralloc_free(mem_ctx);
684 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
685 }
686
687 nir_lower_tes_patch_vertices(tes_nir,
688 tcs_nir->info.tess.tcs_vertices_out);
689
690 /* Copy TCS info into the TES info */
691 merge_tess_info(&tes_nir->info, &tcs_nir->info);
692
693 anv_fill_binding_table(&tcs_prog_data.base.base, 0);
694 anv_fill_binding_table(&tes_prog_data.base.base, 0);
695
696 /* Whacking the key after cache lookup is a bit sketchy, but all of
697 * this comes from the SPIR-V, which is part of the hash used for the
698 * pipeline cache. So it should be safe.
699 */
700 tcs_key.tes_primitive_mode = tes_nir->info.tess.primitive_mode;
701 tcs_key.outputs_written = tcs_nir->info.outputs_written;
702 tcs_key.patch_outputs_written = tcs_nir->info.patch_outputs_written;
703 tcs_key.quads_workaround =
704 devinfo->gen < 9 &&
705 tes_nir->info.tess.primitive_mode == 7 /* GL_QUADS */ &&
706 tes_nir->info.tess.spacing == TESS_SPACING_EQUAL;
707
708 tes_key.inputs_read = tcs_key.outputs_written;
709 tes_key.patch_inputs_read = tcs_key.patch_outputs_written;
710
711 const int shader_time_index = -1;
712 const unsigned *shader_code;
713
714 shader_code =
715 brw_compile_tcs(compiler, NULL, mem_ctx, &tcs_key, &tcs_prog_data,
716 tcs_nir, shader_time_index, NULL);
717 if (shader_code == NULL) {
718 ralloc_free(mem_ctx);
719 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
720 }
721
722 unsigned code_size = tcs_prog_data.base.base.program_size;
723 tcs_bin = anv_pipeline_upload_kernel(pipeline, cache,
724 tcs_sha1, sizeof(tcs_sha1),
725 shader_code, code_size,
726 &tcs_prog_data.base.base,
727 sizeof(tcs_prog_data),
728 &tcs_map);
729 if (!tcs_bin) {
730 ralloc_free(mem_ctx);
731 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
732 }
733
734 shader_code =
735 brw_compile_tes(compiler, NULL, mem_ctx, &tes_key,
736 &tcs_prog_data.base.vue_map, &tes_prog_data, tes_nir,
737 NULL, shader_time_index, NULL);
738 if (shader_code == NULL) {
739 ralloc_free(mem_ctx);
740 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
741 }
742
743 code_size = tes_prog_data.base.base.program_size;
744 tes_bin = anv_pipeline_upload_kernel(pipeline, cache,
745 tes_sha1, sizeof(tes_sha1),
746 shader_code, code_size,
747 &tes_prog_data.base.base,
748 sizeof(tes_prog_data),
749 &tes_map);
750 if (!tes_bin) {
751 ralloc_free(mem_ctx);
752 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
753 }
754
755 ralloc_free(mem_ctx);
756 }
757
758 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_TESS_CTRL, tcs_bin);
759 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_TESS_EVAL, tes_bin);
760
761 return VK_SUCCESS;
762 }
763
764 static VkResult
765 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
766 struct anv_pipeline_cache *cache,
767 const VkGraphicsPipelineCreateInfo *info,
768 struct anv_shader_module *module,
769 const char *entrypoint,
770 const VkSpecializationInfo *spec_info)
771 {
772 const struct brw_compiler *compiler =
773 pipeline->device->instance->physicalDevice.compiler;
774 struct brw_gs_prog_key key;
775 struct anv_shader_bin *bin = NULL;
776 unsigned char sha1[20];
777
778 populate_gs_prog_key(&pipeline->device->info, &key);
779
780 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
781
782 if (cache) {
783 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
784 MESA_SHADER_GEOMETRY, spec_info,
785 &key, sizeof(key), sha1);
786 bin = anv_pipeline_cache_search(cache, sha1, 20);
787 }
788
789 if (bin == NULL) {
790 struct brw_gs_prog_data prog_data = {};
791 struct anv_pipeline_binding surface_to_descriptor[256];
792 struct anv_pipeline_binding sampler_to_descriptor[256];
793
794 struct anv_pipeline_bind_map map = {
795 .surface_to_descriptor = surface_to_descriptor,
796 .sampler_to_descriptor = sampler_to_descriptor
797 };
798
799 void *mem_ctx = ralloc_context(NULL);
800
801 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
802 module, entrypoint,
803 MESA_SHADER_GEOMETRY, spec_info,
804 &prog_data.base.base, &map);
805 if (nir == NULL) {
806 ralloc_free(mem_ctx);
807 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
808 }
809
810 anv_fill_binding_table(&prog_data.base.base, 0);
811
812 brw_compute_vue_map(&pipeline->device->info,
813 &prog_data.base.vue_map,
814 nir->info.outputs_written,
815 nir->info.separate_shader);
816
817 const unsigned *shader_code =
818 brw_compile_gs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
819 NULL, -1, NULL);
820 if (shader_code == NULL) {
821 ralloc_free(mem_ctx);
822 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
823 }
824
825 /* TODO: SIMD8 GS */
826 const unsigned code_size = prog_data.base.base.program_size;
827 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
828 shader_code, code_size,
829 &prog_data.base.base, sizeof(prog_data),
830 &map);
831 if (!bin) {
832 ralloc_free(mem_ctx);
833 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
834 }
835
836 ralloc_free(mem_ctx);
837 }
838
839 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY, bin);
840
841 return VK_SUCCESS;
842 }
843
844 static VkResult
845 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
846 struct anv_pipeline_cache *cache,
847 const VkGraphicsPipelineCreateInfo *info,
848 struct anv_shader_module *module,
849 const char *entrypoint,
850 const VkSpecializationInfo *spec_info)
851 {
852 const struct brw_compiler *compiler =
853 pipeline->device->instance->physicalDevice.compiler;
854 struct brw_wm_prog_key key;
855 struct anv_shader_bin *bin = NULL;
856 unsigned char sha1[20];
857
858 populate_wm_prog_key(pipeline, info, &key);
859
860 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
861
862 if (cache) {
863 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
864 MESA_SHADER_FRAGMENT, spec_info,
865 &key, sizeof(key), sha1);
866 bin = anv_pipeline_cache_search(cache, sha1, 20);
867 }
868
869 if (bin == NULL) {
870 struct brw_wm_prog_data prog_data = {};
871 struct anv_pipeline_binding surface_to_descriptor[256];
872 struct anv_pipeline_binding sampler_to_descriptor[256];
873
874 struct anv_pipeline_bind_map map = {
875 .surface_to_descriptor = surface_to_descriptor + 8,
876 .sampler_to_descriptor = sampler_to_descriptor
877 };
878
879 void *mem_ctx = ralloc_context(NULL);
880
881 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
882 module, entrypoint,
883 MESA_SHADER_FRAGMENT, spec_info,
884 &prog_data.base, &map);
885 if (nir == NULL) {
886 ralloc_free(mem_ctx);
887 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
888 }
889
890 unsigned num_rts = 0;
891 const int max_rt = FRAG_RESULT_DATA7 - FRAG_RESULT_DATA0 + 1;
892 struct anv_pipeline_binding rt_bindings[max_rt];
893 nir_function_impl *impl = nir_shader_get_entrypoint(nir);
894 int rt_to_bindings[max_rt];
895 memset(rt_to_bindings, -1, sizeof(rt_to_bindings));
896 bool rt_used[max_rt];
897 memset(rt_used, 0, sizeof(rt_used));
898
899 /* Flag used render targets */
900 nir_foreach_variable_safe(var, &nir->outputs) {
901 if (var->data.location < FRAG_RESULT_DATA0)
902 continue;
903
904 const unsigned rt = var->data.location - FRAG_RESULT_DATA0;
905 /* Out-of-bounds */
906 if (rt >= key.nr_color_regions)
907 continue;
908
909 const unsigned array_len =
910 glsl_type_is_array(var->type) ? glsl_get_length(var->type) : 1;
911 assert(rt + array_len <= max_rt);
912
913 for (unsigned i = 0; i < array_len; i++)
914 rt_used[rt + i] = true;
915 }
916
917 /* Set new, compacted, location */
918 for (unsigned i = 0; i < max_rt; i++) {
919 if (!rt_used[i])
920 continue;
921
922 rt_to_bindings[i] = num_rts;
923 rt_bindings[rt_to_bindings[i]] = (struct anv_pipeline_binding) {
924 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
925 .binding = 0,
926 .index = i,
927 };
928 num_rts++;
929 }
930
931 nir_foreach_variable_safe(var, &nir->outputs) {
932 if (var->data.location < FRAG_RESULT_DATA0)
933 continue;
934
935 const unsigned rt = var->data.location - FRAG_RESULT_DATA0;
936 if (rt >= key.nr_color_regions) {
937 /* Out-of-bounds, throw it away */
938 var->data.mode = nir_var_local;
939 exec_node_remove(&var->node);
940 exec_list_push_tail(&impl->locals, &var->node);
941 continue;
942 }
943
944 /* Give it the new location */
945 assert(rt_to_bindings[rt] != -1);
946 var->data.location = rt_to_bindings[rt] + FRAG_RESULT_DATA0;
947 }
948
949 if (num_rts == 0) {
950 /* If we have no render targets, we need a null render target */
951 rt_bindings[0] = (struct anv_pipeline_binding) {
952 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
953 .binding = 0,
954 .index = UINT32_MAX,
955 };
956 num_rts = 1;
957 }
958
959 assert(num_rts <= max_rt);
960 map.surface_to_descriptor -= num_rts;
961 map.surface_count += num_rts;
962 assert(map.surface_count <= 256);
963 memcpy(map.surface_to_descriptor, rt_bindings,
964 num_rts * sizeof(*rt_bindings));
965
966 anv_fill_binding_table(&prog_data.base, num_rts);
967
968 const unsigned *shader_code =
969 brw_compile_fs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
970 NULL, -1, -1, true, false, NULL, NULL);
971 if (shader_code == NULL) {
972 ralloc_free(mem_ctx);
973 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
974 }
975
976 unsigned code_size = prog_data.base.program_size;
977 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
978 shader_code, code_size,
979 &prog_data.base, sizeof(prog_data),
980 &map);
981 if (!bin) {
982 ralloc_free(mem_ctx);
983 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
984 }
985
986 ralloc_free(mem_ctx);
987 }
988
989 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT, bin);
990
991 return VK_SUCCESS;
992 }
993
994 VkResult
995 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
996 struct anv_pipeline_cache *cache,
997 const VkComputePipelineCreateInfo *info,
998 struct anv_shader_module *module,
999 const char *entrypoint,
1000 const VkSpecializationInfo *spec_info)
1001 {
1002 const struct brw_compiler *compiler =
1003 pipeline->device->instance->physicalDevice.compiler;
1004 struct brw_cs_prog_key key;
1005 struct anv_shader_bin *bin = NULL;
1006 unsigned char sha1[20];
1007
1008 populate_cs_prog_key(&pipeline->device->info, &key);
1009
1010 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
1011
1012 if (cache) {
1013 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
1014 MESA_SHADER_COMPUTE, spec_info,
1015 &key, sizeof(key), sha1);
1016 bin = anv_pipeline_cache_search(cache, sha1, 20);
1017 }
1018
1019 if (bin == NULL) {
1020 struct brw_cs_prog_data prog_data = {};
1021 struct anv_pipeline_binding surface_to_descriptor[256];
1022 struct anv_pipeline_binding sampler_to_descriptor[256];
1023
1024 struct anv_pipeline_bind_map map = {
1025 .surface_to_descriptor = surface_to_descriptor,
1026 .sampler_to_descriptor = sampler_to_descriptor
1027 };
1028
1029 void *mem_ctx = ralloc_context(NULL);
1030
1031 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
1032 module, entrypoint,
1033 MESA_SHADER_COMPUTE, spec_info,
1034 &prog_data.base, &map);
1035 if (nir == NULL) {
1036 ralloc_free(mem_ctx);
1037 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1038 }
1039
1040 anv_fill_binding_table(&prog_data.base, 1);
1041
1042 const unsigned *shader_code =
1043 brw_compile_cs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
1044 -1, NULL);
1045 if (shader_code == NULL) {
1046 ralloc_free(mem_ctx);
1047 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1048 }
1049
1050 const unsigned code_size = prog_data.base.program_size;
1051 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
1052 shader_code, code_size,
1053 &prog_data.base, sizeof(prog_data),
1054 &map);
1055 if (!bin) {
1056 ralloc_free(mem_ctx);
1057 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1058 }
1059
1060 ralloc_free(mem_ctx);
1061 }
1062
1063 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE, bin);
1064
1065 return VK_SUCCESS;
1066 }
1067
1068 /**
1069 * Copy pipeline state not marked as dynamic.
1070 * Dynamic state is pipeline state which hasn't been provided at pipeline
1071 * creation time, but is dynamically provided afterwards using various
1072 * vkCmdSet* functions.
1073 *
1074 * The set of state considered "non_dynamic" is determined by the pieces of
1075 * state that have their corresponding VkDynamicState enums omitted from
1076 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1077 *
1078 * @param[out] pipeline Destination non_dynamic state.
1079 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1080 */
1081 static void
1082 copy_non_dynamic_state(struct anv_pipeline *pipeline,
1083 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1084 {
1085 anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
1086 struct anv_subpass *subpass = pipeline->subpass;
1087
1088 pipeline->dynamic_state = default_dynamic_state;
1089
1090 if (pCreateInfo->pDynamicState) {
1091 /* Remove all of the states that are marked as dynamic */
1092 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1093 for (uint32_t s = 0; s < count; s++)
1094 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1095 }
1096
1097 struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
1098
1099 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1100 *
1101 * pViewportState is [...] NULL if the pipeline
1102 * has rasterization disabled.
1103 */
1104 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1105 assert(pCreateInfo->pViewportState);
1106
1107 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1108 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1109 typed_memcpy(dynamic->viewport.viewports,
1110 pCreateInfo->pViewportState->pViewports,
1111 pCreateInfo->pViewportState->viewportCount);
1112 }
1113
1114 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1115 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1116 typed_memcpy(dynamic->scissor.scissors,
1117 pCreateInfo->pViewportState->pScissors,
1118 pCreateInfo->pViewportState->scissorCount);
1119 }
1120 }
1121
1122 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1123 assert(pCreateInfo->pRasterizationState);
1124 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1125 }
1126
1127 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1128 assert(pCreateInfo->pRasterizationState);
1129 dynamic->depth_bias.bias =
1130 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1131 dynamic->depth_bias.clamp =
1132 pCreateInfo->pRasterizationState->depthBiasClamp;
1133 dynamic->depth_bias.slope =
1134 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1135 }
1136
1137 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1138 *
1139 * pColorBlendState is [...] NULL if the pipeline has rasterization
1140 * disabled or if the subpass of the render pass the pipeline is
1141 * created against does not use any color attachments.
1142 */
1143 bool uses_color_att = false;
1144 for (unsigned i = 0; i < subpass->color_count; ++i) {
1145 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1146 uses_color_att = true;
1147 break;
1148 }
1149 }
1150
1151 if (uses_color_att &&
1152 !pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1153 assert(pCreateInfo->pColorBlendState);
1154
1155 if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
1156 typed_memcpy(dynamic->blend_constants,
1157 pCreateInfo->pColorBlendState->blendConstants, 4);
1158 }
1159
1160 /* If there is no depthstencil attachment, then don't read
1161 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1162 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1163 * no need to override the depthstencil defaults in
1164 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1165 *
1166 * Section 9.2 of the Vulkan 1.0.15 spec says:
1167 *
1168 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1169 * disabled or if the subpass of the render pass the pipeline is created
1170 * against does not use a depth/stencil attachment.
1171 */
1172 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1173 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1174 assert(pCreateInfo->pDepthStencilState);
1175
1176 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1177 dynamic->depth_bounds.min =
1178 pCreateInfo->pDepthStencilState->minDepthBounds;
1179 dynamic->depth_bounds.max =
1180 pCreateInfo->pDepthStencilState->maxDepthBounds;
1181 }
1182
1183 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1184 dynamic->stencil_compare_mask.front =
1185 pCreateInfo->pDepthStencilState->front.compareMask;
1186 dynamic->stencil_compare_mask.back =
1187 pCreateInfo->pDepthStencilState->back.compareMask;
1188 }
1189
1190 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1191 dynamic->stencil_write_mask.front =
1192 pCreateInfo->pDepthStencilState->front.writeMask;
1193 dynamic->stencil_write_mask.back =
1194 pCreateInfo->pDepthStencilState->back.writeMask;
1195 }
1196
1197 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1198 dynamic->stencil_reference.front =
1199 pCreateInfo->pDepthStencilState->front.reference;
1200 dynamic->stencil_reference.back =
1201 pCreateInfo->pDepthStencilState->back.reference;
1202 }
1203 }
1204
1205 pipeline->dynamic_state_mask = states;
1206 }
1207
1208 static void
1209 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
1210 {
1211 #ifdef DEBUG
1212 struct anv_render_pass *renderpass = NULL;
1213 struct anv_subpass *subpass = NULL;
1214
1215 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1216 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1217 */
1218 assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
1219
1220 renderpass = anv_render_pass_from_handle(info->renderPass);
1221 assert(renderpass);
1222
1223 assert(info->subpass < renderpass->subpass_count);
1224 subpass = &renderpass->subpasses[info->subpass];
1225
1226 assert(info->stageCount >= 1);
1227 assert(info->pVertexInputState);
1228 assert(info->pInputAssemblyState);
1229 assert(info->pRasterizationState);
1230 if (!info->pRasterizationState->rasterizerDiscardEnable) {
1231 assert(info->pViewportState);
1232 assert(info->pMultisampleState);
1233
1234 if (subpass && subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
1235 assert(info->pDepthStencilState);
1236
1237 if (subpass && subpass->color_count > 0)
1238 assert(info->pColorBlendState);
1239 }
1240
1241 for (uint32_t i = 0; i < info->stageCount; ++i) {
1242 switch (info->pStages[i].stage) {
1243 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
1244 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
1245 assert(info->pTessellationState);
1246 break;
1247 default:
1248 break;
1249 }
1250 }
1251 #endif
1252 }
1253
1254 /**
1255 * Calculate the desired L3 partitioning based on the current state of the
1256 * pipeline. For now this simply returns the conservative defaults calculated
1257 * by get_default_l3_weights(), but we could probably do better by gathering
1258 * more statistics from the pipeline state (e.g. guess of expected URB usage
1259 * and bound surfaces), or by using feed-back from performance counters.
1260 */
1261 void
1262 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm)
1263 {
1264 const struct gen_device_info *devinfo = &pipeline->device->info;
1265
1266 const struct gen_l3_weights w =
1267 gen_get_default_l3_weights(devinfo, pipeline->needs_data_cache, needs_slm);
1268
1269 pipeline->urb.l3_config = gen_get_l3_config(devinfo, w);
1270 pipeline->urb.total_size =
1271 gen_get_l3_config_urb_size(devinfo, pipeline->urb.l3_config);
1272 }
1273
1274 VkResult
1275 anv_pipeline_init(struct anv_pipeline *pipeline,
1276 struct anv_device *device,
1277 struct anv_pipeline_cache *cache,
1278 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1279 const VkAllocationCallbacks *alloc)
1280 {
1281 VkResult result;
1282
1283 anv_pipeline_validate_create_info(pCreateInfo);
1284
1285 if (alloc == NULL)
1286 alloc = &device->alloc;
1287
1288 pipeline->device = device;
1289
1290 ANV_FROM_HANDLE(anv_render_pass, render_pass, pCreateInfo->renderPass);
1291 assert(pCreateInfo->subpass < render_pass->subpass_count);
1292 pipeline->subpass = &render_pass->subpasses[pCreateInfo->subpass];
1293
1294 result = anv_reloc_list_init(&pipeline->batch_relocs, alloc);
1295 if (result != VK_SUCCESS)
1296 return result;
1297
1298 pipeline->batch.alloc = alloc;
1299 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
1300 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
1301 pipeline->batch.relocs = &pipeline->batch_relocs;
1302 pipeline->batch.status = VK_SUCCESS;
1303
1304 copy_non_dynamic_state(pipeline, pCreateInfo);
1305 pipeline->depth_clamp_enable = pCreateInfo->pRasterizationState &&
1306 pCreateInfo->pRasterizationState->depthClampEnable;
1307
1308 pipeline->sample_shading_enable = pCreateInfo->pMultisampleState &&
1309 pCreateInfo->pMultisampleState->sampleShadingEnable;
1310
1311 pipeline->needs_data_cache = false;
1312
1313 /* When we free the pipeline, we detect stages based on the NULL status
1314 * of various prog_data pointers. Make them NULL by default.
1315 */
1316 memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
1317
1318 pipeline->active_stages = 0;
1319
1320 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = {};
1321 struct anv_shader_module *modules[MESA_SHADER_STAGES] = {};
1322 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1323 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1324 pStages[stage] = &pCreateInfo->pStages[i];
1325 modules[stage] = anv_shader_module_from_handle(pStages[stage]->module);
1326 }
1327
1328 if (modules[MESA_SHADER_VERTEX]) {
1329 result = anv_pipeline_compile_vs(pipeline, cache, pCreateInfo,
1330 modules[MESA_SHADER_VERTEX],
1331 pStages[MESA_SHADER_VERTEX]->pName,
1332 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo);
1333 if (result != VK_SUCCESS)
1334 goto compile_fail;
1335 }
1336
1337 if (modules[MESA_SHADER_TESS_EVAL]) {
1338 anv_pipeline_compile_tcs_tes(pipeline, cache, pCreateInfo,
1339 modules[MESA_SHADER_TESS_CTRL],
1340 pStages[MESA_SHADER_TESS_CTRL]->pName,
1341 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
1342 modules[MESA_SHADER_TESS_EVAL],
1343 pStages[MESA_SHADER_TESS_EVAL]->pName,
1344 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo);
1345 }
1346
1347 if (modules[MESA_SHADER_GEOMETRY]) {
1348 result = anv_pipeline_compile_gs(pipeline, cache, pCreateInfo,
1349 modules[MESA_SHADER_GEOMETRY],
1350 pStages[MESA_SHADER_GEOMETRY]->pName,
1351 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo);
1352 if (result != VK_SUCCESS)
1353 goto compile_fail;
1354 }
1355
1356 if (modules[MESA_SHADER_FRAGMENT]) {
1357 result = anv_pipeline_compile_fs(pipeline, cache, pCreateInfo,
1358 modules[MESA_SHADER_FRAGMENT],
1359 pStages[MESA_SHADER_FRAGMENT]->pName,
1360 pStages[MESA_SHADER_FRAGMENT]->pSpecializationInfo);
1361 if (result != VK_SUCCESS)
1362 goto compile_fail;
1363 }
1364
1365 assert(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT);
1366
1367 anv_pipeline_setup_l3_config(pipeline, false);
1368
1369 const VkPipelineVertexInputStateCreateInfo *vi_info =
1370 pCreateInfo->pVertexInputState;
1371
1372 const uint64_t inputs_read = get_vs_prog_data(pipeline)->inputs_read;
1373
1374 pipeline->vb_used = 0;
1375 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1376 const VkVertexInputAttributeDescription *desc =
1377 &vi_info->pVertexAttributeDescriptions[i];
1378
1379 if (inputs_read & (1ull << (VERT_ATTRIB_GENERIC0 + desc->location)))
1380 pipeline->vb_used |= 1 << desc->binding;
1381 }
1382
1383 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1384 const VkVertexInputBindingDescription *desc =
1385 &vi_info->pVertexBindingDescriptions[i];
1386
1387 pipeline->binding_stride[desc->binding] = desc->stride;
1388
1389 /* Step rate is programmed per vertex element (attribute), not
1390 * binding. Set up a map of which bindings step per instance, for
1391 * reference by vertex element setup. */
1392 switch (desc->inputRate) {
1393 default:
1394 case VK_VERTEX_INPUT_RATE_VERTEX:
1395 pipeline->instancing_enable[desc->binding] = false;
1396 break;
1397 case VK_VERTEX_INPUT_RATE_INSTANCE:
1398 pipeline->instancing_enable[desc->binding] = true;
1399 break;
1400 }
1401 }
1402
1403 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1404 pCreateInfo->pInputAssemblyState;
1405 const VkPipelineTessellationStateCreateInfo *tess_info =
1406 pCreateInfo->pTessellationState;
1407 pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1408
1409 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
1410 pipeline->topology = _3DPRIM_PATCHLIST(tess_info->patchControlPoints);
1411 else
1412 pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1413
1414 return VK_SUCCESS;
1415
1416 compile_fail:
1417 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
1418 if (pipeline->shaders[s])
1419 anv_shader_bin_unref(device, pipeline->shaders[s]);
1420 }
1421
1422 anv_reloc_list_finish(&pipeline->batch_relocs, alloc);
1423
1424 return result;
1425 }