2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "common/gen_l3_config.h"
32 #include "anv_private.h"
33 #include "compiler/brw_nir.h"
35 #include "spirv/nir_spirv.h"
38 /* Needed for SWIZZLE macros */
39 #include "program/prog_instruction.h"
43 VkResult
anv_CreateShaderModule(
45 const VkShaderModuleCreateInfo
* pCreateInfo
,
46 const VkAllocationCallbacks
* pAllocator
,
47 VkShaderModule
* pShaderModule
)
49 ANV_FROM_HANDLE(anv_device
, device
, _device
);
50 struct anv_shader_module
*module
;
52 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
53 assert(pCreateInfo
->flags
== 0);
55 module
= vk_alloc2(&device
->alloc
, pAllocator
,
56 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
57 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
59 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
61 module
->size
= pCreateInfo
->codeSize
;
62 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
64 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
66 *pShaderModule
= anv_shader_module_to_handle(module
);
71 void anv_DestroyShaderModule(
73 VkShaderModule _module
,
74 const VkAllocationCallbacks
* pAllocator
)
76 ANV_FROM_HANDLE(anv_device
, device
, _device
);
77 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
82 vk_free2(&device
->alloc
, pAllocator
, module
);
85 #define SPIR_V_MAGIC_NUMBER 0x07230203
87 static const uint64_t stage_to_debug
[] = {
88 [MESA_SHADER_VERTEX
] = DEBUG_VS
,
89 [MESA_SHADER_TESS_CTRL
] = DEBUG_TCS
,
90 [MESA_SHADER_TESS_EVAL
] = DEBUG_TES
,
91 [MESA_SHADER_GEOMETRY
] = DEBUG_GS
,
92 [MESA_SHADER_FRAGMENT
] = DEBUG_WM
,
93 [MESA_SHADER_COMPUTE
] = DEBUG_CS
,
96 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
97 * we can't do that yet because we don't have the ability to copy nir.
100 anv_shader_compile_to_nir(struct anv_pipeline
*pipeline
,
102 const struct anv_shader_module
*module
,
103 const char *entrypoint_name
,
104 gl_shader_stage stage
,
105 const VkSpecializationInfo
*spec_info
)
107 const struct anv_device
*device
= pipeline
->device
;
109 const struct brw_compiler
*compiler
=
110 device
->instance
->physicalDevice
.compiler
;
111 const nir_shader_compiler_options
*nir_options
=
112 compiler
->glsl_compiler_options
[stage
].NirOptions
;
114 uint32_t *spirv
= (uint32_t *) module
->data
;
115 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
116 assert(module
->size
% 4 == 0);
118 uint32_t num_spec_entries
= 0;
119 struct nir_spirv_specialization
*spec_entries
= NULL
;
120 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
121 num_spec_entries
= spec_info
->mapEntryCount
;
122 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
123 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
124 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
125 const void *data
= spec_info
->pData
+ entry
.offset
;
126 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
128 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
129 if (spec_info
->dataSize
== 8)
130 spec_entries
[i
].data64
= *(const uint64_t *)data
;
132 spec_entries
[i
].data32
= *(const uint32_t *)data
;
136 struct spirv_to_nir_options spirv_options
= {
137 .lower_workgroup_access_to_offsets
= true,
139 .float64
= device
->instance
->physicalDevice
.info
.gen
>= 8,
140 .int64
= device
->instance
->physicalDevice
.info
.gen
>= 8,
141 .tessellation
= true,
142 .device_group
= true,
143 .draw_parameters
= true,
144 .image_write_without_format
= true,
146 .variable_pointers
= true,
147 .storage_16bit
= device
->instance
->physicalDevice
.info
.gen
>= 8,
148 .int16
= device
->instance
->physicalDevice
.info
.gen
>= 8,
149 .shader_viewport_index_layer
= true,
150 .subgroup_arithmetic
= true,
151 .subgroup_basic
= true,
152 .subgroup_ballot
= true,
153 .subgroup_quad
= true,
154 .subgroup_shuffle
= true,
155 .subgroup_vote
= true,
156 .stencil_export
= device
->instance
->physicalDevice
.info
.gen
>= 9,
157 .storage_8bit
= device
->instance
->physicalDevice
.info
.gen
>= 8,
158 .post_depth_coverage
= device
->instance
->physicalDevice
.info
.gen
>= 9,
162 nir_function
*entry_point
=
163 spirv_to_nir(spirv
, module
->size
/ 4,
164 spec_entries
, num_spec_entries
,
165 stage
, entrypoint_name
, &spirv_options
, nir_options
);
166 nir_shader
*nir
= entry_point
->shader
;
167 assert(nir
->info
.stage
== stage
);
168 nir_validate_shader(nir
);
169 ralloc_steal(mem_ctx
, nir
);
173 if (unlikely(INTEL_DEBUG
& stage_to_debug
[stage
])) {
174 fprintf(stderr
, "NIR (from SPIR-V) for %s shader:\n",
175 gl_shader_stage_name(stage
));
176 nir_print_shader(nir
, stderr
);
179 /* We have to lower away local constant initializers right before we
180 * inline functions. That way they get properly initialized at the top
181 * of the function and not at the top of its caller.
183 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_local
);
184 NIR_PASS_V(nir
, nir_lower_returns
);
185 NIR_PASS_V(nir
, nir_inline_functions
);
186 NIR_PASS_V(nir
, nir_copy_prop
);
188 /* Pick off the single entrypoint that we want */
189 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
190 if (func
!= entry_point
)
191 exec_node_remove(&func
->node
);
193 assert(exec_list_length(&nir
->functions
) == 1);
194 entry_point
->name
= ralloc_strdup(entry_point
, "main");
196 /* Now that we've deleted all but the main function, we can go ahead and
197 * lower the rest of the constant initializers. We do this here so that
198 * nir_remove_dead_variables and split_per_member_structs below see the
199 * corresponding stores.
201 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
203 /* Split member structs. We do this before lower_io_to_temporaries so that
204 * it doesn't lower system values to temporaries by accident.
206 NIR_PASS_V(nir
, nir_split_var_copies
);
207 NIR_PASS_V(nir
, nir_split_per_member_structs
);
209 NIR_PASS_V(nir
, nir_remove_dead_variables
,
210 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
212 if (stage
== MESA_SHADER_FRAGMENT
)
213 NIR_PASS_V(nir
, nir_lower_wpos_center
, pipeline
->sample_shading_enable
);
215 NIR_PASS_V(nir
, nir_propagate_invariant
);
216 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
217 entry_point
->impl
, true, false);
219 /* Vulkan uses the separate-shader linking model */
220 nir
->info
.separate_shader
= true;
222 nir
= brw_preprocess_nir(compiler
, nir
);
224 if (stage
== MESA_SHADER_FRAGMENT
)
225 NIR_PASS_V(nir
, anv_nir_lower_input_attachments
);
230 void anv_DestroyPipeline(
232 VkPipeline _pipeline
,
233 const VkAllocationCallbacks
* pAllocator
)
235 ANV_FROM_HANDLE(anv_device
, device
, _device
);
236 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
241 anv_reloc_list_finish(&pipeline
->batch_relocs
,
242 pAllocator
? pAllocator
: &device
->alloc
);
243 if (pipeline
->blend_state
.map
)
244 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
246 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
247 if (pipeline
->shaders
[s
])
248 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
251 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
254 static const uint32_t vk_to_gen_primitive_type
[] = {
255 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
256 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
257 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
258 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
259 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
260 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
261 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
262 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
263 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
264 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
268 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
269 struct brw_sampler_prog_key_data
*key
)
271 /* Almost all multisampled textures are compressed. The only time when we
272 * don't compress a multisampled texture is for 16x MSAA with a surface
273 * width greater than 8k which is a bit of an edge case. Since the sampler
274 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
275 * to tell the compiler to always assume compression.
277 key
->compressed_multisample_layout_mask
= ~0;
279 /* SkyLake added support for 16x MSAA. With this came a new message for
280 * reading from a 16x MSAA surface with compression. The new message was
281 * needed because now the MCS data is 64 bits instead of 32 or lower as is
282 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
283 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
284 * so we can just use it unconditionally. This may not be quite as
285 * efficient but it saves us from recompiling.
287 if (devinfo
->gen
>= 9)
290 /* XXX: Handle texture swizzle on HSW- */
291 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
292 /* Assume color sampler, no swizzling. (Works for BDW+) */
293 key
->swizzles
[i
] = SWIZZLE_XYZW
;
298 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
299 struct brw_vs_prog_key
*key
)
301 memset(key
, 0, sizeof(*key
));
303 populate_sampler_prog_key(devinfo
, &key
->tex
);
305 /* XXX: Handle vertex input work-arounds */
307 /* XXX: Handle sampler_prog_key */
311 populate_tcs_prog_key(const struct gen_device_info
*devinfo
,
312 unsigned input_vertices
,
313 struct brw_tcs_prog_key
*key
)
315 memset(key
, 0, sizeof(*key
));
317 populate_sampler_prog_key(devinfo
, &key
->tex
);
319 key
->input_vertices
= input_vertices
;
323 populate_tes_prog_key(const struct gen_device_info
*devinfo
,
324 struct brw_tes_prog_key
*key
)
326 memset(key
, 0, sizeof(*key
));
328 populate_sampler_prog_key(devinfo
, &key
->tex
);
332 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
333 struct brw_gs_prog_key
*key
)
335 memset(key
, 0, sizeof(*key
));
337 populate_sampler_prog_key(devinfo
, &key
->tex
);
341 populate_wm_prog_key(const struct gen_device_info
*devinfo
,
342 const struct anv_subpass
*subpass
,
343 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
344 struct brw_wm_prog_key
*key
)
346 memset(key
, 0, sizeof(*key
));
348 populate_sampler_prog_key(devinfo
, &key
->tex
);
350 /* We set this to 0 here and set to the actual value before we call
353 key
->input_slots_valid
= 0;
355 /* Vulkan doesn't specify a default */
356 key
->high_quality_derivatives
= false;
358 /* XXX Vulkan doesn't appear to specify */
359 key
->clamp_fragment_color
= false;
361 assert(subpass
->color_count
<= MAX_RTS
);
362 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
363 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
364 key
->color_outputs_valid
|= (1 << i
);
367 key
->nr_color_regions
= _mesa_bitcount(key
->color_outputs_valid
);
369 key
->replicate_alpha
= key
->nr_color_regions
> 1 &&
370 ms_info
&& ms_info
->alphaToCoverageEnable
;
373 /* We should probably pull this out of the shader, but it's fairly
374 * harmless to compute it and then let dead-code take care of it.
376 if (ms_info
->rasterizationSamples
> 1) {
377 key
->persample_interp
=
378 (ms_info
->minSampleShading
* ms_info
->rasterizationSamples
) > 1;
379 key
->multisample_fbo
= true;
382 key
->frag_coord_adds_sample_pos
= ms_info
->sampleShadingEnable
;
387 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
388 struct brw_cs_prog_key
*key
)
390 memset(key
, 0, sizeof(*key
));
392 populate_sampler_prog_key(devinfo
, &key
->tex
);
395 struct anv_pipeline_stage
{
396 gl_shader_stage stage
;
398 const struct anv_shader_module
*module
;
399 const char *entrypoint
;
400 const VkSpecializationInfo
*spec_info
;
402 union brw_any_prog_key key
;
405 gl_shader_stage stage
;
406 unsigned char sha1
[20];
411 struct anv_pipeline_binding surface_to_descriptor
[256];
412 struct anv_pipeline_binding sampler_to_descriptor
[256];
413 struct anv_pipeline_bind_map bind_map
;
415 union brw_any_prog_data prog_data
;
419 anv_pipeline_hash_shader(struct mesa_sha1
*ctx
,
420 struct anv_pipeline_stage
*stage
)
422 _mesa_sha1_update(ctx
, stage
->module
->sha1
, sizeof(stage
->module
->sha1
));
423 _mesa_sha1_update(ctx
, stage
->entrypoint
, strlen(stage
->entrypoint
));
424 _mesa_sha1_update(ctx
, &stage
->stage
, sizeof(stage
->stage
));
425 if (stage
->spec_info
) {
426 _mesa_sha1_update(ctx
, stage
->spec_info
->pMapEntries
,
427 stage
->spec_info
->mapEntryCount
*
428 sizeof(*stage
->spec_info
->pMapEntries
));
429 _mesa_sha1_update(ctx
, stage
->spec_info
->pData
,
430 stage
->spec_info
->dataSize
);
432 _mesa_sha1_update(ctx
, &stage
->key
, brw_prog_key_size(stage
->stage
));
436 anv_pipeline_hash_graphics(struct anv_pipeline
*pipeline
,
437 struct anv_pipeline_layout
*layout
,
438 struct anv_pipeline_stage
*stages
,
439 unsigned char *sha1_out
)
441 struct mesa_sha1 ctx
;
442 _mesa_sha1_init(&ctx
);
444 _mesa_sha1_update(&ctx
, &pipeline
->subpass
->view_mask
,
445 sizeof(pipeline
->subpass
->view_mask
));
448 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
450 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
451 if (stages
[s
].entrypoint
)
452 anv_pipeline_hash_shader(&ctx
, &stages
[s
]);
455 _mesa_sha1_final(&ctx
, sha1_out
);
459 anv_pipeline_hash_compute(struct anv_pipeline
*pipeline
,
460 struct anv_pipeline_layout
*layout
,
461 struct anv_pipeline_stage
*stage
,
462 unsigned char *sha1_out
)
464 struct mesa_sha1 ctx
;
465 _mesa_sha1_init(&ctx
);
468 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
470 anv_pipeline_hash_shader(&ctx
, stage
);
472 _mesa_sha1_final(&ctx
, sha1_out
);
476 anv_pipeline_compile(struct anv_pipeline
*pipeline
,
478 struct anv_pipeline_layout
*layout
,
479 struct anv_pipeline_stage
*stage
,
480 struct brw_stage_prog_data
*prog_data
,
481 struct anv_pipeline_bind_map
*map
)
483 const struct brw_compiler
*compiler
=
484 pipeline
->device
->instance
->physicalDevice
.compiler
;
486 nir_shader
*nir
= anv_shader_compile_to_nir(pipeline
, mem_ctx
,
494 NIR_PASS_V(nir
, anv_nir_lower_ycbcr_textures
, layout
);
496 NIR_PASS_V(nir
, anv_nir_lower_push_constants
);
498 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
499 NIR_PASS_V(nir
, anv_nir_lower_multiview
, pipeline
->subpass
->view_mask
);
501 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
502 prog_data
->total_shared
= nir
->num_shared
;
504 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
506 if (nir
->num_uniforms
> 0) {
507 assert(prog_data
->nr_params
== 0);
509 /* If the shader uses any push constants at all, we'll just give
510 * them the maximum possible number
512 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
513 nir
->num_uniforms
= MAX_PUSH_CONSTANTS_SIZE
;
514 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
515 prog_data
->param
= ralloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
517 /* We now set the param values to be offsets into a
518 * anv_push_constant_data structure. Since the compiler doesn't
519 * actually dereference any of the gl_constant_value pointers in the
520 * params array, it doesn't really matter what we put here.
522 struct anv_push_constants
*null_data
= NULL
;
523 /* Fill out the push constants section of the param array */
524 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++) {
525 prog_data
->param
[i
] = ANV_PARAM_PUSH(
526 (uintptr_t)&null_data
->client_data
[i
* sizeof(float)]);
530 if (nir
->info
.num_ssbos
> 0 || nir
->info
.num_images
> 0)
531 pipeline
->needs_data_cache
= true;
533 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
535 anv_nir_apply_pipeline_layout(pipeline
, layout
, nir
, prog_data
, map
);
537 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
538 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
540 assert(nir
->num_uniforms
== prog_data
->nr_params
* 4);
546 anv_fill_binding_table(struct brw_stage_prog_data
*prog_data
, unsigned bias
)
548 prog_data
->binding_table
.size_bytes
= 0;
549 prog_data
->binding_table
.texture_start
= bias
;
550 prog_data
->binding_table
.gather_texture_start
= bias
;
551 prog_data
->binding_table
.ubo_start
= bias
;
552 prog_data
->binding_table
.ssbo_start
= bias
;
553 prog_data
->binding_table
.image_start
= bias
;
557 anv_pipeline_link_vs(const struct brw_compiler
*compiler
,
558 struct anv_pipeline_stage
*vs_stage
,
559 struct anv_pipeline_stage
*next_stage
)
561 anv_fill_binding_table(&vs_stage
->prog_data
.vs
.base
.base
, 0);
564 brw_nir_link_shaders(compiler
, &vs_stage
->nir
, &next_stage
->nir
);
567 static const unsigned *
568 anv_pipeline_compile_vs(const struct brw_compiler
*compiler
,
570 struct anv_pipeline_stage
*vs_stage
)
572 brw_compute_vue_map(compiler
->devinfo
,
573 &vs_stage
->prog_data
.vs
.base
.vue_map
,
574 vs_stage
->nir
->info
.outputs_written
,
575 vs_stage
->nir
->info
.separate_shader
);
577 return brw_compile_vs(compiler
, NULL
, mem_ctx
, &vs_stage
->key
.vs
,
578 &vs_stage
->prog_data
.vs
, vs_stage
->nir
, -1, NULL
);
582 merge_tess_info(struct shader_info
*tes_info
,
583 const struct shader_info
*tcs_info
)
585 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
587 * "PointMode. Controls generation of points rather than triangles
588 * or lines. This functionality defaults to disabled, and is
589 * enabled if either shader stage includes the execution mode.
591 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
592 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
593 * and OutputVertices, it says:
595 * "One mode must be set in at least one of the tessellation
598 * So, the fields can be set in either the TCS or TES, but they must
599 * agree if set in both. Our backend looks at TES, so bitwise-or in
600 * the values from the TCS.
602 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
603 tes_info
->tess
.tcs_vertices_out
== 0 ||
604 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
605 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
607 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
608 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
609 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
610 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
612 assert(tcs_info
->tess
.primitive_mode
== 0 ||
613 tes_info
->tess
.primitive_mode
== 0 ||
614 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
615 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
616 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
617 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
621 anv_pipeline_link_tcs(const struct brw_compiler
*compiler
,
622 struct anv_pipeline_stage
*tcs_stage
,
623 struct anv_pipeline_stage
*tes_stage
)
625 assert(tes_stage
&& tes_stage
->stage
== MESA_SHADER_TESS_EVAL
);
627 anv_fill_binding_table(&tcs_stage
->prog_data
.tcs
.base
.base
, 0);
629 brw_nir_link_shaders(compiler
, &tcs_stage
->nir
, &tes_stage
->nir
);
631 nir_lower_patch_vertices(tes_stage
->nir
,
632 tcs_stage
->nir
->info
.tess
.tcs_vertices_out
,
635 /* Copy TCS info into the TES info */
636 merge_tess_info(&tes_stage
->nir
->info
, &tcs_stage
->nir
->info
);
638 anv_fill_binding_table(&tcs_stage
->prog_data
.tcs
.base
.base
, 0);
639 anv_fill_binding_table(&tes_stage
->prog_data
.tes
.base
.base
, 0);
641 /* Whacking the key after cache lookup is a bit sketchy, but all of
642 * this comes from the SPIR-V, which is part of the hash used for the
643 * pipeline cache. So it should be safe.
645 tcs_stage
->key
.tcs
.tes_primitive_mode
=
646 tes_stage
->nir
->info
.tess
.primitive_mode
;
647 tcs_stage
->key
.tcs
.quads_workaround
=
648 compiler
->devinfo
->gen
< 9 &&
649 tes_stage
->nir
->info
.tess
.primitive_mode
== 7 /* GL_QUADS */ &&
650 tes_stage
->nir
->info
.tess
.spacing
== TESS_SPACING_EQUAL
;
653 static const unsigned *
654 anv_pipeline_compile_tcs(const struct brw_compiler
*compiler
,
656 struct anv_pipeline_stage
*tcs_stage
,
657 struct anv_pipeline_stage
*prev_stage
)
659 tcs_stage
->key
.tcs
.outputs_written
=
660 tcs_stage
->nir
->info
.outputs_written
;
661 tcs_stage
->key
.tcs
.patch_outputs_written
=
662 tcs_stage
->nir
->info
.patch_outputs_written
;
664 return brw_compile_tcs(compiler
, NULL
, mem_ctx
, &tcs_stage
->key
.tcs
,
665 &tcs_stage
->prog_data
.tcs
, tcs_stage
->nir
,
670 anv_pipeline_link_tes(const struct brw_compiler
*compiler
,
671 struct anv_pipeline_stage
*tes_stage
,
672 struct anv_pipeline_stage
*next_stage
)
674 anv_fill_binding_table(&tes_stage
->prog_data
.tes
.base
.base
, 0);
677 brw_nir_link_shaders(compiler
, &tes_stage
->nir
, &next_stage
->nir
);
680 static const unsigned *
681 anv_pipeline_compile_tes(const struct brw_compiler
*compiler
,
683 struct anv_pipeline_stage
*tes_stage
,
684 struct anv_pipeline_stage
*tcs_stage
)
686 tes_stage
->key
.tes
.inputs_read
=
687 tcs_stage
->nir
->info
.outputs_written
;
688 tes_stage
->key
.tes
.patch_inputs_read
=
689 tcs_stage
->nir
->info
.patch_outputs_written
;
691 return brw_compile_tes(compiler
, NULL
, mem_ctx
, &tes_stage
->key
.tes
,
692 &tcs_stage
->prog_data
.tcs
.base
.vue_map
,
693 &tes_stage
->prog_data
.tes
, tes_stage
->nir
,
698 anv_pipeline_link_gs(const struct brw_compiler
*compiler
,
699 struct anv_pipeline_stage
*gs_stage
,
700 struct anv_pipeline_stage
*next_stage
)
702 anv_fill_binding_table(&gs_stage
->prog_data
.gs
.base
.base
, 0);
705 brw_nir_link_shaders(compiler
, &gs_stage
->nir
, &next_stage
->nir
);
708 static const unsigned *
709 anv_pipeline_compile_gs(const struct brw_compiler
*compiler
,
711 struct anv_pipeline_stage
*gs_stage
,
712 struct anv_pipeline_stage
*prev_stage
)
714 brw_compute_vue_map(compiler
->devinfo
,
715 &gs_stage
->prog_data
.gs
.base
.vue_map
,
716 gs_stage
->nir
->info
.outputs_written
,
717 gs_stage
->nir
->info
.separate_shader
);
719 return brw_compile_gs(compiler
, NULL
, mem_ctx
, &gs_stage
->key
.gs
,
720 &gs_stage
->prog_data
.gs
, gs_stage
->nir
,
725 anv_pipeline_link_fs(const struct brw_compiler
*compiler
,
726 struct anv_pipeline_stage
*stage
)
728 unsigned num_rts
= 0;
729 const int max_rt
= FRAG_RESULT_DATA7
- FRAG_RESULT_DATA0
+ 1;
730 struct anv_pipeline_binding rt_bindings
[max_rt
];
731 nir_function_impl
*impl
= nir_shader_get_entrypoint(stage
->nir
);
732 int rt_to_bindings
[max_rt
];
733 memset(rt_to_bindings
, -1, sizeof(rt_to_bindings
));
734 bool rt_used
[max_rt
];
735 memset(rt_used
, 0, sizeof(rt_used
));
737 /* Flag used render targets */
738 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
739 if (var
->data
.location
< FRAG_RESULT_DATA0
)
742 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
743 /* Unused or out-of-bounds */
744 if (rt
>= MAX_RTS
|| !(stage
->key
.wm
.color_outputs_valid
& (1 << rt
)))
747 const unsigned array_len
=
748 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
749 assert(rt
+ array_len
<= max_rt
);
751 for (unsigned i
= 0; i
< array_len
; i
++)
752 rt_used
[rt
+ i
] = true;
755 /* Set new, compacted, location */
756 for (unsigned i
= 0; i
< max_rt
; i
++) {
760 rt_to_bindings
[i
] = num_rts
;
761 rt_bindings
[rt_to_bindings
[i
]] = (struct anv_pipeline_binding
) {
762 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
769 bool deleted_output
= false;
770 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
771 if (var
->data
.location
< FRAG_RESULT_DATA0
)
774 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
776 !(stage
->key
.wm
.color_outputs_valid
& (1 << rt
))) {
777 /* Unused or out-of-bounds, throw it away */
778 deleted_output
= true;
779 var
->data
.mode
= nir_var_local
;
780 exec_node_remove(&var
->node
);
781 exec_list_push_tail(&impl
->locals
, &var
->node
);
785 /* Give it the new location */
786 assert(rt_to_bindings
[rt
] != -1);
787 var
->data
.location
= rt_to_bindings
[rt
] + FRAG_RESULT_DATA0
;
791 nir_fixup_deref_modes(stage
->nir
);
794 /* If we have no render targets, we need a null render target */
795 rt_bindings
[0] = (struct anv_pipeline_binding
) {
796 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
803 /* Now that we've determined the actual number of render targets, adjust
804 * the key accordingly.
806 stage
->key
.wm
.nr_color_regions
= num_rts
;
807 stage
->key
.wm
.color_outputs_valid
= (1 << num_rts
) - 1;
809 assert(num_rts
<= max_rt
);
810 assert(stage
->bind_map
.surface_count
+ num_rts
<= 256);
811 memmove(stage
->bind_map
.surface_to_descriptor
+ num_rts
,
812 stage
->bind_map
.surface_to_descriptor
,
813 stage
->bind_map
.surface_count
*
814 sizeof(*stage
->bind_map
.surface_to_descriptor
));
815 typed_memcpy(stage
->bind_map
.surface_to_descriptor
,
816 rt_bindings
, num_rts
);
817 stage
->bind_map
.surface_count
+= num_rts
;
819 anv_fill_binding_table(&stage
->prog_data
.wm
.base
, num_rts
);
822 static const unsigned *
823 anv_pipeline_compile_fs(const struct brw_compiler
*compiler
,
825 struct anv_pipeline_stage
*fs_stage
,
826 struct anv_pipeline_stage
*prev_stage
)
828 /* TODO: we could set this to 0 based on the information in nir_shader, but
829 * we need this before we call spirv_to_nir.
832 fs_stage
->key
.wm
.input_slots_valid
=
833 prev_stage
->prog_data
.vue
.vue_map
.slots_valid
;
835 const unsigned *code
=
836 brw_compile_fs(compiler
, NULL
, mem_ctx
, &fs_stage
->key
.wm
,
837 &fs_stage
->prog_data
.wm
, fs_stage
->nir
,
838 NULL
, -1, -1, -1, true, false, NULL
, NULL
);
840 if (fs_stage
->key
.wm
.nr_color_regions
== 0 &&
841 !fs_stage
->prog_data
.wm
.has_side_effects
&&
842 !fs_stage
->prog_data
.wm
.uses_kill
&&
843 fs_stage
->prog_data
.wm
.computed_depth_mode
== BRW_PSCDEPTH_OFF
&&
844 !fs_stage
->prog_data
.wm
.computed_stencil
) {
845 /* This fragment shader has no outputs and no side effects. Go ahead
846 * and return the code pointer so we don't accidentally think the
847 * compile failed but zero out prog_data which will set program_size to
848 * zero and disable the stage.
850 memset(&fs_stage
->prog_data
, 0, sizeof(fs_stage
->prog_data
));
857 anv_pipeline_compile_graphics(struct anv_pipeline
*pipeline
,
858 struct anv_pipeline_cache
*cache
,
859 const VkGraphicsPipelineCreateInfo
*info
)
861 const struct brw_compiler
*compiler
=
862 pipeline
->device
->instance
->physicalDevice
.compiler
;
863 struct anv_pipeline_stage stages
[MESA_SHADER_STAGES
] = {};
865 pipeline
->active_stages
= 0;
868 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
869 const VkPipelineShaderStageCreateInfo
*sinfo
= &info
->pStages
[i
];
870 gl_shader_stage stage
= vk_to_mesa_shader_stage(sinfo
->stage
);
872 pipeline
->active_stages
|= sinfo
->stage
;
874 stages
[stage
].stage
= stage
;
875 stages
[stage
].module
= anv_shader_module_from_handle(sinfo
->module
);
876 stages
[stage
].entrypoint
= sinfo
->pName
;
877 stages
[stage
].spec_info
= sinfo
->pSpecializationInfo
;
879 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
881 case MESA_SHADER_VERTEX
:
882 populate_vs_prog_key(devinfo
, &stages
[stage
].key
.vs
);
884 case MESA_SHADER_TESS_CTRL
:
885 populate_tcs_prog_key(devinfo
,
886 info
->pTessellationState
->patchControlPoints
,
887 &stages
[stage
].key
.tcs
);
889 case MESA_SHADER_TESS_EVAL
:
890 populate_tes_prog_key(devinfo
, &stages
[stage
].key
.tes
);
892 case MESA_SHADER_GEOMETRY
:
893 populate_gs_prog_key(devinfo
, &stages
[stage
].key
.gs
);
895 case MESA_SHADER_FRAGMENT
:
896 populate_wm_prog_key(devinfo
, pipeline
->subpass
,
897 info
->pMultisampleState
,
898 &stages
[stage
].key
.wm
);
901 unreachable("Invalid graphics shader stage");
905 if (pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
)
906 pipeline
->active_stages
|= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
908 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
910 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
912 unsigned char sha1
[20];
913 anv_pipeline_hash_graphics(pipeline
, layout
, stages
, sha1
);
916 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
917 if (!stages
[s
].entrypoint
)
920 stages
[s
].cache_key
.stage
= s
;
921 memcpy(stages
[s
].cache_key
.sha1
, sha1
, sizeof(sha1
));
923 struct anv_shader_bin
*bin
=
924 anv_device_search_for_kernel(pipeline
->device
, cache
,
925 &stages
[s
].cache_key
,
926 sizeof(stages
[s
].cache_key
));
929 pipeline
->shaders
[s
] = bin
;
933 if (found
== __builtin_popcount(pipeline
->active_stages
)) {
934 /* We found all our shaders in the cache. We're done. */
936 } else if (found
> 0) {
937 /* We found some but not all of our shaders. This shouldn't happen
938 * most of the time but it can if we have a partially populated
941 assert(found
< __builtin_popcount(pipeline
->active_stages
));
943 vk_debug_report(&pipeline
->device
->instance
->debug_report_callbacks
,
944 VK_DEBUG_REPORT_WARNING_BIT_EXT
|
945 VK_DEBUG_REPORT_PERFORMANCE_WARNING_BIT_EXT
,
946 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT
,
947 (uint64_t)(uintptr_t)cache
,
949 "Found a partial pipeline in the cache. This is "
950 "most likely caused by an incomplete pipeline cache "
953 /* We're going to have to recompile anyway, so just throw away our
954 * references to the shaders in the cache. We'll get them out of the
955 * cache again as part of the compilation process.
957 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
958 if (pipeline
->shaders
[s
]) {
959 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
960 pipeline
->shaders
[s
] = NULL
;
965 void *pipeline_ctx
= ralloc_context(NULL
);
967 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
968 if (!stages
[s
].entrypoint
)
971 assert(stages
[s
].stage
== s
);
972 assert(pipeline
->shaders
[s
] == NULL
);
974 stages
[s
].bind_map
= (struct anv_pipeline_bind_map
) {
975 .surface_to_descriptor
= stages
[s
].surface_to_descriptor
,
976 .sampler_to_descriptor
= stages
[s
].sampler_to_descriptor
979 stages
[s
].nir
= anv_pipeline_compile(pipeline
, pipeline_ctx
, layout
,
981 &stages
[s
].prog_data
.base
,
982 &stages
[s
].bind_map
);
983 if (stages
[s
].nir
== NULL
) {
984 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
989 /* Walk backwards to link */
990 struct anv_pipeline_stage
*next_stage
= NULL
;
991 for (int s
= MESA_SHADER_STAGES
- 1; s
>= 0; s
--) {
992 if (!stages
[s
].entrypoint
)
996 case MESA_SHADER_VERTEX
:
997 anv_pipeline_link_vs(compiler
, &stages
[s
], next_stage
);
999 case MESA_SHADER_TESS_CTRL
:
1000 anv_pipeline_link_tcs(compiler
, &stages
[s
], next_stage
);
1002 case MESA_SHADER_TESS_EVAL
:
1003 anv_pipeline_link_tes(compiler
, &stages
[s
], next_stage
);
1005 case MESA_SHADER_GEOMETRY
:
1006 anv_pipeline_link_gs(compiler
, &stages
[s
], next_stage
);
1008 case MESA_SHADER_FRAGMENT
:
1009 anv_pipeline_link_fs(compiler
, &stages
[s
]);
1012 unreachable("Invalid graphics shader stage");
1015 next_stage
= &stages
[s
];
1018 struct anv_pipeline_stage
*prev_stage
= NULL
;
1019 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1020 if (!stages
[s
].entrypoint
)
1023 void *stage_ctx
= ralloc_context(NULL
);
1025 const unsigned *code
;
1027 case MESA_SHADER_VERTEX
:
1028 code
= anv_pipeline_compile_vs(compiler
, stage_ctx
, &stages
[s
]);
1030 case MESA_SHADER_TESS_CTRL
:
1031 code
= anv_pipeline_compile_tcs(compiler
, stage_ctx
,
1032 &stages
[s
], prev_stage
);
1034 case MESA_SHADER_TESS_EVAL
:
1035 code
= anv_pipeline_compile_tes(compiler
, stage_ctx
,
1036 &stages
[s
], prev_stage
);
1038 case MESA_SHADER_GEOMETRY
:
1039 code
= anv_pipeline_compile_gs(compiler
, stage_ctx
,
1040 &stages
[s
], prev_stage
);
1042 case MESA_SHADER_FRAGMENT
:
1043 code
= anv_pipeline_compile_fs(compiler
, stage_ctx
,
1044 &stages
[s
], prev_stage
);
1047 unreachable("Invalid graphics shader stage");
1050 ralloc_free(stage_ctx
);
1051 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1055 struct anv_shader_bin
*bin
=
1056 anv_device_upload_kernel(pipeline
->device
, cache
,
1057 &stages
[s
].cache_key
,
1058 sizeof(stages
[s
].cache_key
),
1059 code
, stages
[s
].prog_data
.base
.program_size
,
1060 stages
[s
].nir
->constant_data
,
1061 stages
[s
].nir
->constant_data_size
,
1062 &stages
[s
].prog_data
.base
,
1063 brw_prog_data_size(s
),
1064 &stages
[s
].bind_map
);
1066 ralloc_free(stage_ctx
);
1067 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1071 pipeline
->shaders
[s
] = bin
;
1072 ralloc_free(stage_ctx
);
1074 prev_stage
= &stages
[s
];
1077 ralloc_free(pipeline_ctx
);
1081 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
] &&
1082 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->prog_data
->program_size
== 0) {
1083 /* This can happen if we decided to implicitly disable the fragment
1084 * shader. See anv_pipeline_compile_fs().
1086 anv_shader_bin_unref(pipeline
->device
,
1087 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
1088 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] = NULL
;
1089 pipeline
->active_stages
&= ~VK_SHADER_STAGE_FRAGMENT_BIT
;
1095 ralloc_free(pipeline_ctx
);
1097 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1098 if (pipeline
->shaders
[s
])
1099 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1106 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1107 struct anv_pipeline_cache
*cache
,
1108 const VkComputePipelineCreateInfo
*info
,
1109 const struct anv_shader_module
*module
,
1110 const char *entrypoint
,
1111 const VkSpecializationInfo
*spec_info
)
1113 const struct brw_compiler
*compiler
=
1114 pipeline
->device
->instance
->physicalDevice
.compiler
;
1116 struct anv_pipeline_stage stage
= {
1117 .stage
= MESA_SHADER_COMPUTE
,
1119 .entrypoint
= entrypoint
,
1120 .spec_info
= spec_info
,
1122 .stage
= MESA_SHADER_COMPUTE
,
1126 struct anv_shader_bin
*bin
= NULL
;
1128 populate_cs_prog_key(&pipeline
->device
->info
, &stage
.key
.cs
);
1130 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1132 anv_pipeline_hash_compute(pipeline
, layout
, &stage
, stage
.cache_key
.sha1
);
1133 bin
= anv_device_search_for_kernel(pipeline
->device
, cache
, &stage
.cache_key
,
1134 sizeof(stage
.cache_key
));
1137 stage
.bind_map
= (struct anv_pipeline_bind_map
) {
1138 .surface_to_descriptor
= stage
.surface_to_descriptor
,
1139 .sampler_to_descriptor
= stage
.sampler_to_descriptor
1142 void *mem_ctx
= ralloc_context(NULL
);
1144 stage
.nir
= anv_pipeline_compile(pipeline
, mem_ctx
, layout
, &stage
,
1145 &stage
.prog_data
.base
,
1147 if (stage
.nir
== NULL
) {
1148 ralloc_free(mem_ctx
);
1149 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1152 NIR_PASS_V(stage
.nir
, anv_nir_add_base_work_group_id
,
1153 &stage
.prog_data
.cs
);
1155 anv_fill_binding_table(&stage
.prog_data
.cs
.base
, 1);
1157 const unsigned *shader_code
=
1158 brw_compile_cs(compiler
, NULL
, mem_ctx
, &stage
.key
.cs
,
1159 &stage
.prog_data
.cs
, stage
.nir
, -1, NULL
);
1160 if (shader_code
== NULL
) {
1161 ralloc_free(mem_ctx
);
1162 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1165 const unsigned code_size
= stage
.prog_data
.base
.program_size
;
1166 bin
= anv_device_upload_kernel(pipeline
->device
, cache
,
1167 &stage
.cache_key
, sizeof(stage
.cache_key
),
1168 shader_code
, code_size
,
1169 stage
.nir
->constant_data
,
1170 stage
.nir
->constant_data_size
,
1171 &stage
.prog_data
.base
,
1172 sizeof(stage
.prog_data
.cs
),
1175 ralloc_free(mem_ctx
);
1176 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1179 ralloc_free(mem_ctx
);
1182 pipeline
->active_stages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1183 pipeline
->shaders
[MESA_SHADER_COMPUTE
] = bin
;
1189 * Copy pipeline state not marked as dynamic.
1190 * Dynamic state is pipeline state which hasn't been provided at pipeline
1191 * creation time, but is dynamically provided afterwards using various
1192 * vkCmdSet* functions.
1194 * The set of state considered "non_dynamic" is determined by the pieces of
1195 * state that have their corresponding VkDynamicState enums omitted from
1196 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1198 * @param[out] pipeline Destination non_dynamic state.
1199 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1202 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
1203 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1205 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
1206 struct anv_subpass
*subpass
= pipeline
->subpass
;
1208 pipeline
->dynamic_state
= default_dynamic_state
;
1210 if (pCreateInfo
->pDynamicState
) {
1211 /* Remove all of the states that are marked as dynamic */
1212 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1213 for (uint32_t s
= 0; s
< count
; s
++)
1214 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1217 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1219 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1221 * pViewportState is [...] NULL if the pipeline
1222 * has rasterization disabled.
1224 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1225 assert(pCreateInfo
->pViewportState
);
1227 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1228 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
1229 typed_memcpy(dynamic
->viewport
.viewports
,
1230 pCreateInfo
->pViewportState
->pViewports
,
1231 pCreateInfo
->pViewportState
->viewportCount
);
1234 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1235 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
1236 typed_memcpy(dynamic
->scissor
.scissors
,
1237 pCreateInfo
->pViewportState
->pScissors
,
1238 pCreateInfo
->pViewportState
->scissorCount
);
1242 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1243 assert(pCreateInfo
->pRasterizationState
);
1244 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1247 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1248 assert(pCreateInfo
->pRasterizationState
);
1249 dynamic
->depth_bias
.bias
=
1250 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1251 dynamic
->depth_bias
.clamp
=
1252 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1253 dynamic
->depth_bias
.slope
=
1254 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1257 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1259 * pColorBlendState is [...] NULL if the pipeline has rasterization
1260 * disabled or if the subpass of the render pass the pipeline is
1261 * created against does not use any color attachments.
1263 bool uses_color_att
= false;
1264 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1265 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1266 uses_color_att
= true;
1271 if (uses_color_att
&&
1272 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1273 assert(pCreateInfo
->pColorBlendState
);
1275 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
1276 typed_memcpy(dynamic
->blend_constants
,
1277 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1280 /* If there is no depthstencil attachment, then don't read
1281 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1282 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1283 * no need to override the depthstencil defaults in
1284 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1286 * Section 9.2 of the Vulkan 1.0.15 spec says:
1288 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1289 * disabled or if the subpass of the render pass the pipeline is created
1290 * against does not use a depth/stencil attachment.
1292 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1293 subpass
->depth_stencil_attachment
) {
1294 assert(pCreateInfo
->pDepthStencilState
);
1296 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1297 dynamic
->depth_bounds
.min
=
1298 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1299 dynamic
->depth_bounds
.max
=
1300 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1303 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1304 dynamic
->stencil_compare_mask
.front
=
1305 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1306 dynamic
->stencil_compare_mask
.back
=
1307 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1310 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1311 dynamic
->stencil_write_mask
.front
=
1312 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1313 dynamic
->stencil_write_mask
.back
=
1314 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1317 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1318 dynamic
->stencil_reference
.front
=
1319 pCreateInfo
->pDepthStencilState
->front
.reference
;
1320 dynamic
->stencil_reference
.back
=
1321 pCreateInfo
->pDepthStencilState
->back
.reference
;
1325 pipeline
->dynamic_state_mask
= states
;
1329 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1332 struct anv_render_pass
*renderpass
= NULL
;
1333 struct anv_subpass
*subpass
= NULL
;
1335 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1336 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1338 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1340 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1343 assert(info
->subpass
< renderpass
->subpass_count
);
1344 subpass
= &renderpass
->subpasses
[info
->subpass
];
1346 assert(info
->stageCount
>= 1);
1347 assert(info
->pVertexInputState
);
1348 assert(info
->pInputAssemblyState
);
1349 assert(info
->pRasterizationState
);
1350 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1351 assert(info
->pViewportState
);
1352 assert(info
->pMultisampleState
);
1354 if (subpass
&& subpass
->depth_stencil_attachment
)
1355 assert(info
->pDepthStencilState
);
1357 if (subpass
&& subpass
->color_count
> 0) {
1358 bool all_color_unused
= true;
1359 for (int i
= 0; i
< subpass
->color_count
; i
++) {
1360 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
1361 all_color_unused
= false;
1363 /* pColorBlendState is ignored if the pipeline has rasterization
1364 * disabled or if the subpass of the render pass the pipeline is
1365 * created against does not use any color attachments.
1367 assert(info
->pColorBlendState
|| all_color_unused
);
1371 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1372 switch (info
->pStages
[i
].stage
) {
1373 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1374 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1375 assert(info
->pTessellationState
);
1385 * Calculate the desired L3 partitioning based on the current state of the
1386 * pipeline. For now this simply returns the conservative defaults calculated
1387 * by get_default_l3_weights(), but we could probably do better by gathering
1388 * more statistics from the pipeline state (e.g. guess of expected URB usage
1389 * and bound surfaces), or by using feed-back from performance counters.
1392 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1394 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1396 const struct gen_l3_weights w
=
1397 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
1399 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
1400 pipeline
->urb
.total_size
=
1401 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
1405 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1406 struct anv_device
*device
,
1407 struct anv_pipeline_cache
*cache
,
1408 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1409 const VkAllocationCallbacks
*alloc
)
1413 anv_pipeline_validate_create_info(pCreateInfo
);
1416 alloc
= &device
->alloc
;
1418 pipeline
->device
= device
;
1420 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, pCreateInfo
->renderPass
);
1421 assert(pCreateInfo
->subpass
< render_pass
->subpass_count
);
1422 pipeline
->subpass
= &render_pass
->subpasses
[pCreateInfo
->subpass
];
1424 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1425 if (result
!= VK_SUCCESS
)
1428 pipeline
->batch
.alloc
= alloc
;
1429 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1430 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1431 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1432 pipeline
->batch
.status
= VK_SUCCESS
;
1434 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1435 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1436 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1438 pipeline
->sample_shading_enable
= pCreateInfo
->pMultisampleState
&&
1439 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
1441 pipeline
->needs_data_cache
= false;
1443 /* When we free the pipeline, we detect stages based on the NULL status
1444 * of various prog_data pointers. Make them NULL by default.
1446 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1448 result
= anv_pipeline_compile_graphics(pipeline
, cache
, pCreateInfo
);
1449 if (result
!= VK_SUCCESS
) {
1450 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);
1454 assert(pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1456 anv_pipeline_setup_l3_config(pipeline
, false);
1458 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1459 pCreateInfo
->pVertexInputState
;
1461 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1463 pipeline
->vb_used
= 0;
1464 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1465 const VkVertexInputAttributeDescription
*desc
=
1466 &vi_info
->pVertexAttributeDescriptions
[i
];
1468 if (inputs_read
& (1ull << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1469 pipeline
->vb_used
|= 1 << desc
->binding
;
1472 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1473 const VkVertexInputBindingDescription
*desc
=
1474 &vi_info
->pVertexBindingDescriptions
[i
];
1476 pipeline
->vb
[desc
->binding
].stride
= desc
->stride
;
1478 /* Step rate is programmed per vertex element (attribute), not
1479 * binding. Set up a map of which bindings step per instance, for
1480 * reference by vertex element setup. */
1481 switch (desc
->inputRate
) {
1483 case VK_VERTEX_INPUT_RATE_VERTEX
:
1484 pipeline
->vb
[desc
->binding
].instanced
= false;
1486 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1487 pipeline
->vb
[desc
->binding
].instanced
= true;
1491 pipeline
->vb
[desc
->binding
].instance_divisor
= 1;
1494 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*vi_div_state
=
1495 vk_find_struct_const(vi_info
->pNext
,
1496 PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
1498 for (uint32_t i
= 0; i
< vi_div_state
->vertexBindingDivisorCount
; i
++) {
1499 const VkVertexInputBindingDivisorDescriptionEXT
*desc
=
1500 &vi_div_state
->pVertexBindingDivisors
[i
];
1502 pipeline
->vb
[desc
->binding
].instance_divisor
= desc
->divisor
;
1506 /* Our implementation of VK_KHR_multiview uses instancing to draw the
1507 * different views. If the client asks for instancing, we need to multiply
1508 * the instance divisor by the number of views ensure that we repeat the
1509 * client's per-instance data once for each view.
1511 if (pipeline
->subpass
->view_mask
) {
1512 const uint32_t view_count
= anv_subpass_view_count(pipeline
->subpass
);
1513 for (uint32_t vb
= 0; vb
< MAX_VBS
; vb
++) {
1514 if (pipeline
->vb
[vb
].instanced
)
1515 pipeline
->vb
[vb
].instance_divisor
*= view_count
;
1519 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1520 pCreateInfo
->pInputAssemblyState
;
1521 const VkPipelineTessellationStateCreateInfo
*tess_info
=
1522 pCreateInfo
->pTessellationState
;
1523 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1525 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1526 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
1528 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];