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anv/pipeline: set active_stages early
[mesa.git] / src / intel / vulkan / anv_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "util/mesa-sha1.h"
31 #include "common/gen_l3_config.h"
32 #include "anv_private.h"
33 #include "compiler/brw_nir.h"
34 #include "anv_nir.h"
35 #include "spirv/nir_spirv.h"
36
37 /* Needed for SWIZZLE macros */
38 #include "program/prog_instruction.h"
39
40 // Shader functions
41
42 VkResult anv_CreateShaderModule(
43 VkDevice _device,
44 const VkShaderModuleCreateInfo* pCreateInfo,
45 const VkAllocationCallbacks* pAllocator,
46 VkShaderModule* pShaderModule)
47 {
48 ANV_FROM_HANDLE(anv_device, device, _device);
49 struct anv_shader_module *module;
50
51 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
52 assert(pCreateInfo->flags == 0);
53
54 module = vk_alloc2(&device->alloc, pAllocator,
55 sizeof(*module) + pCreateInfo->codeSize, 8,
56 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
57 if (module == NULL)
58 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
59
60 module->size = pCreateInfo->codeSize;
61 memcpy(module->data, pCreateInfo->pCode, module->size);
62
63 _mesa_sha1_compute(module->data, module->size, module->sha1);
64
65 *pShaderModule = anv_shader_module_to_handle(module);
66
67 return VK_SUCCESS;
68 }
69
70 void anv_DestroyShaderModule(
71 VkDevice _device,
72 VkShaderModule _module,
73 const VkAllocationCallbacks* pAllocator)
74 {
75 ANV_FROM_HANDLE(anv_device, device, _device);
76 ANV_FROM_HANDLE(anv_shader_module, module, _module);
77
78 if (!module)
79 return;
80
81 vk_free2(&device->alloc, pAllocator, module);
82 }
83
84 #define SPIR_V_MAGIC_NUMBER 0x07230203
85
86 static const uint64_t stage_to_debug[] = {
87 [MESA_SHADER_VERTEX] = DEBUG_VS,
88 [MESA_SHADER_TESS_CTRL] = DEBUG_TCS,
89 [MESA_SHADER_TESS_EVAL] = DEBUG_TES,
90 [MESA_SHADER_GEOMETRY] = DEBUG_GS,
91 [MESA_SHADER_FRAGMENT] = DEBUG_WM,
92 [MESA_SHADER_COMPUTE] = DEBUG_CS,
93 };
94
95 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
96 * we can't do that yet because we don't have the ability to copy nir.
97 */
98 static nir_shader *
99 anv_shader_compile_to_nir(struct anv_pipeline *pipeline,
100 void *mem_ctx,
101 struct anv_shader_module *module,
102 const char *entrypoint_name,
103 gl_shader_stage stage,
104 const VkSpecializationInfo *spec_info)
105 {
106 const struct anv_device *device = pipeline->device;
107
108 const struct brw_compiler *compiler =
109 device->instance->physicalDevice.compiler;
110 const nir_shader_compiler_options *nir_options =
111 compiler->glsl_compiler_options[stage].NirOptions;
112
113 uint32_t *spirv = (uint32_t *) module->data;
114 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
115 assert(module->size % 4 == 0);
116
117 uint32_t num_spec_entries = 0;
118 struct nir_spirv_specialization *spec_entries = NULL;
119 if (spec_info && spec_info->mapEntryCount > 0) {
120 num_spec_entries = spec_info->mapEntryCount;
121 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
122 for (uint32_t i = 0; i < num_spec_entries; i++) {
123 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
124 const void *data = spec_info->pData + entry.offset;
125 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
126
127 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
128 if (spec_info->dataSize == 8)
129 spec_entries[i].data64 = *(const uint64_t *)data;
130 else
131 spec_entries[i].data32 = *(const uint32_t *)data;
132 }
133 }
134
135 struct spirv_to_nir_options spirv_options = {
136 .lower_workgroup_access_to_offsets = true,
137 .caps = {
138 .float64 = device->instance->physicalDevice.info.gen >= 8,
139 .int64 = device->instance->physicalDevice.info.gen >= 8,
140 .tessellation = true,
141 .device_group = true,
142 .draw_parameters = true,
143 .image_write_without_format = true,
144 .multiview = true,
145 .variable_pointers = true,
146 .storage_16bit = device->instance->physicalDevice.info.gen >= 8,
147 .subgroup_arithmetic = true,
148 .subgroup_basic = true,
149 .subgroup_ballot = true,
150 .subgroup_quad = true,
151 .subgroup_shuffle = true,
152 .subgroup_vote = true,
153 },
154 };
155
156 nir_function *entry_point =
157 spirv_to_nir(spirv, module->size / 4,
158 spec_entries, num_spec_entries,
159 stage, entrypoint_name, &spirv_options, nir_options);
160 nir_shader *nir = entry_point->shader;
161 assert(nir->info.stage == stage);
162 nir_validate_shader(nir);
163 ralloc_steal(mem_ctx, nir);
164
165 free(spec_entries);
166
167 if (unlikely(INTEL_DEBUG & stage_to_debug[stage])) {
168 fprintf(stderr, "NIR (from SPIR-V) for %s shader:\n",
169 gl_shader_stage_name(stage));
170 nir_print_shader(nir, stderr);
171 }
172
173 /* We have to lower away local constant initializers right before we
174 * inline functions. That way they get properly initialized at the top
175 * of the function and not at the top of its caller.
176 */
177 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
178 NIR_PASS_V(nir, nir_lower_returns);
179 NIR_PASS_V(nir, nir_inline_functions);
180
181 /* Pick off the single entrypoint that we want */
182 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
183 if (func != entry_point)
184 exec_node_remove(&func->node);
185 }
186 assert(exec_list_length(&nir->functions) == 1);
187 entry_point->name = ralloc_strdup(entry_point, "main");
188
189 /* Make sure we lower constant initializers on output variables so that
190 * nir_remove_dead_variables below sees the corresponding stores
191 */
192 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
193
194 NIR_PASS_V(nir, nir_remove_dead_variables,
195 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
196
197 if (stage == MESA_SHADER_FRAGMENT)
198 NIR_PASS_V(nir, nir_lower_wpos_center, pipeline->sample_shading_enable);
199
200 /* Now that we've deleted all but the main function, we can go ahead and
201 * lower the rest of the constant initializers.
202 */
203 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
204 NIR_PASS_V(nir, nir_propagate_invariant);
205 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
206 entry_point->impl, true, false);
207
208 /* Vulkan uses the separate-shader linking model */
209 nir->info.separate_shader = true;
210
211 nir = brw_preprocess_nir(compiler, nir);
212
213 if (stage == MESA_SHADER_FRAGMENT)
214 NIR_PASS_V(nir, anv_nir_lower_input_attachments);
215
216 return nir;
217 }
218
219 void anv_DestroyPipeline(
220 VkDevice _device,
221 VkPipeline _pipeline,
222 const VkAllocationCallbacks* pAllocator)
223 {
224 ANV_FROM_HANDLE(anv_device, device, _device);
225 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
226
227 if (!pipeline)
228 return;
229
230 anv_reloc_list_finish(&pipeline->batch_relocs,
231 pAllocator ? pAllocator : &device->alloc);
232 if (pipeline->blend_state.map)
233 anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
234
235 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
236 if (pipeline->shaders[s])
237 anv_shader_bin_unref(device, pipeline->shaders[s]);
238 }
239
240 vk_free2(&device->alloc, pAllocator, pipeline);
241 }
242
243 static const uint32_t vk_to_gen_primitive_type[] = {
244 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
245 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
246 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
247 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
248 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
249 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
250 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
251 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
252 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
253 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
254 };
255
256 static void
257 populate_sampler_prog_key(const struct gen_device_info *devinfo,
258 struct brw_sampler_prog_key_data *key)
259 {
260 /* Almost all multisampled textures are compressed. The only time when we
261 * don't compress a multisampled texture is for 16x MSAA with a surface
262 * width greater than 8k which is a bit of an edge case. Since the sampler
263 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
264 * to tell the compiler to always assume compression.
265 */
266 key->compressed_multisample_layout_mask = ~0;
267
268 /* SkyLake added support for 16x MSAA. With this came a new message for
269 * reading from a 16x MSAA surface with compression. The new message was
270 * needed because now the MCS data is 64 bits instead of 32 or lower as is
271 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
272 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
273 * so we can just use it unconditionally. This may not be quite as
274 * efficient but it saves us from recompiling.
275 */
276 if (devinfo->gen >= 9)
277 key->msaa_16 = ~0;
278
279 /* XXX: Handle texture swizzle on HSW- */
280 for (int i = 0; i < MAX_SAMPLERS; i++) {
281 /* Assume color sampler, no swizzling. (Works for BDW+) */
282 key->swizzles[i] = SWIZZLE_XYZW;
283 }
284 }
285
286 static void
287 populate_vs_prog_key(const struct gen_device_info *devinfo,
288 struct brw_vs_prog_key *key)
289 {
290 memset(key, 0, sizeof(*key));
291
292 populate_sampler_prog_key(devinfo, &key->tex);
293
294 /* XXX: Handle vertex input work-arounds */
295
296 /* XXX: Handle sampler_prog_key */
297 }
298
299 static void
300 populate_gs_prog_key(const struct gen_device_info *devinfo,
301 struct brw_gs_prog_key *key)
302 {
303 memset(key, 0, sizeof(*key));
304
305 populate_sampler_prog_key(devinfo, &key->tex);
306 }
307
308 static void
309 populate_wm_prog_key(const struct anv_pipeline *pipeline,
310 const VkGraphicsPipelineCreateInfo *info,
311 struct brw_wm_prog_key *key)
312 {
313 const struct gen_device_info *devinfo = &pipeline->device->info;
314
315 memset(key, 0, sizeof(*key));
316
317 populate_sampler_prog_key(devinfo, &key->tex);
318
319 /* TODO: we could set this to 0 based on the information in nir_shader, but
320 * this function is called before spirv_to_nir. */
321 const struct brw_vue_map *vue_map =
322 &anv_pipeline_get_last_vue_prog_data(pipeline)->vue_map;
323 key->input_slots_valid = vue_map->slots_valid;
324
325 /* Vulkan doesn't specify a default */
326 key->high_quality_derivatives = false;
327
328 /* XXX Vulkan doesn't appear to specify */
329 key->clamp_fragment_color = false;
330
331 key->nr_color_regions = pipeline->subpass->color_count;
332
333 key->replicate_alpha = key->nr_color_regions > 1 &&
334 info->pMultisampleState &&
335 info->pMultisampleState->alphaToCoverageEnable;
336
337 if (info->pMultisampleState) {
338 /* We should probably pull this out of the shader, but it's fairly
339 * harmless to compute it and then let dead-code take care of it.
340 */
341 if (info->pMultisampleState->rasterizationSamples > 1) {
342 key->persample_interp =
343 (info->pMultisampleState->minSampleShading *
344 info->pMultisampleState->rasterizationSamples) > 1;
345 key->multisample_fbo = true;
346 }
347
348 key->frag_coord_adds_sample_pos =
349 info->pMultisampleState->sampleShadingEnable;
350 }
351 }
352
353 static void
354 populate_cs_prog_key(const struct gen_device_info *devinfo,
355 struct brw_cs_prog_key *key)
356 {
357 memset(key, 0, sizeof(*key));
358
359 populate_sampler_prog_key(devinfo, &key->tex);
360 }
361
362 static void
363 anv_pipeline_hash_shader(struct anv_pipeline *pipeline,
364 struct anv_pipeline_layout *layout,
365 struct anv_shader_module *module,
366 const char *entrypoint,
367 gl_shader_stage stage,
368 const VkSpecializationInfo *spec_info,
369 const void *key, size_t key_size,
370 unsigned char *sha1_out)
371 {
372 struct mesa_sha1 ctx;
373
374 _mesa_sha1_init(&ctx);
375 if (stage != MESA_SHADER_COMPUTE) {
376 _mesa_sha1_update(&ctx, &pipeline->subpass->view_mask,
377 sizeof(pipeline->subpass->view_mask));
378 }
379 if (layout)
380 _mesa_sha1_update(&ctx, layout->sha1, sizeof(layout->sha1));
381 _mesa_sha1_update(&ctx, module->sha1, sizeof(module->sha1));
382 _mesa_sha1_update(&ctx, entrypoint, strlen(entrypoint));
383 _mesa_sha1_update(&ctx, &stage, sizeof(stage));
384 if (spec_info) {
385 _mesa_sha1_update(&ctx, spec_info->pMapEntries,
386 spec_info->mapEntryCount * sizeof(*spec_info->pMapEntries));
387 _mesa_sha1_update(&ctx, spec_info->pData, spec_info->dataSize);
388 }
389 _mesa_sha1_update(&ctx, key, key_size);
390 _mesa_sha1_final(&ctx, sha1_out);
391 }
392
393 static nir_shader *
394 anv_pipeline_compile(struct anv_pipeline *pipeline,
395 void *mem_ctx,
396 struct anv_pipeline_layout *layout,
397 struct anv_shader_module *module,
398 const char *entrypoint,
399 gl_shader_stage stage,
400 const VkSpecializationInfo *spec_info,
401 struct brw_stage_prog_data *prog_data,
402 struct anv_pipeline_bind_map *map)
403 {
404 const struct brw_compiler *compiler =
405 pipeline->device->instance->physicalDevice.compiler;
406
407 nir_shader *nir = anv_shader_compile_to_nir(pipeline, mem_ctx,
408 module, entrypoint, stage,
409 spec_info);
410 if (nir == NULL)
411 return NULL;
412
413 NIR_PASS_V(nir, anv_nir_lower_ycbcr_textures, layout);
414
415 NIR_PASS_V(nir, anv_nir_lower_push_constants);
416
417 if (stage != MESA_SHADER_COMPUTE)
418 NIR_PASS_V(nir, anv_nir_lower_multiview, pipeline->subpass->view_mask);
419
420 if (stage == MESA_SHADER_COMPUTE)
421 prog_data->total_shared = nir->num_shared;
422
423 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
424
425 if (nir->num_uniforms > 0) {
426 assert(prog_data->nr_params == 0);
427
428 /* If the shader uses any push constants at all, we'll just give
429 * them the maximum possible number
430 */
431 assert(nir->num_uniforms <= MAX_PUSH_CONSTANTS_SIZE);
432 nir->num_uniforms = MAX_PUSH_CONSTANTS_SIZE;
433 prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
434 prog_data->param = ralloc_array(mem_ctx, uint32_t, prog_data->nr_params);
435
436 /* We now set the param values to be offsets into a
437 * anv_push_constant_data structure. Since the compiler doesn't
438 * actually dereference any of the gl_constant_value pointers in the
439 * params array, it doesn't really matter what we put here.
440 */
441 struct anv_push_constants *null_data = NULL;
442 /* Fill out the push constants section of the param array */
443 for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++) {
444 prog_data->param[i] = ANV_PARAM_PUSH(
445 (uintptr_t)&null_data->client_data[i * sizeof(float)]);
446 }
447 }
448
449 if (nir->info.num_ssbos > 0 || nir->info.num_images > 0)
450 pipeline->needs_data_cache = true;
451
452 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
453 if (layout)
454 anv_nir_apply_pipeline_layout(pipeline, layout, nir, prog_data, map);
455
456 if (stage != MESA_SHADER_COMPUTE)
457 brw_nir_analyze_ubo_ranges(compiler, nir, prog_data->ubo_ranges);
458
459 assert(nir->num_uniforms == prog_data->nr_params * 4);
460
461 return nir;
462 }
463
464 static void
465 anv_fill_binding_table(struct brw_stage_prog_data *prog_data, unsigned bias)
466 {
467 prog_data->binding_table.size_bytes = 0;
468 prog_data->binding_table.texture_start = bias;
469 prog_data->binding_table.gather_texture_start = bias;
470 prog_data->binding_table.ubo_start = bias;
471 prog_data->binding_table.ssbo_start = bias;
472 prog_data->binding_table.image_start = bias;
473 }
474
475 static struct anv_shader_bin *
476 anv_pipeline_upload_kernel(struct anv_pipeline *pipeline,
477 struct anv_pipeline_cache *cache,
478 const void *key_data, uint32_t key_size,
479 const void *kernel_data, uint32_t kernel_size,
480 const struct brw_stage_prog_data *prog_data,
481 uint32_t prog_data_size,
482 const struct anv_pipeline_bind_map *bind_map)
483 {
484 if (cache) {
485 return anv_pipeline_cache_upload_kernel(cache, key_data, key_size,
486 kernel_data, kernel_size,
487 prog_data, prog_data_size,
488 bind_map);
489 } else {
490 return anv_shader_bin_create(pipeline->device, key_data, key_size,
491 kernel_data, kernel_size,
492 prog_data, prog_data_size,
493 prog_data->param, bind_map);
494 }
495 }
496
497
498 static void
499 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
500 gl_shader_stage stage,
501 struct anv_shader_bin *shader)
502 {
503 pipeline->shaders[stage] = shader;
504 }
505
506 static VkResult
507 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
508 struct anv_pipeline_cache *cache,
509 const VkGraphicsPipelineCreateInfo *info,
510 struct anv_shader_module *module,
511 const char *entrypoint,
512 const VkSpecializationInfo *spec_info)
513 {
514 const struct brw_compiler *compiler =
515 pipeline->device->instance->physicalDevice.compiler;
516 struct brw_vs_prog_key key;
517 struct anv_shader_bin *bin = NULL;
518 unsigned char sha1[20];
519
520 populate_vs_prog_key(&pipeline->device->info, &key);
521
522 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
523
524 if (cache) {
525 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
526 MESA_SHADER_VERTEX, spec_info,
527 &key, sizeof(key), sha1);
528 bin = anv_pipeline_cache_search(cache, sha1, 20);
529 }
530
531 if (bin == NULL) {
532 struct brw_vs_prog_data prog_data = {};
533 struct anv_pipeline_binding surface_to_descriptor[256];
534 struct anv_pipeline_binding sampler_to_descriptor[256];
535
536 struct anv_pipeline_bind_map map = {
537 .surface_to_descriptor = surface_to_descriptor,
538 .sampler_to_descriptor = sampler_to_descriptor
539 };
540
541 void *mem_ctx = ralloc_context(NULL);
542
543 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
544 module, entrypoint,
545 MESA_SHADER_VERTEX, spec_info,
546 &prog_data.base.base, &map);
547 if (nir == NULL) {
548 ralloc_free(mem_ctx);
549 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
550 }
551
552 anv_fill_binding_table(&prog_data.base.base, 0);
553
554 brw_compute_vue_map(&pipeline->device->info,
555 &prog_data.base.vue_map,
556 nir->info.outputs_written,
557 nir->info.separate_shader);
558
559 const unsigned *shader_code =
560 brw_compile_vs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
561 -1, NULL);
562 if (shader_code == NULL) {
563 ralloc_free(mem_ctx);
564 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
565 }
566
567 unsigned code_size = prog_data.base.base.program_size;
568 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
569 shader_code, code_size,
570 &prog_data.base.base, sizeof(prog_data),
571 &map);
572 if (!bin) {
573 ralloc_free(mem_ctx);
574 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
575 }
576
577 ralloc_free(mem_ctx);
578 }
579
580 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX, bin);
581
582 return VK_SUCCESS;
583 }
584
585 static void
586 merge_tess_info(struct shader_info *tes_info,
587 const struct shader_info *tcs_info)
588 {
589 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
590 *
591 * "PointMode. Controls generation of points rather than triangles
592 * or lines. This functionality defaults to disabled, and is
593 * enabled if either shader stage includes the execution mode.
594 *
595 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
596 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
597 * and OutputVertices, it says:
598 *
599 * "One mode must be set in at least one of the tessellation
600 * shader stages."
601 *
602 * So, the fields can be set in either the TCS or TES, but they must
603 * agree if set in both. Our backend looks at TES, so bitwise-or in
604 * the values from the TCS.
605 */
606 assert(tcs_info->tess.tcs_vertices_out == 0 ||
607 tes_info->tess.tcs_vertices_out == 0 ||
608 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
609 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
610
611 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
612 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
613 tcs_info->tess.spacing == tes_info->tess.spacing);
614 tes_info->tess.spacing |= tcs_info->tess.spacing;
615
616 assert(tcs_info->tess.primitive_mode == 0 ||
617 tes_info->tess.primitive_mode == 0 ||
618 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
619 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
620 tes_info->tess.ccw |= tcs_info->tess.ccw;
621 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
622 }
623
624 static VkResult
625 anv_pipeline_compile_tcs_tes(struct anv_pipeline *pipeline,
626 struct anv_pipeline_cache *cache,
627 const VkGraphicsPipelineCreateInfo *info,
628 struct anv_shader_module *tcs_module,
629 const char *tcs_entrypoint,
630 const VkSpecializationInfo *tcs_spec_info,
631 struct anv_shader_module *tes_module,
632 const char *tes_entrypoint,
633 const VkSpecializationInfo *tes_spec_info)
634 {
635 const struct gen_device_info *devinfo = &pipeline->device->info;
636 const struct brw_compiler *compiler =
637 pipeline->device->instance->physicalDevice.compiler;
638 struct brw_tcs_prog_key tcs_key = {};
639 struct brw_tes_prog_key tes_key = {};
640 struct anv_shader_bin *tcs_bin = NULL;
641 struct anv_shader_bin *tes_bin = NULL;
642 unsigned char tcs_sha1[40];
643 unsigned char tes_sha1[40];
644
645 populate_sampler_prog_key(&pipeline->device->info, &tcs_key.tex);
646 populate_sampler_prog_key(&pipeline->device->info, &tes_key.tex);
647 tcs_key.input_vertices = info->pTessellationState->patchControlPoints;
648
649 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
650
651 if (cache) {
652 anv_pipeline_hash_shader(pipeline, layout, tcs_module, tcs_entrypoint,
653 MESA_SHADER_TESS_CTRL, tcs_spec_info,
654 &tcs_key, sizeof(tcs_key), tcs_sha1);
655 anv_pipeline_hash_shader(pipeline, layout, tes_module, tes_entrypoint,
656 MESA_SHADER_TESS_EVAL, tes_spec_info,
657 &tes_key, sizeof(tes_key), tes_sha1);
658 memcpy(&tcs_sha1[20], tes_sha1, 20);
659 memcpy(&tes_sha1[20], tcs_sha1, 20);
660 tcs_bin = anv_pipeline_cache_search(cache, tcs_sha1, sizeof(tcs_sha1));
661 tes_bin = anv_pipeline_cache_search(cache, tes_sha1, sizeof(tes_sha1));
662 }
663
664 if (tcs_bin == NULL || tes_bin == NULL) {
665 struct brw_tcs_prog_data tcs_prog_data = {};
666 struct brw_tes_prog_data tes_prog_data = {};
667 struct anv_pipeline_binding tcs_surface_to_descriptor[256];
668 struct anv_pipeline_binding tcs_sampler_to_descriptor[256];
669 struct anv_pipeline_binding tes_surface_to_descriptor[256];
670 struct anv_pipeline_binding tes_sampler_to_descriptor[256];
671
672 struct anv_pipeline_bind_map tcs_map = {
673 .surface_to_descriptor = tcs_surface_to_descriptor,
674 .sampler_to_descriptor = tcs_sampler_to_descriptor
675 };
676 struct anv_pipeline_bind_map tes_map = {
677 .surface_to_descriptor = tes_surface_to_descriptor,
678 .sampler_to_descriptor = tes_sampler_to_descriptor
679 };
680
681 void *mem_ctx = ralloc_context(NULL);
682
683 nir_shader *tcs_nir =
684 anv_pipeline_compile(pipeline, mem_ctx, layout,
685 tcs_module, tcs_entrypoint,
686 MESA_SHADER_TESS_CTRL, tcs_spec_info,
687 &tcs_prog_data.base.base, &tcs_map);
688 nir_shader *tes_nir =
689 anv_pipeline_compile(pipeline, mem_ctx, layout,
690 tes_module, tes_entrypoint,
691 MESA_SHADER_TESS_EVAL, tes_spec_info,
692 &tes_prog_data.base.base, &tes_map);
693 if (tcs_nir == NULL || tes_nir == NULL) {
694 ralloc_free(mem_ctx);
695 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
696 }
697
698 nir_lower_tes_patch_vertices(tes_nir,
699 tcs_nir->info.tess.tcs_vertices_out);
700
701 /* Copy TCS info into the TES info */
702 merge_tess_info(&tes_nir->info, &tcs_nir->info);
703
704 anv_fill_binding_table(&tcs_prog_data.base.base, 0);
705 anv_fill_binding_table(&tes_prog_data.base.base, 0);
706
707 /* Whacking the key after cache lookup is a bit sketchy, but all of
708 * this comes from the SPIR-V, which is part of the hash used for the
709 * pipeline cache. So it should be safe.
710 */
711 tcs_key.tes_primitive_mode = tes_nir->info.tess.primitive_mode;
712 tcs_key.outputs_written = tcs_nir->info.outputs_written;
713 tcs_key.patch_outputs_written = tcs_nir->info.patch_outputs_written;
714 tcs_key.quads_workaround =
715 devinfo->gen < 9 &&
716 tes_nir->info.tess.primitive_mode == 7 /* GL_QUADS */ &&
717 tes_nir->info.tess.spacing == TESS_SPACING_EQUAL;
718
719 tes_key.inputs_read = tcs_key.outputs_written;
720 tes_key.patch_inputs_read = tcs_key.patch_outputs_written;
721
722 const int shader_time_index = -1;
723 const unsigned *shader_code;
724
725 shader_code =
726 brw_compile_tcs(compiler, NULL, mem_ctx, &tcs_key, &tcs_prog_data,
727 tcs_nir, shader_time_index, NULL);
728 if (shader_code == NULL) {
729 ralloc_free(mem_ctx);
730 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
731 }
732
733 unsigned code_size = tcs_prog_data.base.base.program_size;
734 tcs_bin = anv_pipeline_upload_kernel(pipeline, cache,
735 tcs_sha1, sizeof(tcs_sha1),
736 shader_code, code_size,
737 &tcs_prog_data.base.base,
738 sizeof(tcs_prog_data),
739 &tcs_map);
740 if (!tcs_bin) {
741 ralloc_free(mem_ctx);
742 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
743 }
744
745 shader_code =
746 brw_compile_tes(compiler, NULL, mem_ctx, &tes_key,
747 &tcs_prog_data.base.vue_map, &tes_prog_data, tes_nir,
748 NULL, shader_time_index, NULL);
749 if (shader_code == NULL) {
750 ralloc_free(mem_ctx);
751 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
752 }
753
754 code_size = tes_prog_data.base.base.program_size;
755 tes_bin = anv_pipeline_upload_kernel(pipeline, cache,
756 tes_sha1, sizeof(tes_sha1),
757 shader_code, code_size,
758 &tes_prog_data.base.base,
759 sizeof(tes_prog_data),
760 &tes_map);
761 if (!tes_bin) {
762 ralloc_free(mem_ctx);
763 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
764 }
765
766 ralloc_free(mem_ctx);
767 }
768
769 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_TESS_CTRL, tcs_bin);
770 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_TESS_EVAL, tes_bin);
771
772 return VK_SUCCESS;
773 }
774
775 static VkResult
776 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
777 struct anv_pipeline_cache *cache,
778 const VkGraphicsPipelineCreateInfo *info,
779 struct anv_shader_module *module,
780 const char *entrypoint,
781 const VkSpecializationInfo *spec_info)
782 {
783 const struct brw_compiler *compiler =
784 pipeline->device->instance->physicalDevice.compiler;
785 struct brw_gs_prog_key key;
786 struct anv_shader_bin *bin = NULL;
787 unsigned char sha1[20];
788
789 populate_gs_prog_key(&pipeline->device->info, &key);
790
791 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
792
793 if (cache) {
794 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
795 MESA_SHADER_GEOMETRY, spec_info,
796 &key, sizeof(key), sha1);
797 bin = anv_pipeline_cache_search(cache, sha1, 20);
798 }
799
800 if (bin == NULL) {
801 struct brw_gs_prog_data prog_data = {};
802 struct anv_pipeline_binding surface_to_descriptor[256];
803 struct anv_pipeline_binding sampler_to_descriptor[256];
804
805 struct anv_pipeline_bind_map map = {
806 .surface_to_descriptor = surface_to_descriptor,
807 .sampler_to_descriptor = sampler_to_descriptor
808 };
809
810 void *mem_ctx = ralloc_context(NULL);
811
812 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
813 module, entrypoint,
814 MESA_SHADER_GEOMETRY, spec_info,
815 &prog_data.base.base, &map);
816 if (nir == NULL) {
817 ralloc_free(mem_ctx);
818 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
819 }
820
821 anv_fill_binding_table(&prog_data.base.base, 0);
822
823 brw_compute_vue_map(&pipeline->device->info,
824 &prog_data.base.vue_map,
825 nir->info.outputs_written,
826 nir->info.separate_shader);
827
828 const unsigned *shader_code =
829 brw_compile_gs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
830 NULL, -1, NULL);
831 if (shader_code == NULL) {
832 ralloc_free(mem_ctx);
833 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
834 }
835
836 /* TODO: SIMD8 GS */
837 const unsigned code_size = prog_data.base.base.program_size;
838 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
839 shader_code, code_size,
840 &prog_data.base.base, sizeof(prog_data),
841 &map);
842 if (!bin) {
843 ralloc_free(mem_ctx);
844 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
845 }
846
847 ralloc_free(mem_ctx);
848 }
849
850 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY, bin);
851
852 return VK_SUCCESS;
853 }
854
855 static VkResult
856 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
857 struct anv_pipeline_cache *cache,
858 const VkGraphicsPipelineCreateInfo *info,
859 struct anv_shader_module *module,
860 const char *entrypoint,
861 const VkSpecializationInfo *spec_info)
862 {
863 const struct brw_compiler *compiler =
864 pipeline->device->instance->physicalDevice.compiler;
865 struct brw_wm_prog_key key;
866 struct anv_shader_bin *bin = NULL;
867 unsigned char sha1[20];
868
869 populate_wm_prog_key(pipeline, info, &key);
870
871 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
872
873 if (cache) {
874 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
875 MESA_SHADER_FRAGMENT, spec_info,
876 &key, sizeof(key), sha1);
877 bin = anv_pipeline_cache_search(cache, sha1, 20);
878 }
879
880 if (bin == NULL) {
881 struct brw_wm_prog_data prog_data = {};
882 struct anv_pipeline_binding surface_to_descriptor[256];
883 struct anv_pipeline_binding sampler_to_descriptor[256];
884
885 struct anv_pipeline_bind_map map = {
886 .surface_to_descriptor = surface_to_descriptor + 8,
887 .sampler_to_descriptor = sampler_to_descriptor
888 };
889
890 void *mem_ctx = ralloc_context(NULL);
891
892 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
893 module, entrypoint,
894 MESA_SHADER_FRAGMENT, spec_info,
895 &prog_data.base, &map);
896 if (nir == NULL) {
897 ralloc_free(mem_ctx);
898 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
899 }
900
901 unsigned num_rts = 0;
902 const int max_rt = FRAG_RESULT_DATA7 - FRAG_RESULT_DATA0 + 1;
903 struct anv_pipeline_binding rt_bindings[max_rt];
904 nir_function_impl *impl = nir_shader_get_entrypoint(nir);
905 int rt_to_bindings[max_rt];
906 memset(rt_to_bindings, -1, sizeof(rt_to_bindings));
907 bool rt_used[max_rt];
908 memset(rt_used, 0, sizeof(rt_used));
909
910 /* Flag used render targets */
911 nir_foreach_variable_safe(var, &nir->outputs) {
912 if (var->data.location < FRAG_RESULT_DATA0)
913 continue;
914
915 const unsigned rt = var->data.location - FRAG_RESULT_DATA0;
916 /* Out-of-bounds */
917 if (rt >= key.nr_color_regions)
918 continue;
919
920 const unsigned array_len =
921 glsl_type_is_array(var->type) ? glsl_get_length(var->type) : 1;
922 assert(rt + array_len <= max_rt);
923
924 for (unsigned i = 0; i < array_len; i++)
925 rt_used[rt + i] = true;
926 }
927
928 /* Set new, compacted, location */
929 for (unsigned i = 0; i < max_rt; i++) {
930 if (!rt_used[i])
931 continue;
932
933 rt_to_bindings[i] = num_rts;
934 rt_bindings[rt_to_bindings[i]] = (struct anv_pipeline_binding) {
935 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
936 .binding = 0,
937 .index = i,
938 };
939 num_rts++;
940 }
941
942 nir_foreach_variable_safe(var, &nir->outputs) {
943 if (var->data.location < FRAG_RESULT_DATA0)
944 continue;
945
946 const unsigned rt = var->data.location - FRAG_RESULT_DATA0;
947 if (rt >= key.nr_color_regions) {
948 /* Out-of-bounds, throw it away */
949 var->data.mode = nir_var_local;
950 exec_node_remove(&var->node);
951 exec_list_push_tail(&impl->locals, &var->node);
952 continue;
953 }
954
955 /* Give it the new location */
956 assert(rt_to_bindings[rt] != -1);
957 var->data.location = rt_to_bindings[rt] + FRAG_RESULT_DATA0;
958 }
959
960 if (num_rts == 0) {
961 /* If we have no render targets, we need a null render target */
962 rt_bindings[0] = (struct anv_pipeline_binding) {
963 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
964 .binding = 0,
965 .index = UINT32_MAX,
966 };
967 num_rts = 1;
968 }
969
970 assert(num_rts <= max_rt);
971 map.surface_to_descriptor -= num_rts;
972 map.surface_count += num_rts;
973 assert(map.surface_count <= 256);
974 memcpy(map.surface_to_descriptor, rt_bindings,
975 num_rts * sizeof(*rt_bindings));
976
977 anv_fill_binding_table(&prog_data.base, num_rts);
978
979 const unsigned *shader_code =
980 brw_compile_fs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
981 NULL, -1, -1, true, false, NULL, NULL);
982 if (shader_code == NULL) {
983 ralloc_free(mem_ctx);
984 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
985 }
986
987 unsigned code_size = prog_data.base.program_size;
988 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
989 shader_code, code_size,
990 &prog_data.base, sizeof(prog_data),
991 &map);
992 if (!bin) {
993 ralloc_free(mem_ctx);
994 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
995 }
996
997 ralloc_free(mem_ctx);
998 }
999
1000 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT, bin);
1001
1002 return VK_SUCCESS;
1003 }
1004
1005 VkResult
1006 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
1007 struct anv_pipeline_cache *cache,
1008 const VkComputePipelineCreateInfo *info,
1009 struct anv_shader_module *module,
1010 const char *entrypoint,
1011 const VkSpecializationInfo *spec_info)
1012 {
1013 const struct brw_compiler *compiler =
1014 pipeline->device->instance->physicalDevice.compiler;
1015 struct brw_cs_prog_key key;
1016 struct anv_shader_bin *bin = NULL;
1017 unsigned char sha1[20];
1018
1019 populate_cs_prog_key(&pipeline->device->info, &key);
1020
1021 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
1022
1023 if (cache) {
1024 anv_pipeline_hash_shader(pipeline, layout, module, entrypoint,
1025 MESA_SHADER_COMPUTE, spec_info,
1026 &key, sizeof(key), sha1);
1027 bin = anv_pipeline_cache_search(cache, sha1, 20);
1028 }
1029
1030 if (bin == NULL) {
1031 struct brw_cs_prog_data prog_data = {};
1032 struct anv_pipeline_binding surface_to_descriptor[256];
1033 struct anv_pipeline_binding sampler_to_descriptor[256];
1034
1035 struct anv_pipeline_bind_map map = {
1036 .surface_to_descriptor = surface_to_descriptor,
1037 .sampler_to_descriptor = sampler_to_descriptor
1038 };
1039
1040 void *mem_ctx = ralloc_context(NULL);
1041
1042 nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
1043 module, entrypoint,
1044 MESA_SHADER_COMPUTE, spec_info,
1045 &prog_data.base, &map);
1046 if (nir == NULL) {
1047 ralloc_free(mem_ctx);
1048 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1049 }
1050
1051 NIR_PASS_V(nir, anv_nir_add_base_work_group_id, &prog_data);
1052
1053 anv_fill_binding_table(&prog_data.base, 1);
1054
1055 const unsigned *shader_code =
1056 brw_compile_cs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
1057 -1, NULL);
1058 if (shader_code == NULL) {
1059 ralloc_free(mem_ctx);
1060 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1061 }
1062
1063 const unsigned code_size = prog_data.base.program_size;
1064 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
1065 shader_code, code_size,
1066 &prog_data.base, sizeof(prog_data),
1067 &map);
1068 if (!bin) {
1069 ralloc_free(mem_ctx);
1070 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1071 }
1072
1073 ralloc_free(mem_ctx);
1074 }
1075
1076 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE, bin);
1077
1078 return VK_SUCCESS;
1079 }
1080
1081 /**
1082 * Copy pipeline state not marked as dynamic.
1083 * Dynamic state is pipeline state which hasn't been provided at pipeline
1084 * creation time, but is dynamically provided afterwards using various
1085 * vkCmdSet* functions.
1086 *
1087 * The set of state considered "non_dynamic" is determined by the pieces of
1088 * state that have their corresponding VkDynamicState enums omitted from
1089 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1090 *
1091 * @param[out] pipeline Destination non_dynamic state.
1092 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1093 */
1094 static void
1095 copy_non_dynamic_state(struct anv_pipeline *pipeline,
1096 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1097 {
1098 anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
1099 struct anv_subpass *subpass = pipeline->subpass;
1100
1101 pipeline->dynamic_state = default_dynamic_state;
1102
1103 if (pCreateInfo->pDynamicState) {
1104 /* Remove all of the states that are marked as dynamic */
1105 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1106 for (uint32_t s = 0; s < count; s++)
1107 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1108 }
1109
1110 struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
1111
1112 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1113 *
1114 * pViewportState is [...] NULL if the pipeline
1115 * has rasterization disabled.
1116 */
1117 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1118 assert(pCreateInfo->pViewportState);
1119
1120 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1121 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1122 typed_memcpy(dynamic->viewport.viewports,
1123 pCreateInfo->pViewportState->pViewports,
1124 pCreateInfo->pViewportState->viewportCount);
1125 }
1126
1127 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1128 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1129 typed_memcpy(dynamic->scissor.scissors,
1130 pCreateInfo->pViewportState->pScissors,
1131 pCreateInfo->pViewportState->scissorCount);
1132 }
1133 }
1134
1135 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1136 assert(pCreateInfo->pRasterizationState);
1137 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1138 }
1139
1140 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1141 assert(pCreateInfo->pRasterizationState);
1142 dynamic->depth_bias.bias =
1143 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1144 dynamic->depth_bias.clamp =
1145 pCreateInfo->pRasterizationState->depthBiasClamp;
1146 dynamic->depth_bias.slope =
1147 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1148 }
1149
1150 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1151 *
1152 * pColorBlendState is [...] NULL if the pipeline has rasterization
1153 * disabled or if the subpass of the render pass the pipeline is
1154 * created against does not use any color attachments.
1155 */
1156 bool uses_color_att = false;
1157 for (unsigned i = 0; i < subpass->color_count; ++i) {
1158 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1159 uses_color_att = true;
1160 break;
1161 }
1162 }
1163
1164 if (uses_color_att &&
1165 !pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1166 assert(pCreateInfo->pColorBlendState);
1167
1168 if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
1169 typed_memcpy(dynamic->blend_constants,
1170 pCreateInfo->pColorBlendState->blendConstants, 4);
1171 }
1172
1173 /* If there is no depthstencil attachment, then don't read
1174 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1175 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1176 * no need to override the depthstencil defaults in
1177 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1178 *
1179 * Section 9.2 of the Vulkan 1.0.15 spec says:
1180 *
1181 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1182 * disabled or if the subpass of the render pass the pipeline is created
1183 * against does not use a depth/stencil attachment.
1184 */
1185 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1186 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1187 assert(pCreateInfo->pDepthStencilState);
1188
1189 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1190 dynamic->depth_bounds.min =
1191 pCreateInfo->pDepthStencilState->minDepthBounds;
1192 dynamic->depth_bounds.max =
1193 pCreateInfo->pDepthStencilState->maxDepthBounds;
1194 }
1195
1196 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1197 dynamic->stencil_compare_mask.front =
1198 pCreateInfo->pDepthStencilState->front.compareMask;
1199 dynamic->stencil_compare_mask.back =
1200 pCreateInfo->pDepthStencilState->back.compareMask;
1201 }
1202
1203 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1204 dynamic->stencil_write_mask.front =
1205 pCreateInfo->pDepthStencilState->front.writeMask;
1206 dynamic->stencil_write_mask.back =
1207 pCreateInfo->pDepthStencilState->back.writeMask;
1208 }
1209
1210 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1211 dynamic->stencil_reference.front =
1212 pCreateInfo->pDepthStencilState->front.reference;
1213 dynamic->stencil_reference.back =
1214 pCreateInfo->pDepthStencilState->back.reference;
1215 }
1216 }
1217
1218 pipeline->dynamic_state_mask = states;
1219 }
1220
1221 static void
1222 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
1223 {
1224 #ifdef DEBUG
1225 struct anv_render_pass *renderpass = NULL;
1226 struct anv_subpass *subpass = NULL;
1227
1228 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1229 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1230 */
1231 assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
1232
1233 renderpass = anv_render_pass_from_handle(info->renderPass);
1234 assert(renderpass);
1235
1236 assert(info->subpass < renderpass->subpass_count);
1237 subpass = &renderpass->subpasses[info->subpass];
1238
1239 assert(info->stageCount >= 1);
1240 assert(info->pVertexInputState);
1241 assert(info->pInputAssemblyState);
1242 assert(info->pRasterizationState);
1243 if (!info->pRasterizationState->rasterizerDiscardEnable) {
1244 assert(info->pViewportState);
1245 assert(info->pMultisampleState);
1246
1247 if (subpass && subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
1248 assert(info->pDepthStencilState);
1249
1250 if (subpass && subpass->color_count > 0)
1251 assert(info->pColorBlendState);
1252 }
1253
1254 for (uint32_t i = 0; i < info->stageCount; ++i) {
1255 switch (info->pStages[i].stage) {
1256 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
1257 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
1258 assert(info->pTessellationState);
1259 break;
1260 default:
1261 break;
1262 }
1263 }
1264 #endif
1265 }
1266
1267 /**
1268 * Calculate the desired L3 partitioning based on the current state of the
1269 * pipeline. For now this simply returns the conservative defaults calculated
1270 * by get_default_l3_weights(), but we could probably do better by gathering
1271 * more statistics from the pipeline state (e.g. guess of expected URB usage
1272 * and bound surfaces), or by using feed-back from performance counters.
1273 */
1274 void
1275 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm)
1276 {
1277 const struct gen_device_info *devinfo = &pipeline->device->info;
1278
1279 const struct gen_l3_weights w =
1280 gen_get_default_l3_weights(devinfo, pipeline->needs_data_cache, needs_slm);
1281
1282 pipeline->urb.l3_config = gen_get_l3_config(devinfo, w);
1283 pipeline->urb.total_size =
1284 gen_get_l3_config_urb_size(devinfo, pipeline->urb.l3_config);
1285 }
1286
1287 VkResult
1288 anv_pipeline_init(struct anv_pipeline *pipeline,
1289 struct anv_device *device,
1290 struct anv_pipeline_cache *cache,
1291 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1292 const VkAllocationCallbacks *alloc)
1293 {
1294 VkResult result;
1295
1296 anv_pipeline_validate_create_info(pCreateInfo);
1297
1298 if (alloc == NULL)
1299 alloc = &device->alloc;
1300
1301 pipeline->device = device;
1302
1303 ANV_FROM_HANDLE(anv_render_pass, render_pass, pCreateInfo->renderPass);
1304 assert(pCreateInfo->subpass < render_pass->subpass_count);
1305 pipeline->subpass = &render_pass->subpasses[pCreateInfo->subpass];
1306
1307 result = anv_reloc_list_init(&pipeline->batch_relocs, alloc);
1308 if (result != VK_SUCCESS)
1309 return result;
1310
1311 pipeline->batch.alloc = alloc;
1312 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
1313 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
1314 pipeline->batch.relocs = &pipeline->batch_relocs;
1315 pipeline->batch.status = VK_SUCCESS;
1316
1317 copy_non_dynamic_state(pipeline, pCreateInfo);
1318 pipeline->depth_clamp_enable = pCreateInfo->pRasterizationState &&
1319 pCreateInfo->pRasterizationState->depthClampEnable;
1320
1321 pipeline->sample_shading_enable = pCreateInfo->pMultisampleState &&
1322 pCreateInfo->pMultisampleState->sampleShadingEnable;
1323
1324 pipeline->needs_data_cache = false;
1325
1326 /* When we free the pipeline, we detect stages based on the NULL status
1327 * of various prog_data pointers. Make them NULL by default.
1328 */
1329 memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
1330
1331 pipeline->active_stages = 0;
1332
1333 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = {};
1334 struct anv_shader_module *modules[MESA_SHADER_STAGES] = {};
1335 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1336 VkShaderStageFlagBits vk_stage = pCreateInfo->pStages[i].stage;
1337 gl_shader_stage stage = vk_to_mesa_shader_stage(vk_stage);
1338 pStages[stage] = &pCreateInfo->pStages[i];
1339 modules[stage] = anv_shader_module_from_handle(pStages[stage]->module);
1340 pipeline->active_stages |= vk_stage;
1341 }
1342
1343 if (pipeline->active_stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT)
1344 pipeline->active_stages |= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT;
1345
1346 assert(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT);
1347
1348 if (modules[MESA_SHADER_VERTEX]) {
1349 result = anv_pipeline_compile_vs(pipeline, cache, pCreateInfo,
1350 modules[MESA_SHADER_VERTEX],
1351 pStages[MESA_SHADER_VERTEX]->pName,
1352 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo);
1353 if (result != VK_SUCCESS)
1354 goto compile_fail;
1355 }
1356
1357 if (modules[MESA_SHADER_TESS_EVAL]) {
1358 result = anv_pipeline_compile_tcs_tes(pipeline, cache, pCreateInfo,
1359 modules[MESA_SHADER_TESS_CTRL],
1360 pStages[MESA_SHADER_TESS_CTRL]->pName,
1361 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
1362 modules[MESA_SHADER_TESS_EVAL],
1363 pStages[MESA_SHADER_TESS_EVAL]->pName,
1364 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo);
1365 if (result != VK_SUCCESS)
1366 goto compile_fail;
1367 }
1368
1369 if (modules[MESA_SHADER_GEOMETRY]) {
1370 result = anv_pipeline_compile_gs(pipeline, cache, pCreateInfo,
1371 modules[MESA_SHADER_GEOMETRY],
1372 pStages[MESA_SHADER_GEOMETRY]->pName,
1373 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo);
1374 if (result != VK_SUCCESS)
1375 goto compile_fail;
1376 }
1377
1378 if (modules[MESA_SHADER_FRAGMENT]) {
1379 result = anv_pipeline_compile_fs(pipeline, cache, pCreateInfo,
1380 modules[MESA_SHADER_FRAGMENT],
1381 pStages[MESA_SHADER_FRAGMENT]->pName,
1382 pStages[MESA_SHADER_FRAGMENT]->pSpecializationInfo);
1383 if (result != VK_SUCCESS)
1384 goto compile_fail;
1385 }
1386
1387 assert(pipeline->shaders[MESA_SHADER_VERTEX]);
1388
1389 anv_pipeline_setup_l3_config(pipeline, false);
1390
1391 const VkPipelineVertexInputStateCreateInfo *vi_info =
1392 pCreateInfo->pVertexInputState;
1393
1394 const uint64_t inputs_read = get_vs_prog_data(pipeline)->inputs_read;
1395
1396 pipeline->vb_used = 0;
1397 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1398 const VkVertexInputAttributeDescription *desc =
1399 &vi_info->pVertexAttributeDescriptions[i];
1400
1401 if (inputs_read & (1ull << (VERT_ATTRIB_GENERIC0 + desc->location)))
1402 pipeline->vb_used |= 1 << desc->binding;
1403 }
1404
1405 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1406 const VkVertexInputBindingDescription *desc =
1407 &vi_info->pVertexBindingDescriptions[i];
1408
1409 pipeline->binding_stride[desc->binding] = desc->stride;
1410
1411 /* Step rate is programmed per vertex element (attribute), not
1412 * binding. Set up a map of which bindings step per instance, for
1413 * reference by vertex element setup. */
1414 switch (desc->inputRate) {
1415 default:
1416 case VK_VERTEX_INPUT_RATE_VERTEX:
1417 pipeline->instancing_enable[desc->binding] = false;
1418 break;
1419 case VK_VERTEX_INPUT_RATE_INSTANCE:
1420 pipeline->instancing_enable[desc->binding] = true;
1421 break;
1422 }
1423 }
1424
1425 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1426 pCreateInfo->pInputAssemblyState;
1427 const VkPipelineTessellationStateCreateInfo *tess_info =
1428 pCreateInfo->pTessellationState;
1429 pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1430
1431 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
1432 pipeline->topology = _3DPRIM_PATCHLIST(tess_info->patchControlPoints);
1433 else
1434 pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1435
1436 return VK_SUCCESS;
1437
1438 compile_fail:
1439 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
1440 if (pipeline->shaders[s])
1441 anv_shader_bin_unref(device, pipeline->shaders[s]);
1442 }
1443
1444 anv_reloc_list_finish(&pipeline->batch_relocs, alloc);
1445
1446 return result;
1447 }