2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/mesa-sha1.h"
25 #include "util/debug.h"
26 #include "anv_private.h"
30 * - Compact binding table layout so it's tight and not dependent on
31 * descriptor set layout.
33 * - Review prog_data struct for size and cacheability: struct
34 * brw_stage_prog_data has binding_table which uses a lot of uint32_t for 8
35 * bit quantities etc; param, pull_param, and image_params are pointers, we
36 * just need the compation map. use bit fields for all bools, eg
41 anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
42 struct anv_device
*device
)
44 cache
->device
= device
;
45 anv_state_stream_init(&cache
->program_stream
,
46 &device
->instruction_block_pool
);
47 pthread_mutex_init(&cache
->mutex
, NULL
);
49 cache
->kernel_count
= 0;
50 cache
->total_size
= 0;
51 cache
->table_size
= 1024;
52 const size_t byte_size
= cache
->table_size
* sizeof(cache
->hash_table
[0]);
53 cache
->hash_table
= malloc(byte_size
);
55 /* We don't consider allocation failure fatal, we just start with a 0-sized
57 if (cache
->hash_table
== NULL
||
58 !env_var_as_boolean("ANV_ENABLE_PIPELINE_CACHE", true))
59 cache
->table_size
= 0;
61 memset(cache
->hash_table
, 0xff, byte_size
);
65 anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
)
67 anv_state_stream_finish(&cache
->program_stream
);
68 pthread_mutex_destroy(&cache
->mutex
);
69 free(cache
->hash_table
);
73 unsigned char sha1
[20];
74 uint32_t prog_data_size
;
76 uint32_t surface_count
;
77 uint32_t sampler_count
;
82 /* kernel follows prog_data at next 64 byte aligned address */
86 entry_size(struct cache_entry
*entry
)
88 /* This returns the number of bytes needed to serialize an entry, which
89 * doesn't include the alignment padding bytes.
92 const uint32_t map_size
=
93 entry
->surface_count
* sizeof(struct anv_pipeline_binding
) +
94 entry
->sampler_count
* sizeof(struct anv_pipeline_binding
);
96 return sizeof(*entry
) + entry
->prog_data_size
+ map_size
;
100 anv_hash_shader(unsigned char *hash
, const void *key
, size_t key_size
,
101 struct anv_shader_module
*module
,
102 const char *entrypoint
,
103 const VkSpecializationInfo
*spec_info
)
105 struct mesa_sha1
*ctx
;
107 ctx
= _mesa_sha1_init();
108 _mesa_sha1_update(ctx
, key
, key_size
);
109 _mesa_sha1_update(ctx
, module
->sha1
, sizeof(module
->sha1
));
110 _mesa_sha1_update(ctx
, entrypoint
, strlen(entrypoint
));
111 /* hash in shader stage, pipeline layout? */
113 _mesa_sha1_update(ctx
, spec_info
->pMapEntries
,
114 spec_info
->mapEntryCount
* sizeof spec_info
->pMapEntries
[0]);
115 _mesa_sha1_update(ctx
, spec_info
->pData
, spec_info
->dataSize
);
117 _mesa_sha1_final(ctx
, hash
);
121 anv_pipeline_cache_search_unlocked(struct anv_pipeline_cache
*cache
,
122 const unsigned char *sha1
,
123 const struct brw_stage_prog_data
**prog_data
,
124 struct anv_pipeline_bind_map
*map
)
126 const uint32_t mask
= cache
->table_size
- 1;
127 const uint32_t start
= (*(uint32_t *) sha1
);
129 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
130 const uint32_t index
= (start
+ i
) & mask
;
131 const uint32_t offset
= cache
->hash_table
[index
];
136 struct cache_entry
*entry
=
137 cache
->program_stream
.block_pool
->map
+ offset
;
138 if (memcmp(entry
->sha1
, sha1
, sizeof(entry
->sha1
)) == 0) {
141 void *p
= entry
->prog_data
;
143 p
+= entry
->prog_data_size
;
144 map
->surface_count
= entry
->surface_count
;
145 map
->sampler_count
= entry
->sampler_count
;
146 map
->image_count
= entry
->image_count
;
147 map
->surface_to_descriptor
= p
;
148 p
+= map
->surface_count
* sizeof(struct anv_pipeline_binding
);
149 map
->sampler_to_descriptor
= p
;
152 return offset
+ align_u32(entry_size(entry
), 64);
156 unreachable("hash table should never be full");
160 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
161 const unsigned char *sha1
,
162 const struct brw_stage_prog_data
**prog_data
,
163 struct anv_pipeline_bind_map
*map
)
167 pthread_mutex_lock(&cache
->mutex
);
169 kernel
= anv_pipeline_cache_search_unlocked(cache
, sha1
, prog_data
, map
);
171 pthread_mutex_unlock(&cache
->mutex
);
177 anv_pipeline_cache_set_entry(struct anv_pipeline_cache
*cache
,
178 struct cache_entry
*entry
, uint32_t entry_offset
)
180 const uint32_t mask
= cache
->table_size
- 1;
181 const uint32_t start
= (*(uint32_t *) entry
->sha1
);
183 /* We'll always be able to insert when we get here. */
184 assert(cache
->kernel_count
< cache
->table_size
/ 2);
186 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
187 const uint32_t index
= (start
+ i
) & mask
;
188 if (cache
->hash_table
[index
] == ~0) {
189 cache
->hash_table
[index
] = entry_offset
;
194 cache
->total_size
+= entry_size(entry
) + entry
->kernel_size
;
195 cache
->kernel_count
++;
199 anv_pipeline_cache_grow(struct anv_pipeline_cache
*cache
)
201 const uint32_t table_size
= cache
->table_size
* 2;
202 const uint32_t old_table_size
= cache
->table_size
;
203 const size_t byte_size
= table_size
* sizeof(cache
->hash_table
[0]);
205 uint32_t *old_table
= cache
->hash_table
;
207 table
= malloc(byte_size
);
209 return VK_ERROR_OUT_OF_HOST_MEMORY
;
211 cache
->hash_table
= table
;
212 cache
->table_size
= table_size
;
213 cache
->kernel_count
= 0;
214 cache
->total_size
= 0;
216 memset(cache
->hash_table
, 0xff, byte_size
);
217 for (uint32_t i
= 0; i
< old_table_size
; i
++) {
218 const uint32_t offset
= old_table
[i
];
222 struct cache_entry
*entry
=
223 cache
->program_stream
.block_pool
->map
+ offset
;
224 anv_pipeline_cache_set_entry(cache
, entry
, offset
);
233 anv_pipeline_cache_add_entry(struct anv_pipeline_cache
*cache
,
234 struct cache_entry
*entry
, uint32_t entry_offset
)
236 if (cache
->kernel_count
== cache
->table_size
/ 2)
237 anv_pipeline_cache_grow(cache
);
239 /* Failing to grow that hash table isn't fatal, but may mean we don't
240 * have enough space to add this new kernel. Only add it if there's room.
242 if (cache
->kernel_count
< cache
->table_size
/ 2)
243 anv_pipeline_cache_set_entry(cache
, entry
, entry_offset
);
247 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
248 const unsigned char *sha1
,
249 const void *kernel
, size_t kernel_size
,
250 const struct brw_stage_prog_data
**prog_data
,
251 size_t prog_data_size
,
252 struct anv_pipeline_bind_map
*map
)
254 pthread_mutex_lock(&cache
->mutex
);
256 /* Before uploading, check again that another thread didn't upload this
257 * shader while we were compiling it.
260 uint32_t cached_kernel
=
261 anv_pipeline_cache_search_unlocked(cache
, sha1
, prog_data
, map
);
262 if (cached_kernel
!= NO_KERNEL
) {
263 pthread_mutex_unlock(&cache
->mutex
);
264 return cached_kernel
;
268 struct cache_entry
*entry
;
270 const uint32_t map_size
=
271 map
->surface_count
* sizeof(struct anv_pipeline_binding
) +
272 map
->sampler_count
* sizeof(struct anv_pipeline_binding
);
274 const uint32_t preamble_size
=
275 align_u32(sizeof(*entry
) + prog_data_size
+ map_size
, 64);
277 const uint32_t size
= preamble_size
+ kernel_size
;
279 assert(size
< cache
->program_stream
.block_pool
->block_size
);
280 const struct anv_state state
=
281 anv_state_stream_alloc(&cache
->program_stream
, size
, 64);
284 entry
->prog_data_size
= prog_data_size
;
285 entry
->surface_count
= map
->surface_count
;
286 entry
->sampler_count
= map
->sampler_count
;
287 entry
->image_count
= map
->image_count
;
288 entry
->kernel_size
= kernel_size
;
290 void *p
= entry
->prog_data
;
291 memcpy(p
, *prog_data
, prog_data_size
);
294 memcpy(p
, map
->surface_to_descriptor
,
295 map
->surface_count
* sizeof(struct anv_pipeline_binding
));
296 map
->surface_to_descriptor
= p
;
297 p
+= map
->surface_count
* sizeof(struct anv_pipeline_binding
);
299 memcpy(p
, map
->sampler_to_descriptor
,
300 map
->sampler_count
* sizeof(struct anv_pipeline_binding
));
301 map
->sampler_to_descriptor
= p
;
304 assert(anv_pipeline_cache_search_unlocked(cache
, sha1
,
305 NULL
, NULL
) == NO_KERNEL
);
307 memcpy(entry
->sha1
, sha1
, sizeof(entry
->sha1
));
308 anv_pipeline_cache_add_entry(cache
, entry
, state
.offset
);
311 pthread_mutex_unlock(&cache
->mutex
);
313 memcpy(state
.map
+ preamble_size
, kernel
, kernel_size
);
315 if (!cache
->device
->info
.has_llc
)
316 anv_state_clflush(state
);
318 *prog_data
= (const struct brw_stage_prog_data
*) entry
->prog_data
;
320 return state
.offset
+ preamble_size
;
323 struct cache_header
{
324 uint32_t header_size
;
325 uint32_t header_version
;
328 uint8_t uuid
[VK_UUID_SIZE
];
332 anv_pipeline_cache_load(struct anv_pipeline_cache
*cache
,
333 const void *data
, size_t size
)
335 struct anv_device
*device
= cache
->device
;
336 struct cache_header header
;
337 uint8_t uuid
[VK_UUID_SIZE
];
339 if (size
< sizeof(header
))
341 memcpy(&header
, data
, sizeof(header
));
342 if (header
.header_size
< sizeof(header
))
344 if (header
.header_version
!= VK_PIPELINE_CACHE_HEADER_VERSION_ONE
)
346 if (header
.vendor_id
!= 0x8086)
348 if (header
.device_id
!= device
->chipset_id
)
350 anv_device_get_cache_uuid(uuid
);
351 if (memcmp(header
.uuid
, uuid
, VK_UUID_SIZE
) != 0)
354 void *end
= (void *) data
+ size
;
355 void *p
= (void *) data
+ header
.header_size
;
358 struct cache_entry
*entry
= p
;
360 void *data
= entry
->prog_data
;
361 const struct brw_stage_prog_data
*prog_data
= data
;
362 data
+= entry
->prog_data_size
;
364 struct anv_pipeline_binding
*surface_to_descriptor
= data
;
365 data
+= entry
->surface_count
* sizeof(struct anv_pipeline_binding
);
366 struct anv_pipeline_binding
*sampler_to_descriptor
= data
;
367 data
+= entry
->sampler_count
* sizeof(struct anv_pipeline_binding
);
370 struct anv_pipeline_bind_map map
= {
371 .surface_count
= entry
->surface_count
,
372 .sampler_count
= entry
->sampler_count
,
373 .image_count
= entry
->image_count
,
374 .surface_to_descriptor
= surface_to_descriptor
,
375 .sampler_to_descriptor
= sampler_to_descriptor
378 anv_pipeline_cache_upload_kernel(cache
, entry
->sha1
,
379 kernel
, entry
->kernel_size
,
381 entry
->prog_data_size
, &map
);
382 p
= kernel
+ entry
->kernel_size
;
386 VkResult
anv_CreatePipelineCache(
388 const VkPipelineCacheCreateInfo
* pCreateInfo
,
389 const VkAllocationCallbacks
* pAllocator
,
390 VkPipelineCache
* pPipelineCache
)
392 ANV_FROM_HANDLE(anv_device
, device
, _device
);
393 struct anv_pipeline_cache
*cache
;
395 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
);
396 assert(pCreateInfo
->flags
== 0);
398 cache
= anv_alloc2(&device
->alloc
, pAllocator
,
400 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
402 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
404 anv_pipeline_cache_init(cache
, device
);
406 if (pCreateInfo
->initialDataSize
> 0)
407 anv_pipeline_cache_load(cache
,
408 pCreateInfo
->pInitialData
,
409 pCreateInfo
->initialDataSize
);
411 *pPipelineCache
= anv_pipeline_cache_to_handle(cache
);
416 void anv_DestroyPipelineCache(
418 VkPipelineCache _cache
,
419 const VkAllocationCallbacks
* pAllocator
)
421 ANV_FROM_HANDLE(anv_device
, device
, _device
);
422 ANV_FROM_HANDLE(anv_pipeline_cache
, cache
, _cache
);
424 anv_pipeline_cache_finish(cache
);
426 anv_free2(&device
->alloc
, pAllocator
, cache
);
429 VkResult
anv_GetPipelineCacheData(
431 VkPipelineCache _cache
,
435 ANV_FROM_HANDLE(anv_device
, device
, _device
);
436 ANV_FROM_HANDLE(anv_pipeline_cache
, cache
, _cache
);
437 struct cache_header
*header
;
439 const size_t size
= sizeof(*header
) + cache
->total_size
;
446 if (*pDataSize
< sizeof(*header
)) {
448 return VK_INCOMPLETE
;
451 void *p
= pData
, *end
= pData
+ *pDataSize
;
453 header
->header_size
= sizeof(*header
);
454 header
->header_version
= VK_PIPELINE_CACHE_HEADER_VERSION_ONE
;
455 header
->vendor_id
= 0x8086;
456 header
->device_id
= device
->chipset_id
;
457 anv_device_get_cache_uuid(header
->uuid
);
458 p
+= header
->header_size
;
460 struct cache_entry
*entry
;
461 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
462 if (cache
->hash_table
[i
] == ~0)
465 entry
= cache
->program_stream
.block_pool
->map
+ cache
->hash_table
[i
];
466 const uint32_t size
= entry_size(entry
);
467 if (end
< p
+ size
+ entry
->kernel_size
)
470 memcpy(p
, entry
, size
);
473 void *kernel
= (void *) entry
+ align_u32(size
, 64);
475 memcpy(p
, kernel
, entry
->kernel_size
);
476 p
+= entry
->kernel_size
;
479 *pDataSize
= p
- pData
;
485 anv_pipeline_cache_merge(struct anv_pipeline_cache
*dst
,
486 struct anv_pipeline_cache
*src
)
488 for (uint32_t i
= 0; i
< src
->table_size
; i
++) {
489 const uint32_t offset
= src
->hash_table
[i
];
493 struct cache_entry
*entry
=
494 src
->program_stream
.block_pool
->map
+ offset
;
496 if (anv_pipeline_cache_search(dst
, entry
->sha1
, NULL
, NULL
) != NO_KERNEL
)
499 anv_pipeline_cache_add_entry(dst
, entry
, offset
);
503 VkResult
anv_MergePipelineCaches(
505 VkPipelineCache destCache
,
506 uint32_t srcCacheCount
,
507 const VkPipelineCache
* pSrcCaches
)
509 ANV_FROM_HANDLE(anv_pipeline_cache
, dst
, destCache
);
511 for (uint32_t i
= 0; i
< srcCacheCount
; i
++) {
512 ANV_FROM_HANDLE(anv_pipeline_cache
, src
, pSrcCaches
[i
]);
514 anv_pipeline_cache_merge(dst
, src
);