2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/mesa-sha1.h"
25 #include "util/debug.h"
26 #include "anv_private.h"
30 * - Compact binding table layout so it's tight and not dependent on
31 * descriptor set layout.
33 * - Review prog_data struct for size and cacheability: struct
34 * brw_stage_prog_data has binding_table which uses a lot of uint32_t for 8
35 * bit quantities etc; param, pull_param, and image_params are pointers, we
36 * just need the compation map. use bit fields for all bools, eg
41 anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
42 struct anv_device
*device
)
44 cache
->device
= device
;
45 anv_state_stream_init(&cache
->program_stream
,
46 &device
->instruction_block_pool
);
47 pthread_mutex_init(&cache
->mutex
, NULL
);
49 cache
->kernel_count
= 0;
50 cache
->total_size
= 0;
51 cache
->table_size
= 1024;
52 const size_t byte_size
= cache
->table_size
* sizeof(cache
->hash_table
[0]);
53 cache
->hash_table
= malloc(byte_size
);
55 /* We don't consider allocation failure fatal, we just start with a 0-sized
57 if (cache
->hash_table
== NULL
)
58 cache
->table_size
= 0;
60 memset(cache
->hash_table
, 0xff, byte_size
);
64 anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
)
66 anv_state_stream_finish(&cache
->program_stream
);
67 pthread_mutex_destroy(&cache
->mutex
);
68 free(cache
->hash_table
);
72 unsigned char sha1
[20];
73 uint32_t prog_data_size
;
75 uint32_t surface_count
;
76 uint32_t sampler_count
;
81 /* kernel follows prog_data at next 64 byte aligned address */
85 entry_size(struct cache_entry
*entry
)
87 /* This returns the number of bytes needed to serialize an entry, which
88 * doesn't include the alignment padding bytes.
91 const uint32_t map_size
=
92 entry
->surface_count
* sizeof(struct anv_pipeline_binding
) +
93 entry
->sampler_count
* sizeof(struct anv_pipeline_binding
);
95 return sizeof(*entry
) + entry
->prog_data_size
+ map_size
;
99 anv_hash_shader(unsigned char *hash
, const void *key
, size_t key_size
,
100 struct anv_shader_module
*module
,
101 const char *entrypoint
,
102 const VkSpecializationInfo
*spec_info
)
104 struct mesa_sha1
*ctx
;
106 ctx
= _mesa_sha1_init();
107 _mesa_sha1_update(ctx
, key
, key_size
);
108 _mesa_sha1_update(ctx
, module
->sha1
, sizeof(module
->sha1
));
109 _mesa_sha1_update(ctx
, entrypoint
, strlen(entrypoint
));
110 /* hash in shader stage, pipeline layout? */
112 _mesa_sha1_update(ctx
, spec_info
->pMapEntries
,
113 spec_info
->mapEntryCount
* sizeof spec_info
->pMapEntries
[0]);
114 _mesa_sha1_update(ctx
, spec_info
->pData
, spec_info
->dataSize
);
116 _mesa_sha1_final(ctx
, hash
);
120 anv_pipeline_cache_search_unlocked(struct anv_pipeline_cache
*cache
,
121 const unsigned char *sha1
,
122 const struct brw_stage_prog_data
**prog_data
,
123 struct anv_pipeline_bind_map
*map
)
125 const uint32_t mask
= cache
->table_size
- 1;
126 const uint32_t start
= (*(uint32_t *) sha1
);
128 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
129 const uint32_t index
= (start
+ i
) & mask
;
130 const uint32_t offset
= cache
->hash_table
[index
];
135 struct cache_entry
*entry
=
136 cache
->program_stream
.block_pool
->map
+ offset
;
137 if (memcmp(entry
->sha1
, sha1
, sizeof(entry
->sha1
)) == 0) {
140 void *p
= entry
->prog_data
;
142 p
+= entry
->prog_data_size
;
143 map
->surface_count
= entry
->surface_count
;
144 map
->sampler_count
= entry
->sampler_count
;
145 map
->image_count
= entry
->image_count
;
146 map
->surface_to_descriptor
= p
;
147 p
+= map
->surface_count
* sizeof(struct anv_pipeline_binding
);
148 map
->sampler_to_descriptor
= p
;
151 return offset
+ align_u32(entry_size(entry
), 64);
155 unreachable("hash table should never be full");
159 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
160 const unsigned char *sha1
,
161 const struct brw_stage_prog_data
**prog_data
,
162 struct anv_pipeline_bind_map
*map
)
166 pthread_mutex_lock(&cache
->mutex
);
168 kernel
= anv_pipeline_cache_search_unlocked(cache
, sha1
, prog_data
, map
);
170 pthread_mutex_unlock(&cache
->mutex
);
176 anv_pipeline_cache_set_entry(struct anv_pipeline_cache
*cache
,
177 struct cache_entry
*entry
, uint32_t entry_offset
)
179 const uint32_t mask
= cache
->table_size
- 1;
180 const uint32_t start
= (*(uint32_t *) entry
->sha1
);
182 /* We'll always be able to insert when we get here. */
183 assert(cache
->kernel_count
< cache
->table_size
/ 2);
185 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
186 const uint32_t index
= (start
+ i
) & mask
;
187 if (cache
->hash_table
[index
] == ~0) {
188 cache
->hash_table
[index
] = entry_offset
;
193 cache
->total_size
+= entry_size(entry
) + entry
->kernel_size
;
194 cache
->kernel_count
++;
198 anv_pipeline_cache_grow(struct anv_pipeline_cache
*cache
)
200 const uint32_t table_size
= cache
->table_size
* 2;
201 const uint32_t old_table_size
= cache
->table_size
;
202 const size_t byte_size
= table_size
* sizeof(cache
->hash_table
[0]);
204 uint32_t *old_table
= cache
->hash_table
;
206 table
= malloc(byte_size
);
208 return VK_ERROR_OUT_OF_HOST_MEMORY
;
210 cache
->hash_table
= table
;
211 cache
->table_size
= table_size
;
212 cache
->kernel_count
= 0;
213 cache
->total_size
= 0;
215 memset(cache
->hash_table
, 0xff, byte_size
);
216 for (uint32_t i
= 0; i
< old_table_size
; i
++) {
217 const uint32_t offset
= old_table
[i
];
221 struct cache_entry
*entry
=
222 cache
->program_stream
.block_pool
->map
+ offset
;
223 anv_pipeline_cache_set_entry(cache
, entry
, offset
);
232 anv_pipeline_cache_add_entry(struct anv_pipeline_cache
*cache
,
233 struct cache_entry
*entry
, uint32_t entry_offset
)
235 if (cache
->kernel_count
== cache
->table_size
/ 2)
236 anv_pipeline_cache_grow(cache
);
238 /* Failing to grow that hash table isn't fatal, but may mean we don't
239 * have enough space to add this new kernel. Only add it if there's room.
241 if (cache
->kernel_count
< cache
->table_size
/ 2)
242 anv_pipeline_cache_set_entry(cache
, entry
, entry_offset
);
246 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
247 const unsigned char *sha1
,
248 const void *kernel
, size_t kernel_size
,
249 const struct brw_stage_prog_data
**prog_data
,
250 size_t prog_data_size
,
251 struct anv_pipeline_bind_map
*map
)
253 pthread_mutex_lock(&cache
->mutex
);
255 /* Before uploading, check again that another thread didn't upload this
256 * shader while we were compiling it.
259 uint32_t cached_kernel
=
260 anv_pipeline_cache_search_unlocked(cache
, sha1
, prog_data
, map
);
261 if (cached_kernel
!= NO_KERNEL
) {
262 pthread_mutex_unlock(&cache
->mutex
);
263 return cached_kernel
;
267 struct cache_entry
*entry
;
269 const uint32_t map_size
=
270 map
->surface_count
* sizeof(struct anv_pipeline_binding
) +
271 map
->sampler_count
* sizeof(struct anv_pipeline_binding
);
273 const uint32_t preamble_size
=
274 align_u32(sizeof(*entry
) + prog_data_size
+ map_size
, 64);
276 const uint32_t size
= preamble_size
+ kernel_size
;
278 assert(size
< cache
->program_stream
.block_pool
->block_size
);
279 const struct anv_state state
=
280 anv_state_stream_alloc(&cache
->program_stream
, size
, 64);
283 entry
->prog_data_size
= prog_data_size
;
284 entry
->surface_count
= map
->surface_count
;
285 entry
->sampler_count
= map
->sampler_count
;
286 entry
->image_count
= map
->image_count
;
287 entry
->kernel_size
= kernel_size
;
289 void *p
= entry
->prog_data
;
290 memcpy(p
, *prog_data
, prog_data_size
);
293 memcpy(p
, map
->surface_to_descriptor
,
294 map
->surface_count
* sizeof(struct anv_pipeline_binding
));
295 map
->surface_to_descriptor
= p
;
296 p
+= map
->surface_count
* sizeof(struct anv_pipeline_binding
);
298 memcpy(p
, map
->sampler_to_descriptor
,
299 map
->sampler_count
* sizeof(struct anv_pipeline_binding
));
300 map
->sampler_to_descriptor
= p
;
302 if (sha1
&& env_var_as_boolean("ANV_ENABLE_PIPELINE_CACHE", false)) {
303 assert(anv_pipeline_cache_search_unlocked(cache
, sha1
,
304 NULL
, NULL
) == NO_KERNEL
);
306 memcpy(entry
->sha1
, sha1
, sizeof(entry
->sha1
));
307 anv_pipeline_cache_add_entry(cache
, entry
, state
.offset
);
310 pthread_mutex_unlock(&cache
->mutex
);
312 memcpy(state
.map
+ preamble_size
, kernel
, kernel_size
);
314 if (!cache
->device
->info
.has_llc
)
315 anv_state_clflush(state
);
317 *prog_data
= (const struct brw_stage_prog_data
*) entry
->prog_data
;
319 return state
.offset
+ preamble_size
;
322 struct cache_header
{
323 uint32_t header_size
;
324 uint32_t header_version
;
327 uint8_t uuid
[VK_UUID_SIZE
];
331 anv_pipeline_cache_load(struct anv_pipeline_cache
*cache
,
332 const void *data
, size_t size
)
334 struct anv_device
*device
= cache
->device
;
335 struct cache_header header
;
336 uint8_t uuid
[VK_UUID_SIZE
];
338 if (size
< sizeof(header
))
340 memcpy(&header
, data
, sizeof(header
));
341 if (header
.header_size
< sizeof(header
))
343 if (header
.header_version
!= VK_PIPELINE_CACHE_HEADER_VERSION_ONE
)
345 if (header
.vendor_id
!= 0x8086)
347 if (header
.device_id
!= device
->chipset_id
)
349 anv_device_get_cache_uuid(uuid
);
350 if (memcmp(header
.uuid
, uuid
, VK_UUID_SIZE
) != 0)
353 void *end
= (void *) data
+ size
;
354 void *p
= (void *) data
+ header
.header_size
;
357 struct cache_entry
*entry
= p
;
359 void *data
= entry
->prog_data
;
360 const struct brw_stage_prog_data
*prog_data
= data
;
361 data
+= entry
->prog_data_size
;
363 struct anv_pipeline_binding
*surface_to_descriptor
= data
;
364 data
+= entry
->surface_count
* sizeof(struct anv_pipeline_binding
);
365 struct anv_pipeline_binding
*sampler_to_descriptor
= data
;
366 data
+= entry
->sampler_count
* sizeof(struct anv_pipeline_binding
);
369 struct anv_pipeline_bind_map map
= {
370 .surface_count
= entry
->surface_count
,
371 .sampler_count
= entry
->sampler_count
,
372 .image_count
= entry
->image_count
,
373 .surface_to_descriptor
= surface_to_descriptor
,
374 .sampler_to_descriptor
= sampler_to_descriptor
377 anv_pipeline_cache_upload_kernel(cache
, entry
->sha1
,
378 kernel
, entry
->kernel_size
,
380 entry
->prog_data_size
, &map
);
381 p
= kernel
+ entry
->kernel_size
;
385 VkResult
anv_CreatePipelineCache(
387 const VkPipelineCacheCreateInfo
* pCreateInfo
,
388 const VkAllocationCallbacks
* pAllocator
,
389 VkPipelineCache
* pPipelineCache
)
391 ANV_FROM_HANDLE(anv_device
, device
, _device
);
392 struct anv_pipeline_cache
*cache
;
394 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
);
395 assert(pCreateInfo
->flags
== 0);
397 cache
= anv_alloc2(&device
->alloc
, pAllocator
,
399 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
401 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
403 anv_pipeline_cache_init(cache
, device
);
405 if (pCreateInfo
->initialDataSize
> 0)
406 anv_pipeline_cache_load(cache
,
407 pCreateInfo
->pInitialData
,
408 pCreateInfo
->initialDataSize
);
410 *pPipelineCache
= anv_pipeline_cache_to_handle(cache
);
415 void anv_DestroyPipelineCache(
417 VkPipelineCache _cache
,
418 const VkAllocationCallbacks
* pAllocator
)
420 ANV_FROM_HANDLE(anv_device
, device
, _device
);
421 ANV_FROM_HANDLE(anv_pipeline_cache
, cache
, _cache
);
423 anv_pipeline_cache_finish(cache
);
425 anv_free2(&device
->alloc
, pAllocator
, cache
);
428 VkResult
anv_GetPipelineCacheData(
430 VkPipelineCache _cache
,
434 ANV_FROM_HANDLE(anv_device
, device
, _device
);
435 ANV_FROM_HANDLE(anv_pipeline_cache
, cache
, _cache
);
436 struct cache_header
*header
;
438 const size_t size
= sizeof(*header
) + cache
->total_size
;
445 if (*pDataSize
< sizeof(*header
)) {
447 return VK_INCOMPLETE
;
450 void *p
= pData
, *end
= pData
+ *pDataSize
;
452 header
->header_size
= sizeof(*header
);
453 header
->header_version
= VK_PIPELINE_CACHE_HEADER_VERSION_ONE
;
454 header
->vendor_id
= 0x8086;
455 header
->device_id
= device
->chipset_id
;
456 anv_device_get_cache_uuid(header
->uuid
);
457 p
+= header
->header_size
;
459 struct cache_entry
*entry
;
460 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
461 if (cache
->hash_table
[i
] == ~0)
464 entry
= cache
->program_stream
.block_pool
->map
+ cache
->hash_table
[i
];
465 const uint32_t size
= entry_size(entry
);
466 if (end
< p
+ size
+ entry
->kernel_size
)
469 memcpy(p
, entry
, size
);
472 void *kernel
= (void *) entry
+ align_u32(size
, 64);
474 memcpy(p
, kernel
, entry
->kernel_size
);
475 p
+= entry
->kernel_size
;
478 *pDataSize
= p
- pData
;
484 anv_pipeline_cache_merge(struct anv_pipeline_cache
*dst
,
485 struct anv_pipeline_cache
*src
)
487 for (uint32_t i
= 0; i
< src
->table_size
; i
++) {
488 const uint32_t offset
= src
->hash_table
[i
];
492 struct cache_entry
*entry
=
493 src
->program_stream
.block_pool
->map
+ offset
;
495 if (anv_pipeline_cache_search(dst
, entry
->sha1
, NULL
, NULL
) != NO_KERNEL
)
498 anv_pipeline_cache_add_entry(dst
, entry
, offset
);
502 VkResult
anv_MergePipelineCaches(
504 VkPipelineCache destCache
,
505 uint32_t srcCacheCount
,
506 const VkPipelineCache
* pSrcCaches
)
508 ANV_FROM_HANDLE(anv_pipeline_cache
, dst
, destCache
);
510 for (uint32_t i
= 0; i
< srcCacheCount
; i
++) {
511 ANV_FROM_HANDLE(anv_pipeline_cache
, src
, pSrcCaches
[i
]);
513 anv_pipeline_cache_merge(dst
, src
);