2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 #include "drm-uapi/i915_drm.h"
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
43 #define VG(x) ((void)0)
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "common/gen_l3_config.h"
50 #include "dev/gen_device_info.h"
51 #include "blorp/blorp.h"
52 #include "compiler/brw_compiler.h"
53 #include "util/bitset.h"
54 #include "util/macros.h"
55 #include "util/hash_table.h"
56 #include "util/list.h"
57 #include "util/sparse_array.h"
58 #include "util/u_atomic.h"
59 #include "util/u_vector.h"
60 #include "util/u_math.h"
62 #include "util/xmlconfig.h"
64 #include "vk_debug_report.h"
66 /* Pre-declarations needed for WSI entrypoints */
69 typedef struct xcb_connection_t xcb_connection_t
;
70 typedef uint32_t xcb_visualid_t
;
71 typedef uint32_t xcb_window_t
;
75 struct anv_buffer_view
;
76 struct anv_image_view
;
79 struct gen_aux_map_context
;
80 struct gen_perf_config
;
82 #include <vulkan/vulkan.h>
83 #include <vulkan/vulkan_intel.h>
84 #include <vulkan/vk_icd.h>
86 #include "anv_android.h"
87 #include "anv_entrypoints.h"
88 #include "anv_extensions.h"
91 #include "dev/gen_debug.h"
92 #include "common/intel_log.h"
93 #include "wsi_common.h"
95 #define NSEC_PER_SEC 1000000000ull
97 /* anv Virtual Memory Layout
98 * =========================
100 * When the anv driver is determining the virtual graphics addresses of memory
101 * objects itself using the softpin mechanism, the following memory ranges
104 * Three special considerations to notice:
106 * (1) the dynamic state pool is located within the same 4 GiB as the low
107 * heap. This is to work around a VF cache issue described in a comment in
108 * anv_physical_device_init_heaps.
110 * (2) the binding table pool is located at lower addresses than the surface
111 * state pool, within a 4 GiB range. This allows surface state base addresses
112 * to cover both binding tables (16 bit offsets) and surface states (32 bit
115 * (3) the last 4 GiB of the address space is withheld from the high
116 * heap. Various hardware units will read past the end of an object for
117 * various reasons. This healthy margin prevents reads from wrapping around
120 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
121 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
122 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
123 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
124 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
125 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
126 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
127 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
128 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
129 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
130 #define CLIENT_VISIBLE_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
131 #define CLIENT_VISIBLE_HEAP_MAX_ADDRESS 0x0002bfffffffULL
132 #define HIGH_HEAP_MIN_ADDRESS 0x0002c0000000ULL /* 11 GiB */
134 #define LOW_HEAP_SIZE \
135 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
136 #define DYNAMIC_STATE_POOL_SIZE \
137 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
138 #define BINDING_TABLE_POOL_SIZE \
139 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
140 #define SURFACE_STATE_POOL_SIZE \
141 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
142 #define INSTRUCTION_STATE_POOL_SIZE \
143 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
144 #define CLIENT_VISIBLE_HEAP_SIZE \
145 (CLIENT_VISIBLE_HEAP_MAX_ADDRESS - CLIENT_VISIBLE_HEAP_MIN_ADDRESS + 1)
147 /* Allowing different clear colors requires us to perform a depth resolve at
148 * the end of certain render passes. This is because while slow clears store
149 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
150 * See the PRMs for examples describing when additional resolves would be
151 * necessary. To enable fast clears without requiring extra resolves, we set
152 * the clear value to a globally-defined one. We could allow different values
153 * if the user doesn't expect coherent data during or after a render passes
154 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
155 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
156 * 1.0f seems to be the only value used. The only application that doesn't set
157 * this value does so through the usage of an seemingly uninitialized clear
160 #define ANV_HZ_FC_VAL 1.0f
163 #define MAX_XFB_BUFFERS 4
164 #define MAX_XFB_STREAMS 4
167 #define MAX_VIEWPORTS 16
168 #define MAX_SCISSORS 16
169 #define MAX_PUSH_CONSTANTS_SIZE 128
170 #define MAX_DYNAMIC_BUFFERS 16
171 #define MAX_IMAGES 64
172 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
173 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
174 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
176 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
178 * "The surface state model is used when a Binding Table Index (specified
179 * in the message descriptor) of less than 240 is specified. In this model,
180 * the Binding Table Index is used to index into the binding table, and the
181 * binding table entry contains a pointer to the SURFACE_STATE."
183 * Binding table values above 240 are used for various things in the hardware
184 * such as stateless, stateless with incoherent cache, SLM, and bindless.
186 #define MAX_BINDING_TABLE_SIZE 240
188 /* The kernel relocation API has a limitation of a 32-bit delta value
189 * applied to the address before it is written which, in spite of it being
190 * unsigned, is treated as signed . Because of the way that this maps to
191 * the Vulkan API, we cannot handle an offset into a buffer that does not
192 * fit into a signed 32 bits. The only mechanism we have for dealing with
193 * this at the moment is to limit all VkDeviceMemory objects to a maximum
194 * of 2GB each. The Vulkan spec allows us to do this:
196 * "Some platforms may have a limit on the maximum size of a single
197 * allocation. For example, certain systems may fail to create
198 * allocations with a size greater than or equal to 4GB. Such a limit is
199 * implementation-dependent, and if such a failure occurs then the error
200 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
202 * We don't use vk_error here because it's not an error so much as an
203 * indication to the application that the allocation is too large.
205 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
207 #define ANV_SVGS_VB_INDEX MAX_VBS
208 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
210 /* We reserve this MI ALU register for the purpose of handling predication.
211 * Other code which uses the MI ALU should leave it alone.
213 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
215 /* For gen12 we set the streamout buffers using 4 separate commands
216 * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout
217 * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of
218 * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the
219 * 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode.
220 * SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for
221 * 3DSTATE_SO_BUFFER_INDEX_0.
223 #define SO_BUFFER_INDEX_0_CMD 0x60
224 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
226 static inline uint32_t
227 align_down_npot_u32(uint32_t v
, uint32_t a
)
232 static inline uint32_t
233 align_u32(uint32_t v
, uint32_t a
)
235 assert(a
!= 0 && a
== (a
& -a
));
236 return (v
+ a
- 1) & ~(a
- 1);
239 static inline uint64_t
240 align_down_u64(uint64_t v
, uint64_t a
)
242 assert(a
!= 0 && a
== (a
& -a
));
246 static inline uint64_t
247 align_u64(uint64_t v
, uint64_t a
)
249 return align_down_u64(v
+ a
- 1, a
);
252 static inline int32_t
253 align_i32(int32_t v
, int32_t a
)
255 assert(a
!= 0 && a
== (a
& -a
));
256 return (v
+ a
- 1) & ~(a
- 1);
259 /** Alignment must be a power of 2. */
261 anv_is_aligned(uintmax_t n
, uintmax_t a
)
263 assert(a
== (a
& -a
));
264 return (n
& (a
- 1)) == 0;
267 static inline uint32_t
268 anv_minify(uint32_t n
, uint32_t levels
)
270 if (unlikely(n
== 0))
273 return MAX2(n
>> levels
, 1);
277 anv_clamp_f(float f
, float min
, float max
)
290 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
292 if (*inout_mask
& clear_mask
) {
293 *inout_mask
&= ~clear_mask
;
300 static inline union isl_color_value
301 vk_to_isl_color(VkClearColorValue color
)
303 return (union isl_color_value
) {
313 static inline void *anv_unpack_ptr(uintptr_t ptr
, int bits
, int *flags
)
315 uintptr_t mask
= (1ull << bits
) - 1;
317 return (void *) (ptr
& ~mask
);
320 static inline uintptr_t anv_pack_ptr(void *ptr
, int bits
, int flags
)
322 uintptr_t value
= (uintptr_t) ptr
;
323 uintptr_t mask
= (1ull << bits
) - 1;
324 return value
| (mask
& flags
);
327 #define for_each_bit(b, dword) \
328 for (uint32_t __dword = (dword); \
329 (b) = __builtin_ffs(__dword) - 1, __dword; \
330 __dword &= ~(1 << (b)))
332 #define typed_memcpy(dest, src, count) ({ \
333 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
334 memcpy((dest), (src), (count) * sizeof(*(src))); \
337 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
338 * to be added here in order to utilize mapping in debug/error/perf macros.
340 #define REPORT_OBJECT_TYPE(o) \
341 __builtin_choose_expr ( \
342 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
343 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
344 __builtin_choose_expr ( \
345 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
346 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
347 __builtin_choose_expr ( \
348 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
349 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
350 __builtin_choose_expr ( \
351 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
352 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
353 __builtin_choose_expr ( \
354 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
355 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
356 __builtin_choose_expr ( \
357 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
358 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
359 __builtin_choose_expr ( \
360 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
361 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
362 __builtin_choose_expr ( \
363 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
364 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
365 __builtin_choose_expr ( \
366 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
367 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
368 __builtin_choose_expr ( \
369 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
370 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
371 __builtin_choose_expr ( \
372 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
373 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
374 __builtin_choose_expr ( \
375 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
376 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
377 __builtin_choose_expr ( \
378 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
379 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
380 __builtin_choose_expr ( \
381 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
382 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
383 __builtin_choose_expr ( \
384 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
385 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
386 __builtin_choose_expr ( \
387 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
388 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
389 __builtin_choose_expr ( \
390 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
391 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
392 __builtin_choose_expr ( \
393 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
394 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
395 __builtin_choose_expr ( \
396 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
397 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
398 __builtin_choose_expr ( \
399 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
400 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
401 __builtin_choose_expr ( \
402 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
403 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
404 __builtin_choose_expr ( \
405 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
406 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
407 __builtin_choose_expr ( \
408 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
409 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
410 __builtin_choose_expr ( \
411 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
412 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
413 __builtin_choose_expr ( \
414 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
415 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
416 __builtin_choose_expr ( \
417 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
418 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
419 __builtin_choose_expr ( \
420 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
421 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
422 __builtin_choose_expr ( \
423 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
424 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
425 __builtin_choose_expr ( \
426 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
427 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
428 __builtin_choose_expr ( \
429 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
430 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
431 __builtin_choose_expr ( \
432 __builtin_types_compatible_p (__typeof (o), void*), \
433 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
434 /* The void expression results in a compile-time error \
435 when assigning the result to something. */ \
436 (void)0)))))))))))))))))))))))))))))))
438 /* Whenever we generate an error, pass it through this function. Useful for
439 * debugging, where we can break on it. Only call at error site, not when
440 * propagating errors. Might be useful to plug in a stack trace here.
443 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
444 VkDebugReportObjectTypeEXT type
, VkResult error
,
445 const char *file
, int line
, const char *format
,
448 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
449 VkDebugReportObjectTypeEXT type
, VkResult error
,
450 const char *file
, int line
, const char *format
, ...)
451 anv_printflike(7, 8);
454 #define vk_error(error) __vk_errorf(NULL, NULL,\
455 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
456 error, __FILE__, __LINE__, NULL)
457 #define vk_errorfi(instance, obj, error, format, ...)\
458 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
459 __FILE__, __LINE__, format, ## __VA_ARGS__)
460 #define vk_errorf(device, obj, error, format, ...)\
461 vk_errorfi(anv_device_instance_or_null(device),\
462 obj, error, format, ## __VA_ARGS__)
464 #define vk_error(error) error
465 #define vk_errorfi(instance, obj, error, format, ...) error
466 #define vk_errorf(device, obj, error, format, ...) error
470 * Warn on ignored extension structs.
472 * The Vulkan spec requires us to ignore unsupported or unknown structs in
473 * a pNext chain. In debug mode, emitting warnings for ignored structs may
474 * help us discover structs that we should not have ignored.
477 * From the Vulkan 1.0.38 spec:
479 * Any component of the implementation (the loader, any enabled layers,
480 * and drivers) must skip over, without processing (other than reading the
481 * sType and pNext members) any chained structures with sType values not
482 * defined by extensions supported by that component.
484 #define anv_debug_ignored_stype(sType) \
485 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
487 void __anv_perf_warn(struct anv_device
*device
, const void *object
,
488 VkDebugReportObjectTypeEXT type
, const char *file
,
489 int line
, const char *format
, ...)
490 anv_printflike(6, 7);
491 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
492 void anv_loge_v(const char *format
, va_list va
);
495 * Print a FINISHME message, including its source location.
497 #define anv_finishme(format, ...) \
499 static bool reported = false; \
501 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
508 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
510 #define anv_perf_warn(instance, obj, format, ...) \
512 static bool reported = false; \
513 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
514 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
515 format, ##__VA_ARGS__); \
520 /* A non-fatal assert. Useful for debugging. */
522 #define anv_assert(x) ({ \
523 if (unlikely(!(x))) \
524 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
527 #define anv_assert(x)
530 /* A multi-pointer allocator
532 * When copying data structures from the user (such as a render pass), it's
533 * common to need to allocate data for a bunch of different things. Instead
534 * of doing several allocations and having to handle all of the error checking
535 * that entails, it can be easier to do a single allocation. This struct
536 * helps facilitate that. The intended usage looks like this:
539 * anv_multialloc_add(&ma, &main_ptr, 1);
540 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
541 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
543 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
544 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
546 struct anv_multialloc
{
554 #define ANV_MULTIALLOC_INIT \
555 ((struct anv_multialloc) { 0, })
557 #define ANV_MULTIALLOC(_name) \
558 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
560 __attribute__((always_inline
))
562 _anv_multialloc_add(struct anv_multialloc
*ma
,
563 void **ptr
, size_t size
, size_t align
)
565 size_t offset
= align_u64(ma
->size
, align
);
566 ma
->size
= offset
+ size
;
567 ma
->align
= MAX2(ma
->align
, align
);
569 /* Store the offset in the pointer. */
570 *ptr
= (void *)(uintptr_t)offset
;
572 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
573 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
576 #define anv_multialloc_add_size(_ma, _ptr, _size) \
577 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
579 #define anv_multialloc_add(_ma, _ptr, _count) \
580 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
582 __attribute__((always_inline
))
584 anv_multialloc_alloc(struct anv_multialloc
*ma
,
585 const VkAllocationCallbacks
*alloc
,
586 VkSystemAllocationScope scope
)
588 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
592 /* Fill out each of the pointers with their final value.
594 * for (uint32_t i = 0; i < ma->ptr_count; i++)
595 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
597 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
598 * constant, GCC is incapable of figuring this out and unrolling the loop
599 * so we have to give it a little help.
601 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
602 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
603 if ((_i) < ma->ptr_count) \
604 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
605 _ANV_MULTIALLOC_UPDATE_POINTER(0);
606 _ANV_MULTIALLOC_UPDATE_POINTER(1);
607 _ANV_MULTIALLOC_UPDATE_POINTER(2);
608 _ANV_MULTIALLOC_UPDATE_POINTER(3);
609 _ANV_MULTIALLOC_UPDATE_POINTER(4);
610 _ANV_MULTIALLOC_UPDATE_POINTER(5);
611 _ANV_MULTIALLOC_UPDATE_POINTER(6);
612 _ANV_MULTIALLOC_UPDATE_POINTER(7);
613 #undef _ANV_MULTIALLOC_UPDATE_POINTER
618 __attribute__((always_inline
))
620 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
621 const VkAllocationCallbacks
*parent_alloc
,
622 const VkAllocationCallbacks
*alloc
,
623 VkSystemAllocationScope scope
)
625 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
633 /* Index into the current validation list. This is used by the
634 * validation list building alrogithm to track which buffers are already
635 * in the validation list so that we can ensure uniqueness.
639 /* Index for use with util_sparse_array_free_list */
642 /* Last known offset. This value is provided by the kernel when we
643 * execbuf and is used as the presumed offset for the next bunch of
648 /** Size of the buffer not including implicit aux */
651 /* Map for internally mapped BOs.
653 * If ANV_BO_WRAPPER is set in flags, map points to the wrapped BO.
657 /** Size of the implicit CCS range at the end of the buffer
659 * On Gen12, CCS data is always a direct 1/256 scale-down. A single 64K
660 * page of main surface data maps to a 256B chunk of CCS data and that
661 * mapping is provided on TGL-LP by the AUX table which maps virtual memory
662 * addresses in the main surface to virtual memory addresses for CCS data.
664 * Because we can't change these maps around easily and because Vulkan
665 * allows two VkImages to be bound to overlapping memory regions (as long
666 * as the app is careful), it's not feasible to make this mapping part of
667 * the image. (On Gen11 and earlier, the mapping was provided via
668 * RENDER_SURFACE_STATE so each image had its own main -> CCS mapping.)
669 * Instead, we attach the CCS data directly to the buffer object and setup
670 * the AUX table mapping at BO creation time.
672 * This field is for internal tracking use by the BO allocator only and
673 * should not be touched by other parts of the code. If something wants to
674 * know if a BO has implicit CCS data, it should instead look at the
675 * has_implicit_ccs boolean below.
677 * This data is not included in maps of this buffer.
681 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
684 /** True if this BO may be shared with other processes */
687 /** True if this BO is a wrapper
689 * When set to true, none of the fields in this BO are meaningful except
690 * for anv_bo::is_wrapper and anv_bo::map which points to the actual BO.
691 * See also anv_bo_unwrap(). Wrapper BOs are not allowed when use_softpin
692 * is set in the physical device.
696 /** See also ANV_BO_ALLOC_FIXED_ADDRESS */
697 bool has_fixed_address
:1;
699 /** True if this BO wraps a host pointer */
700 bool from_host_ptr
:1;
702 /** See also ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS */
703 bool has_client_visible_address
:1;
705 /** True if this BO has implicit CCS data attached to it */
706 bool has_implicit_ccs
:1;
709 static inline struct anv_bo
*
710 anv_bo_ref(struct anv_bo
*bo
)
712 p_atomic_inc(&bo
->refcount
);
716 static inline struct anv_bo
*
717 anv_bo_unwrap(struct anv_bo
*bo
)
719 while (bo
->is_wrapper
)
724 /* Represents a lock-free linked list of "free" things. This is used by
725 * both the block pool and the state pools. Unfortunately, in order to
726 * solve the ABA problem, we can't use a single uint32_t head.
728 union anv_free_list
{
732 /* A simple count that is incremented every time the head changes. */
735 /* Make sure it's aligned to 64 bits. This will make atomic operations
736 * faster on 32 bit platforms.
738 uint64_t u64
__attribute__ ((aligned (8)));
741 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
743 struct anv_block_state
{
749 /* Make sure it's aligned to 64 bits. This will make atomic operations
750 * faster on 32 bit platforms.
752 uint64_t u64
__attribute__ ((aligned (8)));
756 #define anv_block_pool_foreach_bo(bo, pool) \
757 for (struct anv_bo **_pp_bo = (pool)->bos, *bo; \
758 _pp_bo != &(pool)->bos[(pool)->nbos] && (bo = *_pp_bo, true); \
761 #define ANV_MAX_BLOCK_POOL_BOS 20
763 struct anv_block_pool
{
764 struct anv_device
*device
;
767 /* Wrapper BO for use in relocation lists. This BO is simply a wrapper
768 * around the actual BO so that we grow the pool after the wrapper BO has
769 * been put in a relocation list. This is only used in the non-softpin
772 struct anv_bo wrapper_bo
;
774 struct anv_bo
*bos
[ANV_MAX_BLOCK_POOL_BOS
];
780 /* The address where the start of the pool is pinned. The various bos that
781 * are created as the pool grows will have addresses in the range
782 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
784 uint64_t start_address
;
786 /* The offset from the start of the bo to the "center" of the block
787 * pool. Pointers to allocated blocks are given by
788 * bo.map + center_bo_offset + offsets.
790 uint32_t center_bo_offset
;
792 /* Current memory map of the block pool. This pointer may or may not
793 * point to the actual beginning of the block pool memory. If
794 * anv_block_pool_alloc_back has ever been called, then this pointer
795 * will point to the "center" position of the buffer and all offsets
796 * (negative or positive) given out by the block pool alloc functions
797 * will be valid relative to this pointer.
799 * In particular, map == bo.map + center_offset
801 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
802 * since it will handle the softpin case as well, where this points to NULL.
808 * Array of mmaps and gem handles owned by the block pool, reclaimed when
809 * the block pool is destroyed.
811 struct u_vector mmap_cleanups
;
813 struct anv_block_state state
;
815 struct anv_block_state back_state
;
818 /* Block pools are backed by a fixed-size 1GB memfd */
819 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
821 /* The center of the block pool is also the middle of the memfd. This may
822 * change in the future if we decide differently for some reason.
824 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
826 static inline uint32_t
827 anv_block_pool_size(struct anv_block_pool
*pool
)
829 return pool
->state
.end
+ pool
->back_state
.end
;
839 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
841 struct anv_fixed_size_state_pool
{
842 union anv_free_list free_list
;
843 struct anv_block_state block
;
846 #define ANV_MIN_STATE_SIZE_LOG2 6
847 #define ANV_MAX_STATE_SIZE_LOG2 21
849 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
851 struct anv_free_entry
{
853 struct anv_state state
;
856 struct anv_state_table
{
857 struct anv_device
*device
;
859 struct anv_free_entry
*map
;
861 struct anv_block_state state
;
862 struct u_vector cleanups
;
865 struct anv_state_pool
{
866 struct anv_block_pool block_pool
;
868 struct anv_state_table table
;
870 /* The size of blocks which will be allocated from the block pool */
873 /** Free list for "back" allocations */
874 union anv_free_list back_alloc_free_list
;
876 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
879 struct anv_state_stream_block
;
881 struct anv_state_stream
{
882 struct anv_state_pool
*state_pool
;
884 /* The size of blocks to allocate from the state pool */
887 /* Current block we're allocating from */
888 struct anv_state block
;
890 /* Offset into the current block at which to allocate the next state */
893 /* List of all blocks allocated from this pool */
894 struct anv_state_stream_block
*block_list
;
897 /* The block_pool functions exported for testing only. The block pool should
898 * only be used via a state pool (see below).
900 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
901 struct anv_device
*device
,
902 uint64_t start_address
,
903 uint32_t initial_size
);
904 void anv_block_pool_finish(struct anv_block_pool
*pool
);
905 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
906 uint32_t block_size
, uint32_t *padding
);
907 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
908 uint32_t block_size
);
909 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
, uint32_t
912 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
913 struct anv_device
*device
,
914 uint64_t start_address
,
915 uint32_t block_size
);
916 void anv_state_pool_finish(struct anv_state_pool
*pool
);
917 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
918 uint32_t state_size
, uint32_t alignment
);
919 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
920 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
921 void anv_state_stream_init(struct anv_state_stream
*stream
,
922 struct anv_state_pool
*state_pool
,
923 uint32_t block_size
);
924 void anv_state_stream_finish(struct anv_state_stream
*stream
);
925 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
926 uint32_t size
, uint32_t alignment
);
928 VkResult
anv_state_table_init(struct anv_state_table
*table
,
929 struct anv_device
*device
,
930 uint32_t initial_entries
);
931 void anv_state_table_finish(struct anv_state_table
*table
);
932 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
934 void anv_free_list_push(union anv_free_list
*list
,
935 struct anv_state_table
*table
,
936 uint32_t idx
, uint32_t count
);
937 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
938 struct anv_state_table
*table
);
941 static inline struct anv_state
*
942 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
944 return &table
->map
[idx
].state
;
947 * Implements a pool of re-usable BOs. The interface is identical to that
948 * of block_pool except that each block is its own BO.
951 struct anv_device
*device
;
953 struct util_sparse_array_free_list free_list
[16];
956 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
957 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
958 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, uint32_t size
,
959 struct anv_bo
**bo_out
);
960 void anv_bo_pool_free(struct anv_bo_pool
*pool
, struct anv_bo
*bo
);
962 struct anv_scratch_pool
{
963 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
964 struct anv_bo
*bos
[16][MESA_SHADER_STAGES
];
967 void anv_scratch_pool_init(struct anv_device
*device
,
968 struct anv_scratch_pool
*pool
);
969 void anv_scratch_pool_finish(struct anv_device
*device
,
970 struct anv_scratch_pool
*pool
);
971 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
972 struct anv_scratch_pool
*pool
,
973 gl_shader_stage stage
,
974 unsigned per_thread_scratch
);
976 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
977 struct anv_bo_cache
{
978 struct util_sparse_array bo_map
;
979 pthread_mutex_t mutex
;
982 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
983 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
985 struct anv_memory_type
{
986 /* Standard bits passed on to the client */
987 VkMemoryPropertyFlags propertyFlags
;
991 struct anv_memory_heap
{
992 /* Standard bits passed on to the client */
994 VkMemoryHeapFlags flags
;
996 /* Driver-internal book-keeping */
1000 struct anv_physical_device
{
1001 VK_LOADER_DATA _loader_data
;
1003 /* Link in anv_instance::physical_devices */
1004 struct list_head link
;
1006 struct anv_instance
* instance
;
1016 struct gen_device_info info
;
1017 /** Amount of "GPU memory" we want to advertise
1019 * Clearly, this value is bogus since Intel is a UMA architecture. On
1020 * gen7 platforms, we are limited by GTT size unless we want to implement
1021 * fine-grained tracking and GTT splitting. On Broadwell and above we are
1022 * practically unlimited. However, we will never report more than 3/4 of
1023 * the total system ram to try and avoid running out of RAM.
1025 bool supports_48bit_addresses
;
1026 struct brw_compiler
* compiler
;
1027 struct isl_device isl_dev
;
1028 struct gen_perf_config
* perf
;
1029 int cmd_parser_version
;
1031 bool has_exec_async
;
1032 bool has_exec_capture
;
1033 bool has_exec_fence
;
1035 bool has_syncobj_wait
;
1036 bool has_context_priority
;
1037 bool has_context_isolation
;
1038 bool has_mem_available
;
1042 bool always_use_bindless
;
1044 /** True if we can access buffers using A64 messages */
1045 bool has_a64_buffer_access
;
1046 /** True if we can use bindless access for images */
1047 bool has_bindless_images
;
1048 /** True if we can use bindless access for samplers */
1049 bool has_bindless_samplers
;
1051 /** True if this device has implicit AUX
1053 * If true, CCS is handled as an implicit attachment to the BO rather than
1054 * as an explicitly bound surface.
1056 bool has_implicit_ccs
;
1058 bool always_flush_cache
;
1060 struct anv_device_extension_table supported_extensions
;
1063 uint32_t subslice_total
;
1066 uint32_t type_count
;
1067 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
1068 uint32_t heap_count
;
1069 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
1072 uint8_t driver_build_sha1
[20];
1073 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
1074 uint8_t driver_uuid
[VK_UUID_SIZE
];
1075 uint8_t device_uuid
[VK_UUID_SIZE
];
1077 struct disk_cache
* disk_cache
;
1079 struct wsi_device wsi_device
;
1084 struct anv_app_info
{
1085 const char* app_name
;
1086 uint32_t app_version
;
1087 const char* engine_name
;
1088 uint32_t engine_version
;
1089 uint32_t api_version
;
1092 struct anv_instance
{
1093 VK_LOADER_DATA _loader_data
;
1095 VkAllocationCallbacks alloc
;
1097 struct anv_app_info app_info
;
1099 struct anv_instance_extension_table enabled_extensions
;
1100 struct anv_instance_dispatch_table dispatch
;
1101 struct anv_physical_device_dispatch_table physical_device_dispatch
;
1102 struct anv_device_dispatch_table device_dispatch
;
1104 bool physical_devices_enumerated
;
1105 struct list_head physical_devices
;
1107 bool pipeline_cache_enabled
;
1109 struct vk_debug_report_instance debug_report_callbacks
;
1111 struct driOptionCache dri_options
;
1112 struct driOptionCache available_dri_options
;
1115 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
1116 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
1118 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
1119 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
1122 struct anv_queue_submit
{
1123 struct anv_cmd_buffer
* cmd_buffer
;
1125 uint32_t fence_count
;
1126 uint32_t fence_array_length
;
1127 struct drm_i915_gem_exec_fence
* fences
;
1129 uint32_t temporary_semaphore_count
;
1130 uint32_t temporary_semaphore_array_length
;
1131 struct anv_semaphore_impl
* temporary_semaphores
;
1133 /* Semaphores to be signaled with a SYNC_FD. */
1134 struct anv_semaphore
** sync_fd_semaphores
;
1135 uint32_t sync_fd_semaphore_count
;
1136 uint32_t sync_fd_semaphore_array_length
;
1138 /* Allocated only with non shareable timelines. */
1139 struct anv_timeline
** wait_timelines
;
1140 uint32_t wait_timeline_count
;
1141 uint32_t wait_timeline_array_length
;
1142 uint64_t * wait_timeline_values
;
1144 struct anv_timeline
** signal_timelines
;
1145 uint32_t signal_timeline_count
;
1146 uint32_t signal_timeline_array_length
;
1147 uint64_t * signal_timeline_values
;
1150 bool need_out_fence
;
1153 uint32_t fence_bo_count
;
1154 uint32_t fence_bo_array_length
;
1155 /* An array of struct anv_bo pointers with lower bit used as a flag to
1156 * signal we will wait on that BO (see anv_(un)pack_ptr).
1158 uintptr_t * fence_bos
;
1160 const VkAllocationCallbacks
* alloc
;
1161 VkSystemAllocationScope alloc_scope
;
1163 struct anv_bo
* simple_bo
;
1164 uint32_t simple_bo_size
;
1166 struct list_head link
;
1170 VK_LOADER_DATA _loader_data
;
1172 struct anv_device
* device
;
1175 * A list of struct anv_queue_submit to be submitted to i915.
1177 struct list_head queued_submits
;
1179 VkDeviceQueueCreateFlags flags
;
1182 struct anv_pipeline_cache
{
1183 struct anv_device
* device
;
1184 pthread_mutex_t mutex
;
1186 struct hash_table
* nir_cache
;
1188 struct hash_table
* cache
;
1191 struct nir_xfb_info
;
1192 struct anv_pipeline_bind_map
;
1194 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1195 struct anv_device
*device
,
1196 bool cache_enabled
);
1197 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1199 struct anv_shader_bin
*
1200 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1201 const void *key
, uint32_t key_size
);
1202 struct anv_shader_bin
*
1203 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1204 const void *key_data
, uint32_t key_size
,
1205 const void *kernel_data
, uint32_t kernel_size
,
1206 const void *constant_data
,
1207 uint32_t constant_data_size
,
1208 const struct brw_stage_prog_data
*prog_data
,
1209 uint32_t prog_data_size
,
1210 const struct brw_compile_stats
*stats
,
1212 const struct nir_xfb_info
*xfb_info
,
1213 const struct anv_pipeline_bind_map
*bind_map
);
1215 struct anv_shader_bin
*
1216 anv_device_search_for_kernel(struct anv_device
*device
,
1217 struct anv_pipeline_cache
*cache
,
1218 const void *key_data
, uint32_t key_size
,
1219 bool *user_cache_bit
);
1221 struct anv_shader_bin
*
1222 anv_device_upload_kernel(struct anv_device
*device
,
1223 struct anv_pipeline_cache
*cache
,
1224 const void *key_data
, uint32_t key_size
,
1225 const void *kernel_data
, uint32_t kernel_size
,
1226 const void *constant_data
,
1227 uint32_t constant_data_size
,
1228 const struct brw_stage_prog_data
*prog_data
,
1229 uint32_t prog_data_size
,
1230 const struct brw_compile_stats
*stats
,
1232 const struct nir_xfb_info
*xfb_info
,
1233 const struct anv_pipeline_bind_map
*bind_map
);
1236 struct nir_shader_compiler_options
;
1239 anv_device_search_for_nir(struct anv_device
*device
,
1240 struct anv_pipeline_cache
*cache
,
1241 const struct nir_shader_compiler_options
*nir_options
,
1242 unsigned char sha1_key
[20],
1246 anv_device_upload_nir(struct anv_device
*device
,
1247 struct anv_pipeline_cache
*cache
,
1248 const struct nir_shader
*nir
,
1249 unsigned char sha1_key
[20]);
1252 VK_LOADER_DATA _loader_data
;
1254 VkAllocationCallbacks alloc
;
1256 struct anv_physical_device
* physical
;
1258 struct gen_device_info info
;
1259 struct isl_device isl_dev
;
1262 bool can_chain_batches
;
1263 bool robust_buffer_access
;
1264 struct anv_device_extension_table enabled_extensions
;
1265 struct anv_device_dispatch_table dispatch
;
1267 pthread_mutex_t vma_mutex
;
1268 struct util_vma_heap vma_lo
;
1269 struct util_vma_heap vma_cva
;
1270 struct util_vma_heap vma_hi
;
1272 /** List of all anv_device_memory objects */
1273 struct list_head memory_objects
;
1275 struct anv_bo_pool batch_bo_pool
;
1277 struct anv_bo_cache bo_cache
;
1279 struct anv_state_pool dynamic_state_pool
;
1280 struct anv_state_pool instruction_state_pool
;
1281 struct anv_state_pool binding_table_pool
;
1282 struct anv_state_pool surface_state_pool
;
1284 struct anv_bo
* workaround_bo
;
1285 struct anv_bo
* trivial_batch_bo
;
1286 struct anv_bo
* hiz_clear_bo
;
1288 struct anv_pipeline_cache default_pipeline_cache
;
1289 struct blorp_context blorp
;
1291 struct anv_state border_colors
;
1293 struct anv_state slice_hash
;
1295 struct anv_queue queue
;
1297 struct anv_scratch_pool scratch_pool
;
1299 pthread_mutex_t mutex
;
1300 pthread_cond_t queue_submit
;
1303 struct gen_batch_decode_ctx decoder_ctx
;
1305 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1306 * the cmd_buffer's list.
1308 struct anv_cmd_buffer
*cmd_buffer_being_decoded
;
1310 int perf_fd
; /* -1 if no opened */
1311 uint64_t perf_metric
; /* 0 if unset */
1313 struct gen_aux_map_context
*aux_map_ctx
;
1316 static inline struct anv_instance
*
1317 anv_device_instance_or_null(const struct anv_device
*device
)
1319 return device
? device
->physical
->instance
: NULL
;
1322 static inline struct anv_state_pool
*
1323 anv_binding_table_pool(struct anv_device
*device
)
1325 if (device
->physical
->use_softpin
)
1326 return &device
->binding_table_pool
;
1328 return &device
->surface_state_pool
;
1331 static inline struct anv_state
1332 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1333 if (device
->physical
->use_softpin
)
1334 return anv_state_pool_alloc(&device
->binding_table_pool
,
1335 device
->binding_table_pool
.block_size
, 0);
1337 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1341 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1342 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1345 static inline uint32_t
1346 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1348 if (bo
->is_external
)
1349 return device
->isl_dev
.mocs
.external
;
1351 return device
->isl_dev
.mocs
.internal
;
1354 void anv_device_init_blorp(struct anv_device
*device
);
1355 void anv_device_finish_blorp(struct anv_device
*device
);
1357 void _anv_device_set_all_queue_lost(struct anv_device
*device
);
1358 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1359 const char *file
, int line
,
1360 const char *msg
, ...)
1361 anv_printflike(4, 5);
1362 VkResult
_anv_queue_set_lost(struct anv_queue
*queue
,
1363 const char *file
, int line
,
1364 const char *msg
, ...)
1365 anv_printflike(4, 5);
1366 #define anv_device_set_lost(dev, ...) \
1367 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1368 #define anv_queue_set_lost(queue, ...) \
1369 _anv_queue_set_lost(queue, __FILE__, __LINE__, __VA_ARGS__)
1372 anv_device_is_lost(struct anv_device
*device
)
1374 return unlikely(p_atomic_read(&device
->_lost
));
1377 VkResult
anv_device_query_status(struct anv_device
*device
);
1380 enum anv_bo_alloc_flags
{
1381 /** Specifies that the BO must have a 32-bit address
1383 * This is the opposite of EXEC_OBJECT_SUPPORTS_48B_ADDRESS.
1385 ANV_BO_ALLOC_32BIT_ADDRESS
= (1 << 0),
1387 /** Specifies that the BO may be shared externally */
1388 ANV_BO_ALLOC_EXTERNAL
= (1 << 1),
1390 /** Specifies that the BO should be mapped */
1391 ANV_BO_ALLOC_MAPPED
= (1 << 2),
1393 /** Specifies that the BO should be snooped so we get coherency */
1394 ANV_BO_ALLOC_SNOOPED
= (1 << 3),
1396 /** Specifies that the BO should be captured in error states */
1397 ANV_BO_ALLOC_CAPTURE
= (1 << 4),
1399 /** Specifies that the BO will have an address assigned by the caller
1401 * Such BOs do not exist in any VMA heap.
1403 ANV_BO_ALLOC_FIXED_ADDRESS
= (1 << 5),
1405 /** Enables implicit synchronization on the BO
1407 * This is the opposite of EXEC_OBJECT_ASYNC.
1409 ANV_BO_ALLOC_IMPLICIT_SYNC
= (1 << 6),
1411 /** Enables implicit synchronization on the BO
1413 * This is equivalent to EXEC_OBJECT_WRITE.
1415 ANV_BO_ALLOC_IMPLICIT_WRITE
= (1 << 7),
1417 /** Has an address which is visible to the client */
1418 ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS
= (1 << 8),
1420 /** This buffer has implicit CCS data attached to it */
1421 ANV_BO_ALLOC_IMPLICIT_CCS
= (1 << 9),
1424 VkResult
anv_device_alloc_bo(struct anv_device
*device
, uint64_t size
,
1425 enum anv_bo_alloc_flags alloc_flags
,
1426 uint64_t explicit_address
,
1427 struct anv_bo
**bo
);
1428 VkResult
anv_device_import_bo_from_host_ptr(struct anv_device
*device
,
1429 void *host_ptr
, uint32_t size
,
1430 enum anv_bo_alloc_flags alloc_flags
,
1431 uint64_t client_address
,
1432 struct anv_bo
**bo_out
);
1433 VkResult
anv_device_import_bo(struct anv_device
*device
, int fd
,
1434 enum anv_bo_alloc_flags alloc_flags
,
1435 uint64_t client_address
,
1436 struct anv_bo
**bo
);
1437 VkResult
anv_device_export_bo(struct anv_device
*device
,
1438 struct anv_bo
*bo
, int *fd_out
);
1439 void anv_device_release_bo(struct anv_device
*device
,
1442 static inline struct anv_bo
*
1443 anv_device_lookup_bo(struct anv_device
*device
, uint32_t gem_handle
)
1445 return util_sparse_array_get(&device
->bo_cache
.bo_map
, gem_handle
);
1448 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1449 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1452 VkResult
anv_queue_init(struct anv_device
*device
, struct anv_queue
*queue
);
1453 void anv_queue_finish(struct anv_queue
*queue
);
1455 VkResult
anv_queue_execbuf_locked(struct anv_queue
*queue
, struct anv_queue_submit
*submit
);
1456 VkResult
anv_queue_submit_simple_batch(struct anv_queue
*queue
,
1457 struct anv_batch
*batch
);
1459 uint64_t anv_gettime_ns(void);
1460 uint64_t anv_get_absolute_timeout(uint64_t timeout
);
1462 void* anv_gem_mmap(struct anv_device
*device
,
1463 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1464 void anv_gem_munmap(void *p
, uint64_t size
);
1465 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1466 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1467 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1468 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1469 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1470 int anv_gem_execbuffer(struct anv_device
*device
,
1471 struct drm_i915_gem_execbuffer2
*execbuf
);
1472 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1473 uint32_t stride
, uint32_t tiling
);
1474 int anv_gem_create_context(struct anv_device
*device
);
1475 bool anv_gem_has_context_priority(int fd
);
1476 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1477 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1479 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1481 int anv_gem_get_param(int fd
, uint32_t param
);
1482 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1483 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1484 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1485 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1486 uint32_t *active
, uint32_t *pending
);
1487 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1488 int anv_gem_reg_read(struct anv_device
*device
,
1489 uint32_t offset
, uint64_t *result
);
1490 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1491 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1492 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1493 uint32_t read_domains
, uint32_t write_domain
);
1494 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1495 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1496 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1497 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1498 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1499 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1501 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1502 uint32_t handle
, int fd
);
1503 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1504 bool anv_gem_supports_syncobj_wait(int fd
);
1505 int anv_gem_syncobj_wait(struct anv_device
*device
,
1506 uint32_t *handles
, uint32_t num_handles
,
1507 int64_t abs_timeout_ns
, bool wait_all
);
1509 uint64_t anv_vma_alloc(struct anv_device
*device
,
1510 uint64_t size
, uint64_t align
,
1511 enum anv_bo_alloc_flags alloc_flags
,
1512 uint64_t client_address
);
1513 void anv_vma_free(struct anv_device
*device
,
1514 uint64_t address
, uint64_t size
);
1516 struct anv_reloc_list
{
1517 uint32_t num_relocs
;
1518 uint32_t array_length
;
1519 struct drm_i915_gem_relocation_entry
* relocs
;
1520 struct anv_bo
** reloc_bos
;
1525 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1526 const VkAllocationCallbacks
*alloc
);
1527 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1528 const VkAllocationCallbacks
*alloc
);
1530 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1531 const VkAllocationCallbacks
*alloc
,
1532 uint32_t offset
, struct anv_bo
*target_bo
,
1533 uint32_t delta
, uint64_t *address_u64_out
);
1535 struct anv_batch_bo
{
1536 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1537 struct list_head link
;
1541 /* Bytes actually consumed in this batch BO */
1544 struct anv_reloc_list relocs
;
1548 const VkAllocationCallbacks
* alloc
;
1554 struct anv_reloc_list
* relocs
;
1556 /* This callback is called (with the associated user data) in the event
1557 * that the batch runs out of space.
1559 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1563 * Current error status of the command buffer. Used to track inconsistent
1564 * or incomplete command buffer states that are the consequence of run-time
1565 * errors such as out of memory scenarios. We want to track this in the
1566 * batch because the command buffer object is not visible to some parts
1572 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1573 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1574 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1575 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1577 static inline VkResult
1578 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1580 assert(error
!= VK_SUCCESS
);
1581 if (batch
->status
== VK_SUCCESS
)
1582 batch
->status
= error
;
1583 return batch
->status
;
1587 anv_batch_has_error(struct anv_batch
*batch
)
1589 return batch
->status
!= VK_SUCCESS
;
1592 struct anv_address
{
1597 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1600 anv_address_is_null(struct anv_address addr
)
1602 return addr
.bo
== NULL
&& addr
.offset
== 0;
1605 static inline uint64_t
1606 anv_address_physical(struct anv_address addr
)
1608 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1609 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1611 return gen_canonical_address(addr
.offset
);
1614 static inline struct anv_address
1615 anv_address_add(struct anv_address addr
, uint64_t offset
)
1617 addr
.offset
+= offset
;
1622 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1624 unsigned reloc_size
= 0;
1625 if (device
->info
.gen
>= 8) {
1626 reloc_size
= sizeof(uint64_t);
1627 *(uint64_t *)p
= gen_canonical_address(v
);
1629 reloc_size
= sizeof(uint32_t);
1633 if (flush
&& !device
->info
.has_llc
)
1634 gen_flush_range(p
, reloc_size
);
1637 static inline uint64_t
1638 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1639 const struct anv_address address
, uint32_t delta
)
1641 if (address
.bo
== NULL
) {
1642 return address
.offset
+ delta
;
1644 assert(batch
->start
<= location
&& location
< batch
->end
);
1646 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1650 #define __gen_address_type struct anv_address
1651 #define __gen_user_data struct anv_batch
1652 #define __gen_combine_address _anv_combine_address
1654 /* Wrapper macros needed to work around preprocessor argument issues. In
1655 * particular, arguments don't get pre-evaluated if they are concatenated.
1656 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1657 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1658 * We can work around this easily enough with these helpers.
1660 #define __anv_cmd_length(cmd) cmd ## _length
1661 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1662 #define __anv_cmd_header(cmd) cmd ## _header
1663 #define __anv_cmd_pack(cmd) cmd ## _pack
1664 #define __anv_reg_num(reg) reg ## _num
1666 #define anv_pack_struct(dst, struc, ...) do { \
1667 struct struc __template = { \
1670 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1671 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1674 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1675 void *__dst = anv_batch_emit_dwords(batch, n); \
1677 struct cmd __template = { \
1678 __anv_cmd_header(cmd), \
1679 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1682 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1687 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1691 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1692 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1695 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1696 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1697 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1700 #define anv_batch_emit(batch, cmd, name) \
1701 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1702 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1703 __builtin_expect(_dst != NULL, 1); \
1704 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1705 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1709 struct anv_device_memory
{
1710 struct list_head link
;
1713 struct anv_memory_type
* type
;
1714 VkDeviceSize map_size
;
1717 /* If set, we are holding reference to AHardwareBuffer
1718 * which we must release when memory is freed.
1720 struct AHardwareBuffer
* ahw
;
1722 /* If set, this memory comes from a host pointer. */
1727 * Header for Vertex URB Entry (VUE)
1729 struct anv_vue_header
{
1731 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1732 uint32_t ViewportIndex
;
1736 /** Struct representing a sampled image descriptor
1738 * This descriptor layout is used for sampled images, bare sampler, and
1739 * combined image/sampler descriptors.
1741 struct anv_sampled_image_descriptor
{
1742 /** Bindless image handle
1744 * This is expected to already be shifted such that the 20-bit
1745 * SURFACE_STATE table index is in the top 20 bits.
1749 /** Bindless sampler handle
1751 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1752 * to the dynamic state base address.
1757 struct anv_texture_swizzle_descriptor
{
1760 * See also nir_intrinsic_channel_select_intel
1764 /** Unused padding to ensure the struct is a multiple of 64 bits */
1768 /** Struct representing a storage image descriptor */
1769 struct anv_storage_image_descriptor
{
1770 /** Bindless image handles
1772 * These are expected to already be shifted such that the 20-bit
1773 * SURFACE_STATE table index is in the top 20 bits.
1775 uint32_t read_write
;
1776 uint32_t write_only
;
1779 /** Struct representing a address/range descriptor
1781 * The fields of this struct correspond directly to the data layout of
1782 * nir_address_format_64bit_bounded_global addresses. The last field is the
1783 * offset in the NIR address so it must be zero so that when you load the
1784 * descriptor you get a pointer to the start of the range.
1786 struct anv_address_range_descriptor
{
1792 enum anv_descriptor_data
{
1793 /** The descriptor contains a BTI reference to a surface state */
1794 ANV_DESCRIPTOR_SURFACE_STATE
= (1 << 0),
1795 /** The descriptor contains a BTI reference to a sampler state */
1796 ANV_DESCRIPTOR_SAMPLER_STATE
= (1 << 1),
1797 /** The descriptor contains an actual buffer view */
1798 ANV_DESCRIPTOR_BUFFER_VIEW
= (1 << 2),
1799 /** The descriptor contains auxiliary image layout data */
1800 ANV_DESCRIPTOR_IMAGE_PARAM
= (1 << 3),
1801 /** The descriptor contains auxiliary image layout data */
1802 ANV_DESCRIPTOR_INLINE_UNIFORM
= (1 << 4),
1803 /** anv_address_range_descriptor with a buffer address and range */
1804 ANV_DESCRIPTOR_ADDRESS_RANGE
= (1 << 5),
1805 /** Bindless surface handle */
1806 ANV_DESCRIPTOR_SAMPLED_IMAGE
= (1 << 6),
1807 /** Storage image handles */
1808 ANV_DESCRIPTOR_STORAGE_IMAGE
= (1 << 7),
1809 /** Storage image handles */
1810 ANV_DESCRIPTOR_TEXTURE_SWIZZLE
= (1 << 8),
1813 struct anv_descriptor_set_binding_layout
{
1815 /* The type of the descriptors in this binding */
1816 VkDescriptorType type
;
1819 /* Flags provided when this binding was created */
1820 VkDescriptorBindingFlagsEXT flags
;
1822 /* Bitfield representing the type of data this descriptor contains */
1823 enum anv_descriptor_data data
;
1825 /* Maximum number of YCbCr texture/sampler planes */
1826 uint8_t max_plane_count
;
1828 /* Number of array elements in this binding (or size in bytes for inline
1831 uint16_t array_size
;
1833 /* Index into the flattend descriptor set */
1834 uint16_t descriptor_index
;
1836 /* Index into the dynamic state array for a dynamic buffer */
1837 int16_t dynamic_offset_index
;
1839 /* Index into the descriptor set buffer views */
1840 int16_t buffer_view_index
;
1842 /* Offset into the descriptor buffer where this descriptor lives */
1843 uint32_t descriptor_offset
;
1845 /* Immutable samplers (or NULL if no immutable samplers) */
1846 struct anv_sampler
**immutable_samplers
;
1849 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout
*layout
);
1851 unsigned anv_descriptor_type_size(const struct anv_physical_device
*pdevice
,
1852 VkDescriptorType type
);
1854 bool anv_descriptor_supports_bindless(const struct anv_physical_device
*pdevice
,
1855 const struct anv_descriptor_set_binding_layout
*binding
,
1858 bool anv_descriptor_requires_bindless(const struct anv_physical_device
*pdevice
,
1859 const struct anv_descriptor_set_binding_layout
*binding
,
1862 struct anv_descriptor_set_layout
{
1863 /* Descriptor set layouts can be destroyed at almost any time */
1866 /* Number of bindings in this descriptor set */
1867 uint16_t binding_count
;
1869 /* Total size of the descriptor set with room for all array entries */
1872 /* Shader stages affected by this descriptor set */
1873 uint16_t shader_stages
;
1875 /* Number of buffer views in this descriptor set */
1876 uint16_t buffer_view_count
;
1878 /* Number of dynamic offsets used by this descriptor set */
1879 uint16_t dynamic_offset_count
;
1881 /* For each shader stage, which offsets apply to that stage */
1882 uint16_t stage_dynamic_offsets
[MESA_SHADER_STAGES
];
1884 /* Size of the descriptor buffer for this descriptor set */
1885 uint32_t descriptor_buffer_size
;
1887 /* Bindings in this descriptor set */
1888 struct anv_descriptor_set_binding_layout binding
[0];
1892 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1894 assert(layout
&& layout
->ref_cnt
>= 1);
1895 p_atomic_inc(&layout
->ref_cnt
);
1899 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1900 struct anv_descriptor_set_layout
*layout
)
1902 assert(layout
&& layout
->ref_cnt
>= 1);
1903 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1904 vk_free(&device
->alloc
, layout
);
1907 struct anv_descriptor
{
1908 VkDescriptorType type
;
1912 VkImageLayout layout
;
1913 struct anv_image_view
*image_view
;
1914 struct anv_sampler
*sampler
;
1918 struct anv_buffer
*buffer
;
1923 struct anv_buffer_view
*buffer_view
;
1927 struct anv_descriptor_set
{
1928 struct anv_descriptor_pool
*pool
;
1929 struct anv_descriptor_set_layout
*layout
;
1932 /* State relative to anv_descriptor_pool::bo */
1933 struct anv_state desc_mem
;
1934 /* Surface state for the descriptor buffer */
1935 struct anv_state desc_surface_state
;
1937 uint32_t buffer_view_count
;
1938 struct anv_buffer_view
*buffer_views
;
1940 /* Link to descriptor pool's desc_sets list . */
1941 struct list_head pool_link
;
1943 struct anv_descriptor descriptors
[0];
1946 struct anv_buffer_view
{
1947 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1948 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1950 struct anv_address address
;
1952 struct anv_state surface_state
;
1953 struct anv_state storage_surface_state
;
1954 struct anv_state writeonly_storage_surface_state
;
1956 struct brw_image_param storage_image_param
;
1959 struct anv_push_descriptor_set
{
1960 struct anv_descriptor_set set
;
1962 /* Put this field right behind anv_descriptor_set so it fills up the
1963 * descriptors[0] field. */
1964 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1966 /** True if the descriptor set buffer has been referenced by a draw or
1969 bool set_used_on_gpu
;
1971 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1974 struct anv_descriptor_pool
{
1980 struct util_vma_heap bo_heap
;
1982 struct anv_state_stream surface_state_stream
;
1983 void *surface_state_free_list
;
1985 struct list_head desc_sets
;
1990 enum anv_descriptor_template_entry_type
{
1991 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1992 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1993 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1996 struct anv_descriptor_template_entry
{
1997 /* The type of descriptor in this entry */
1998 VkDescriptorType type
;
2000 /* Binding in the descriptor set */
2003 /* Offset at which to write into the descriptor set binding */
2004 uint32_t array_element
;
2006 /* Number of elements to write into the descriptor set binding */
2007 uint32_t array_count
;
2009 /* Offset into the user provided data */
2012 /* Stride between elements into the user provided data */
2016 struct anv_descriptor_update_template
{
2017 VkPipelineBindPoint bind_point
;
2019 /* The descriptor set this template corresponds to. This value is only
2020 * valid if the template was created with the templateType
2021 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
2025 /* Number of entries in this template */
2026 uint32_t entry_count
;
2028 /* Entries of the template */
2029 struct anv_descriptor_template_entry entries
[0];
2033 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
2036 anv_descriptor_set_write_image_view(struct anv_device
*device
,
2037 struct anv_descriptor_set
*set
,
2038 const VkDescriptorImageInfo
* const info
,
2039 VkDescriptorType type
,
2044 anv_descriptor_set_write_buffer_view(struct anv_device
*device
,
2045 struct anv_descriptor_set
*set
,
2046 VkDescriptorType type
,
2047 struct anv_buffer_view
*buffer_view
,
2052 anv_descriptor_set_write_buffer(struct anv_device
*device
,
2053 struct anv_descriptor_set
*set
,
2054 struct anv_state_stream
*alloc_stream
,
2055 VkDescriptorType type
,
2056 struct anv_buffer
*buffer
,
2059 VkDeviceSize offset
,
2060 VkDeviceSize range
);
2062 anv_descriptor_set_write_inline_uniform_data(struct anv_device
*device
,
2063 struct anv_descriptor_set
*set
,
2070 anv_descriptor_set_write_template(struct anv_device
*device
,
2071 struct anv_descriptor_set
*set
,
2072 struct anv_state_stream
*alloc_stream
,
2073 const struct anv_descriptor_update_template
*template,
2077 anv_descriptor_set_create(struct anv_device
*device
,
2078 struct anv_descriptor_pool
*pool
,
2079 struct anv_descriptor_set_layout
*layout
,
2080 struct anv_descriptor_set
**out_set
);
2083 anv_descriptor_set_destroy(struct anv_device
*device
,
2084 struct anv_descriptor_pool
*pool
,
2085 struct anv_descriptor_set
*set
);
2087 #define ANV_DESCRIPTOR_SET_NULL (UINT8_MAX - 5)
2088 #define ANV_DESCRIPTOR_SET_PUSH_CONSTANTS (UINT8_MAX - 4)
2089 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
2090 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
2091 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
2092 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
2094 struct anv_pipeline_binding
{
2095 /** Index in the descriptor set
2097 * This is a flattened index; the descriptor set layout is already taken
2102 /** The descriptor set this surface corresponds to.
2104 * The special ANV_DESCRIPTOR_SET_* values above indicates that this
2105 * binding is not a normal descriptor set but something else.
2110 /** Plane in the binding index for images */
2113 /** Input attachment index (relative to the subpass) */
2114 uint8_t input_attachment_index
;
2116 /** Dynamic offset index (for dynamic UBOs and SSBOs) */
2117 uint8_t dynamic_offset_index
;
2120 /** For a storage image, whether it is write-only */
2123 /** Pad to 64 bits so that there are no holes and we can safely memcmp
2124 * assuming POD zero-initialization.
2129 struct anv_push_range
{
2130 /** Index in the descriptor set */
2133 /** Descriptor set index */
2136 /** Dynamic offset index (for dynamic UBOs) */
2137 uint8_t dynamic_offset_index
;
2139 /** Start offset in units of 32B */
2142 /** Range in units of 32B */
2146 struct anv_pipeline_layout
{
2148 struct anv_descriptor_set_layout
*layout
;
2149 uint32_t dynamic_offset_start
;
2154 unsigned char sha1
[20];
2158 struct anv_device
* device
;
2161 VkBufferUsageFlags usage
;
2163 /* Set when bound */
2164 struct anv_address address
;
2167 static inline uint64_t
2168 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
2170 assert(offset
<= buffer
->size
);
2171 if (range
== VK_WHOLE_SIZE
) {
2172 return buffer
->size
- offset
;
2174 assert(range
+ offset
>= range
);
2175 assert(range
+ offset
<= buffer
->size
);
2180 enum anv_cmd_dirty_bits
{
2181 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
2182 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
2183 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
2184 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
2185 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
2186 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
2187 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
2188 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
2189 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
2190 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
2191 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
2192 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
2193 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
2194 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
2196 typedef uint32_t anv_cmd_dirty_mask_t
;
2198 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
2199 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
2200 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
2201 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
2202 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
2203 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
2204 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
2205 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
2206 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
2207 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
2208 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2210 static inline enum anv_cmd_dirty_bits
2211 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state
)
2214 case VK_DYNAMIC_STATE_VIEWPORT
:
2215 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2216 case VK_DYNAMIC_STATE_SCISSOR
:
2217 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2218 case VK_DYNAMIC_STATE_LINE_WIDTH
:
2219 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2220 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
2221 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2222 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
2223 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2224 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
2225 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2226 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
2227 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2228 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
2229 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2230 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2231 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2232 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
2233 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
2235 assert(!"Unsupported dynamic state");
2241 enum anv_pipe_bits
{
2242 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
2243 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
2244 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
2245 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
2246 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
2247 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
2248 ANV_PIPE_TILE_CACHE_FLUSH_BIT
= (1 << 6),
2249 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
2250 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
2251 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
2252 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
2253 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
2255 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2256 * a flush has happened but not a CS stall. The next time we do any sort
2257 * of invalidation we need to insert a CS stall at that time. Otherwise,
2258 * we would have to CS stall on every flush which could be bad.
2260 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
2262 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2263 * target operations related to transfer commands with VkBuffer as
2264 * destination are ongoing. Some operations like copies on the command
2265 * streamer might need to be aware of this to trigger the appropriate stall
2266 * before they can proceed with the copy.
2268 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 22),
2270 /* This bit does not exist directly in PIPE_CONTROL. It means that Gen12
2271 * AUX-TT data has changed and we need to invalidate AUX-TT data. This is
2272 * done by writing the AUX-TT register.
2274 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
= (1 << 23),
2276 /* This bit does not exist directly in PIPE_CONTROL. It means that a
2277 * PIPE_CONTROL with a post-sync operation will follow. This is used to
2278 * implement a workaround for Gen9.
2280 ANV_PIPE_POST_SYNC_BIT
= (1 << 24),
2283 #define ANV_PIPE_FLUSH_BITS ( \
2284 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2285 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2286 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
2287 ANV_PIPE_TILE_CACHE_FLUSH_BIT)
2289 #define ANV_PIPE_STALL_BITS ( \
2290 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2291 ANV_PIPE_DEPTH_STALL_BIT | \
2292 ANV_PIPE_CS_STALL_BIT)
2294 #define ANV_PIPE_INVALIDATE_BITS ( \
2295 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2296 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2297 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2298 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2299 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2300 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT | \
2301 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT)
2303 static inline enum anv_pipe_bits
2304 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
2306 enum anv_pipe_bits pipe_bits
= 0;
2309 for_each_bit(b
, flags
) {
2310 switch ((VkAccessFlagBits
)(1 << b
)) {
2311 case VK_ACCESS_SHADER_WRITE_BIT
:
2312 /* We're transitioning a buffer that was previously used as write
2313 * destination through the data port. To make its content available
2314 * to future operations, flush the data cache.
2316 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2318 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2319 /* We're transitioning a buffer that was previously used as render
2320 * target. To make its content available to future operations, flush
2321 * the render target cache.
2323 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2325 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2326 /* We're transitioning a buffer that was previously used as depth
2327 * buffer. To make its content available to future operations, flush
2330 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2332 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2333 /* We're transitioning a buffer that was previously used as a
2334 * transfer write destination. Generic write operations include color
2335 * & depth operations as well as buffer operations like :
2336 * - vkCmdClearColorImage()
2337 * - vkCmdClearDepthStencilImage()
2338 * - vkCmdBlitImage()
2339 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2341 * Most of these operations are implemented using Blorp which writes
2342 * through the render target, so flush that cache to make it visible
2343 * to future operations. And for depth related operations we also
2344 * need to flush the depth cache.
2346 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2347 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2349 case VK_ACCESS_MEMORY_WRITE_BIT
:
2350 /* We're transitioning a buffer for generic write operations. Flush
2353 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2356 break; /* Nothing to do */
2363 static inline enum anv_pipe_bits
2364 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
2366 enum anv_pipe_bits pipe_bits
= 0;
2369 for_each_bit(b
, flags
) {
2370 switch ((VkAccessFlagBits
)(1 << b
)) {
2371 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2372 /* Indirect draw commands take a buffer as input that we're going to
2373 * read from the command streamer to load some of the HW registers
2374 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2375 * command streamer stall so that all the cache flushes have
2376 * completed before the command streamer loads from memory.
2378 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2379 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2380 * through a vertex buffer, so invalidate that cache.
2382 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2383 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2384 * UBO from the buffer, so we need to invalidate constant cache.
2386 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2388 case VK_ACCESS_INDEX_READ_BIT
:
2389 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2390 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2391 * commands, so we invalidate the VF cache to make sure there is no
2392 * stale data when we start rendering.
2394 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2396 case VK_ACCESS_UNIFORM_READ_BIT
:
2397 /* We transitioning a buffer to be used as uniform data. Because
2398 * uniform is accessed through the data port & sampler, we need to
2399 * invalidate the texture cache (sampler) & constant cache (data
2400 * port) to avoid stale data.
2402 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2403 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2405 case VK_ACCESS_SHADER_READ_BIT
:
2406 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2407 case VK_ACCESS_TRANSFER_READ_BIT
:
2408 /* Transitioning a buffer to be read through the sampler, so
2409 * invalidate the texture cache, we don't want any stale data.
2411 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2413 case VK_ACCESS_MEMORY_READ_BIT
:
2414 /* Transitioning a buffer for generic read, invalidate all the
2417 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
2419 case VK_ACCESS_MEMORY_WRITE_BIT
:
2420 /* Generic write, make sure all previously written things land in
2423 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2425 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
2426 /* Transitioning a buffer for conditional rendering. We'll load the
2427 * content of this buffer into HW registers using the command
2428 * streamer, so we need to stall the command streamer to make sure
2429 * any in-flight flush operations have completed.
2431 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2434 break; /* Nothing to do */
2441 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2442 VK_IMAGE_ASPECT_COLOR_BIT | \
2443 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2444 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2445 VK_IMAGE_ASPECT_PLANE_2_BIT)
2446 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2447 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2448 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2449 VK_IMAGE_ASPECT_PLANE_2_BIT)
2451 struct anv_vertex_binding
{
2452 struct anv_buffer
* buffer
;
2453 VkDeviceSize offset
;
2456 struct anv_xfb_binding
{
2457 struct anv_buffer
* buffer
;
2458 VkDeviceSize offset
;
2462 struct anv_push_constants
{
2463 /** Push constant data provided by the client through vkPushConstants */
2464 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2466 /** Dynamic offsets for dynamic UBOs and SSBOs */
2467 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2470 /** Base workgroup ID
2472 * Used for vkCmdDispatchBase.
2474 uint32_t base_work_group_id
[3];
2478 * This is never set by software but is implicitly filled out when
2479 * uploading the push constants for compute shaders.
2481 uint32_t subgroup_id
;
2483 /** Pad out to a multiple of 32 bytes */
2488 struct anv_dynamic_state
{
2491 VkViewport viewports
[MAX_VIEWPORTS
];
2496 VkRect2D scissors
[MAX_SCISSORS
];
2507 float blend_constants
[4];
2517 } stencil_compare_mask
;
2522 } stencil_write_mask
;
2527 } stencil_reference
;
2535 extern const struct anv_dynamic_state default_dynamic_state
;
2537 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2538 const struct anv_dynamic_state
*src
,
2539 uint32_t copy_mask
);
2541 struct anv_surface_state
{
2542 struct anv_state state
;
2543 /** Address of the surface referred to by this state
2545 * This address is relative to the start of the BO.
2547 struct anv_address address
;
2548 /* Address of the aux surface, if any
2550 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2552 * With the exception of gen8, the bottom 12 bits of this address' offset
2553 * include extra aux information.
2555 struct anv_address aux_address
;
2556 /* Address of the clear color, if any
2558 * This address is relative to the start of the BO.
2560 struct anv_address clear_address
;
2564 * Attachment state when recording a renderpass instance.
2566 * The clear value is valid only if there exists a pending clear.
2568 struct anv_attachment_state
{
2569 enum isl_aux_usage aux_usage
;
2570 enum isl_aux_usage input_aux_usage
;
2571 struct anv_surface_state color
;
2572 struct anv_surface_state input
;
2574 VkImageLayout current_layout
;
2575 VkImageLayout current_stencil_layout
;
2576 VkImageAspectFlags pending_clear_aspects
;
2577 VkImageAspectFlags pending_load_aspects
;
2579 VkClearValue clear_value
;
2580 bool clear_color_is_zero_one
;
2581 bool clear_color_is_zero
;
2583 /* When multiview is active, attachments with a renderpass clear
2584 * operation have their respective layers cleared on the first
2585 * subpass that uses them, and only in that subpass. We keep track
2586 * of this using a bitfield to indicate which layers of an attachment
2587 * have not been cleared yet when multiview is active.
2589 uint32_t pending_clear_views
;
2590 struct anv_image_view
* image_view
;
2593 /** State tracking for vertex buffer flushes
2595 * On Gen8-9, the VF cache only considers the bottom 32 bits of memory
2596 * addresses. If you happen to have two vertex buffers which get placed
2597 * exactly 4 GiB apart and use them in back-to-back draw calls, you can get
2598 * collisions. In order to solve this problem, we track vertex address ranges
2599 * which are live in the cache and invalidate the cache if one ever exceeds 32
2602 struct anv_vb_cache_range
{
2603 /* Virtual address at which the live vertex buffer cache range starts for
2604 * this vertex buffer index.
2608 /* Virtual address of the byte after where vertex buffer cache range ends.
2609 * This is exclusive such that end - start is the size of the range.
2614 /** State tracking for particular pipeline bind point
2616 * This struct is the base struct for anv_cmd_graphics_state and
2617 * anv_cmd_compute_state. These are used to track state which is bound to a
2618 * particular type of pipeline. Generic state that applies per-stage such as
2619 * binding table offsets and push constants is tracked generically with a
2620 * per-stage array in anv_cmd_state.
2622 struct anv_cmd_pipeline_state
{
2623 struct anv_pipeline
*pipeline
;
2625 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2626 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2629 /** State tracking for graphics pipeline
2631 * This has anv_cmd_pipeline_state as a base struct to track things which get
2632 * bound to a graphics pipeline. Along with general pipeline bind point state
2633 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2634 * state which is graphics-specific.
2636 struct anv_cmd_graphics_state
{
2637 struct anv_cmd_pipeline_state base
;
2639 anv_cmd_dirty_mask_t dirty
;
2642 struct anv_vb_cache_range ib_bound_range
;
2643 struct anv_vb_cache_range ib_dirty_range
;
2644 struct anv_vb_cache_range vb_bound_ranges
[33];
2645 struct anv_vb_cache_range vb_dirty_ranges
[33];
2647 struct anv_dynamic_state dynamic
;
2650 struct anv_buffer
*index_buffer
;
2651 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2652 uint32_t index_offset
;
2656 /** State tracking for compute pipeline
2658 * This has anv_cmd_pipeline_state as a base struct to track things which get
2659 * bound to a compute pipeline. Along with general pipeline bind point state
2660 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2661 * state which is compute-specific.
2663 struct anv_cmd_compute_state
{
2664 struct anv_cmd_pipeline_state base
;
2666 bool pipeline_dirty
;
2668 struct anv_address num_workgroups
;
2671 /** State required while building cmd buffer */
2672 struct anv_cmd_state
{
2673 /* PIPELINE_SELECT.PipelineSelection */
2674 uint32_t current_pipeline
;
2675 const struct gen_l3_config
* current_l3_config
;
2676 uint32_t last_aux_map_state
;
2678 struct anv_cmd_graphics_state gfx
;
2679 struct anv_cmd_compute_state compute
;
2681 enum anv_pipe_bits pending_pipe_bits
;
2682 VkShaderStageFlags descriptors_dirty
;
2683 VkShaderStageFlags push_constants_dirty
;
2685 struct anv_framebuffer
* framebuffer
;
2686 struct anv_render_pass
* pass
;
2687 struct anv_subpass
* subpass
;
2688 VkRect2D render_area
;
2689 uint32_t restart_index
;
2690 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2692 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2693 VkShaderStageFlags push_constant_stages
;
2694 struct anv_push_constants push_constants
[MESA_SHADER_STAGES
];
2695 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2696 struct anv_state samplers
[MESA_SHADER_STAGES
];
2698 unsigned char sampler_sha1s
[MESA_SHADER_STAGES
][20];
2699 unsigned char surface_sha1s
[MESA_SHADER_STAGES
][20];
2700 unsigned char push_sha1s
[MESA_SHADER_STAGES
][20];
2703 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2704 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2705 * and before invoking the secondary in ExecuteCommands.
2707 bool pma_fix_enabled
;
2710 * Whether or not we know for certain that HiZ is enabled for the current
2711 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2712 * enabled or not, this will be false.
2716 bool conditional_render_enabled
;
2719 * Last rendering scale argument provided to
2720 * genX(cmd_buffer_emit_hashing_mode)().
2722 unsigned current_hash_scale
;
2725 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2726 * valid only when recording a render pass instance.
2728 struct anv_attachment_state
* attachments
;
2731 * Surface states for color render targets. These are stored in a single
2732 * flat array. For depth-stencil attachments, the surface state is simply
2735 struct anv_state render_pass_states
;
2738 * A null surface state of the right size to match the framebuffer. This
2739 * is one of the states in render_pass_states.
2741 struct anv_state null_surface_state
;
2744 struct anv_cmd_pool
{
2745 VkAllocationCallbacks alloc
;
2746 struct list_head cmd_buffers
;
2749 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2751 enum anv_cmd_buffer_exec_mode
{
2752 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2753 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2754 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2755 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2756 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2759 struct anv_cmd_buffer
{
2760 VK_LOADER_DATA _loader_data
;
2762 struct anv_device
* device
;
2764 struct anv_cmd_pool
* pool
;
2765 struct list_head pool_link
;
2767 struct anv_batch batch
;
2769 /* Fields required for the actual chain of anv_batch_bo's.
2771 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2773 struct list_head batch_bos
;
2774 enum anv_cmd_buffer_exec_mode exec_mode
;
2776 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2777 * referenced by this command buffer
2779 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2781 struct u_vector seen_bbos
;
2783 /* A vector of int32_t's for every block of binding tables.
2785 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2787 struct u_vector bt_block_states
;
2788 struct anv_state bt_next
;
2790 struct anv_reloc_list surface_relocs
;
2791 /** Last seen surface state block pool center bo offset */
2792 uint32_t last_ss_pool_center
;
2794 /* Serial for tracking buffer completion */
2797 /* Stream objects for storing temporary data */
2798 struct anv_state_stream surface_state_stream
;
2799 struct anv_state_stream dynamic_state_stream
;
2801 VkCommandBufferUsageFlags usage_flags
;
2802 VkCommandBufferLevel level
;
2804 struct anv_cmd_state state
;
2806 /* Set by SetPerformanceMarkerINTEL, written into queries by CmdBeginQuery */
2807 uint64_t intel_perf_marker
;
2810 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2811 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2812 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2813 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2814 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2815 struct anv_cmd_buffer
*secondary
);
2816 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2817 VkResult
anv_cmd_buffer_execbuf(struct anv_queue
*queue
,
2818 struct anv_cmd_buffer
*cmd_buffer
,
2819 const VkSemaphore
*in_semaphores
,
2820 const uint64_t *in_wait_values
,
2821 uint32_t num_in_semaphores
,
2822 const VkSemaphore
*out_semaphores
,
2823 const uint64_t *out_signal_values
,
2824 uint32_t num_out_semaphores
,
2827 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2829 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2830 const void *data
, uint32_t size
, uint32_t alignment
);
2831 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2832 uint32_t *a
, uint32_t *b
,
2833 uint32_t dwords
, uint32_t alignment
);
2836 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2838 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2839 uint32_t entries
, uint32_t *state_offset
);
2841 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2843 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2844 uint32_t size
, uint32_t alignment
);
2847 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2849 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2850 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2851 bool depth_clamp_enable
);
2852 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2854 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2855 struct anv_render_pass
*pass
,
2856 struct anv_framebuffer
*framebuffer
,
2857 const VkClearValue
*clear_values
);
2859 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2862 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2863 gl_shader_stage stage
);
2865 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2867 const struct anv_image_view
*
2868 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2871 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2872 uint32_t num_entries
,
2873 uint32_t *state_offset
,
2874 struct anv_state
*bt_state
);
2876 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2878 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
2880 enum anv_fence_type
{
2881 ANV_FENCE_TYPE_NONE
= 0,
2883 ANV_FENCE_TYPE_WSI_BO
,
2884 ANV_FENCE_TYPE_SYNCOBJ
,
2888 enum anv_bo_fence_state
{
2889 /** Indicates that this is a new (or newly reset fence) */
2890 ANV_BO_FENCE_STATE_RESET
,
2892 /** Indicates that this fence has been submitted to the GPU but is still
2893 * (as far as we know) in use by the GPU.
2895 ANV_BO_FENCE_STATE_SUBMITTED
,
2897 ANV_BO_FENCE_STATE_SIGNALED
,
2900 struct anv_fence_impl
{
2901 enum anv_fence_type type
;
2904 /** Fence implementation for BO fences
2906 * These fences use a BO and a set of CPU-tracked state flags. The BO
2907 * is added to the object list of the last execbuf call in a QueueSubmit
2908 * and is marked EXEC_WRITE. The state flags track when the BO has been
2909 * submitted to the kernel. We need to do this because Vulkan lets you
2910 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2911 * will say it's idle in this case.
2915 enum anv_bo_fence_state state
;
2918 /** DRM syncobj handle for syncobj-based fences */
2922 struct wsi_fence
*fence_wsi
;
2927 /* Permanent fence state. Every fence has some form of permanent state
2928 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2929 * cross-process fences) or it could just be a dummy for use internally.
2931 struct anv_fence_impl permanent
;
2933 /* Temporary fence state. A fence *may* have temporary state. That state
2934 * is added to the fence by an import operation and is reset back to
2935 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2936 * state cannot be signaled because the fence must already be signaled
2937 * before the temporary state can be exported from the fence in the other
2938 * process and imported here.
2940 struct anv_fence_impl temporary
;
2943 void anv_fence_reset_temporary(struct anv_device
*device
,
2944 struct anv_fence
*fence
);
2948 struct anv_state state
;
2951 enum anv_semaphore_type
{
2952 ANV_SEMAPHORE_TYPE_NONE
= 0,
2953 ANV_SEMAPHORE_TYPE_DUMMY
,
2954 ANV_SEMAPHORE_TYPE_BO
,
2955 ANV_SEMAPHORE_TYPE_WSI_BO
,
2956 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2957 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2958 ANV_SEMAPHORE_TYPE_TIMELINE
,
2961 struct anv_timeline_point
{
2962 struct list_head link
;
2966 /* Number of waiter on this point, when > 0 the point should not be garbage
2971 /* BO used for synchronization. */
2975 struct anv_timeline
{
2976 pthread_mutex_t mutex
;
2977 pthread_cond_t cond
;
2979 uint64_t highest_past
;
2980 uint64_t highest_pending
;
2982 struct list_head points
;
2983 struct list_head free_points
;
2986 struct anv_semaphore_impl
{
2987 enum anv_semaphore_type type
;
2990 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO
2991 * or type == ANV_SEMAPHORE_TYPE_WSI_BO. This BO will be added to the
2992 * object list on any execbuf2 calls for which this semaphore is used as
2993 * a wait or signal fence. When used as a signal fence or when type ==
2994 * ANV_SEMAPHORE_TYPE_WSI_BO, the EXEC_OBJECT_WRITE flag will be set.
2998 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2999 * If the semaphore is in the unsignaled state due to either just being
3000 * created or because it has been used for a wait, fd will be -1.
3004 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
3005 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
3006 * import so we don't need to bother with a userspace cache.
3010 /* Non shareable timeline semaphore
3012 * Used when kernel don't have support for timeline semaphores.
3014 struct anv_timeline timeline
;
3018 struct anv_semaphore
{
3021 /* Permanent semaphore state. Every semaphore has some form of permanent
3022 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
3023 * (for cross-process semaphores0 or it could just be a dummy for use
3026 struct anv_semaphore_impl permanent
;
3028 /* Temporary semaphore state. A semaphore *may* have temporary state.
3029 * That state is added to the semaphore by an import operation and is reset
3030 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
3031 * semaphore with temporary state cannot be signaled because the semaphore
3032 * must already be signaled before the temporary state can be exported from
3033 * the semaphore in the other process and imported here.
3035 struct anv_semaphore_impl temporary
;
3038 void anv_semaphore_reset_temporary(struct anv_device
*device
,
3039 struct anv_semaphore
*semaphore
);
3041 struct anv_shader_module
{
3042 unsigned char sha1
[20];
3047 static inline gl_shader_stage
3048 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
3050 assert(__builtin_popcount(vk_stage
) == 1);
3051 return ffs(vk_stage
) - 1;
3054 static inline VkShaderStageFlagBits
3055 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
3057 return (1 << mesa_stage
);
3060 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
3062 #define anv_foreach_stage(stage, stage_bits) \
3063 for (gl_shader_stage stage, \
3064 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
3065 stage = __builtin_ffs(__tmp) - 1, __tmp; \
3066 __tmp &= ~(1 << (stage)))
3068 struct anv_pipeline_bind_map
{
3069 unsigned char surface_sha1
[20];
3070 unsigned char sampler_sha1
[20];
3071 unsigned char push_sha1
[20];
3073 uint32_t surface_count
;
3074 uint32_t sampler_count
;
3076 struct anv_pipeline_binding
* surface_to_descriptor
;
3077 struct anv_pipeline_binding
* sampler_to_descriptor
;
3079 struct anv_push_range push_ranges
[4];
3082 struct anv_shader_bin_key
{
3087 struct anv_shader_bin
{
3090 const struct anv_shader_bin_key
*key
;
3092 struct anv_state kernel
;
3093 uint32_t kernel_size
;
3095 struct anv_state constant_data
;
3096 uint32_t constant_data_size
;
3098 const struct brw_stage_prog_data
*prog_data
;
3099 uint32_t prog_data_size
;
3101 struct brw_compile_stats stats
[3];
3104 struct nir_xfb_info
*xfb_info
;
3106 struct anv_pipeline_bind_map bind_map
;
3109 struct anv_shader_bin
*
3110 anv_shader_bin_create(struct anv_device
*device
,
3111 const void *key
, uint32_t key_size
,
3112 const void *kernel
, uint32_t kernel_size
,
3113 const void *constant_data
, uint32_t constant_data_size
,
3114 const struct brw_stage_prog_data
*prog_data
,
3115 uint32_t prog_data_size
, const void *prog_data_param
,
3116 const struct brw_compile_stats
*stats
, uint32_t num_stats
,
3117 const struct nir_xfb_info
*xfb_info
,
3118 const struct anv_pipeline_bind_map
*bind_map
);
3121 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
3124 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
3126 assert(shader
&& shader
->ref_cnt
>= 1);
3127 p_atomic_inc(&shader
->ref_cnt
);
3131 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
3133 assert(shader
&& shader
->ref_cnt
>= 1);
3134 if (p_atomic_dec_zero(&shader
->ref_cnt
))
3135 anv_shader_bin_destroy(device
, shader
);
3138 /* 5 possible simultaneous shader stages and FS may have up to 3 binaries */
3139 #define MAX_PIPELINE_EXECUTABLES 7
3141 struct anv_pipeline_executable
{
3142 gl_shader_stage stage
;
3144 struct brw_compile_stats stats
;
3150 struct anv_pipeline
{
3151 struct anv_device
* device
;
3152 struct anv_batch batch
;
3153 uint32_t batch_data
[512];
3154 struct anv_reloc_list batch_relocs
;
3155 anv_cmd_dirty_mask_t dynamic_state_mask
;
3156 struct anv_dynamic_state dynamic_state
;
3160 VkPipelineCreateFlags flags
;
3161 struct anv_subpass
* subpass
;
3163 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
3165 uint32_t num_executables
;
3166 struct anv_pipeline_executable executables
[MAX_PIPELINE_EXECUTABLES
];
3168 const struct gen_l3_config
* l3_config
;
3170 VkShaderStageFlags active_stages
;
3171 struct anv_state blend_state
;
3174 struct anv_pipeline_vertex_binding
{
3177 uint32_t instance_divisor
;
3180 bool primitive_restart
;
3183 uint32_t cs_right_mask
;
3186 bool depth_test_enable
;
3187 bool writes_stencil
;
3188 bool stencil_test_enable
;
3189 bool depth_clamp_enable
;
3190 bool depth_clip_enable
;
3191 bool sample_shading_enable
;
3193 bool depth_bounds_test_enable
;
3197 uint32_t depth_stencil_state
[3];
3203 uint32_t wm_depth_stencil
[3];
3207 uint32_t wm_depth_stencil
[4];
3210 uint32_t interface_descriptor_data
[8];
3214 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
3215 gl_shader_stage stage
)
3217 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
3220 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
3221 static inline const struct brw_##prefix##_prog_data * \
3222 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
3224 if (anv_pipeline_has_stage(pipeline, stage)) { \
3225 return (const struct brw_##prefix##_prog_data *) \
3226 pipeline->shaders[stage]->prog_data; \
3232 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
3233 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
3234 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
3235 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
3236 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
3237 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
3239 static inline const struct brw_vue_prog_data
*
3240 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
3242 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
3243 return &get_gs_prog_data(pipeline
)->base
;
3244 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
3245 return &get_tes_prog_data(pipeline
)->base
;
3247 return &get_vs_prog_data(pipeline
)->base
;
3251 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
3252 struct anv_pipeline_cache
*cache
,
3253 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3254 const VkAllocationCallbacks
*alloc
);
3257 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
3258 struct anv_pipeline_cache
*cache
,
3259 const VkComputePipelineCreateInfo
*info
,
3260 const struct anv_shader_module
*module
,
3261 const char *entrypoint
,
3262 const VkSpecializationInfo
*spec_info
);
3264 struct anv_format_plane
{
3265 enum isl_format isl_format
:16;
3266 struct isl_swizzle swizzle
;
3268 /* Whether this plane contains chroma channels */
3271 /* For downscaling of YUV planes */
3272 uint8_t denominator_scales
[2];
3274 /* How to map sampled ycbcr planes to a single 4 component element. */
3275 struct isl_swizzle ycbcr_swizzle
;
3277 /* What aspect is associated to this plane */
3278 VkImageAspectFlags aspect
;
3283 struct anv_format_plane planes
[3];
3290 * Return the aspect's _format_ plane, not its _memory_ plane (using the
3291 * vocabulary of VK_EXT_image_drm_format_modifier). As a consequence, \a
3292 * aspect_mask may contain VK_IMAGE_ASPECT_PLANE_*, but must not contain
3293 * VK_IMAGE_ASPECT_MEMORY_PLANE_* .
3295 static inline uint32_t
3296 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
3297 VkImageAspectFlags aspect_mask
)
3299 switch (aspect_mask
) {
3300 case VK_IMAGE_ASPECT_COLOR_BIT
:
3301 case VK_IMAGE_ASPECT_DEPTH_BIT
:
3302 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
3304 case VK_IMAGE_ASPECT_STENCIL_BIT
:
3305 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
3308 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
3310 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
3313 /* Purposefully assert with depth/stencil aspects. */
3314 unreachable("invalid image aspect");
3318 static inline VkImageAspectFlags
3319 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
3322 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3323 if (util_bitcount(image_aspects
) > 1)
3324 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
3325 return VK_IMAGE_ASPECT_COLOR_BIT
;
3327 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
3328 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
3329 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
3330 return VK_IMAGE_ASPECT_STENCIL_BIT
;
3333 #define anv_foreach_image_aspect_bit(b, image, aspects) \
3334 for_each_bit(b, anv_image_expand_aspects(image, aspects))
3336 const struct anv_format
*
3337 anv_get_format(VkFormat format
);
3339 static inline uint32_t
3340 anv_get_format_planes(VkFormat vk_format
)
3342 const struct anv_format
*format
= anv_get_format(vk_format
);
3344 return format
!= NULL
? format
->n_planes
: 0;
3347 struct anv_format_plane
3348 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3349 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
3351 static inline enum isl_format
3352 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3353 VkImageAspectFlags aspect
, VkImageTiling tiling
)
3355 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
3358 bool anv_formats_ccs_e_compatible(const struct gen_device_info
*devinfo
,
3359 VkImageCreateFlags create_flags
,
3361 VkImageTiling vk_tiling
,
3362 const VkImageFormatListCreateInfoKHR
*fmt_list
);
3364 static inline struct isl_swizzle
3365 anv_swizzle_for_render(struct isl_swizzle swizzle
)
3367 /* Sometimes the swizzle will have alpha map to one. We do this to fake
3368 * RGB as RGBA for texturing
3370 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
3371 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
3373 /* But it doesn't matter what we render to that channel */
3374 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
3380 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
3383 * Subsurface of an anv_image.
3385 struct anv_surface
{
3386 /** Valid only if isl_surf::size_B > 0. */
3387 struct isl_surf isl
;
3390 * Offset from VkImage's base address, as bound by vkBindImageMemory().
3396 VkImageType type
; /**< VkImageCreateInfo::imageType */
3397 /* The original VkFormat provided by the client. This may not match any
3398 * of the actual surface formats.
3401 const struct anv_format
*format
;
3403 VkImageAspectFlags aspects
;
3406 uint32_t array_size
;
3407 uint32_t samples
; /**< VkImageCreateInfo::samples */
3409 VkImageUsageFlags usage
; /**< VkImageCreateInfo::usage. */
3410 VkImageUsageFlags stencil_usage
;
3411 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
3412 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
3414 /** True if this is needs to be bound to an appropriately tiled BO.
3416 * When not using modifiers, consumers such as X11, Wayland, and KMS need
3417 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
3418 * we require a dedicated allocation so that we can know to allocate a
3421 bool needs_set_tiling
;
3424 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
3425 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
3427 uint64_t drm_format_mod
;
3432 /* Whether the image is made of several underlying buffer objects rather a
3433 * single one with different offsets.
3437 /* Image was created with external format. */
3438 bool external_format
;
3443 * For each foo, anv_image::planes[x].surface is valid if and only if
3444 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
3445 * to figure the number associated with a given aspect.
3447 * The hardware requires that the depth buffer and stencil buffer be
3448 * separate surfaces. From Vulkan's perspective, though, depth and stencil
3449 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
3450 * allocate the depth and stencil buffers as separate surfaces in the same
3455 * -----------------------
3457 * ----------------------- |
3458 * | shadow surface0 | |
3459 * ----------------------- | Plane 0
3460 * | aux surface0 | |
3461 * ----------------------- |
3462 * | fast clear colors0 | \|/
3463 * -----------------------
3465 * ----------------------- |
3466 * | shadow surface1 | |
3467 * ----------------------- | Plane 1
3468 * | aux surface1 | |
3469 * ----------------------- |
3470 * | fast clear colors1 | \|/
3471 * -----------------------
3474 * -----------------------
3478 * Offset of the entire plane (whenever the image is disjoint this is
3486 struct anv_surface surface
;
3489 * A surface which shadows the main surface and may have different
3490 * tiling. This is used for sampling using a tiling that isn't supported
3491 * for other operations.
3493 struct anv_surface shadow_surface
;
3496 * The base aux usage for this image. For color images, this can be
3497 * either CCS_E or CCS_D depending on whether or not we can reliably
3498 * leave CCS on all the time.
3500 enum isl_aux_usage aux_usage
;
3502 struct anv_surface aux_surface
;
3505 * Offset of the fast clear state (used to compute the
3506 * fast_clear_state_offset of the following planes).
3508 uint32_t fast_clear_state_offset
;
3511 * BO associated with this plane, set when bound.
3513 struct anv_address address
;
3516 * When destroying the image, also free the bo.
3522 /* The ordering of this enum is important */
3523 enum anv_fast_clear_type
{
3524 /** Image does not have/support any fast-clear blocks */
3525 ANV_FAST_CLEAR_NONE
= 0,
3526 /** Image has/supports fast-clear but only to the default value */
3527 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
3528 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3529 ANV_FAST_CLEAR_ANY
= 2,
3532 /* Returns the number of auxiliary buffer levels attached to an image. */
3533 static inline uint8_t
3534 anv_image_aux_levels(const struct anv_image
* const image
,
3535 VkImageAspectFlagBits aspect
)
3537 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3538 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
3541 /* The Gen12 CCS aux surface is represented with only one level. */
3542 return image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3543 image
->planes
[plane
].surface
.isl
.levels
:
3544 image
->planes
[plane
].aux_surface
.isl
.levels
;
3547 /* Returns the number of auxiliary buffer layers attached to an image. */
3548 static inline uint32_t
3549 anv_image_aux_layers(const struct anv_image
* const image
,
3550 VkImageAspectFlagBits aspect
,
3551 const uint8_t miplevel
)
3555 /* The miplevel must exist in the main buffer. */
3556 assert(miplevel
< image
->levels
);
3558 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
3559 /* There are no layers with auxiliary data because the miplevel has no
3564 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3566 /* The Gen12 CCS aux surface is represented with only one layer. */
3567 const struct isl_extent4d
*aux_logical_level0_px
=
3568 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3569 &image
->planes
[plane
].surface
.isl
.logical_level0_px
:
3570 &image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
;
3572 return MAX2(aux_logical_level0_px
->array_len
,
3573 aux_logical_level0_px
->depth
>> miplevel
);
3577 static inline struct anv_address
3578 anv_image_get_clear_color_addr(const struct anv_device
*device
,
3579 const struct anv_image
*image
,
3580 VkImageAspectFlagBits aspect
)
3582 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
3584 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3585 return anv_address_add(image
->planes
[plane
].address
,
3586 image
->planes
[plane
].fast_clear_state_offset
);
3589 static inline struct anv_address
3590 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3591 const struct anv_image
*image
,
3592 VkImageAspectFlagBits aspect
)
3594 struct anv_address addr
=
3595 anv_image_get_clear_color_addr(device
, image
, aspect
);
3597 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3598 device
->isl_dev
.ss
.clear_color_state_size
:
3599 device
->isl_dev
.ss
.clear_value_size
;
3600 return anv_address_add(addr
, clear_color_state_size
);
3603 static inline struct anv_address
3604 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3605 const struct anv_image
*image
,
3606 VkImageAspectFlagBits aspect
,
3607 uint32_t level
, uint32_t array_layer
)
3609 assert(level
< anv_image_aux_levels(image
, aspect
));
3610 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3611 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3612 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3614 struct anv_address addr
=
3615 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3616 addr
.offset
+= 4; /* Go past the fast clear type */
3618 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3619 for (uint32_t l
= 0; l
< level
; l
++)
3620 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3622 addr
.offset
+= level
* image
->array_size
* 4;
3624 addr
.offset
+= array_layer
* 4;
3626 assert(addr
.offset
<
3627 image
->planes
[plane
].address
.offset
+ image
->planes
[plane
].size
);
3631 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3633 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3634 const struct anv_image
*image
)
3636 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3639 /* Allow this feature on BDW even though it is disabled in the BDW devinfo
3640 * struct. There's documentation which suggests that this feature actually
3641 * reduces performance on BDW, but it has only been observed to help so
3642 * far. Sampling fast-cleared blocks on BDW must also be handled with care
3643 * (see depth_stencil_attachment_compute_aux_usage() for more info).
3645 if (devinfo
->gen
!= 8 && !devinfo
->has_sample_with_hiz
)
3648 return image
->samples
== 1;
3652 anv_image_plane_uses_aux_map(const struct anv_device
*device
,
3653 const struct anv_image
*image
,
3656 return device
->info
.has_aux_map
&&
3657 isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
);
3661 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3662 const struct anv_image
*image
,
3663 VkImageAspectFlagBits aspect
,
3664 enum isl_aux_usage aux_usage
,
3666 uint32_t base_layer
,
3667 uint32_t layer_count
);
3670 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
3671 const struct anv_image
*image
,
3672 VkImageAspectFlagBits aspect
,
3673 enum isl_aux_usage aux_usage
,
3674 enum isl_format format
, struct isl_swizzle swizzle
,
3675 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
3676 VkRect2D area
, union isl_color_value clear_color
);
3678 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
3679 const struct anv_image
*image
,
3680 VkImageAspectFlags aspects
,
3681 enum isl_aux_usage depth_aux_usage
,
3683 uint32_t base_layer
, uint32_t layer_count
,
3685 float depth_value
, uint8_t stencil_value
);
3687 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
3688 const struct anv_image
*src_image
,
3689 enum isl_aux_usage src_aux_usage
,
3690 uint32_t src_level
, uint32_t src_base_layer
,
3691 const struct anv_image
*dst_image
,
3692 enum isl_aux_usage dst_aux_usage
,
3693 uint32_t dst_level
, uint32_t dst_base_layer
,
3694 VkImageAspectFlagBits aspect
,
3695 uint32_t src_x
, uint32_t src_y
,
3696 uint32_t dst_x
, uint32_t dst_y
,
3697 uint32_t width
, uint32_t height
,
3698 uint32_t layer_count
,
3699 enum blorp_filter filter
);
3701 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
3702 const struct anv_image
*image
,
3703 VkImageAspectFlagBits aspect
, uint32_t level
,
3704 uint32_t base_layer
, uint32_t layer_count
,
3705 enum isl_aux_op hiz_op
);
3707 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
3708 const struct anv_image
*image
,
3709 VkImageAspectFlags aspects
,
3711 uint32_t base_layer
, uint32_t layer_count
,
3712 VkRect2D area
, uint8_t stencil_value
);
3714 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3715 const struct anv_image
*image
,
3716 enum isl_format format
,
3717 VkImageAspectFlagBits aspect
,
3718 uint32_t base_layer
, uint32_t layer_count
,
3719 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
3722 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
3723 const struct anv_image
*image
,
3724 enum isl_format format
,
3725 VkImageAspectFlagBits aspect
, uint32_t level
,
3726 uint32_t base_layer
, uint32_t layer_count
,
3727 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
3731 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
3732 const struct anv_image
*image
,
3733 VkImageAspectFlagBits aspect
,
3734 uint32_t base_level
, uint32_t level_count
,
3735 uint32_t base_layer
, uint32_t layer_count
);
3738 anv_layout_to_aux_state(const struct gen_device_info
* const devinfo
,
3739 const struct anv_image
*image
,
3740 const VkImageAspectFlagBits aspect
,
3741 const VkImageLayout layout
);
3744 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
3745 const struct anv_image
*image
,
3746 const VkImageAspectFlagBits aspect
,
3747 const VkImageUsageFlagBits usage
,
3748 const VkImageLayout layout
);
3750 enum anv_fast_clear_type
3751 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
3752 const struct anv_image
* const image
,
3753 const VkImageAspectFlagBits aspect
,
3754 const VkImageLayout layout
);
3756 /* This is defined as a macro so that it works for both
3757 * VkImageSubresourceRange and VkImageSubresourceLayers
3759 #define anv_get_layerCount(_image, _range) \
3760 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3761 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3763 static inline uint32_t
3764 anv_get_levelCount(const struct anv_image
*image
,
3765 const VkImageSubresourceRange
*range
)
3767 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
3768 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
3771 static inline VkImageAspectFlags
3772 anv_image_expand_aspects(const struct anv_image
*image
,
3773 VkImageAspectFlags aspects
)
3775 /* If the underlying image has color plane aspects and
3776 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3777 * the underlying image. */
3778 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
3779 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
3780 return image
->aspects
;
3786 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
3787 VkImageAspectFlags aspects2
)
3789 if (aspects1
== aspects2
)
3792 /* Only 1 color aspects are compatibles. */
3793 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3794 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3795 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3801 struct anv_image_view
{
3802 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
3804 VkImageAspectFlags aspect_mask
;
3806 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3810 uint32_t image_plane
;
3812 struct isl_view isl
;
3815 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3816 * image layout of SHADER_READ_ONLY_OPTIMAL or
3817 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3819 struct anv_surface_state optimal_sampler_surface_state
;
3822 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3823 * image layout of GENERAL.
3825 struct anv_surface_state general_sampler_surface_state
;
3828 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3829 * states for write-only and readable, using the real format for
3830 * write-only and the lowered format for readable.
3832 struct anv_surface_state storage_surface_state
;
3833 struct anv_surface_state writeonly_storage_surface_state
;
3835 struct brw_image_param storage_image_param
;
3839 enum anv_image_view_state_flags
{
3840 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
3841 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
3844 void anv_image_fill_surface_state(struct anv_device
*device
,
3845 const struct anv_image
*image
,
3846 VkImageAspectFlagBits aspect
,
3847 const struct isl_view
*view
,
3848 isl_surf_usage_flags_t view_usage
,
3849 enum isl_aux_usage aux_usage
,
3850 const union isl_color_value
*clear_color
,
3851 enum anv_image_view_state_flags flags
,
3852 struct anv_surface_state
*state_inout
,
3853 struct brw_image_param
*image_param_out
);
3855 struct anv_image_create_info
{
3856 const VkImageCreateInfo
*vk_info
;
3858 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3859 isl_tiling_flags_t isl_tiling_flags
;
3861 /** These flags will be added to any derived from VkImageCreateInfo. */
3862 isl_surf_usage_flags_t isl_extra_usage_flags
;
3865 bool external_format
;
3868 VkResult
anv_image_create(VkDevice _device
,
3869 const struct anv_image_create_info
*info
,
3870 const VkAllocationCallbacks
* alloc
,
3874 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3876 static inline VkExtent3D
3877 anv_sanitize_image_extent(const VkImageType imageType
,
3878 const VkExtent3D imageExtent
)
3880 switch (imageType
) {
3881 case VK_IMAGE_TYPE_1D
:
3882 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3883 case VK_IMAGE_TYPE_2D
:
3884 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3885 case VK_IMAGE_TYPE_3D
:
3888 unreachable("invalid image type");
3892 static inline VkOffset3D
3893 anv_sanitize_image_offset(const VkImageType imageType
,
3894 const VkOffset3D imageOffset
)
3896 switch (imageType
) {
3897 case VK_IMAGE_TYPE_1D
:
3898 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3899 case VK_IMAGE_TYPE_2D
:
3900 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3901 case VK_IMAGE_TYPE_3D
:
3904 unreachable("invalid image type");
3908 VkFormatFeatureFlags
3909 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
3911 const struct anv_format
*anv_format
,
3912 VkImageTiling vk_tiling
);
3914 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3915 struct anv_state state
,
3916 enum isl_format format
,
3917 struct anv_address address
,
3918 uint32_t range
, uint32_t stride
);
3921 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3922 const struct anv_attachment_state
*att_state
,
3923 const struct anv_image_view
*iview
)
3925 const struct isl_format_layout
*view_fmtl
=
3926 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3928 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3929 if (view_fmtl->channels.c.bits) \
3930 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3932 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3933 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3934 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3935 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3937 #undef COPY_CLEAR_COLOR_CHANNEL
3941 struct anv_ycbcr_conversion
{
3942 const struct anv_format
* format
;
3943 VkSamplerYcbcrModelConversion ycbcr_model
;
3944 VkSamplerYcbcrRange ycbcr_range
;
3945 VkComponentSwizzle mapping
[4];
3946 VkChromaLocation chroma_offsets
[2];
3947 VkFilter chroma_filter
;
3948 bool chroma_reconstruction
;
3951 struct anv_sampler
{
3952 uint32_t state
[3][4];
3954 struct anv_ycbcr_conversion
*conversion
;
3956 /* Blob of sampler state data which is guaranteed to be 32-byte aligned
3957 * and with a 32-byte stride for use as bindless samplers.
3959 struct anv_state bindless_state
;
3962 struct anv_framebuffer
{
3967 uint32_t attachment_count
;
3968 struct anv_image_view
* attachments
[0];
3971 struct anv_subpass_attachment
{
3972 VkImageUsageFlagBits usage
;
3973 uint32_t attachment
;
3974 VkImageLayout layout
;
3976 /* Used only with attachment containing stencil data. */
3977 VkImageLayout stencil_layout
;
3980 struct anv_subpass
{
3981 uint32_t attachment_count
;
3984 * A pointer to all attachment references used in this subpass.
3985 * Only valid if ::attachment_count > 0.
3987 struct anv_subpass_attachment
* attachments
;
3988 uint32_t input_count
;
3989 struct anv_subpass_attachment
* input_attachments
;
3990 uint32_t color_count
;
3991 struct anv_subpass_attachment
* color_attachments
;
3992 struct anv_subpass_attachment
* resolve_attachments
;
3994 struct anv_subpass_attachment
* depth_stencil_attachment
;
3995 struct anv_subpass_attachment
* ds_resolve_attachment
;
3996 VkResolveModeFlagBitsKHR depth_resolve_mode
;
3997 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
4001 /** Subpass has a depth/stencil self-dependency */
4002 bool has_ds_self_dep
;
4004 /** Subpass has at least one color resolve attachment */
4005 bool has_color_resolve
;
4008 static inline unsigned
4009 anv_subpass_view_count(const struct anv_subpass
*subpass
)
4011 return MAX2(1, util_bitcount(subpass
->view_mask
));
4014 struct anv_render_pass_attachment
{
4015 /* TODO: Consider using VkAttachmentDescription instead of storing each of
4016 * its members individually.
4020 VkImageUsageFlags usage
;
4021 VkAttachmentLoadOp load_op
;
4022 VkAttachmentStoreOp store_op
;
4023 VkAttachmentLoadOp stencil_load_op
;
4024 VkImageLayout initial_layout
;
4025 VkImageLayout final_layout
;
4026 VkImageLayout first_subpass_layout
;
4028 VkImageLayout stencil_initial_layout
;
4029 VkImageLayout stencil_final_layout
;
4031 /* The subpass id in which the attachment will be used last. */
4032 uint32_t last_subpass_idx
;
4035 struct anv_render_pass
{
4036 uint32_t attachment_count
;
4037 uint32_t subpass_count
;
4038 /* An array of subpass_count+1 flushes, one per subpass boundary */
4039 enum anv_pipe_bits
* subpass_flushes
;
4040 struct anv_render_pass_attachment
* attachments
;
4041 struct anv_subpass subpasses
[0];
4044 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
4046 struct anv_query_pool
{
4048 VkQueryPipelineStatisticFlags pipeline_statistics
;
4049 /** Stride between slots, in bytes */
4051 /** Number of slots in this query pool */
4056 int anv_get_instance_entrypoint_index(const char *name
);
4057 int anv_get_device_entrypoint_index(const char *name
);
4058 int anv_get_physical_device_entrypoint_index(const char *name
);
4060 const char *anv_get_instance_entry_name(int index
);
4061 const char *anv_get_physical_device_entry_name(int index
);
4062 const char *anv_get_device_entry_name(int index
);
4065 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
4066 const struct anv_instance_extension_table
*instance
);
4068 anv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
4069 const struct anv_instance_extension_table
*instance
);
4071 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
4072 const struct anv_instance_extension_table
*instance
,
4073 const struct anv_device_extension_table
*device
);
4075 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
4078 void anv_dump_image_to_ppm(struct anv_device
*device
,
4079 struct anv_image
*image
, unsigned miplevel
,
4080 unsigned array_layer
, VkImageAspectFlagBits aspect
,
4081 const char *filename
);
4083 enum anv_dump_action
{
4084 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
4087 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
4088 void anv_dump_finish(void);
4090 void anv_dump_add_attachments(struct anv_cmd_buffer
*cmd_buffer
);
4092 static inline uint32_t
4093 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
4095 /* This function must be called from within a subpass. */
4096 assert(cmd_state
->pass
&& cmd_state
->subpass
);
4098 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
4100 /* The id of this subpass shouldn't exceed the number of subpasses in this
4101 * render pass minus 1.
4103 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
4107 struct gen_perf_config
*anv_get_perf(const struct gen_device_info
*devinfo
, int fd
);
4108 void anv_device_perf_init(struct anv_device
*device
);
4110 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
4112 static inline struct __anv_type * \
4113 __anv_type ## _from_handle(__VkType _handle) \
4115 return (struct __anv_type *) _handle; \
4118 static inline __VkType \
4119 __anv_type ## _to_handle(struct __anv_type *_obj) \
4121 return (__VkType) _obj; \
4124 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
4126 static inline struct __anv_type * \
4127 __anv_type ## _from_handle(__VkType _handle) \
4129 return (struct __anv_type *)(uintptr_t) _handle; \
4132 static inline __VkType \
4133 __anv_type ## _to_handle(struct __anv_type *_obj) \
4135 return (__VkType)(uintptr_t) _obj; \
4138 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
4139 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
4141 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
4142 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
4143 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
4144 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
4145 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
4147 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
4148 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
4149 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
4150 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
4151 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
4152 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
4153 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
4154 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
4155 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
4156 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
4157 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
4158 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
4159 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
4160 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
4161 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
4162 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
4163 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
4164 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
4165 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
4166 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
4167 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
4168 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
4169 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
4171 /* Gen-specific function declarations */
4173 # include "anv_genX.h"
4175 # define genX(x) gen7_##x
4176 # include "anv_genX.h"
4178 # define genX(x) gen75_##x
4179 # include "anv_genX.h"
4181 # define genX(x) gen8_##x
4182 # include "anv_genX.h"
4184 # define genX(x) gen9_##x
4185 # include "anv_genX.h"
4187 # define genX(x) gen10_##x
4188 # include "anv_genX.h"
4190 # define genX(x) gen11_##x
4191 # include "anv_genX.h"
4193 # define genX(x) gen12_##x
4194 # include "anv_genX.h"
4198 #endif /* ANV_PRIVATE_H */