2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
44 #include "common/gen_device_info.h"
45 #include "blorp/blorp.h"
46 #include "compiler/brw_compiler.h"
47 #include "util/macros.h"
48 #include "util/list.h"
49 #include "util/u_vector.h"
50 #include "util/vk_alloc.h"
52 /* Pre-declarations needed for WSI entrypoints */
55 typedef struct xcb_connection_t xcb_connection_t
;
56 typedef uint32_t xcb_visualid_t
;
57 typedef uint32_t xcb_window_t
;
60 struct anv_buffer_view
;
61 struct anv_image_view
;
65 #include <vulkan/vulkan.h>
66 #include <vulkan/vulkan_intel.h>
67 #include <vulkan/vk_icd.h>
69 #include "anv_entrypoints.h"
72 #include "common/gen_debug.h"
73 #include "wsi_common.h"
75 /* Allowing different clear colors requires us to perform a depth resolve at
76 * the end of certain render passes. This is because while slow clears store
77 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
78 * See the PRMs for examples describing when additional resolves would be
79 * necessary. To enable fast clears without requiring extra resolves, we set
80 * the clear value to a globally-defined one. We could allow different values
81 * if the user doesn't expect coherent data during or after a render passes
82 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
83 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
84 * 1.0f seems to be the only value used. The only application that doesn't set
85 * this value does so through the usage of an seemingly uninitialized clear
88 #define ANV_HZ_FC_VAL 1.0f
93 #define MAX_VIEWPORTS 16
94 #define MAX_SCISSORS 16
95 #define MAX_PUSH_CONSTANTS_SIZE 128
96 #define MAX_DYNAMIC_BUFFERS 16
98 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
100 #define ANV_SVGS_VB_INDEX MAX_VBS
101 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
103 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
105 static inline uint32_t
106 align_down_npot_u32(uint32_t v
, uint32_t a
)
111 static inline uint32_t
112 align_u32(uint32_t v
, uint32_t a
)
114 assert(a
!= 0 && a
== (a
& -a
));
115 return (v
+ a
- 1) & ~(a
- 1);
118 static inline uint64_t
119 align_u64(uint64_t v
, uint64_t a
)
121 assert(a
!= 0 && a
== (a
& -a
));
122 return (v
+ a
- 1) & ~(a
- 1);
125 static inline int32_t
126 align_i32(int32_t v
, int32_t a
)
128 assert(a
!= 0 && a
== (a
& -a
));
129 return (v
+ a
- 1) & ~(a
- 1);
132 /** Alignment must be a power of 2. */
134 anv_is_aligned(uintmax_t n
, uintmax_t a
)
136 assert(a
== (a
& -a
));
137 return (n
& (a
- 1)) == 0;
140 static inline uint32_t
141 anv_minify(uint32_t n
, uint32_t levels
)
143 if (unlikely(n
== 0))
146 return MAX2(n
>> levels
, 1);
150 anv_clamp_f(float f
, float min
, float max
)
163 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
165 if (*inout_mask
& clear_mask
) {
166 *inout_mask
&= ~clear_mask
;
173 static inline union isl_color_value
174 vk_to_isl_color(VkClearColorValue color
)
176 return (union isl_color_value
) {
186 #define for_each_bit(b, dword) \
187 for (uint32_t __dword = (dword); \
188 (b) = __builtin_ffs(__dword) - 1, __dword; \
189 __dword &= ~(1 << (b)))
191 #define typed_memcpy(dest, src, count) ({ \
192 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
193 memcpy((dest), (src), (count) * sizeof(*(src))); \
196 /* Whenever we generate an error, pass it through this function. Useful for
197 * debugging, where we can break on it. Only call at error site, not when
198 * propagating errors. Might be useful to plug in a stack trace here.
201 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
204 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
205 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
206 #define anv_debug(format, ...) fprintf(stderr, "debug: " format, ##__VA_ARGS__)
208 #define vk_error(error) error
209 #define vk_errorf(error, format, ...) error
210 #define anv_debug(format, ...)
214 * Warn on ignored extension structs.
216 * The Vulkan spec requires us to ignore unsupported or unknown structs in
217 * a pNext chain. In debug mode, emitting warnings for ignored structs may
218 * help us discover structs that we should not have ignored.
221 * From the Vulkan 1.0.38 spec:
223 * Any component of the implementation (the loader, any enabled layers,
224 * and drivers) must skip over, without processing (other than reading the
225 * sType and pNext members) any chained structures with sType values not
226 * defined by extensions supported by that component.
228 #define anv_debug_ignored_stype(sType) \
229 anv_debug("debug: %s: ignored VkStructureType %u\n", __func__, (sType))
231 void __anv_finishme(const char *file
, int line
, const char *format
, ...)
232 anv_printflike(3, 4);
233 void __anv_perf_warn(const char *file
, int line
, const char *format
, ...)
234 anv_printflike(3, 4);
235 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
236 void anv_loge_v(const char *format
, va_list va
);
239 * Print a FINISHME message, including its source location.
241 #define anv_finishme(format, ...) \
243 static bool reported = false; \
245 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
251 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
253 #define anv_perf_warn(format, ...) \
255 static bool reported = false; \
256 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
257 __anv_perf_warn(__FILE__, __LINE__, format, ##__VA_ARGS__); \
262 /* A non-fatal assert. Useful for debugging. */
264 #define anv_assert(x) ({ \
265 if (unlikely(!(x))) \
266 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
269 #define anv_assert(x)
273 * A dynamically growable, circular buffer. Elements are added at head and
274 * removed from tail. head and tail are free-running uint32_t indices and we
275 * only compute the modulo with size when accessing the array. This way,
276 * number of bytes in the queue is always head - tail, even in case of
283 /* Index into the current validation list. This is used by the
284 * validation list building alrogithm to track which buffers are already
285 * in the validation list so that we can ensure uniqueness.
289 /* Last known offset. This value is provided by the kernel when we
290 * execbuf and is used as the presumed offset for the next bunch of
298 /* We need to set the WRITE flag on winsys bos so GEM will know we're
299 * writing to them and synchronize uses on other rings (eg if the display
300 * server uses the blitter ring).
306 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
308 bo
->gem_handle
= gem_handle
;
313 bo
->is_winsys_bo
= false;
316 /* Represents a lock-free linked list of "free" things. This is used by
317 * both the block pool and the state pools. Unfortunately, in order to
318 * solve the ABA problem, we can't use a single uint32_t head.
320 union anv_free_list
{
324 /* A simple count that is incremented every time the head changes. */
330 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
332 struct anv_block_state
{
342 struct anv_block_pool
{
343 struct anv_device
*device
;
347 /* The offset from the start of the bo to the "center" of the block
348 * pool. Pointers to allocated blocks are given by
349 * bo.map + center_bo_offset + offsets.
351 uint32_t center_bo_offset
;
353 /* Current memory map of the block pool. This pointer may or may not
354 * point to the actual beginning of the block pool memory. If
355 * anv_block_pool_alloc_back has ever been called, then this pointer
356 * will point to the "center" position of the buffer and all offsets
357 * (negative or positive) given out by the block pool alloc functions
358 * will be valid relative to this pointer.
360 * In particular, map == bo.map + center_offset
366 * Array of mmaps and gem handles owned by the block pool, reclaimed when
367 * the block pool is destroyed.
369 struct u_vector mmap_cleanups
;
373 union anv_free_list free_list
;
374 struct anv_block_state state
;
376 union anv_free_list back_free_list
;
377 struct anv_block_state back_state
;
380 /* Block pools are backed by a fixed-size 2GB memfd */
381 #define BLOCK_POOL_MEMFD_SIZE (1ul << 31)
383 /* The center of the block pool is also the middle of the memfd. This may
384 * change in the future if we decide differently for some reason.
386 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
388 static inline uint32_t
389 anv_block_pool_size(struct anv_block_pool
*pool
)
391 return pool
->state
.end
+ pool
->back_state
.end
;
400 struct anv_fixed_size_state_pool
{
402 union anv_free_list free_list
;
403 struct anv_block_state block
;
406 #define ANV_MIN_STATE_SIZE_LOG2 6
407 #define ANV_MAX_STATE_SIZE_LOG2 20
409 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
411 struct anv_state_pool
{
412 struct anv_block_pool
*block_pool
;
413 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
416 struct anv_state_stream_block
;
418 struct anv_state_stream
{
419 struct anv_block_pool
*block_pool
;
421 /* The current working block */
422 struct anv_state_stream_block
*block
;
424 /* Offset at which the current block starts */
426 /* Offset at which to allocate the next state */
428 /* Offset at which the current block ends */
432 #define CACHELINE_SIZE 64
433 #define CACHELINE_MASK 63
436 anv_clflush_range(void *start
, size_t size
)
438 void *p
= (void *) (((uintptr_t) start
) & ~CACHELINE_MASK
);
439 void *end
= start
+ size
;
442 __builtin_ia32_clflush(p
);
448 anv_flush_range(void *start
, size_t size
)
450 __builtin_ia32_mfence();
451 anv_clflush_range(start
, size
);
455 anv_invalidate_range(void *start
, size_t size
)
457 anv_clflush_range(start
, size
);
458 __builtin_ia32_mfence();
461 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
462 struct anv_device
*device
, uint32_t block_size
);
463 void anv_block_pool_finish(struct anv_block_pool
*pool
);
464 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
);
465 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
);
466 void anv_block_pool_free(struct anv_block_pool
*pool
, int32_t offset
);
467 void anv_state_pool_init(struct anv_state_pool
*pool
,
468 struct anv_block_pool
*block_pool
);
469 void anv_state_pool_finish(struct anv_state_pool
*pool
);
470 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
471 size_t state_size
, size_t alignment
);
472 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
473 void anv_state_stream_init(struct anv_state_stream
*stream
,
474 struct anv_block_pool
*block_pool
);
475 void anv_state_stream_finish(struct anv_state_stream
*stream
);
476 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
477 uint32_t size
, uint32_t alignment
);
480 * Implements a pool of re-usable BOs. The interface is identical to that
481 * of block_pool except that each block is its own BO.
484 struct anv_device
*device
;
489 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
490 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
491 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
493 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
495 struct anv_scratch_bo
{
500 struct anv_scratch_pool
{
501 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
502 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
505 void anv_scratch_pool_init(struct anv_device
*device
,
506 struct anv_scratch_pool
*pool
);
507 void anv_scratch_pool_finish(struct anv_device
*device
,
508 struct anv_scratch_pool
*pool
);
509 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
510 struct anv_scratch_pool
*pool
,
511 gl_shader_stage stage
,
512 unsigned per_thread_scratch
);
514 struct anv_physical_device
{
515 VK_LOADER_DATA _loader_data
;
517 struct anv_instance
* instance
;
521 struct gen_device_info info
;
522 uint64_t aperture_size
;
523 struct brw_compiler
* compiler
;
524 struct isl_device isl_dev
;
525 int cmd_parser_version
;
528 uint32_t subslice_total
;
530 uint8_t uuid
[VK_UUID_SIZE
];
532 struct wsi_device wsi_device
;
536 struct anv_instance
{
537 VK_LOADER_DATA _loader_data
;
539 VkAllocationCallbacks alloc
;
542 int physicalDeviceCount
;
543 struct anv_physical_device physicalDevice
;
546 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
547 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
550 VK_LOADER_DATA _loader_data
;
552 struct anv_device
* device
;
554 struct anv_state_pool
* pool
;
557 struct anv_pipeline_cache
{
558 struct anv_device
* device
;
559 pthread_mutex_t mutex
;
561 struct hash_table
* cache
;
564 struct anv_pipeline_bind_map
;
566 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
567 struct anv_device
*device
,
569 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
571 struct anv_shader_bin
*
572 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
573 const void *key
, uint32_t key_size
);
574 struct anv_shader_bin
*
575 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
576 const void *key_data
, uint32_t key_size
,
577 const void *kernel_data
, uint32_t kernel_size
,
578 const struct brw_stage_prog_data
*prog_data
,
579 uint32_t prog_data_size
,
580 const struct anv_pipeline_bind_map
*bind_map
);
583 VK_LOADER_DATA _loader_data
;
585 VkAllocationCallbacks alloc
;
587 struct anv_instance
* instance
;
589 struct gen_device_info info
;
590 struct isl_device isl_dev
;
593 bool can_chain_batches
;
594 bool robust_buffer_access
;
596 struct anv_bo_pool batch_bo_pool
;
598 struct anv_block_pool dynamic_state_block_pool
;
599 struct anv_state_pool dynamic_state_pool
;
601 struct anv_block_pool instruction_block_pool
;
602 struct anv_state_pool instruction_state_pool
;
604 struct anv_block_pool surface_state_block_pool
;
605 struct anv_state_pool surface_state_pool
;
607 struct anv_bo workaround_bo
;
609 struct anv_pipeline_cache blorp_shader_cache
;
610 struct blorp_context blorp
;
612 struct anv_state border_colors
;
614 struct anv_queue queue
;
616 struct anv_scratch_pool scratch_pool
;
618 uint32_t default_mocs
;
620 pthread_mutex_t mutex
;
621 pthread_cond_t queue_submit
;
625 anv_state_flush(struct anv_device
*device
, struct anv_state state
)
627 if (device
->info
.has_llc
)
630 anv_flush_range(state
.map
, state
.alloc_size
);
633 void anv_device_init_blorp(struct anv_device
*device
);
634 void anv_device_finish_blorp(struct anv_device
*device
);
636 VkResult
anv_device_execbuf(struct anv_device
*device
,
637 struct drm_i915_gem_execbuffer2
*execbuf
,
638 struct anv_bo
**execbuf_bos
);
640 void* anv_gem_mmap(struct anv_device
*device
,
641 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
642 void anv_gem_munmap(void *p
, uint64_t size
);
643 uint32_t anv_gem_create(struct anv_device
*device
, size_t size
);
644 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
645 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
646 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
647 int anv_gem_execbuffer(struct anv_device
*device
,
648 struct drm_i915_gem_execbuffer2
*execbuf
);
649 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
650 uint32_t stride
, uint32_t tiling
);
651 int anv_gem_create_context(struct anv_device
*device
);
652 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
653 int anv_gem_get_param(int fd
, uint32_t param
);
654 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
655 int anv_gem_get_aperture(int fd
, uint64_t *size
);
656 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
657 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
658 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
659 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
660 uint32_t read_domains
, uint32_t write_domain
);
662 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
664 struct anv_reloc_list
{
667 struct drm_i915_gem_relocation_entry
* relocs
;
668 struct anv_bo
** reloc_bos
;
671 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
672 const VkAllocationCallbacks
*alloc
);
673 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
674 const VkAllocationCallbacks
*alloc
);
676 uint64_t anv_reloc_list_add(struct anv_reloc_list
*list
,
677 const VkAllocationCallbacks
*alloc
,
678 uint32_t offset
, struct anv_bo
*target_bo
,
681 struct anv_batch_bo
{
682 /* Link in the anv_cmd_buffer.owned_batch_bos list */
683 struct list_head link
;
687 /* Bytes actually consumed in this batch BO */
690 struct anv_reloc_list relocs
;
694 const VkAllocationCallbacks
* alloc
;
700 struct anv_reloc_list
* relocs
;
702 /* This callback is called (with the associated user data) in the event
703 * that the batch runs out of space.
705 VkResult (*extend_cb
)(struct anv_batch
*, void *);
709 * Current error status of the command buffer. Used to track inconsistent
710 * or incomplete command buffer states that are the consequence of run-time
711 * errors such as out of memory scenarios. We want to track this in the
712 * batch because the command buffer object is not visible to some parts
718 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
719 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
720 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
721 void *location
, struct anv_bo
*bo
, uint32_t offset
);
722 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
723 struct anv_batch
*batch
);
725 static inline VkResult
726 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
728 assert(error
!= VK_SUCCESS
);
729 if (batch
->status
== VK_SUCCESS
)
730 batch
->status
= error
;
731 return batch
->status
;
735 anv_batch_has_error(struct anv_batch
*batch
)
737 return batch
->status
!= VK_SUCCESS
;
745 static inline uint64_t
746 _anv_combine_address(struct anv_batch
*batch
, void *location
,
747 const struct anv_address address
, uint32_t delta
)
749 if (address
.bo
== NULL
) {
750 return address
.offset
+ delta
;
752 assert(batch
->start
<= location
&& location
< batch
->end
);
754 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
758 #define __gen_address_type struct anv_address
759 #define __gen_user_data struct anv_batch
760 #define __gen_combine_address _anv_combine_address
762 /* Wrapper macros needed to work around preprocessor argument issues. In
763 * particular, arguments don't get pre-evaluated if they are concatenated.
764 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
765 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
766 * We can work around this easily enough with these helpers.
768 #define __anv_cmd_length(cmd) cmd ## _length
769 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
770 #define __anv_cmd_header(cmd) cmd ## _header
771 #define __anv_cmd_pack(cmd) cmd ## _pack
772 #define __anv_reg_num(reg) reg ## _num
774 #define anv_pack_struct(dst, struc, ...) do { \
775 struct struc __template = { \
778 __anv_cmd_pack(struc)(NULL, dst, &__template); \
779 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
782 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
783 void *__dst = anv_batch_emit_dwords(batch, n); \
784 struct cmd __template = { \
785 __anv_cmd_header(cmd), \
786 .DWordLength = n - __anv_cmd_length_bias(cmd), \
789 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
793 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
797 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
798 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
799 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
800 dw[i] = (dwords0)[i] | (dwords1)[i]; \
801 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
804 #define anv_batch_emit(batch, cmd, name) \
805 for (struct cmd name = { __anv_cmd_header(cmd) }, \
806 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
807 __builtin_expect(_dst != NULL, 1); \
808 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
809 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
813 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
814 .GraphicsDataTypeGFDT = 0, \
815 .LLCCacheabilityControlLLCCC = 0, \
816 .L3CacheabilityControlL3CC = 1, \
819 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
820 .LLCeLLCCacheabilityControlLLCCC = 0, \
821 .L3CacheabilityControlL3CC = 1, \
824 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
825 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
826 .TargetCache = L3DefertoPATforLLCeLLCselection, \
830 /* Skylake: MOCS is now an index into an array of 62 different caching
831 * configurations programmed by the kernel.
834 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
835 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
836 .IndextoMOCSTables = 2 \
839 #define GEN9_MOCS_PTE { \
840 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
841 .IndextoMOCSTables = 1 \
844 struct anv_device_memory
{
847 VkDeviceSize map_size
;
852 * Header for Vertex URB Entry (VUE)
854 struct anv_vue_header
{
856 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
857 uint32_t ViewportIndex
;
861 struct anv_descriptor_set_binding_layout
{
863 /* The type of the descriptors in this binding */
864 VkDescriptorType type
;
867 /* Number of array elements in this binding */
870 /* Index into the flattend descriptor set */
871 uint16_t descriptor_index
;
873 /* Index into the dynamic state array for a dynamic buffer */
874 int16_t dynamic_offset_index
;
876 /* Index into the descriptor set buffer views */
877 int16_t buffer_index
;
880 /* Index into the binding table for the associated surface */
881 int16_t surface_index
;
883 /* Index into the sampler table for the associated sampler */
884 int16_t sampler_index
;
886 /* Index into the image table for the associated image */
888 } stage
[MESA_SHADER_STAGES
];
890 /* Immutable samplers (or NULL if no immutable samplers) */
891 struct anv_sampler
**immutable_samplers
;
894 struct anv_descriptor_set_layout
{
895 /* Number of bindings in this descriptor set */
896 uint16_t binding_count
;
898 /* Total size of the descriptor set with room for all array entries */
901 /* Shader stages affected by this descriptor set */
902 uint16_t shader_stages
;
904 /* Number of buffers in this descriptor set */
905 uint16_t buffer_count
;
907 /* Number of dynamic offsets used by this descriptor set */
908 uint16_t dynamic_offset_count
;
910 /* Bindings in this descriptor set */
911 struct anv_descriptor_set_binding_layout binding
[0];
914 struct anv_descriptor
{
915 VkDescriptorType type
;
919 struct anv_image_view
*image_view
;
920 struct anv_sampler
*sampler
;
922 /* Used to determine whether or not we need the surface state to have
923 * the auxiliary buffer enabled.
925 enum isl_aux_usage aux_usage
;
929 struct anv_buffer
*buffer
;
934 struct anv_buffer_view
*buffer_view
;
938 struct anv_descriptor_set
{
939 const struct anv_descriptor_set_layout
*layout
;
941 uint32_t buffer_count
;
942 struct anv_buffer_view
*buffer_views
;
943 struct anv_descriptor descriptors
[0];
946 struct anv_buffer_view
{
947 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
949 uint32_t offset
; /**< Offset into bo. */
950 uint64_t range
; /**< VkBufferViewCreateInfo::range */
952 struct anv_state surface_state
;
953 struct anv_state storage_surface_state
;
954 struct anv_state writeonly_storage_surface_state
;
956 struct brw_image_param storage_image_param
;
959 struct anv_push_descriptor_set
{
960 struct anv_descriptor_set set
;
962 /* Put this field right behind anv_descriptor_set so it fills up the
963 * descriptors[0] field. */
964 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
966 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
969 struct anv_descriptor_pool
{
974 struct anv_state_stream surface_state_stream
;
975 void *surface_state_free_list
;
980 enum anv_descriptor_template_entry_type
{
981 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
982 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
983 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
986 struct anv_descriptor_template_entry
{
987 /* The type of descriptor in this entry */
988 VkDescriptorType type
;
990 /* Binding in the descriptor set */
993 /* Offset at which to write into the descriptor set binding */
994 uint32_t array_element
;
996 /* Number of elements to write into the descriptor set binding */
997 uint32_t array_count
;
999 /* Offset into the user provided data */
1002 /* Stride between elements into the user provided data */
1006 struct anv_descriptor_update_template
{
1007 /* The descriptor set this template corresponds to. This value is only
1008 * valid if the template was created with the templateType
1009 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1013 /* Number of entries in this template */
1014 uint32_t entry_count
;
1016 /* Entries of the template */
1017 struct anv_descriptor_template_entry entries
[0];
1021 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1024 anv_descriptor_set_write_image_view(struct anv_descriptor_set
*set
,
1025 const struct gen_device_info
* const devinfo
,
1026 const VkDescriptorImageInfo
* const info
,
1027 VkDescriptorType type
,
1032 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set
*set
,
1033 VkDescriptorType type
,
1034 struct anv_buffer_view
*buffer_view
,
1039 anv_descriptor_set_write_buffer(struct anv_descriptor_set
*set
,
1040 struct anv_device
*device
,
1041 struct anv_state_stream
*alloc_stream
,
1042 VkDescriptorType type
,
1043 struct anv_buffer
*buffer
,
1046 VkDeviceSize offset
,
1047 VkDeviceSize range
);
1050 anv_descriptor_set_write_template(struct anv_descriptor_set
*set
,
1051 struct anv_device
*device
,
1052 struct anv_state_stream
*alloc_stream
,
1053 const struct anv_descriptor_update_template
*template,
1057 anv_descriptor_set_create(struct anv_device
*device
,
1058 struct anv_descriptor_pool
*pool
,
1059 const struct anv_descriptor_set_layout
*layout
,
1060 struct anv_descriptor_set
**out_set
);
1063 anv_descriptor_set_destroy(struct anv_device
*device
,
1064 struct anv_descriptor_pool
*pool
,
1065 struct anv_descriptor_set
*set
);
1067 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1069 struct anv_pipeline_binding
{
1070 /* The descriptor set this surface corresponds to. The special value of
1071 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1072 * to a color attachment and not a regular descriptor.
1076 /* Binding in the descriptor set */
1079 /* Index in the binding */
1082 /* Input attachment index (relative to the subpass) */
1083 uint8_t input_attachment_index
;
1085 /* For a storage image, whether it is write-only */
1089 struct anv_pipeline_layout
{
1091 struct anv_descriptor_set_layout
*layout
;
1092 uint32_t dynamic_offset_start
;
1098 bool has_dynamic_offsets
;
1099 } stage
[MESA_SHADER_STAGES
];
1101 unsigned char sha1
[20];
1105 struct anv_device
* device
;
1108 VkBufferUsageFlags usage
;
1110 /* Set when bound */
1112 VkDeviceSize offset
;
1115 static inline uint64_t
1116 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
1118 assert(offset
<= buffer
->size
);
1119 if (range
== VK_WHOLE_SIZE
) {
1120 return buffer
->size
- offset
;
1122 assert(range
<= buffer
->size
);
1127 enum anv_cmd_dirty_bits
{
1128 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1129 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1130 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1131 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1132 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1133 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1134 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1135 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1136 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1137 ANV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
1138 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1139 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1140 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1142 typedef uint32_t anv_cmd_dirty_mask_t
;
1144 enum anv_pipe_bits
{
1145 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
1146 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
1147 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
1148 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
1149 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
1150 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
1151 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
1152 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
1153 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
1154 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
1155 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
1157 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1158 * a flush has happened but not a CS stall. The next time we do any sort
1159 * of invalidation we need to insert a CS stall at that time. Otherwise,
1160 * we would have to CS stall on every flush which could be bad.
1162 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
1165 #define ANV_PIPE_FLUSH_BITS ( \
1166 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1167 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1168 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1170 #define ANV_PIPE_STALL_BITS ( \
1171 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1172 ANV_PIPE_DEPTH_STALL_BIT | \
1173 ANV_PIPE_CS_STALL_BIT)
1175 #define ANV_PIPE_INVALIDATE_BITS ( \
1176 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1177 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1178 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1179 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1180 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1181 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1183 struct anv_vertex_binding
{
1184 struct anv_buffer
* buffer
;
1185 VkDeviceSize offset
;
1188 struct anv_push_constants
{
1189 /* Current allocated size of this push constants data structure.
1190 * Because a decent chunk of it may not be used (images on SKL, for
1191 * instance), we won't actually allocate the entire structure up-front.
1195 /* Push constant data provided by the client through vkPushConstants */
1196 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
1198 /* Our hardware only provides zero-based vertex and instance id so, in
1199 * order to satisfy the vulkan requirements, we may have to push one or
1200 * both of these into the shader.
1202 uint32_t base_vertex
;
1203 uint32_t base_instance
;
1205 /* Image data for image_load_store on pre-SKL */
1206 struct brw_image_param images
[MAX_IMAGES
];
1209 struct anv_dynamic_state
{
1212 VkViewport viewports
[MAX_VIEWPORTS
];
1217 VkRect2D scissors
[MAX_SCISSORS
];
1228 float blend_constants
[4];
1238 } stencil_compare_mask
;
1243 } stencil_write_mask
;
1248 } stencil_reference
;
1251 extern const struct anv_dynamic_state default_dynamic_state
;
1253 void anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
1254 const struct anv_dynamic_state
*src
,
1255 uint32_t copy_mask
);
1258 * Attachment state when recording a renderpass instance.
1260 * The clear value is valid only if there exists a pending clear.
1262 struct anv_attachment_state
{
1263 enum isl_aux_usage aux_usage
;
1264 enum isl_aux_usage input_aux_usage
;
1265 struct anv_state color_rt_state
;
1266 struct anv_state input_att_state
;
1268 VkImageLayout current_layout
;
1269 VkImageAspectFlags pending_clear_aspects
;
1271 VkClearValue clear_value
;
1272 bool clear_color_is_zero_one
;
1275 /** State required while building cmd buffer */
1276 struct anv_cmd_state
{
1277 /* PIPELINE_SELECT.PipelineSelection */
1278 uint32_t current_pipeline
;
1279 const struct gen_l3_config
* current_l3_config
;
1281 anv_cmd_dirty_mask_t dirty
;
1282 anv_cmd_dirty_mask_t compute_dirty
;
1283 enum anv_pipe_bits pending_pipe_bits
;
1284 uint32_t num_workgroups_offset
;
1285 struct anv_bo
*num_workgroups_bo
;
1286 VkShaderStageFlags descriptors_dirty
;
1287 VkShaderStageFlags push_constants_dirty
;
1288 uint32_t scratch_size
;
1289 struct anv_pipeline
* pipeline
;
1290 struct anv_pipeline
* compute_pipeline
;
1291 struct anv_framebuffer
* framebuffer
;
1292 struct anv_render_pass
* pass
;
1293 struct anv_subpass
* subpass
;
1294 VkRect2D render_area
;
1295 uint32_t restart_index
;
1296 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
1297 struct anv_descriptor_set
* descriptors
[MAX_SETS
];
1298 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
1299 VkShaderStageFlags push_constant_stages
;
1300 struct anv_push_constants
* push_constants
[MESA_SHADER_STAGES
];
1301 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
1302 struct anv_state samplers
[MESA_SHADER_STAGES
];
1303 struct anv_dynamic_state dynamic
;
1306 struct anv_push_descriptor_set push_descriptor
;
1309 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1310 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1311 * and before invoking the secondary in ExecuteCommands.
1313 bool pma_fix_enabled
;
1316 * Whether or not we know for certain that HiZ is enabled for the current
1317 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1318 * enabled or not, this will be false.
1323 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1324 * valid only when recording a render pass instance.
1326 struct anv_attachment_state
* attachments
;
1329 * Surface states for color render targets. These are stored in a single
1330 * flat array. For depth-stencil attachments, the surface state is simply
1333 struct anv_state render_pass_states
;
1336 * A null surface state of the right size to match the framebuffer. This
1337 * is one of the states in render_pass_states.
1339 struct anv_state null_surface_state
;
1342 struct anv_buffer
* index_buffer
;
1343 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1344 uint32_t index_offset
;
1348 struct anv_cmd_pool
{
1349 VkAllocationCallbacks alloc
;
1350 struct list_head cmd_buffers
;
1353 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1355 enum anv_cmd_buffer_exec_mode
{
1356 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
1357 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
1358 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
1359 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
1360 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
1363 struct anv_cmd_buffer
{
1364 VK_LOADER_DATA _loader_data
;
1366 struct anv_device
* device
;
1368 struct anv_cmd_pool
* pool
;
1369 struct list_head pool_link
;
1371 struct anv_batch batch
;
1373 /* Fields required for the actual chain of anv_batch_bo's.
1375 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1377 struct list_head batch_bos
;
1378 enum anv_cmd_buffer_exec_mode exec_mode
;
1380 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1381 * referenced by this command buffer
1383 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1385 struct u_vector seen_bbos
;
1387 /* A vector of int32_t's for every block of binding tables.
1389 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1391 struct u_vector bt_blocks
;
1394 struct anv_reloc_list surface_relocs
;
1395 /** Last seen surface state block pool center bo offset */
1396 uint32_t last_ss_pool_center
;
1398 /* Serial for tracking buffer completion */
1401 /* Stream objects for storing temporary data */
1402 struct anv_state_stream surface_state_stream
;
1403 struct anv_state_stream dynamic_state_stream
;
1405 VkCommandBufferUsageFlags usage_flags
;
1406 VkCommandBufferLevel level
;
1408 struct anv_cmd_state state
;
1411 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1412 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1413 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1414 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
1415 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
1416 struct anv_cmd_buffer
*secondary
);
1417 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
1418 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
1419 struct anv_cmd_buffer
*cmd_buffer
);
1421 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
1424 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer
*cmd_buffer
,
1425 gl_shader_stage stage
, uint32_t size
);
1426 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1427 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1428 (offsetof(struct anv_push_constants, field) + \
1429 sizeof(cmd_buffer->state.push_constants[0]->field)))
1431 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1432 const void *data
, uint32_t size
, uint32_t alignment
);
1433 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1434 uint32_t *a
, uint32_t *b
,
1435 uint32_t dwords
, uint32_t alignment
);
1438 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1440 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1441 uint32_t entries
, uint32_t *state_offset
);
1443 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
1445 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
1446 uint32_t size
, uint32_t alignment
);
1449 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
1451 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
1452 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
1453 bool depth_clamp_enable
);
1454 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
1456 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
1457 struct anv_render_pass
*pass
,
1458 struct anv_framebuffer
*framebuffer
,
1459 const VkClearValue
*clear_values
);
1461 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1464 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
1465 gl_shader_stage stage
);
1467 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
1469 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1470 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1472 const struct anv_image_view
*
1473 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
1476 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1477 uint32_t num_entries
,
1478 uint32_t *state_offset
);
1480 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
1482 enum anv_fence_state
{
1483 /** Indicates that this is a new (or newly reset fence) */
1484 ANV_FENCE_STATE_RESET
,
1486 /** Indicates that this fence has been submitted to the GPU but is still
1487 * (as far as we know) in use by the GPU.
1489 ANV_FENCE_STATE_SUBMITTED
,
1491 ANV_FENCE_STATE_SIGNALED
,
1496 struct drm_i915_gem_execbuffer2 execbuf
;
1497 struct drm_i915_gem_exec_object2 exec2_objects
[1];
1498 enum anv_fence_state state
;
1503 struct anv_state state
;
1506 struct anv_shader_module
{
1507 unsigned char sha1
[20];
1512 void anv_hash_shader(unsigned char *hash
, const void *key
, size_t key_size
,
1513 struct anv_shader_module
*module
,
1514 const char *entrypoint
,
1515 const struct anv_pipeline_layout
*pipeline_layout
,
1516 const VkSpecializationInfo
*spec_info
);
1518 static inline gl_shader_stage
1519 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1521 assert(__builtin_popcount(vk_stage
) == 1);
1522 return ffs(vk_stage
) - 1;
1525 static inline VkShaderStageFlagBits
1526 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1528 return (1 << mesa_stage
);
1531 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1533 #define anv_foreach_stage(stage, stage_bits) \
1534 for (gl_shader_stage stage, \
1535 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1536 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1537 __tmp &= ~(1 << (stage)))
1539 struct anv_pipeline_bind_map
{
1540 uint32_t surface_count
;
1541 uint32_t sampler_count
;
1542 uint32_t image_count
;
1544 struct anv_pipeline_binding
* surface_to_descriptor
;
1545 struct anv_pipeline_binding
* sampler_to_descriptor
;
1548 struct anv_shader_bin_key
{
1553 struct anv_shader_bin
{
1556 const struct anv_shader_bin_key
*key
;
1558 struct anv_state kernel
;
1559 uint32_t kernel_size
;
1561 const struct brw_stage_prog_data
*prog_data
;
1562 uint32_t prog_data_size
;
1564 struct anv_pipeline_bind_map bind_map
;
1566 /* Prog data follows, then params, then the key, all aligned to 8-bytes */
1569 struct anv_shader_bin
*
1570 anv_shader_bin_create(struct anv_device
*device
,
1571 const void *key
, uint32_t key_size
,
1572 const void *kernel
, uint32_t kernel_size
,
1573 const struct brw_stage_prog_data
*prog_data
,
1574 uint32_t prog_data_size
, const void *prog_data_param
,
1575 const struct anv_pipeline_bind_map
*bind_map
);
1578 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
1581 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
1583 assert(shader
&& shader
->ref_cnt
>= 1);
1584 __sync_fetch_and_add(&shader
->ref_cnt
, 1);
1588 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
1590 assert(shader
&& shader
->ref_cnt
>= 1);
1591 if (__sync_fetch_and_add(&shader
->ref_cnt
, -1) == 1)
1592 anv_shader_bin_destroy(device
, shader
);
1595 struct anv_pipeline
{
1596 struct anv_device
* device
;
1597 struct anv_batch batch
;
1598 uint32_t batch_data
[512];
1599 struct anv_reloc_list batch_relocs
;
1600 uint32_t dynamic_state_mask
;
1601 struct anv_dynamic_state dynamic_state
;
1603 struct anv_pipeline_layout
* layout
;
1605 bool needs_data_cache
;
1607 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
1610 const struct gen_l3_config
* l3_config
;
1611 uint32_t total_size
;
1614 VkShaderStageFlags active_stages
;
1615 struct anv_state blend_state
;
1618 uint32_t binding_stride
[MAX_VBS
];
1619 bool instancing_enable
[MAX_VBS
];
1620 bool primitive_restart
;
1623 uint32_t cs_right_mask
;
1626 bool depth_test_enable
;
1627 bool writes_stencil
;
1628 bool stencil_test_enable
;
1629 bool depth_clamp_enable
;
1634 uint32_t depth_stencil_state
[3];
1640 uint32_t wm_depth_stencil
[3];
1644 uint32_t wm_depth_stencil
[4];
1647 uint32_t interface_descriptor_data
[8];
1651 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
1652 gl_shader_stage stage
)
1654 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
1657 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
1658 static inline const struct brw_##prefix##_prog_data * \
1659 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
1661 if (anv_pipeline_has_stage(pipeline, stage)) { \
1662 return (const struct brw_##prefix##_prog_data *) \
1663 pipeline->shaders[stage]->prog_data; \
1669 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
1670 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
1671 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
1672 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
1673 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
1674 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
1676 static inline const struct brw_vue_prog_data
*
1677 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
1679 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
1680 return &get_gs_prog_data(pipeline
)->base
;
1681 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1682 return &get_tes_prog_data(pipeline
)->base
;
1684 return &get_vs_prog_data(pipeline
)->base
;
1688 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
1689 struct anv_pipeline_cache
*cache
,
1690 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1691 const VkAllocationCallbacks
*alloc
);
1694 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1695 struct anv_pipeline_cache
*cache
,
1696 const VkComputePipelineCreateInfo
*info
,
1697 struct anv_shader_module
*module
,
1698 const char *entrypoint
,
1699 const VkSpecializationInfo
*spec_info
);
1702 enum isl_format isl_format
:16;
1703 struct isl_swizzle swizzle
;
1707 anv_get_format(const struct gen_device_info
*devinfo
, VkFormat format
,
1708 VkImageAspectFlags aspect
, VkImageTiling tiling
);
1710 static inline enum isl_format
1711 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
1712 VkImageAspectFlags aspect
, VkImageTiling tiling
)
1714 return anv_get_format(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
1717 static inline struct isl_swizzle
1718 anv_swizzle_for_render(struct isl_swizzle swizzle
)
1720 /* Sometimes the swizzle will have alpha map to one. We do this to fake
1721 * RGB as RGBA for texturing
1723 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
1724 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
1726 /* But it doesn't matter what we render to that channel */
1727 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
1733 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
1736 * Subsurface of an anv_image.
1738 struct anv_surface
{
1739 /** Valid only if isl_surf::size > 0. */
1740 struct isl_surf isl
;
1743 * Offset from VkImage's base address, as bound by vkBindImageMemory().
1750 /* The original VkFormat provided by the client. This may not match any
1751 * of the actual surface formats.
1754 VkImageAspectFlags aspects
;
1757 uint32_t array_size
;
1758 uint32_t samples
; /**< VkImageCreateInfo::samples */
1759 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1760 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1765 /* Set when bound */
1767 VkDeviceSize offset
;
1772 * For each foo, anv_image::foo_surface is valid if and only if
1773 * anv_image::aspects has a foo aspect.
1775 * The hardware requires that the depth buffer and stencil buffer be
1776 * separate surfaces. From Vulkan's perspective, though, depth and stencil
1777 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
1778 * allocate the depth and stencil buffers as separate surfaces in the same
1782 struct anv_surface color_surface
;
1785 struct anv_surface depth_surface
;
1786 struct anv_surface stencil_surface
;
1791 * For color images, this is the aux usage for this image when not used as a
1794 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the image
1797 enum isl_aux_usage aux_usage
;
1799 struct anv_surface aux_surface
;
1802 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
1804 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
1805 const VkImageAspectFlags aspect_mask
,
1806 const uint32_t samples
)
1808 /* Validate the inputs. */
1809 assert(devinfo
&& aspect_mask
&& samples
);
1810 return devinfo
->gen
>= 8 && (aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1815 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer
*cmd_buffer
,
1816 const struct anv_image
*image
,
1817 enum blorp_hiz_op op
);
1820 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
1821 const struct anv_image
*image
,
1822 const VkImageAspectFlags aspects
,
1823 const VkImageLayout layout
);
1824 static inline uint32_t
1825 anv_get_layerCount(const struct anv_image
*image
,
1826 const VkImageSubresourceRange
*range
)
1828 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1829 image
->array_size
- range
->baseArrayLayer
: range
->layerCount
;
1832 static inline uint32_t
1833 anv_get_levelCount(const struct anv_image
*image
,
1834 const VkImageSubresourceRange
*range
)
1836 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1837 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
1841 struct anv_image_view
{
1842 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
1844 uint32_t offset
; /**< Offset into bo. */
1846 struct isl_view isl
;
1848 VkImageAspectFlags aspect_mask
;
1850 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1852 /** RENDER_SURFACE_STATE when using image as a sampler surface. */
1853 struct anv_state sampler_surface_state
;
1856 * RENDER_SURFACE_STATE when using image as a sampler surface with the
1857 * auxiliary buffer disabled.
1859 struct anv_state no_aux_sampler_surface_state
;
1862 * RENDER_SURFACE_STATE when using image as a storage image. Separate states
1863 * for write-only and readable, using the real format for write-only and the
1864 * lowered format for readable.
1866 struct anv_state storage_surface_state
;
1867 struct anv_state writeonly_storage_surface_state
;
1869 struct brw_image_param storage_image_param
;
1872 struct anv_image_create_info
{
1873 const VkImageCreateInfo
*vk_info
;
1875 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
1876 isl_tiling_flags_t isl_tiling_flags
;
1881 VkResult
anv_image_create(VkDevice _device
,
1882 const struct anv_image_create_info
*info
,
1883 const VkAllocationCallbacks
* alloc
,
1886 const struct anv_surface
*
1887 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
1888 VkImageAspectFlags aspect_mask
);
1891 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
1893 static inline struct VkExtent3D
1894 anv_sanitize_image_extent(const VkImageType imageType
,
1895 const struct VkExtent3D imageExtent
)
1897 switch (imageType
) {
1898 case VK_IMAGE_TYPE_1D
:
1899 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1900 case VK_IMAGE_TYPE_2D
:
1901 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1902 case VK_IMAGE_TYPE_3D
:
1905 unreachable("invalid image type");
1909 static inline struct VkOffset3D
1910 anv_sanitize_image_offset(const VkImageType imageType
,
1911 const struct VkOffset3D imageOffset
)
1913 switch (imageType
) {
1914 case VK_IMAGE_TYPE_1D
:
1915 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1916 case VK_IMAGE_TYPE_2D
:
1917 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1918 case VK_IMAGE_TYPE_3D
:
1921 unreachable("invalid image type");
1926 void anv_fill_buffer_surface_state(struct anv_device
*device
,
1927 struct anv_state state
,
1928 enum isl_format format
,
1929 uint32_t offset
, uint32_t range
,
1932 void anv_image_view_fill_image_param(struct anv_device
*device
,
1933 struct anv_image_view
*view
,
1934 struct brw_image_param
*param
);
1935 void anv_buffer_view_fill_image_param(struct anv_device
*device
,
1936 struct anv_buffer_view
*view
,
1937 struct brw_image_param
*param
);
1939 struct anv_sampler
{
1943 struct anv_framebuffer
{
1948 uint32_t attachment_count
;
1949 struct anv_image_view
* attachments
[0];
1952 struct anv_subpass
{
1953 uint32_t attachment_count
;
1956 * A pointer to all attachment references used in this subpass.
1957 * Only valid if ::attachment_count > 0.
1959 VkAttachmentReference
* attachments
;
1960 uint32_t input_count
;
1961 VkAttachmentReference
* input_attachments
;
1962 uint32_t color_count
;
1963 VkAttachmentReference
* color_attachments
;
1964 VkAttachmentReference
* resolve_attachments
;
1966 VkAttachmentReference depth_stencil_attachment
;
1968 /** Subpass has a depth/stencil self-dependency */
1969 bool has_ds_self_dep
;
1971 /** Subpass has at least one resolve attachment */
1975 enum anv_subpass_usage
{
1976 ANV_SUBPASS_USAGE_DRAW
= (1 << 0),
1977 ANV_SUBPASS_USAGE_INPUT
= (1 << 1),
1978 ANV_SUBPASS_USAGE_RESOLVE_SRC
= (1 << 2),
1979 ANV_SUBPASS_USAGE_RESOLVE_DST
= (1 << 3),
1982 struct anv_render_pass_attachment
{
1983 /* TODO: Consider using VkAttachmentDescription instead of storing each of
1984 * its members individually.
1988 VkImageUsageFlags usage
;
1989 VkAttachmentLoadOp load_op
;
1990 VkAttachmentStoreOp store_op
;
1991 VkAttachmentLoadOp stencil_load_op
;
1992 VkImageLayout initial_layout
;
1993 VkImageLayout final_layout
;
1995 /* An array, indexed by subpass id, of how the attachment will be used. */
1996 enum anv_subpass_usage
* subpass_usage
;
1998 /* The subpass id in which the attachment will be used last. */
1999 uint32_t last_subpass_idx
;
2002 struct anv_render_pass
{
2003 uint32_t attachment_count
;
2004 uint32_t subpass_count
;
2005 VkAttachmentReference
* subpass_attachments
;
2006 enum anv_subpass_usage
* subpass_usages
;
2007 struct anv_render_pass_attachment
* attachments
;
2008 struct anv_subpass subpasses
[0];
2011 struct anv_query_pool_slot
{
2017 struct anv_query_pool
{
2023 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
2026 void anv_dump_image_to_ppm(struct anv_device
*device
,
2027 struct anv_image
*image
, unsigned miplevel
,
2028 unsigned array_layer
, VkImageAspectFlagBits aspect
,
2029 const char *filename
);
2031 enum anv_dump_action
{
2032 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
2035 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
2036 void anv_dump_finish(void);
2038 void anv_dump_add_framebuffer(struct anv_cmd_buffer
*cmd_buffer
,
2039 struct anv_framebuffer
*fb
);
2041 static inline uint32_t
2042 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
2044 /* This function must be called from within a subpass. */
2045 assert(cmd_state
->pass
&& cmd_state
->subpass
);
2047 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
2049 /* The id of this subpass shouldn't exceed the number of subpasses in this
2050 * render pass minus 1.
2052 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
2056 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
2058 static inline struct __anv_type * \
2059 __anv_type ## _from_handle(__VkType _handle) \
2061 return (struct __anv_type *) _handle; \
2064 static inline __VkType \
2065 __anv_type ## _to_handle(struct __anv_type *_obj) \
2067 return (__VkType) _obj; \
2070 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
2072 static inline struct __anv_type * \
2073 __anv_type ## _from_handle(__VkType _handle) \
2075 return (struct __anv_type *)(uintptr_t) _handle; \
2078 static inline __VkType \
2079 __anv_type ## _to_handle(struct __anv_type *_obj) \
2081 return (__VkType)(uintptr_t) _obj; \
2084 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
2085 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
2087 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
2088 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
2089 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
2090 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
2091 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
2093 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
2094 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
2095 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
2096 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
2097 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
2098 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
2099 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplateKHR
)
2100 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
2101 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
2102 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
2103 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
2104 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
2105 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
2106 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
2107 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
2108 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
2109 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
2110 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
2111 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
2112 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
2114 /* Gen-specific function declarations */
2116 # include "anv_genX.h"
2118 # define genX(x) gen7_##x
2119 # include "anv_genX.h"
2121 # define genX(x) gen75_##x
2122 # include "anv_genX.h"
2124 # define genX(x) gen8_##x
2125 # include "anv_genX.h"
2127 # define genX(x) gen9_##x
2128 # include "anv_genX.h"
2132 #endif /* ANV_PRIVATE_H */